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https://github.com/pound-emu/ballistic.git
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334 lines
16 KiB
XML
334 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="luti4_mz4_ztz" title="LUTI4 (four registers)" type="instruction">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LUTI4" />
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</docvars>
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<heading>LUTI4 (four registers)</heading>
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<desc>
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<brief>Lookup table read with 4-bit indexes</brief>
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<description>
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<para>Copy 16-bit or 32-bit elements from ZT0 to four destination vectors using packed 4-bit indices from a segment of the source vector register. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index modulo the total number of segments.</para>
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<para>This instruction is unpredicated.</para>
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</description>
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<status>S1: Green, S2: Amber</status>
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<predicated>False</predicated>
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<sm_policy>SM_1_only</sm_policy>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_consecutive">Consecutive</a>
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<txt> and </txt>
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<a href="#iclass_strided">Strided</a>
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</classesintro>
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<iclass name="Consecutive" oneof="2" id="iclass_consecutive" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LUTI4" />
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<docvar key="stride-type" value="consecutive" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
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</arch_variants>
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<regdiagram form="32" psname="LUTI4-MZ4.ZTZ-1">
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<box hibit="31" width="13" settings="13">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="18" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="16" name="i1" usename="1">
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<c></c>
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</box>
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<box hibit="15" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="13" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="11" width="2" name="opc2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="3" name="Zd" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="1" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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</regdiagram>
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<encoding name="luti4_mz4_ztz_1" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LUTI4" />
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<docvar key="stride-type" value="consecutive" />
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</docvars>
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<asmtemplate><text>LUTI4 </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)"><Zd1></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [H,S]"><T></a><text>-</text><a link="sa_zd4" hover="Fourth destination scalable vector register of a multi-vector sequence (field Zd)"><Zd4></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [H,S]"><T></a><text> </text><text>}</text><text>, ZT0, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>[</text><a link="sa_index" hover="Vector segment index [0-1] (field "i1")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LUTI4-MZ4.ZTZ-1" mylink="LUTI4-MZ4.ZTZ-1" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
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if size == '00' || size == '11' then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer isize = 4;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer dstride = 1;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
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integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Strided" oneof="2" id="iclass_strided" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LUTI4" />
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<docvar key="stride-type" value="strided" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SME2p1" feature="FEAT_SME2p1" />
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</arch_variants>
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<regdiagram form="32" psname="LUTI4-MZ4.ZTZ-4">
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<box hibit="31" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="29" width="10" settings="10">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" settings="1">
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<c>1</c>
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</box>
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<box hibit="18" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="16" name="i1" usename="1">
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<c></c>
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</box>
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<box hibit="15" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="13" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="11" width="2" name="opc2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="3" settings="1">
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<c>0</c>
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</box>
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<box hibit="2" settings="1">
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<c>0</c>
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</box>
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<box hibit="1" width="2" name="Zd" usename="1">
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<c colspan="2"></c>
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</box>
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</regdiagram>
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<encoding name="luti4_mz4_ztz_4" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="mortlach2" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LUTI4" />
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<docvar key="stride-type" value="strided" />
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</docvars>
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<asmtemplate><text>LUTI4 </text><text>{</text><text> </text><a link="sa_zd1_1" hover="First destination scalable vector register Z0-Z3 or Z16-Z19 of a multi-vector sequence (field D:'00':Zd)"><Zd1></a><text>.H, </text><a link="sa_zd2" hover="Second destination scalable vector register Z4-Z7 or Z20-Z23 of a multi-vector sequence (field D:'01':Zd)"><Zd2></a><text>.H, </text><a link="sa_zd3" hover="Third destination scalable vector register Z8-Z11 or Z24-Z27 of a multi-vector sequence (field D:'10':Zd)"><Zd3></a><text>.H, </text><a link="sa_zd4_1" hover="Fourth destination scalable vector register Z12-Z15 or Z28-Z31 of a multi-vector sequence (field D:'11':Zd)"><Zd4></a><text>.H </text><text>}</text><text>, ZT0, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>[</text><a link="sa_index" hover="Vector segment index [0-1] (field "i1")"><index></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="LUTI4-MZ4.ZTZ-4" mylink="LUTI4-MZ4.ZTZ-4" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
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if size != '01' then UNDEFINED;
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constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer isize = 4;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer dstride = 4;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:'00':Zd);
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integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(i1);
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constant integer nreg = 4;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
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<symbol link="sa_zd1"><Zd1></symbol>
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<account encodedin="Zd">
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<docvars>
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<docvar key="stride-type" value="consecutive" />
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</docvars>
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<intro>
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<para>For the consecutive variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_4" symboldefcount="2">
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<symbol link="sa_zd1_1"><Zd1></symbol>
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<account encodedin="00:D:Zd">
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<docvars>
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<docvar key="stride-type" value="strided" />
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</docvars>
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<intro>
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<para>For the strided variant: is the name of the first destination scalable vector register Z0-Z3 or Z16-Z19 of a multi-vector sequence, encoded as "D:'00':Zd".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_4" symboldefcount="1">
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<symbol link="sa_zd2"><Zd2></symbol>
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<account encodedin="01:D:Zd">
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<intro>
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<para>Is the name of the second destination scalable vector register Z4-Z7 or Z20-Z23 of a multi-vector sequence, encoded as "D:'01':Zd".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_4" symboldefcount="1">
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<symbol link="sa_zd3"><Zd3></symbol>
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<account encodedin="10:D:Zd">
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<intro>
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<para>Is the name of the third destination scalable vector register Z8-Z11 or Z24-Z27 of a multi-vector sequence, encoded as "D:'10':Zd".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size">
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<intro>Is the size specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_1" symboldefcount="1">
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<symbol link="sa_zd4"><Zd4></symbol>
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<account encodedin="Zd">
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<docvars>
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<docvar key="stride-type" value="consecutive" />
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</docvars>
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<intro>
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<para>For the consecutive variant: is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_4" symboldefcount="2">
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<symbol link="sa_zd4_1"><Zd4></symbol>
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<account encodedin="11:D:Zd">
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<docvars>
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<docvar key="stride-type" value="strided" />
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</docvars>
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<intro>
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<para>For the strided variant: is the name of the fourth destination scalable vector register Z12-Z15 or Z28-Z31 of a multi-vector sequence, encoded as "D:'11':Zd".</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_1, luti4_mz4_ztz_4" symboldefcount="1">
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<symbol link="sa_zn"><Zn></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="luti4_mz4_ztz_1, luti4_mz4_ztz_4" symboldefcount="1">
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<symbol link="sa_index"><index></symbol>
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<account encodedin="i1">
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<intro>
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<para>Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="LUTI4-MZ4.ZTZ-1" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
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<a link="impl-aarch64.CheckSMEZT0Enabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEZT0Enabled()">CheckSMEZT0Enabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer elements = VL DIV esize;
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integer segments = esize DIV (isize * nreg);
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integer segment = imm MOD segments;
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bits(VL) indexes = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
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bits(512) table = <a link="impl-aarch64.ZT0.read.1" file="shared_pseudocode.xml" hover="accessor: bits(width) ZT0[integer width]">ZT0</a>[512];
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for r = 0 to nreg-1
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integer base = (segment * nreg + r) * elements;
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bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
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for e = 0 to elements-1
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integer index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indexes, base+e, isize]);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 32]<esize-1:0>;
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;
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d = d + dstride;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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