archived-ballistic/spec/arm64_xml/sha512h_advsimd.xml

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<instructionsection id="SHA512H_advsimd" title="SHA512H -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="advsimd" />
    <docvar key="isa" value="A64" />
    <docvar key="mnemonic" value="SHA512H" />
  </docvars>
  <heading>SHA512H</heading>
  <desc>
    <brief>
      <para>SHA512 Hash update part 1</para>
    </brief>
    <authored>
      <para>SHA512 Hash update part 1 takes the values from the three 128-bit source SIMD&amp;FP registers and produces a 128-bit output value that combines the sigma1 and chi functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&amp;FP register.</para>
      <para>This instruction is implemented only when <xref linkend="v8.2.SHA512">FEAT_SHA512</xref> is implemented.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If PSTATE.DIT is 1:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="advsimd" />
        <docvar key="isa" value="A64" />
        <docvar key="mnemonic" value="SHA512H" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_SHA512" />
      </arch_variants>
      <regdiagram form="32" psname="aarch64/instrs/vector/crypto/sha512/sha512h">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" name="O" settings="1">
          <c>0</c>
        </box>
        <box hibit="13" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="opcode" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="SHA512H_QQV_cryptosha512_3" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="advsimd" />
          <docvar key="isa" value="A64" />
          <docvar key="mnemonic" value="SHA512H" />
        </docvars>
        <asmtemplate><text>SHA512H  </text><a link="sa_qd" hover="128-bit SIMD&amp;FP source and destination register (field &quot;Rd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="Second 128-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_vm" hover="Third SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Vm&gt;</a><text>.2D</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch64/instrs/vector/crypto/sha512/sha512h" mylink="aarch64.instrs.vector.crypto.sha512.sha512h" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSHA512Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA512Ext()">HaveSHA512Ext</a>() then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SHA512H_QQV_cryptosha512_3" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source and destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA512H_QQV_cryptosha512_3" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SHA512H_QQV_cryptosha512_3" symboldefcount="1">
      <symbol link="sa_vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the third SIMD&amp;FP source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch64/instrs/vector/crypto/sha512/sha512h" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();

bits(128) Vtmp;
bits(64)  MSigma1;
bits(64)  tmp;
bits(128) x = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
bits(128) y = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
bits(128) w = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];

MSigma1 =  <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(y&lt;127:64&gt;, 14) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(y&lt;127:64&gt;,18) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(y&lt;127:64&gt;,41);
Vtmp&lt;127:64&gt; =  (y&lt;127:64&gt; AND x&lt;63:0&gt;) EOR (NOT(y&lt;127:64&gt;) AND x&lt;127:64&gt;);
Vtmp&lt;127:64&gt; = (Vtmp&lt;127:64&gt; + MSigma1 +  w&lt;127:64&gt;);
tmp = Vtmp&lt;127:64&gt; + y&lt;63:0&gt;;
MSigma1 = <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(tmp, 14) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(tmp,18) EOR <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(tmp,41);
Vtmp&lt;63:0&gt; = (tmp AND y&lt;127:64&gt;) EOR (NOT(tmp) AND x&lt;63:0&gt;);
Vtmp&lt;63:0&gt; = (Vtmp&lt;63:0&gt; + MSigma1 + w&lt;63:0&gt;);
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] =  Vtmp;</pstext>
    </ps>
  </ps_section>
</instructionsection>