mirror of
https://github.com/pound-emu/ballistic.git
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682 lines
38 KiB
XML
682 lines
38 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STR_imm_fpsimd" title="STR (immediate, SIMD&FP) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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</docvars>
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<heading>STR (immediate, SIMD&FP)</heading>
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<desc>
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<brief>
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<para>Store SIMD&FP register (immediate offset)</para>
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</brief>
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<authored>
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<para>Store SIMD&FP register (immediate offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from 3 classes:</txt>
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<a href="#iclass_post_indexed">Post-index</a>
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<txt>, </txt>
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<a href="#iclass_pre_indexed">Pre-index</a>
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<txt> and </txt>
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<a href="#iclass_unsigned_scaled_offset">Unsigned offset</a>
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</classesintro>
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<iclass name="Post-index" oneof="3" id="iclass_post_indexed" no_encodings="5" isa="A64">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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</docvars>
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<iclassintro count="5"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/single/simdfp/immediate/signed/post-idx" tworows="1">
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<box hibit="31" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc" usename="1" settings="1" psbits="xx">
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<c>x</c>
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="9" name="imm9" usename="1">
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<c colspan="9"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STR_B_ldst_immpost" oneofinclass="5" oneof="15" label="8-bit" bitdiffs="size == 00 && opc == 00">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-8-fsreg" />
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<docvar key="atomic-ops" value="STR-8-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="8-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_bt" hover="8-bit SIMD&FP register to be transferred (field "Rt")"><Bt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a></asmtemplate>
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</encoding>
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<encoding name="STR_H_ldst_immpost" oneofinclass="5" oneof="15" label="16-bit" bitdiffs="size == 01 && opc == 00">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-16-fsreg" />
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<docvar key="atomic-ops" value="STR-16-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="16-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_ht" hover="16-bit SIMD&FP register to be transferred (field "Rt")"><Ht></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a></asmtemplate>
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</encoding>
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<encoding name="STR_S_ldst_immpost" oneofinclass="5" oneof="15" label="32-bit" bitdiffs="size == 10 && opc == 00">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-32-fsreg" />
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<docvar key="atomic-ops" value="STR-32-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="32-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_st" hover="32-bit SIMD&FP register to be transferred (field "Rt")"><St></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a></asmtemplate>
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</encoding>
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<encoding name="STR_D_ldst_immpost" oneofinclass="5" oneof="15" label="64-bit" bitdiffs="size == 11 && opc == 00">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-64-fsreg" />
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<docvar key="atomic-ops" value="STR-64-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="64-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_dt" hover="64-bit SIMD&FP register to be transferred (field "Rt")"><Dt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a></asmtemplate>
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</encoding>
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<encoding name="STR_Q_ldst_immpost" oneofinclass="5" oneof="15" label="128-bit" bitdiffs="size == 00 && opc == 10">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-form-reg-type" value="post-indexed-128-fsreg" />
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<docvar key="atomic-ops" value="STR-128-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="128-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>1</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_qt" hover="128-bit SIMD&FP register to be transferred (field "Rt")"><Qt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/single/simdfp/immediate/signed/post-idx" mylink="aarch64.instrs.memory.single.simdfp.immediate.signed.post-idx" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = TRUE;
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boolean postindex = TRUE;
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integer scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc<1>:size);
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if scale > 4 then UNDEFINED;
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bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Pre-index" oneof="3" id="iclass_pre_indexed" no_encodings="5" isa="A64">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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</docvars>
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<iclassintro count="5"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/single/simdfp/immediate/signed/pre-idx" tworows="1">
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<box hibit="31" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc" usename="1" settings="1" psbits="xx">
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<c>x</c>
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="9" name="imm9" usename="1">
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<c colspan="9"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STR_B_ldst_immpre" oneofinclass="5" oneof="15" label="8-bit" bitdiffs="size == 00 && opc == 00">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-8-fsreg" />
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<docvar key="atomic-ops" value="STR-8-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="8-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_bt" hover="8-bit SIMD&FP register to be transferred (field "Rt")"><Bt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STR_H_ldst_immpre" oneofinclass="5" oneof="15" label="16-bit" bitdiffs="size == 01 && opc == 00">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-16-fsreg" />
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<docvar key="atomic-ops" value="STR-16-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="16-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_ht" hover="16-bit SIMD&FP register to be transferred (field "Rt")"><Ht></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a><text>]!</text></asmtemplate>
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</encoding>
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|
<encoding name="STR_S_ldst_immpre" oneofinclass="5" oneof="15" label="32-bit" bitdiffs="size == 10 && opc == 00">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-32-fsreg" />
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|
<docvar key="atomic-ops" value="STR-32-fsreg" />
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|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
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|
<docvar key="mnemonic" value="STR" />
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|
<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="32-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_st" hover="32-bit SIMD&FP register to be transferred (field "Rt")"><St></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STR_D_ldst_immpre" oneofinclass="5" oneof="15" label="64-bit" bitdiffs="size == 11 && opc == 00">
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|
<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="address-form-reg-type" value="pre-indexed-64-fsreg" />
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<docvar key="atomic-ops" value="STR-64-fsreg" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STR" />
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<docvar key="offset-type" value="off9s_u" />
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<docvar key="reg-type" value="64-fsreg" />
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</docvars>
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<box hibit="31" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="opc">
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<c>0</c>
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<c></c>
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</box>
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<asmtemplate><text>STR </text><a link="sa_dt" hover="64-bit SIMD&FP register to be transferred (field "Rt")"><Dt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a><text>]!</text></asmtemplate>
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</encoding>
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|
<encoding name="STR_Q_ldst_immpre" oneofinclass="5" oneof="15" label="128-bit" bitdiffs="size == 00 && opc == 10">
|
|
<docvars>
|
|
<docvar key="address-form" value="pre-indexed" />
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|
<docvar key="address-form-reg-type" value="pre-indexed-128-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-128-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off9s_u" />
|
|
<docvar key="reg-type" value="128-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>1</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_qt" hover="128-bit SIMD&FP register to be transferred (field "Rt")"><Qt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_simm" hover="Signed immediate byte offset [-256-255] (field "imm9")"><simm></a><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/single/simdfp/immediate/signed/pre-idx" mylink="aarch64.instrs.memory.single.simdfp.immediate.signed.pre-idx" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = TRUE;
|
|
boolean postindex = FALSE;
|
|
integer scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc<1>:size);
|
|
if scale > 4 then UNDEFINED;
|
|
bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="Unsigned offset" oneof="3" id="iclass_unsigned_scaled_offset" no_encodings="5" isa="A64">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
</docvars>
|
|
<iclassintro count="5"></iclassintro>
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/single/simdfp/immediate/unsigned" tworows="1">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1" settings="1" psbits="xx">
|
|
<c>x</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="12" name="imm12" usename="1">
|
|
<c colspan="12"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="STR_B_ldst_pos" oneofinclass="5" oneof="15" label="8-bit" bitdiffs="size == 00 && opc == 00">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-8-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-8-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
<docvar key="reg-type" value="8-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>0</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_bt" hover="8-bit SIMD&FP register to be transferred (field "Rt")"><Bt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_pimm" hover="Optional positive immediate byte offset [0-4095], default 0 (field "imm12")"><pimm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STR_H_ldst_pos" oneofinclass="5" oneof="15" label="16-bit" bitdiffs="size == 01 && opc == 00">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-16-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-16-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
<docvar key="reg-type" value="16-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>0</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_ht" hover="16-bit SIMD&FP register to be transferred (field "Rt")"><Ht></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_pimm_2" hover="Optional positive immediate byte offset, multiple of 2 [0-8190], default 0 (field "imm12")"><pimm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STR_S_ldst_pos" oneofinclass="5" oneof="15" label="32-bit" bitdiffs="size == 10 && opc == 00">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-32-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-32-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
<docvar key="reg-type" value="32-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>0</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_st" hover="32-bit SIMD&FP register to be transferred (field "Rt")"><St></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_pimm_4" hover="Optional positive immediate byte offset, multiple of 4 [0-16380], default 0 (field "imm12")"><pimm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STR_D_ldst_pos" oneofinclass="5" oneof="15" label="64-bit" bitdiffs="size == 11 && opc == 00">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-64-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-64-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
<docvar key="reg-type" value="64-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>0</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_dt" hover="64-bit SIMD&FP register to be transferred (field "Rt")"><Dt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_pimm_1" hover="Optional positive immediate byte offset, multiple of 8 [0-32760], default 0 (field "imm12")"><pimm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STR_Q_ldst_pos" oneofinclass="5" oneof="15" label="128-bit" bitdiffs="size == 00 && opc == 10">
|
|
<docvars>
|
|
<docvar key="address-form" value="unsigned-scaled-offset" />
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-128-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-128-fsreg" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="STR" />
|
|
<docvar key="offset-type" value="off12u_s" />
|
|
<docvar key="reg-type" value="128-fsreg" />
|
|
</docvars>
|
|
<box hibit="31" width="2" name="size">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc">
|
|
<c>1</c>
|
|
<c></c>
|
|
</box>
|
|
<asmtemplate><text>STR </text><a link="sa_qt" hover="128-bit SIMD&FP register to be transferred (field "Rt")"><Qt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_pimm_3" hover="Optional positive immediate byte offset, multiple of 16 [0-65520], default 0 (field "imm12")"><pimm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/single/simdfp/immediate/unsigned" mylink="aarch64.instrs.memory.single.simdfp.immediate.unsigned" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = FALSE;
|
|
boolean postindex = FALSE;
|
|
integer scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc<1>:size);
|
|
if scale > 4 then UNDEFINED;
|
|
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 64), scale);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="STR_B_ldst_immpost, STR_B_ldst_immpre, STR_B_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_bt"><Bt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_D_ldst_immpost, STR_D_ldst_immpre, STR_D_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_dt"><Dt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_H_ldst_immpost, STR_H_ldst_immpre, STR_H_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_ht"><Ht></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_Q_ldst_immpost, STR_Q_ldst_immpre, STR_Q_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_qt"><Qt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_S_ldst_immpost, STR_S_ldst_immpre, STR_S_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_st"><St></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_B_ldst_immpost, STR_B_ldst_immpre, STR_B_ldst_pos, STR_D_ldst_immpost, STR_D_ldst_immpre, STR_D_ldst_pos, STR_H_ldst_immpost, STR_H_ldst_immpre, STR_H_ldst_pos, STR_Q_ldst_immpost, STR_Q_ldst_immpre, STR_Q_ldst_pos, STR_S_ldst_immpost, STR_S_ldst_immpre, STR_S_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_B_ldst_immpost, STR_B_ldst_immpre, STR_D_ldst_immpost, STR_D_ldst_immpre, STR_H_ldst_immpost, STR_H_ldst_immpre, STR_Q_ldst_immpost, STR_Q_ldst_immpre, STR_S_ldst_immpost, STR_S_ldst_immpre" symboldefcount="1">
|
|
<symbol link="sa_simm"><simm></symbol>
|
|
<account encodedin="imm9">
|
|
<intro>
|
|
<para>Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_B_ldst_pos" symboldefcount="1">
|
|
<symbol link="sa_pimm"><pimm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-8-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-8-fsreg" />
|
|
<docvar key="reg-type" value="8-fsreg" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 8-bit variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_H_ldst_pos" symboldefcount="2">
|
|
<symbol link="sa_pimm_2"><pimm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-16-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-16-fsreg" />
|
|
<docvar key="reg-type" value="16-fsreg" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 16-bit variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_S_ldst_pos" symboldefcount="3">
|
|
<symbol link="sa_pimm_4"><pimm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-32-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-32-fsreg" />
|
|
<docvar key="reg-type" value="32-fsreg" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_D_ldst_pos" symboldefcount="4">
|
|
<symbol link="sa_pimm_1"><pimm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-64-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-64-fsreg" />
|
|
<docvar key="reg-type" value="64-fsreg" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STR_Q_ldst_pos" symboldefcount="5">
|
|
<symbol link="sa_pimm_3"><pimm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form-reg-type" value="unsigned-scaled-offset-128-fsreg" />
|
|
<docvar key="atomic-ops" value="STR-128-fsreg" />
|
|
<docvar key="reg-type" value="128-fsreg" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the 128-bit variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/single/simdfp/immediate/signed/post-idx" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
|
|
<pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
|
boolean nontemporal = FALSE;
|
|
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if opc<0> == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
|
|
integer datasize = 8 << scale;
|
|
boolean tagchecked = memop != <a link="MemOp_PREFETCH" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a> && (wback || n != 31);</pstext>
|
|
</ps>
|
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</ps_section>
|
|
<ps_section howmany="1">
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|
<ps name="aarch64/instrs/memory/single/simdfp/immediate/signed/post-idx" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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bits(64) address;
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bits(datasize) data;
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|
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|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);
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|
|
|
if n == 31 then
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|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
|
|
else
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|
address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
|
|
if ! postindex then
|
|
address = address + offset;
|
|
|
|
case memop of
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|
when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
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|
data = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t, datasize];
|
|
Mem[address, datasize DIV 8, accdesc] = data;
|
|
|
|
when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
|
|
data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, datasize DIV 8, accdesc];
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = data;
|
|
|
|
if wback then
|
|
if postindex then
|
|
address = address + offset;
|
|
if n == 31 then
|
|
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
|
|
else
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|