mirror of
https://github.com/pound-emu/ballistic.git
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157 lines
8.6 KiB
XML
157 lines
8.6 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STZGM" title="STZGM -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STZGM" />
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</docvars>
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<heading>STZGM</heading>
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<desc>
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<brief>
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<para>Store Tag and Zero Multiple</para>
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</brief>
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<authored>
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<para>Store Tag and Zero Multiple writes a naturally aligned block of N Allocation Tags and stores zero to the associated data locations, where the size of N is identified in DCZID_EL0.BS, and the Allocation Tag is taken from the source register bits<3:0>.</para>
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<para>This instruction is <arm-defined-word>undefined</arm-defined-word> at EL0.</para>
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<para>This instruction generates an Unchecked access.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STZGM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.5" feature="FEAT_MTE2" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcsettagandzeroarray">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="opc<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="opc<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" name="imm9<8>" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" name="imm9<7>" settings="1">
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<c>0</c>
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</box>
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<box hibit="18" name="imm9<6>" settings="1">
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<c>0</c>
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</box>
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<box hibit="17" name="imm9<5>" settings="1">
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<c>0</c>
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</box>
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<box hibit="16" name="imm9<4>" settings="1">
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<c>0</c>
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</box>
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<box hibit="15" name="imm9<3>" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" name="imm9<2>" settings="1">
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<c>0</c>
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</box>
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<box hibit="13" name="imm9<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="12" name="imm9<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="11" name="op2<1>" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" name="op2<0>" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Xn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Xt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="STZGM_64bulk_ldsttags" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="STZGM" />
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</docvars>
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<asmtemplate><text>STZGM </text><a link="sa_xt" hover="64-bit general-purpose source register (field "Xt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Xn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettagandzeroarray" mylink="aarch64.instrs.integer.tags.mcsettagandzeroarray" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTE2Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTE2Ext()">HaveMTE2Ext</a>() then UNDEFINED;
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="STZGM_64bulk_ldsttags" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Xt">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Xt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STZGM_64bulk_ldsttags" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Xn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/tags/mcsettagandzeroarray" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
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UNDEFINED;
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bits(64) data = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, 64];
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bits(4) tag = data<3:0>;
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bits(64) address;
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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integer size = 4*(2^(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DCZID_EL0.BS)));
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address = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(address,size);
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integer count = size >> <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLDGSTG.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)">CreateAccDescLDGSTG</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>);
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for i = 0 to count-1
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<a link="AArch64.MemTag.write.2" file="shared_pseudocode.xml" hover="accessor: AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value">AArch64.MemTag</a>[address, accdesc] = tag;
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Mem[address, TAG_GRANULE, accdesc] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(8*<a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 << LOG2_TAG_GRANULE">TAG_GRANULE</a>);
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address = address + <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 << LOG2_TAG_GRANULE">TAG_GRANULE</a>;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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