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https://github.com/pound-emu/ballistic.git
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211 lines
12 KiB
XML
211 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SYS" title="SYS -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<heading>SYS</heading>
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<desc>
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<brief>
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<para>System instruction</para>
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</brief>
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<authored>
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<para>System instruction. For more information, see <xref linkend="BABEJJJE">Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions</xref> for the encodings of System instructions.</para>
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</authored>
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</desc>
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<alias_list howmany="15">
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<alias_list_intro>This instruction is used by the aliases </alias_list_intro>
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<aliasref aliaspageid="AT_SYS" aliasfile="at_sys.xml" hover="Address translate" punct=", ">
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<text>AT</text>
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<aliaspref>CRn == '0111' && CRm == '100x' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,'0111',CRm,op2) == <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a></aliaspref>
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</aliasref>
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<aliasref aliaspageid="BRB_SYS" aliasfile="brb_sys.xml" hover="Branch record buffer" punct=", ">
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<text>BRB</text>
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<aliaspref>op1 == '001' && CRn == '0111' && CRm == '0010' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>('001','0111','0010',op2) == <a link="Sys_BRB" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_BRB</a></aliaspref>
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</aliasref>
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<aliasref aliaspageid="CFP_SYS" aliasfile="cfp_sys.xml" hover="CFP" punct=", ">
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<text>CFP</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0011' && op2 == '100'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="COSP_SYS" aliasfile="cosp_sys.xml" hover="COSP" punct=", ">
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<text>COSP</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0011' && op2 == '110'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="CPP_SYS" aliasfile="cpp_sys.xml" hover="CPP" punct=", ">
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<text>CPP</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0011' && op2 == '111'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="DC_SYS" aliasfile="dc_sys.xml" hover="Data cache operation" punct=", ">
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<text>DC</text>
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<aliaspref>CRn == '0111' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,'0111',CRm,op2) == <a link="Sys_DC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_DC</a></aliaspref>
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</aliasref>
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<aliasref aliaspageid="DVP_SYS" aliasfile="dvp_sys.xml" hover="DVP" punct=", ">
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<text>DVP</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0011' && op2 == '101'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="GCSPOPCX_SYS" aliasfile="gcspopcx_sys.xml" hover="GCSPOPCX" punct=", ">
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<text>GCSPOPCX</text>
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<aliaspref>op1 == '000' && CRn == '0111' && CRm == '0111' && op2 == '101'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="GCSPOPX_SYS" aliasfile="gcspopx_sys.xml" hover="GCSPOPX" punct=", ">
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<text>GCSPOPX</text>
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<aliaspref>op1 == '000' && CRn == '0111' && CRm == '0111' && op2 == '110'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="GCSPUSHM_SYS" aliasfile="gcspushm_sys.xml" hover="GCSPUSHM" punct=", ">
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<text>GCSPUSHM</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0111' && op2 == '000'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="GCSPUSHX_SYS" aliasfile="gcspushx_sys.xml" hover="GCSPUSHX" punct=", ">
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<text>GCSPUSHX</text>
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<aliaspref>op1 == '000' && CRn == '0111' && CRm == '0111' && op2 == '100'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="GCSSS1_SYS" aliasfile="gcsss1_sys.xml" hover="GCSSS1" punct=", ">
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<text>GCSSS1</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0111' && op2 == '010'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="IC_SYS" aliasfile="ic_sys.xml" hover="Instruction cache operation" punct=", ">
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<text>IC</text>
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<aliaspref>CRn == '0111' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,'0111',CRm,op2) == <a link="Sys_IC" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_IC</a></aliaspref>
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</aliasref>
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<aliasref aliaspageid="TLBI_SYS" aliasfile="tlbi_sys.xml" hover="TLB invalidate operation" punct=" and ">
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<text>TLBI</text>
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<aliaspref>CRn == '100x' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,CRn,CRm,op2) == <a link="Sys_TLBI" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_TLBI</a></aliaspref>
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</aliasref>
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<aliasref aliaspageid="TRCIT_SYS" aliasfile="trcit_sys.xml" hover="TRCIT" punct=".">
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<text>TRCIT</text>
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<aliaspref>op1 == '011' && CRn == '0111' && CRm == '0010' && op2 == '111'</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when each alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
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<box hibit="31" width="10" settings="10">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="20" width="2" name="op0" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="op1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="CRn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="CRm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="3" name="op2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYS" />
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</docvars>
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<asmtemplate><text>SYS #</text><a link="sa_op1" hover="3-bit unsigned immediate [0-7] (field "op1")"><op1></a><text>, </text><a link="sa_cn" hover="Name 'Cn', with 'n' [0-15] (field "CRn")"><Cn></a><text>, </text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-15] (field "CRm")"><Cm></a><text>, #</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field "op2")"><op2></a><text>{</text><text>, </text><a link="sa_xt" hover="64-bit optional general-purpose source register, default '11111' (field "Rt")"><Xt></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/sysops" mylink="aarch64.instrs.system.sysops" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode"><a link="AArch64.CheckSystemAccess.7" file="shared_pseudocode.xml" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)">AArch64.CheckSystemAccess</a>('01', op1, CRn, CRm, op2, Rt, L);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer sys_op0 = 1;
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integer sys_op1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1);
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integer sys_op2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2);
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integer sys_crn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRn);
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integer sys_crm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRm);
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boolean has_result = (L == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_op1"><op1></symbol>
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<account encodedin="op1">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_cn"><Cn></symbol>
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<account encodedin="CRn">
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<intro>
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<para>Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_cm"><Cm></symbol>
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<account encodedin="CRm">
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<intro>
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<para>Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_op2"><op2></symbol>
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<account encodedin="op2">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYS_CR_systeminstrs" symboldefcount="1">
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<symbol link="sa_xt"><Xt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/sysops" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if has_result then
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// No architecturally defined instructions here.
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<a link="AArch64.SysInstrWithResult.6" file="shared_pseudocode.xml" hover="function: AArch64.SysInstrWithResult(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstrWithResult</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t);
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else
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<a link="AArch64.SysInstr.6" file="shared_pseudocode.xml" hover="function: AArch64.SysInstr(integer op0, integer op1, integer crn, integer crm, integer op2, integer t)">AArch64.SysInstr</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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