mirror of
https://github.com/pound-emu/ballistic.git
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164 lines
8.4 KiB
XML
164 lines
8.4 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SYSP" title="SYSP -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYSP" />
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</docvars>
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<heading>SYSP</heading>
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<desc>
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<brief>
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<para>128-bit System instruction</para>
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</brief>
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<authored>
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<para>128-bit System instruction.</para>
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</authored>
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</desc>
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<alias_list howmany="1">
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<alias_list_intro>This instruction is used by the alias </alias_list_intro>
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<aliasref aliaspageid="TLBIP_SYSP" aliasfile="tlbip_sysp.xml" hover="TLB invalidate pair operation" punct=".">
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<text>TLBIP</text>
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<aliaspref>CRn == '100x' && <a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,CRn,CRm,op2) == <a link="Sys_TLBIP" file="shared_pseudocode.xml" hover="enumeration SystemOp128 {Sys_TLBIP, Sys_SYSP}">Sys_TLBIP</a></aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when the alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYSP" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="FEAT_SYSINSTR128" feature="FEAT_SYSINSTR128" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/system/sysops_128" tworows="1">
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<box hibit="31" width="10" settings="10">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" name="L" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="20" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="op1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="CRn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="CRm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="3" name="op2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SYSP_CR_syspairinstrs" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="system" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SYSP" />
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</docvars>
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<asmtemplate><text>SYSP #</text><a link="sa_op1" hover="3-bit unsigned immediate [0-6] (field "op1")"><op1></a><text>, </text><a link="sa_cn" hover="Name 'Cn', with 'n' [8-9] (field "CRn")"><Cn></a><text>, </text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-7] (field "CRm")"><Cm></a><text>, #</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field "op2")"><op2></a><text>{</text><text>, </text><a link="sa_xt1" hover="First 64-bit optional general-purpose source register, default '11111' (field "Rt")"><Xt1></a><text>, </text><a link="sa_xt2" hover="Second 64-bit optional general-purpose source register (field Rt)"><Xt2></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/sysops_128" mylink="aarch64.instrs.system.sysops_128" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSysInstr128.0" file="shared_pseudocode.xml" hover="function: boolean HaveSysInstr128()">HaveSysInstr128</a>() then UNDEFINED;
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if Rt<0> == '1' && Rt != '11111' then UNDEFINED;
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<a link="AArch64.CheckSystemAccess.7" file="shared_pseudocode.xml" hover="function: AArch64.CheckSystemAccess(bits(2) op0, bits(3) op1, bits(4) crn, bits(4) crm, bits(3) op2, bits(5) rt, bit read)">AArch64.CheckSystemAccess</a>('01', op1, CRn, CRm, op2, Rt, L);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer t2 = if t == 31 then 31 else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt)+1;
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integer sys_op0 = 1;
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integer sys_op1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op1);
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integer sys_op2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op2);
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integer sys_crn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRn);
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integer sys_crm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(CRm);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_op1"><op1></symbol>
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<account encodedin="op1">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 6, encoded in the "op1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_cn"><Cn></symbol>
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<account encodedin="CRn">
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<intro>
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<para>Is a name 'Cn', with 'n' in the range 8 to 9, encoded in the "CRn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_cm"><Cm></symbol>
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<account encodedin="CRm">
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<intro>
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<para>Is a name 'Cm', with 'm' in the range 0 to 7, encoded in the "CRm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_op2"><op2></symbol>
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<account encodedin="op2">
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<intro>
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<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_xt1"><Xt1></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the first optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SYSP_CR_syspairinstrs" symboldefcount="1">
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<symbol link="sa_xt2"><Xt2></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the second optional general-purpose source register, defaulting to '11111', encoded as "Rt" +1. Defaults to '11111' if "Rt" = '11111'.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/system/sysops_128" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.SysInstr128.7" file="shared_pseudocode.xml" hover="function: AArch64.SysInstr128(integer op0, integer op1, integer crn, integer crm, integer op2, integer t, integer t2)">AArch64.SysInstr128</a>(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, t2);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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