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https://github.com/pound-emu/ballistic.git
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210 lines
13 KiB
XML
210 lines
13 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CASH" title="CASH, CASAH, CASALH, CASLH -- A64" type="instruction">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<heading>CASH, CASAH, CASALH, CASLH</heading>
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<desc>
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<brief>
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<para>Compare and Swap halfword in memory</para>
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</brief>
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<authored>
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<para>Compare and Swap halfword in memory reads a 16-bit halfword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.</para>
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<list type="unordered">
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<listitem><content><instruction>CASAH</instruction> and <instruction>CASALH</instruction> load from memory with acquire semantics.</content></listitem>
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<listitem><content><instruction>CASLH</instruction> and <instruction>CASALH</instruction> store to memory with release semantics.</content></listitem>
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<listitem><content><instruction>CASH</instruction> has neither acquire nor release semantics.</content></listitem>
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</list>
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<para>For more information about memory ordering semantics, see <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>.</para>
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<para>For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
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<para>The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.</para>
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<para>If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <syntax><Ws></syntax>, is restored to the values held in the register before the instruction was executed.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="No offset" oneof="1" id="iclass_base_register" no_encodings="4" isa="A64">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.1" feature="FEAT_LSE" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/memory/atomicops/cas/single" tworows="1">
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<box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" width="7" settings="7">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" usename="1">
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<c></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rs" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" name="o0" usename="1">
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<c></c>
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</box>
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<box hibit="14" width="5" name="Rt2" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="CASAH_C32_comswap" oneofinclass="4" oneof="4" label="CASAH" bitdiffs="L == 1 && o0 == 0">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CASAH" />
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</docvars>
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<box hibit="22" width="1" name="L">
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<c>1</c>
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</box>
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<box hibit="15" width="1" name="o0">
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<c>0</c>
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</box>
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<asmtemplate><text>CASAH </text><a link="sa_ws" hover="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="CASALH_C32_comswap" oneofinclass="4" oneof="4" label="CASALH" bitdiffs="L == 1 && o0 == 1">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CASALH" />
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</docvars>
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<box hibit="22" width="1" name="L">
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<c>1</c>
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</box>
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<box hibit="15" width="1" name="o0">
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<c>1</c>
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</box>
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<asmtemplate><text>CASALH </text><a link="sa_ws" hover="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="CASH_C32_comswap" oneofinclass="4" oneof="4" label="CASH" bitdiffs="L == 0 && o0 == 0">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CASH" />
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</docvars>
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<box hibit="22" width="1" name="L">
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<c>0</c>
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</box>
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<box hibit="15" width="1" name="o0">
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<c>0</c>
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</box>
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<asmtemplate><text>CASH </text><a link="sa_ws" hover="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="CASLH_C32_comswap" oneofinclass="4" oneof="4" label="CASLH" bitdiffs="L == 0 && o0 == 1">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="CASLH" />
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</docvars>
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<box hibit="22" width="1" name="L">
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<c>0</c>
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</box>
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<box hibit="15" width="1" name="o0">
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<c>1</c>
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</box>
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<asmtemplate><text>CASLH </text><a link="sa_ws" hover="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a><text>, </text><a link="sa_wt" hover="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/atomicops/cas/single" mylink="aarch64.instrs.memory.atomicops.cas.single" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAtomicExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAtomicExt()">HaveAtomicExt</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
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integer datasize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer regsize = if datasize == 64 then 64 else 32;
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boolean acquire = L == '1';
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boolean release = o0 == '1';
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boolean tagchecked = n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CASH_C32_comswap, CASAH_C32_comswap, CASALH_C32_comswap, CASLH_C32_comswap" symboldefcount="1">
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<symbol link="sa_ws"><Ws></symbol>
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<account encodedin="Rs">
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<intro>
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<para>Is the 32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CASH_C32_comswap, CASAH_C32_comswap, CASALH_C32_comswap, CASLH_C32_comswap" symboldefcount="1">
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<symbol link="sa_wt"><Wt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CASH_C32_comswap, CASAH_C32_comswap, CASALH_C32_comswap, CASLH_C32_comswap" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/atomicops/cas/single" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
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bits(datasize) comparevalue;
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bits(datasize) newvalue;
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bits(datasize) data;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescAtomicOp.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</a>(<a link="MemAtomicOp_CAS" file="shared_pseudocode.xml" hover="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>, acquire, release, tagchecked);
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comparevalue = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[s, datasize];
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newvalue = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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data = <a link="impl-aarch64.MemAtomic.4" file="shared_pseudocode.xml" hover="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</a>(address, comparevalue, newvalue, accdesc);
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, regsize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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