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210 lines
11 KiB
XML
210 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="CMP_SUBS_addsub_shift" title="CMP (shifted register) -- A64" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<heading>CMP (shifted register)</heading>
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<desc>
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<brief>
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<para>Compare (shifted register)</para>
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</brief>
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<authored>
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<para>Compare (shifted register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<aliasto refiform="subs_addsub_shift.xml" iformid="SUBS_addsub_shift">SUBS (shifted register)</aliasto>
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<classes>
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<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="cond-setting" value="S" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" tworows="1">
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<box hibit="31" name="sf" usename="1">
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<c></c>
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</box>
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<box hibit="30" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="29" name="S" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="23" width="2" name="shift" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1" settings="5" psbits="xxxxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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</regdiagram>
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<encoding name="CMP_SUBS_32_addsub_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="32" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>0</c>
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</box>
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<asmtemplate><text>CMP </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="subs_addsub_shift.xml#SUBS_32_addsub_shift">SUBS</a><text> WZR, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="CMP_SUBS_64_addsub_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="CMP" />
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<docvar key="cond-setting" value="S" />
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<docvar key="datatype" value="64" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="31" width="1" name="sf">
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<c>1</c>
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</box>
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<asmtemplate><text>CMP </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="subs_addsub_shift.xml#SUBS_64_addsub_shift">SUBS</a><text> XZR, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="CMP_SUBS_32_addsub_shift" symboldefcount="1">
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<symbol link="sa_wn"><Wn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_32_addsub_shift" symboldefcount="1">
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<symbol link="sa_wm"><Wm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_64_addsub_shift" symboldefcount="1">
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<symbol link="sa_xn"><Xn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_64_addsub_shift" symboldefcount="1">
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<symbol link="sa_xm"><Xm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_32_addsub_shift, CMP_SUBS_64_addsub_shift" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="shift">
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<intro>Is the optional shift type to be applied to the second source operand, defaulting to LSL and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">shift</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">LSL</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">LSR</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">ASR</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="CMP_SUBS_32_addsub_shift" symboldefcount="1">
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<symbol link="sa_amount"><amount></symbol>
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<account encodedin="imm6">
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<docvars>
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<docvar key="datatype" value="32" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="CMP_SUBS_64_addsub_shift" symboldefcount="2">
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<symbol link="sa_amount_1"><amount></symbol>
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<account encodedin="imm6">
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<docvars>
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<docvar key="datatype" value="64" />
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</docvars>
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<intro>
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<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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