mirror of
https://github.com/pound-emu/ballistic.git
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226 lines
12 KiB
XML
226 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="ext_z_zi" title="EXT" type="instruction">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="EXT" />
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</docvars>
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<heading>EXT</heading>
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<desc>
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<brief>Extract vector from pair of vectors</brief>
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<description>
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<para>Copy the indexed byte up to the last byte of the first source vector to the bottom of the result vector, then fill the remainder of the result starting from the first byte of the second source vector. The result is placed destructively in the destination and first source vector, or constructively in the destination vector. This instruction is unpredicated.</para>
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<para>An index that is greater than or equal to the vector length in bytes is treated as zero, resulting in the first source vector being copied to the result unchanged.</para>
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<para>The Destructive encoding of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is UNPREDICTABLE: The MOVPRFX instruction must be unpredicated. The MOVPRFX instruction must specify the same destination register as this instruction. The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</para>
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</description>
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<status>Green</status>
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<predicated>False</predicated>
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<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
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<takes_movprfx>False</takes_movprfx>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_sve_const">Constructive</a>
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<txt> and </txt>
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<a href="#iclass_sve_dest">Destructive</a>
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</classesintro>
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<iclass name="Constructive" oneof="2" id="iclass_sve_const" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="EXT" />
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<docvar key="sve-dest_const" value="sve-const" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="EXT-Z.ZI-Con">
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<box hibit="31" width="11" settings="11">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="imm8h" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="imm8l" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ext_z_zi_con" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="EXT" />
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<docvar key="sve-dest_const" value="sve-const" />
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</docvars>
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<asmtemplate><text>EXT </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.B, </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field "Zn")"><Zn1></a><text>.B, </text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field "Zn")"><Zn2></a><text>.B </text><text>}</text><text>, #</text><a link="sa_imm" hover="Unsigned immediate operand [0-255] (field "imm8h:imm8l")"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="EXT-Z.ZI-Con" mylink="EXT-Z.ZI-Con" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8;
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integer dst = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
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integer s1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
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integer s2 = (s1 + 1) MOD 32;
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integer position = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8h:imm8l);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Destructive" oneof="2" id="iclass_sve_dest" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="EXT" />
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<docvar key="sve-dest_const" value="sve-dest" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="EXT-Z.ZI-Des">
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<box hibit="31" width="11" settings="11">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="imm8h" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="12" width="3" name="imm8l" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="9" width="5" name="Zm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Zdn" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="ext_z_zi_des" oneofinclass="1" oneof="2" label="">
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<docvars>
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<docvar key="instr-class" value="sve" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="EXT" />
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<docvar key="sve-dest_const" value="sve-dest" />
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</docvars>
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<asmtemplate><text>EXT </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.B, #</text><a link="sa_imm" hover="Unsigned immediate operand [0-255] (field "imm8h:imm8l")"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="EXT-Z.ZI-Des" mylink="EXT-Z.ZI-Des" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
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constant integer esize = 8;
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integer dst = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
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integer s1 = dst;
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integer s2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
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integer position = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8h:imm8l);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="ext_z_zi_con" symboldefcount="1">
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<symbol link="sa_zd"><Zd></symbol>
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<account encodedin="Zd">
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<intro>
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<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ext_z_zi_con" symboldefcount="1">
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<symbol link="sa_zn1"><Zn1></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ext_z_zi_con" symboldefcount="1">
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<symbol link="sa_zn2"><Zn2></symbol>
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<account encodedin="Zn">
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<intro>
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<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded in the "Zn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ext_z_zi_des" symboldefcount="1">
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<symbol link="sa_zdn"><Zdn></symbol>
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<account encodedin="Zdn">
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<intro>
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<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ext_z_zi_des" symboldefcount="1">
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<symbol link="sa_zm"><Zm></symbol>
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<account encodedin="Zm">
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<intro>
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<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="ext_z_zi_con, ext_z_zi_des" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm8h:imm8l">
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<intro>
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<para>Is the unsigned immediate operand, in the range 0 to 255, encoded in the "imm8h:imm8l" fields.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="EXT-Z.ZI-Con" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
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constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
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constant integer PL = VL DIV 8;
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constant integer elements = VL DIV esize;
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bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[s1, VL];
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bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[s2, VL];
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bits(VL) result;
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if position >= elements then
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position = 0;
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position = position << 3;
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bits(VL*2) concat = operand2 : operand1;
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result = concat<(position+VL)-1:position>;
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<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dst, VL] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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