mirror of
https://github.com/pound-emu/ballistic.git
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560 lines
29 KiB
XML
560 lines
29 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FCMEQ_advsimd_zero" title="FCMEQ (zero) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<heading>FCMEQ (zero)</heading>
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<desc>
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<brief>
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<para>Floating-point Compare Equal to zero (vector)</para>
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</brief>
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<authored>
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<para>Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.</para>
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<para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from 4 classes:</txt>
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<a href="#iclass_sisd_half">Scalar half precision</a>
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<txt>, </txt>
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<a href="#iclass_sisd_single_and_double">Scalar single-precision and double-precision</a>
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<txt>, </txt>
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<a href="#iclass_simd_half">Vector half precision</a>
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<txt> and </txt>
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<a href="#iclass_simd_single_and_double">Vector single-precision and double-precision</a>
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</classesintro>
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<iclass name="Scalar half precision" oneof="4" id="iclass_sisd_half" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/cmp/fp16/bulk/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="a" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="4" name="opcode[4:1]" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="12" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FCMEQ_asisdmiscfp16_FZ" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-half" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<asmtemplate><text>FCMEQ </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_hn" hover="16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, #0.0</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/cmp/fp16/bulk/sisd" mylink="aarch64.instrs.vector.arithmetic.unary.cmp.fp16.bulk.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 16;
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integer datasize = esize;
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integer elements = 1;
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<a link="CompareOp" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp</a> comparison;
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case op:U of
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when '00' comparison = <a link="CompareOp_GT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</a>;
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when '01' comparison = <a link="CompareOp_GE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</a>;
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when '10' comparison = <a link="CompareOp_EQ" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a>;
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when '11' comparison = <a link="CompareOp_LE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Scalar single-precision and double-precision" oneof="4" id="iclass_sisd_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/cmp/float/bulk/sisd" tworows="1">
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<box hibit="31" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="size[1]" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="4" name="opcode[4:1]" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="12" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FCMEQ_asisdmisc_FZ" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="sisd-single-and-double" />
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<docvar key="advsimd-type" value="sisd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<asmtemplate><text>FCMEQ </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "sz") [D,S]"><V></a><a link="sa_n" hover="SIMD&FP source register number (field "Rn")"><n></a><text>, #0.0</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/cmp/float/bulk/sisd" mylink="aarch64.instrs.vector.arithmetic.unary.cmp.float.bulk.sisd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
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integer datasize = esize;
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integer elements = 1;
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<a link="CompareOp" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp</a> comparison;
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case op:U of
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when '00' comparison = <a link="CompareOp_GT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</a>;
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when '01' comparison = <a link="CompareOp_GE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</a>;
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when '10' comparison = <a link="CompareOp_EQ" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a>;
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when '11' comparison = <a link="CompareOp_LE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector half precision" oneof="4" id="iclass_simd_half" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-half" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/cmp/fp16/bulk/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="a" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="6" settings="6">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="4" name="opcode[4:1]" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="12" name="op" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FCMEQ_asimdmiscfp16_FZ" oneofinclass="1" oneof="4" label="">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-half" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<asmtemplate><text>FCMEQ </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field "Q") [4H,8H]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t_1" hover="Arrangement specifier (field "Q") [4H,8H]"><T></a><text>, #0.0</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/cmp/fp16/bulk/simd" mylink="aarch64.instrs.vector.arithmetic.unary.cmp.fp16.bulk.simd" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer esize = 16;
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV esize;
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<a link="CompareOp" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp</a> comparison;
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case op:U of
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when '00' comparison = <a link="CompareOp_GT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</a>;
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when '01' comparison = <a link="CompareOp_GE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</a>;
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when '10' comparison = <a link="CompareOp_EQ" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a>;
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when '11' comparison = <a link="CompareOp_LE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</a>;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Vector single-precision and double-precision" oneof="4" id="iclass_simd_single_and_double" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-datatype" value="simd-single-and-double" />
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<docvar key="advsimd-type" value="simd" />
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<docvar key="datatype" value="single-and-double" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FCMEQ" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/cmp/float/bulk/simd" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="size[1]" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="4" name="opcode[4:1]" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1" settings="1" psbits="x">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="FCMEQ_asimdmisc_FZ" oneofinclass="1" oneof="4" label="">
|
|
<docvars>
|
|
<docvar key="advsimd-datatype" value="simd-single-and-double" />
|
|
<docvar key="advsimd-type" value="simd" />
|
|
<docvar key="datatype" value="single-and-double" />
|
|
<docvar key="instr-class" value="advsimd" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="FCMEQ" />
|
|
</docvars>
|
|
<asmtemplate><text>FCMEQ </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "sz:Q") [2D,2S,4S]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "sz:Q") [2D,2S,4S]"><T></a><text>, #0.0</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/unary/cmp/float/bulk/simd" mylink="aarch64.instrs.vector.arithmetic.unary.cmp.float.bulk.simd" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
|
|
if sz:Q == '10' then UNDEFINED;
|
|
integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
|
integer datasize = if Q == '1' then 128 else 64;
|
|
integer elements = datasize DIV esize;
|
|
|
|
<a link="CompareOp" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp</a> comparison;
|
|
case op:U of
|
|
when '00' comparison = <a link="CompareOp_GT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</a>;
|
|
when '01' comparison = <a link="CompareOp_GE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</a>;
|
|
when '10' comparison = <a link="CompareOp_EQ" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a>;
|
|
when '11' comparison = <a link="CompareOp_LE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</a>;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="FCMEQ_asisdmiscfp16_FZ" symboldefcount="1">
|
|
<symbol link="sa_hd"><Hd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asisdmiscfp16_FZ" symboldefcount="1">
|
|
<symbol link="sa_hn"><Hn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asisdmisc_FZ" symboldefcount="1">
|
|
<symbol link="sa_v"><V></symbol>
|
|
<definition encodedin="sz">
|
|
<intro>Is a width specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><V></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asisdmisc_FZ" symboldefcount="1">
|
|
<symbol link="sa_d"><d></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asisdmisc_FZ" symboldefcount="1">
|
|
<symbol link="sa_n"><n></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the number of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asimdmisc_FZ, FCMEQ_asimdmiscfp16_FZ" symboldefcount="1">
|
|
<symbol link="sa_vd"><Vd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asimdmiscfp16_FZ" symboldefcount="1">
|
|
<symbol link="sa_t_1"><T></symbol>
|
|
<definition encodedin="Q">
|
|
<intro>For the half-precision variant: is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">4H</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">8H</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asimdmisc_FZ" symboldefcount="2">
|
|
<symbol link="sa_t"><T></symbol>
|
|
<definition encodedin="sz:Q">
|
|
<intro>For the single-precision and double-precision variant: is an arrangement specifier, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="bitfield">Q</entry>
|
|
<entry class="symbol"><T></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">2S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">4S</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">2D</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="FCMEQ_asimdmisc_FZ, FCMEQ_asimdmiscfp16_FZ" symboldefcount="1">
|
|
<symbol link="sa_vn"><Vn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/vector/arithmetic/unary/cmp/fp16/bulk/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
|
bits(datasize) result;
|
|
bits(esize) zero = <a link="impl-shared.FPZero.2" file="shared_pseudocode.xml" hover="function: bits(N) FPZero(bit sign, integer N)">FPZero</a>('0', esize);
|
|
bits(esize) element;
|
|
boolean test_passed;
|
|
|
|
for e = 0 to elements-1
|
|
element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
|
case comparison of
|
|
when <a link="CompareOp_GT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GT</a> test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(element, zero, FPCR[]);
|
|
when <a link="CompareOp_GE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_GE</a> test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(element, zero, FPCR[]);
|
|
when <a link="CompareOp_EQ" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_EQ</a> test_passed = <a link="impl-shared.FPCompareEQ.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareEQ(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareEQ</a>(element, zero, FPCR[]);
|
|
when <a link="CompareOp_LE" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LE</a> test_passed = <a link="impl-shared.FPCompareGE.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGE(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGE</a>(zero, element, FPCR[]);
|
|
when <a link="CompareOp_LT" file="shared_pseudocode.xml" hover="enumeration CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}">CompareOp_LT</a> test_passed = <a link="impl-shared.FPCompareGT.3" file="shared_pseudocode.xml" hover="function: boolean FPCompareGT(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPCompareGT</a>(zero, element, FPCR[]);
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = if test_passed then <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize) else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(esize);
|
|
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|