mirror of
https://github.com/pound-emu/ballistic.git
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443 lines
25 KiB
XML
443 lines
25 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LD4R_advsimd" title="LD4R -- A64" type="instruction">
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<docvars>
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<heading>LD4R</heading>
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<desc>
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<brief>
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<para>Load single 4-element structure and Replicate to all lanes of four registers</para>
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</brief>
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<authored>
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<para>Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from 2 classes:</txt>
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<a href="#iclass_as_no_post_index">No offset</a>
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<txt> and </txt>
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<a href="#iclass_as_post_index">Post-index</a>
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</classesintro>
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<iclass name="No offset" oneof="2" id="iclass_as_no_post_index" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="as-structure-post-index" value="as-no-post-index" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/vector/single/no-wb" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" width="7" settings="7">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="21" name="R" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="20" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" name="o2" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="15" width="3" name="opcode" usename="1" settings="3" psbits="xxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="12" name="S" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="LD4R_asisdlso_R4" oneofinclass="1" oneof="3" label="">
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<docvars>
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="as-structure-post-index" value="as-no-post-index" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<asmtemplate><text>LD4R </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&FP register to be transferred (field "Rt")"><Vt></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt2" hover="Second SIMD&FP register to be transferred (field Rt)"><Vt2></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt3" hover="Third SIMD&FP register to be transferred (field Rt)"><Vt3></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt4" hover="Fourth SIMD&FP register to be transferred (field Rt)"><Vt4></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text> </text><text>}</text><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="aarch64.instrs.memory.vector.single.no-wb" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = integer UNKNOWN;
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boolean wback = FALSE;
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boolean nontemporal = FALSE;
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boolean tagchecked = wback || n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="Post-index" oneof="2" id="iclass_as_post_index" no_encodings="2" isa="A64">
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<docvars>
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="as-structure-post-index" value="as-post-index" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/vector/single/post-inc" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" width="7" settings="7">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="21" name="R" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" name="opcode" usename="1" settings="3" psbits="xxx">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="12" name="S" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="11" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="LD4R_asisdlsop_R4_i" oneofinclass="2" oneof="3" label="Immediate offset" bitdiffs="Rm == 11111">
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<docvars>
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<docvar key="as-structure-index-source" value="post-index-imm" />
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="as-structure-post-index" value="as-post-index" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="ld1-single-labels" value="to-all-lanes-post-index-imm" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<box hibit="20" width="5" name="Rm">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>LD4R </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&FP register to be transferred (field "Rt")"><Vt></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt2" hover="Second SIMD&FP register to be transferred (field Rt)"><Vt2></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt3" hover="Third SIMD&FP register to be transferred (field Rt)"><Vt3></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt4" hover="Fourth SIMD&FP register to be transferred (field Rt)"><Vt4></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text> </text><text>}</text><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], </text><a link="sa_imm" hover="Post-index immediate offset (field "size") [#4,#8,#16,#32]"><imm></a></asmtemplate>
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</encoding>
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<encoding name="LD4R_asisdlsop_RX4_r" oneofinclass="2" oneof="3" label="Register offset" bitdiffs="Rm != 11111">
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<docvars>
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<docvar key="as-structure-index-source" value="post-index-reg" />
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<docvar key="as-structure-org" value="to-all-lanes" />
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<docvar key="as-structure-post-index" value="as-post-index" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="ld1-single-labels" value="to-all-lanes-post-index-reg" />
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<docvar key="mnemonic" value="LD4R" />
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</docvars>
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<box hibit="20" width="5" name="Rm">
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<c>N</c>
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<c>N</c>
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<c>N</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>LD4R </text><text>{</text><text> </text><a link="sa_vt" hover="First or only SIMD&FP register to be transferred (field "Rt")"><Vt></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt2" hover="Second SIMD&FP register to be transferred (field Rt)"><Vt2></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt3" hover="Third SIMD&FP register to be transferred (field Rt)"><Vt3></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vt4" hover="Fourth SIMD&FP register to be transferred (field Rt)"><Vt4></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [1D,2D,2S,4H,4S,8B,8H,16B]"><T></a><text> </text><text>}</text><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>], </text><a link="sa_xm" hover="64-bit general-purpose post-index register, excluding XZR (field "Rm")"><Xm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/vector/single/post-inc" mylink="aarch64.instrs.memory.vector.single.post-inc" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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boolean wback = TRUE;
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boolean nontemporal = FALSE;
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boolean tagchecked = wback || n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_vt"><Vt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">1D</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">2D</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_vt2"><Vt2></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_vt3"><Vt3></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_vt4"><Vt4></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LD4R_asisdlso_R4, LD4R_asisdlsop_R4_i, LD4R_asisdlsop_RX4_r" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LD4R_asisdlsop_R4_i" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<definition encodedin="size">
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<intro>Is the post-index immediate offset, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><imm></entry>
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</row>
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</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">#4</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">#8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">#16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">#32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="LD4R_asisdlsop_RX4_r" symboldefcount="1">
|
|
<symbol link="sa_xm"><Xm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
|
|
<pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer init_scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opcode<2:1>);
|
|
integer scale = init_scale;
|
|
integer selem = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opcode<0>:R) + 1;
|
|
boolean replicate = FALSE;
|
|
integer index;
|
|
|
|
case scale of
|
|
when 3
|
|
// load and replicate
|
|
if L == '0' || S == '1' then UNDEFINED;
|
|
scale = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
|
replicate = TRUE;
|
|
when 0
|
|
index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S:size); // B[0-15]
|
|
when 1
|
|
if size<0> == '1' then UNDEFINED;
|
|
index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S:size<1>); // H[0-7]
|
|
when 2
|
|
if size<1> == '1' then UNDEFINED;
|
|
if size<0> == '0' then
|
|
index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q:S); // S[0-3]
|
|
else
|
|
if S == '1' then UNDEFINED;
|
|
index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q); // D[0-1]
|
|
scale = 3;
|
|
|
|
<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
|
|
integer datasize = if Q == '1' then 128 else 64;
|
|
integer esize = 8 << scale;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/memory/vector/single/no-wb" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
|
|
|
bits(64) address;
|
|
bits(64) offs;
|
|
bits(128) rval;
|
|
bits(esize) element;
|
|
constant integer ebytes = esize DIV 8;
|
|
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);
|
|
|
|
if n == 31 then
|
|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
|
|
else
|
|
address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
|
|
offs = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(64);
|
|
if replicate then
|
|
// load and replicate to all elements
|
|
for s = 0 to selem-1
|
|
element = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + offs, ebytes, accdesc];
|
|
// replicate to fill 128- or 64-bit register
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element, datasize DIV esize);
|
|
offs = offs + ebytes;
|
|
t = (t + 1) MOD 32;
|
|
else
|
|
// load/store one element per register
|
|
for s = 0 to selem-1
|
|
rval = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t, 128];
|
|
if memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
|
|
// insert into one lane of 128-bit register
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[rval, index, esize] = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + offs, ebytes, accdesc];
|
|
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, 128] = rval;
|
|
else // memop == MemOp_STORE
|
|
// extract from one lane of 128-bit register
|
|
Mem[address + offs, ebytes, accdesc] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, index, esize];
|
|
offs = offs + ebytes;
|
|
t = (t + 1) MOD 32;
|
|
|
|
if wback then
|
|
if m != 31 then
|
|
offs = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
|
|
if n == 31 then
|
|
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address + offs;
|
|
else
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address + offs;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|