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https://github.com/pound-emu/ballistic.git
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180 lines
10 KiB
XML
180 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDARB" title="LDARB -- A64" type="instruction">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="address-form-reg-type" value="base-register-32-reg" />
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<docvar key="atomic-ops" value="LDARB-32-reg" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDARB" />
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<docvar key="reg-type" value="32-reg" />
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</docvars>
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<heading>LDARB</heading>
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<desc>
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<brief>
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<para>Load-Acquire Register Byte</para>
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</brief>
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<authored>
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<para>Load-Acquire Register Byte derives an address from a base register value, loads a byte from memory, zero-extends it and writes it to a register. The instruction also has memory ordering semantics as described in <xref linkend="BEIHCHEF">Load-Acquire, Store-Release</xref>. For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
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<note>
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<para>For this instruction, if the destination is WZR/XZR, it is impossible for software to observe the presence of the acquire semantic other than its effect on the arrival at endpoints.</para>
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</note>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="No offset" oneof="1" id="iclass_base_register" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="address-form-reg-type" value="base-register-32-reg" />
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<docvar key="atomic-ops" value="LDARB-32-reg" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDARB" />
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<docvar key="reg-type" value="32-reg" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/ordered" tworows="1">
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<box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="29" width="6" settings="6">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="o2" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="21" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rs" usename="1" settings="5" psbits="xxxxx">
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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</box>
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<box hibit="15" name="o0" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="14" width="5" name="Rt2" usename="1" settings="5" psbits="xxxxx">
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="LDARB_LR32_ldstord" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="address-form" value="base-register" />
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<docvar key="address-form-reg-type" value="base-register-32-reg" />
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<docvar key="atomic-ops" value="LDARB-32-reg" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDARB" />
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<docvar key="reg-type" value="32-reg" />
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</docvars>
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<asmtemplate><text>LDARB </text><a link="sa_wt" hover="32-bit general-purpose register to be transferred (field "Rt")"><Wt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{,#0}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/ordered" mylink="aarch64.instrs.memory.ordered" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2); // ignored by load/store single register
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integer s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs); // ignored by all loads and store-release
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boolean wback = FALSE;
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integer offset = 0;
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boolean rt_unknown = FALSE;
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limitedordered = o0 == '0';
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<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
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integer elsize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer regsize = if elsize == 64 then 64 else 32;
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integer datasize = elsize;
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boolean tagchecked = n != 31;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDARB_LR32_ldstord" symboldefcount="1">
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<symbol link="sa_wt"><Wt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDARB_LR32_ldstord" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/ordered" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
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bits(datasize) data;
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constant integer dbytes = datasize DIV 8;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc;
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if limitedordered then
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accdesc = <a link="impl-shared.CreateAccDescLOR.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLOR(MemOp memop, boolean tagchecked)">CreateAccDescLOR</a>(memop, tagchecked);
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else
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accdesc = <a link="impl-shared.CreateAccDescAcqRel.2" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescAcqRel(MemOp memop, boolean tagchecked)">CreateAccDescAcqRel</a>(memop, tagchecked);
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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case memop of
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when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
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address = address + offset;
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if rt_unknown then
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data = bits(datasize) UNKNOWN;
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else
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data = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
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Mem[address, dbytes, accdesc] = data;
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if wback then
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if n == 31 then
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<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
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else
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;
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when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
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data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, dbytes, accdesc];
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, regsize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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