mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
134 lines
7.9 KiB
XML
134 lines
7.9 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="LDG" title="LDG -- A64" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="LDG" />
|
|
</docvars>
|
|
<heading>LDG</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Load Allocation Tag</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Load Allocation Tag loads an Allocation Tag from a memory address, generates a Logical Address Tag from the Allocation Tag and merges it into the destination register. The address used for the load is calculated from the base register and an immediate signed offset scaled by the Tag granule.</para>
|
|
</authored>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
|
|
<docvars>
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="LDG" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
|
|
</arch_variants>
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcgettag">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="opc<1>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="opc<0>" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" name="op2<1>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op2<0>" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Xn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Xt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="LDG_64Loffset_ldsttags" oneofinclass="1" oneof="1" label="">
|
|
<docvars>
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A64" />
|
|
<docvar key="mnemonic" value="LDG" />
|
|
</docvars>
|
|
<asmtemplate><text>LDG </text><a link="sa_xt" hover="64-bit general-purpose destination register (field "Xt")"><Xt></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Xn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_simm" hover="Optional signed immediate offset, multiple of 16 [-4096-4080], default 0 (field "imm9")"><simm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/integer/tags/mcgettag" mylink="aarch64.instrs.integer.tags.mcgettag" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
|
|
integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xt);
|
|
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
|
|
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm9, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="LDG_64Loffset_ldsttags" symboldefcount="1">
|
|
<symbol link="sa_xt"><Xt></symbol>
|
|
<account encodedin="Xt">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Xt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDG_64Loffset_ldsttags" symboldefcount="1">
|
|
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
|
<account encodedin="Xn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDG_64Loffset_ldsttags" symboldefcount="1">
|
|
<symbol link="sa_simm"><simm></symbol>
|
|
<account encodedin="imm9">
|
|
<intro>
|
|
<para>Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch64/instrs/integer/tags/mcgettag" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address;
|
|
bits(4) tag;
|
|
|
|
if n == 31 then
|
|
<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
|
address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
|
|
else
|
|
address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
|
|
|
address = address + offset;
|
|
address = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(address, <a link="TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer TAG_GRANULE = 1 << LOG2_TAG_GRANULE">TAG_GRANULE</a>);
|
|
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescLDGSTG.1" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescLDGSTG(MemOp memop)">CreateAccDescLDGSTG</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>);
|
|
tag = <a link="AArch64.MemTag.read.2" file="shared_pseudocode.xml" hover="accessor: bits(4) AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in]">AArch64.MemTag</a>[address, accdesc];
|
|
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, 64] = AArch64.AddressWithAllocationTag(X[t, 64], tag);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|