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https://github.com/pound-emu/ballistic.git
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301 lines
26 KiB
XML
301 lines
26 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDNP_fpsimd" title="LDNP (SIMD&FP) -- A64" type="instruction">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<heading>LDNP (SIMD&FP)</heading>
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<desc>
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<brief>
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<para>Load Pair of SIMD&FP registers, with Non-temporal hint</para>
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</brief>
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<authored>
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<para>Load Pair of SIMD&FP registers, with Non-temporal hint. This instruction loads a pair of SIMD&FP registers from memory, issuing a hint to the memory system that the access is non-temporal. The address that is used for the load is calculated from a base register value and an optional immediate offset.</para>
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<para>For information about non-temporal pair instructions, see <xref linkend="BABJADHH">Load/Store SIMD and Floating-point Non-temporal pair</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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<encodingnotes>
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<para>For information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CHDHFEFI">LDNP (SIMD&FP)</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Signed offset" oneof="1" id="iclass_signed_scaled_offset" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNP" />
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<docvar key="offset-type" value="off7s_s" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/pair/simdfp/no-alloc" tworows="1">
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<box hibit="31" width="2" name="opc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="L" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="21" width="7" name="imm7" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="14" width="5" name="Rt2" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="LDNP_S_ldstnapair_offs" oneofinclass="3" oneof="3" label="32-bit" bitdiffs="opc == 00">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-words" />
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<docvar key="atomic-ops" value="LDNP-pair-words" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-words" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>LDNP </text><a link="sa_st1" hover="First 32-bit SIMD&FP register to be transferred (field "Rt")"><St1></a><text>, </text><a link="sa_st2" hover="Second 32-bit SIMD&FP register to be transferred (field "Rt2")"><St2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm_2" hover="Optional signed immediate byte offset, multiple of 4 [-256-252], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="LDNP_D_ldstnapair_offs" oneofinclass="3" oneof="3" label="64-bit" bitdiffs="opc == 01">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-doublewords" />
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<docvar key="atomic-ops" value="LDNP-pair-doublewords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-doublewords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>LDNP </text><a link="sa_dt1" hover="First 64-bit SIMD&FP register to be transferred (field "Rt")"><Dt1></a><text>, </text><a link="sa_dt2" hover="Second 64-bit SIMD&FP register to be transferred (field "Rt2")"><Dt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm" hover="Optional signed immediate byte offset, multiple of 8 [-512-504], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="LDNP_Q_ldstnapair_offs" oneofinclass="3" oneof="3" label="128-bit" bitdiffs="opc == 10">
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<docvars>
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<docvar key="address-form" value="signed-scaled-offset" />
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-quadwords" />
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<docvar key="atomic-ops" value="LDNP-pair-quadwords" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="LDNP" />
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<docvar key="offset-type" value="off7s_s" />
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<docvar key="reg-type" value="pair-quadwords" />
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</docvars>
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<box hibit="31" width="2" name="opc">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>LDNP </text><a link="sa_qt1" hover="First 128-bit SIMD&FP register to be transferred (field "Rt")"><Qt1></a><text>, </text><a link="sa_qt2" hover="Second 128-bit SIMD&FP register to be transferred (field "Rt2")"><Qt2></a><text>, [</text><a link="sa_xn_sp" hover="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a><text>{</text><text>, #</text><a link="sa_imm_1" hover="Optional signed immediate byte offset, multiple of 16 [-1024-1008], default 0 (field "imm7")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/pair/simdfp/no-alloc" mylink="aarch64.instrs.memory.pair.simdfp.no-alloc" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean wback = FALSE;
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boolean postindex = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDNP_D_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_dt1"><Dt1></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_D_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_dt2"><Dt2></symbol>
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<account encodedin="Rt2">
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<intro>
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<para>Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_Q_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_qt1"><Qt1></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_Q_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_qt2"><Qt2></symbol>
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<account encodedin="Rt2">
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<intro>
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<para>Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_S_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_st1"><St1></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_S_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_st2"><St2></symbol>
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<account encodedin="Rt2">
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<intro>
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<para>Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_D_ldstnapair_offs, LDNP_Q_ldstnapair_offs, LDNP_S_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_xn_sp"><Xn|SP></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_S_ldstnapair_offs" symboldefcount="1">
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<symbol link="sa_imm_2"><imm></symbol>
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<account encodedin="imm7">
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<docvars>
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-words" />
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<docvar key="atomic-ops" value="LDNP-pair-words" />
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<docvar key="reg-type" value="pair-words" />
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</docvars>
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<intro>
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<para>For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_D_ldstnapair_offs" symboldefcount="2">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm7">
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<docvars>
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-doublewords" />
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<docvar key="atomic-ops" value="LDNP-pair-doublewords" />
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<docvar key="reg-type" value="pair-doublewords" />
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</docvars>
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<intro>
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<para>For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDNP_Q_ldstnapair_offs" symboldefcount="3">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="imm7">
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<docvars>
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<docvar key="address-form-reg-type" value="signed-scaled-offset-pair-quadwords" />
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<docvar key="atomic-ops" value="LDNP-pair-quadwords" />
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<docvar key="reg-type" value="pair-quadwords" />
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</docvars>
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<intro>
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<para>For the 128-bit variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/pair/simdfp/no-alloc" mylink="postdecode" enclabels="" sections="1" secttype="Shared Decode">
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<pstext mayhavelinks="1" section="Postdecode" rep_section="postdecode">integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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integer t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);
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boolean nontemporal = TRUE;
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<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
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if opc == '11' then UNDEFINED;
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integer scale = 2 + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc);
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integer datasize = 8 << scale;
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bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm7, 64), scale);
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boolean tagchecked = wback || n != 31;
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boolean rt_unknown = FALSE;
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if memop == <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> && t == t2 then
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<a link="Constraint" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint</a> c = <a link="impl-shared.ConstrainUnpredictable.1" file="shared_pseudocode.xml" hover="function: Constraint ConstrainUnpredictable(Unpredictable which)">ConstrainUnpredictable</a>(<a link="Unpredictable_LDPOVERLAP" file="shared_pseudocode.xml" hover="enumeration Unpredictable { Unpredictable_VMSR, Unpredictable_WBOVERLAPLD, Unpredictable_WBOVERLAPST, Unpredictable_LDPOVERLAP, Unpredictable_BASEOVERLAP, Unpredictable_DATAOVERLAP, Unpredictable_DEVPAGE2, Unpredictable_INSTRDEVICE, Unpredictable_RESCPACR, Unpredictable_RESMAIR, Unpredictable_S1CTAGGED, Unpredictable_S2RESMEMATTR, Unpredictable_RESTEXCB, Unpredictable_RESPRRR, Unpredictable_RESDACR, Unpredictable_RESVTCRS, Unpredictable_RESTnSZ, Unpredictable_RESTCF, Unpredictable_DEVICETAGSTORE, Unpredictable_OORTnSZ, Unpredictable_LARGEIPA, Unpredictable_ESRCONDPASS, Unpredictable_ILZEROIT, Unpredictable_ILZEROT, Unpredictable_BPVECTORCATCHPRI, Unpredictable_VCMATCHHALF, Unpredictable_VCMATCHDAPA, Unpredictable_WPMASKANDBAS, Unpredictable_WPBASCONTIGUOUS, Unpredictable_RESWPMASK, Unpredictable_WPMASKEDBITS, Unpredictable_RESBPWPCTRL, Unpredictable_BPNOTIMPL, Unpredictable_RESBPTYPE, Unpredictable_BPNOTCTXCMP, Unpredictable_BPMATCHHALF, Unpredictable_BPMISMATCHHALF, Unpredictable_RESTARTALIGNPC, Unpredictable_RESTARTZEROUPPERPC, Unpredictable_ZEROUPPER, Unpredictable_ERETZEROUPPERPC, Unpredictable_A32FORCEALIGNPC, Unpredictable_SMD, Unpredictable_NONFAULT, Unpredictable_SVEZEROUPPER, Unpredictable_SVELDNFDATA, Unpredictable_SVELDNFZERO, Unpredictable_CHECKSPNONEACTIVE, Unpredictable_SMEZEROUPPER, Unpredictable_NVNV1, Unpredictable_Shareability, Unpredictable_AFUPDATE, Unpredictable_DBUPDATE, Unpredictable_IESBinDebug, Unpredictable_BADPMSFCR, Unpredictable_ZEROBTYPE, Unpredictable_EL2TIMESTAMP, Unpredictable_EL1TIMESTAMP, Unpredictable_RESERVEDNSxB, Unpredictable_WFxTDEBUG, Unpredictable_LS64UNSUPPORTED, Unpredictable_MISALIGNEDATOMIC, Unpredictable_CLEARERRITEZERO, Unpredictable_ALUEXCEPTIONRETURN, Unpredictable_IGNORETRAPINDEBUG, Unpredictable_DBGxVR_RESS, Unpredictable_PMUEVENTCOUNTER, Unpredictable_PMSCR_PCT, Unpredictable_CounterReservedForEL2, Unpredictable_BRBFILTRATE, Unpredictable_MOPSOVERLAP31, Unpredictable_STOREONLYTAGCHECKEDCAS, Unpredictable_RESTC }">Unpredictable_LDPOVERLAP</a>);
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assert c IN {<a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a>, <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a>, <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a>};
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case c of
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when <a link="Constraint_UNKNOWN" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNKNOWN</a> rt_unknown = TRUE; // result is UNKNOWN
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when <a link="Constraint_UNDEF" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_UNDEF</a> UNDEFINED;
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when <a link="Constraint_NOP" file="shared_pseudocode.xml" hover="enumeration Constraint { Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_UNDEFEL0, Constraint_NOP, Constraint_TRUE, Constraint_FALSE, Constraint_DISABLED, Constraint_UNCOND, Constraint_COND, Constraint_ADDITIONAL_DECODE, Constraint_WBSUPPRESS, Constraint_FAULT, Constraint_LIMITED_ATOMICITY, Constraint_NVNV1_00, Constraint_NVNV1_01, Constraint_NVNV1_11, Constraint_EL1TIMESTAMP, Constraint_EL2TIMESTAMP, Constraint_OSH, Constraint_ISH, Constraint_NSH, Constraint_NC, Constraint_WT, Constraint_WB, Constraint_FORCE, Constraint_FORCENOSLCHECK, Constraint_MAPTOALLOCATED, Constraint_PMSCR_PCT_VIRT }">Constraint_NOP</a> <a link="impl-shared.EndOfInstruction.0" file="shared_pseudocode.xml" hover="function: EndOfInstruction()">EndOfInstruction</a>();</pstext>
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</ps>
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</ps_section>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/pair/simdfp/no-alloc" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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bits(64) address;
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bits(datasize) data1;
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bits(datasize) data2;
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constant integer dbytes = datasize DIV 8;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);
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if n == 31 then
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<a link="impl-aarch64.CheckSPAlignment.0" file="shared_pseudocode.xml" hover="function: CheckSPAlignment()">CheckSPAlignment</a>();
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address = <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[];
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else
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address = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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if ! postindex then
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address = address + offset;
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case memop of
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when <a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>
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data1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t, datasize];
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data2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[t2, datasize];
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Mem[address + 0 , dbytes, accdesc] = data1;
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Mem[address + dbytes, dbytes, accdesc] = data2;
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when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
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data1 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + 0 , dbytes, accdesc];
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data2 = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address + dbytes, dbytes, accdesc];
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if rt_unknown then
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data1 = bits(datasize) UNKNOWN;
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data2 = bits(datasize) UNKNOWN;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t, datasize] = data1;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[t2, datasize] = data2;
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if wback then
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if postindex then
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address = address + offset;
|
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if n == 31 then
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<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = address;
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else
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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