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https://github.com/pound-emu/ballistic.git
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185 lines
11 KiB
XML
185 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="PRFM_lit" title="PRFM (literal) -- A64" type="instruction">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFM" />
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<docvar key="offset-type" value="off19s" />
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</docvars>
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<heading>PRFM (literal)</heading>
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<desc>
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<brief>
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<para>Prefetch Memory (literal)</para>
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</brief>
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<authored>
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<para>Prefetch Memory (literal) signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into one or more caches.</para>
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<para>The effect of a <instruction>PRFM</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGGGIDE">Prefetch memory</xref>.</para>
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<para>For information about memory accesses, see <xref linkend="CHDIIIBB">Load/Store addressing modes</xref>.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Literal" oneof="1" id="iclass_literal" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFM" />
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<docvar key="offset-type" value="off19s" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/memory/literal/general" tworows="1">
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<box hibit="31" width="2" name="opc" usename="1" settings="2" psbits="xx">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="29" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="26" name="V" settings="1">
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<c>0</c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="19" name="imm19" usename="1">
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<c colspan="19"></c>
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</box>
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<box hibit="4" width="5" name="Rt" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="PRFM_P_loadlit" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="PRFM" />
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<docvar key="offset-type" value="off19s" />
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</docvars>
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<asmtemplate><text>PRFM (</text><a link="sa_prfop" hover="Prefetch operation, defined as {syntax{<type><target><policy>}} (field "Rt<4:3>")"><prfop></a><text>|#</text><a link="sa_imm5" hover="Prefetch operation encoding as an immediate [0-31] (field "Rt")"><imm5></a><text>), </text><a link="sa_label" hover="Label from which the data is to be loaded (field imm19)"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/literal/general" mylink="aarch64.instrs.memory.literal.general" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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<a link="MemOp" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>;
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boolean signed = FALSE;
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boolean nontemporal = FALSE;
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integer size;
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bits(64) offset;
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case opc of
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when '00'
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size = 4;
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when '01'
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size = 8;
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when '10'
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size = 4;
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signed = TRUE;
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when '11'
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memop = <a link="MemOp_PREFETCH" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a>;
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offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
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boolean tagchecked = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="PRFM_P_loadlit" symboldefcount="1">
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<symbol link="sa_prfop"><prfop></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the prefetch operation, defined as <syntax><type><target><policy></syntax>.</para>
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<para><syntax><type></syntax> is one of:</para>
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<list type="param">
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<listitem>
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<param>PLD</param><content>Prefetch for load, encoded in the "Rt<4:3>" field as <binarynumber>0b00</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>PLI</param><content>Preload instructions, encoded in the "Rt<4:3>" field as <binarynumber>0b01</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>PST</param><content>Prefetch for store, encoded in the "Rt<4:3>" field as <binarynumber>0b10</binarynumber>.</content>
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</listitem>
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</list>
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<para><syntax><target></syntax> is one of:</para>
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<list type="param">
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<listitem>
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<param>L1</param><content>Level 1 cache, encoded in the "Rt<2:1>" field as <binarynumber>0b00</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>L2</param><content>Level 2 cache, encoded in the "Rt<2:1>" field as <binarynumber>0b01</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>L3</param><content>Level 3 cache, encoded in the "Rt<2:1>" field as <binarynumber>0b10</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>SLC</param><content>When FEAT_PRFMSLC is implemented, system level cache, encoded in the "Rt<2:1>" field as <binarynumber>0b11</binarynumber>.</content>
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</listitem>
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</list>
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<para><syntax><policy></syntax> is one of:</para>
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<list type="param">
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<listitem>
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<param>KEEP</param><content>Retained or temporal prefetch, allocated in the cache normally. Encoded in the "Rt<0>" field as <binarynumber>0</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>STRM</param><content>Streaming or non-temporal prefetch, for data that is used only once. Encoded in the "Rt<0>" field as <binarynumber>1</binarynumber>.</content>
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</listitem>
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</list>
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<para>For more information on these prefetch operations, see <xref linkend="CEGGGIDE">Prefetch memory</xref>.</para>
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<para>For other encodings of the "Rt" field, use <syntax><imm5></syntax>.</para>
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</intro>
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</account>
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<arch_variants>
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<arch_variant name="ARMv8.9" />
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</arch_variants>
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</explanation>
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<explanation enclist="PRFM_P_loadlit" symboldefcount="1">
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<symbol link="sa_imm5"><imm5></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.</para>
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<para>This syntax is only for encodings that are not accessible using <syntax><prfop></syntax>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PRFM_P_loadlit" symboldefcount="1">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="imm19">
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<intro>
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<para>Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/memory/literal/general" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) address = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset;
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bits(size*8) data;
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boolean privileged = PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a>;
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<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescGPR.4" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescGPR(MemOp memop, boolean nontemporal, boolean privileged, boolean tagchecked)">CreateAccDescGPR</a>(memop, nontemporal, privileged, tagchecked);
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case memop of
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when <a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>
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data = <a link="impl-aarch64.Mem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address, size, accdesc];
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if signed then
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, 64] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 64);
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else
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<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[t, size*8] = data;
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when <a link="MemOp_PREFETCH" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_PREFETCH</a>
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<a link="impl-aarch64.Prefetch.2" file="shared_pseudocode.xml" hover="function: Prefetch(bits(64) address, bits(5) prfop)">Prefetch</a>(address, t<4:0>);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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