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https://github.com/pound-emu/ballistic.git
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225 lines
10 KiB
XML
225 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="REV64_advsimd" title="REV64 -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="REV64" />
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</docvars>
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<heading>REV64</heading>
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<desc>
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<brief>
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<para>Reverse elements in 64-bit doublewords (vector)</para>
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</brief>
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<authored>
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<para>Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Vector" oneof="1" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="REV64" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/rev" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="16" width="4" name="opcode[4:1]" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="12" name="o0" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="REV64_asimdmisc_R" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="REV64" />
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</docvars>
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<asmtemplate><text>REV64 </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2S,4H,4S,8B,8H,16B]"><T></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/rev" mylink="aarch64.instrs.vector.arithmetic.unary.rev" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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// size=esize: B(0), H(1), S(1), D(S)
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integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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integer datasize = if Q == '1' then 128 else 64;
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// op=REVx: 64(0), 32(1), 16(2)
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bits(2) op = o0:U;
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// => op+size:
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// 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X
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// 32+B = 1, 32+H = 2, 32+S = X, 32+D = X
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// 16+B = 2, 16+H = X, 16+S = X, 16+D = X
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// 8+B = X, 8+H = X, 8+S = X, 8+D = X
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// => 3-(op+size) (index bits in group)
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// 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X
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// 32+B = 2, 32+H = 1, 32+S = X, 32+D = X
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// 16+B = 1, 16+H = X, 16+S = X, 16+D = X
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// 8+B = X, 8+H = X, 8+S = X, 8+D = X
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// index bits within group: 1, 2, 3
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if <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(op)+<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size) >= 3 then UNDEFINED;
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integer container_size;
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case op of
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when '10' container_size = 16;
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when '01' container_size = 32;
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when '00' container_size = 64;
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integer containers = datasize DIV container_size;
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integer elements_per_container = container_size DIV esize;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="REV64_asimdmisc_R" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="REV64_asimdmisc_R" symboldefcount="1">
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<symbol link="sa_t"><T></symbol>
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<definition encodedin="size:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">size</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><T></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="REV64_asimdmisc_R" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/arithmetic/unary/rev" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
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bits(datasize) result;
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integer element = 0;
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integer rev_element;
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for c = 0 to containers-1
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rev_element = (element + elements_per_container) - 1;
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for e = 0 to elements_per_container-1
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, rev_element, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, element, esize];
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element = element + 1;
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rev_element = rev_element - 1;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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