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136 lines
6.6 KiB
XML
136 lines
6.6 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="RMIF" title="RMIF -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RMIF" />
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</docvars>
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<heading>RMIF</heading>
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<desc>
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<brief>
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<para>Rotate, Mask Insert Flags</para>
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</brief>
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<authored>
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<para>Performs a rotation right of a value held in a general purpose register by an immediate value, and then inserts a selection of the bottom four bits of the result of the rotation into the PSTATE flags, under the control of a second immediate mask.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RMIF" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.4" feature="FEAT_FlagM" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/integer/flags/rmif" tworows="1">
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<box hibit="31" name="sf" usename="1" settings="1" psbits="x">
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<c>1</c>
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</box>
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<box hibit="30" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>1</c>
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</box>
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<box hibit="28" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="14" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" name="o2" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="mask" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="RMIF_only_rmif" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="RMIF" />
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</docvars>
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<asmtemplate><text>RMIF </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_shift" hover="Shift amount [0-63], default 0 (field "imm6")"><shift></a><text>, #</text><a link="sa_mask" hover="Flag bit mask, an immediate [0-15], which selects the bits that are inserted into the NZCV condition flags (field "mask")"><mask></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/flags/rmif" mylink="aarch64.instrs.integer.flags.rmif" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFlagManipulateExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFlagManipulateExt()">HaveFlagManipulateExt</a>() || sf != '1' then UNDEFINED;
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integer lsb = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="RMIF_only_rmif" symboldefcount="1">
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<symbol link="sa_xn"><Xn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RMIF_only_rmif" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<account encodedin="imm6">
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<intro>
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<para>Is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RMIF_only_rmif" symboldefcount="1">
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<symbol link="sa_mask"><mask></symbol>
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<account encodedin="mask">
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<intro>
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<para>Is the flag bit mask, an immediate in the range 0 to 15, which selects the bits that are inserted into the NZCV condition flags, encoded in the "mask" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/integer/flags/rmif" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(4) tmp;
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bits(64) tmpreg = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
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tmp = (tmpreg:tmpreg)<lsb+3:lsb>;
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if mask<3> == '1' then PSTATE.N = tmp<3>;
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if mask<2> == '1' then PSTATE.Z = tmp<2>;
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if mask<1> == '1' then PSTATE.C = tmp<1>;
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if mask<0> == '1' then PSTATE.V = tmp<0>;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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