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https://github.com/pound-emu/ballistic.git
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316 lines
15 KiB
XML
316 lines
15 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SSHLL_advsimd" title="SSHLL, SSHLL2 -- A64" type="instruction">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SSHLL" />
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</docvars>
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<heading>SSHLL, SSHLL2</heading>
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<desc>
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<brief>
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<para>Signed Shift Left Long (immediate)</para>
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</brief>
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<authored>
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<para>Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.</para>
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<para>The <instruction>SSHLL</instruction> instruction extracts vector elements from the lower half of the source register. The <instruction>SSHLL2</instruction> instruction extracts vector elements from the upper half of the source register.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="1">
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<alias_list_intro>This instruction is used by the alias </alias_list_intro>
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<aliasref aliaspageid="SXTL_SSHLL_advsimd" aliasfile="sxtl_sshll_advsimd.xml" hover="Signed extend long" punct=".">
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<text>SXTL, SXTL2</text>
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<aliaspref>immb == '000' && <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(immh) == 1</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when the alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<iclass name="Vector" oneof="1" id="iclass_simd" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SSHLL" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/shift/left-long" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" name="U" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="28" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
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<c colspan="4">!= 0000</c>
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</box>
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<box hibit="18" width="3" name="immb" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="5" name="opcode" settings="5">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="10" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="SSHLL_asimdshf_L" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="advsimd-type" value="simd" />
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="SSHLL" />
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</docvars>
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<asmtemplate><text>SSHLL</text><a link="sa_2" hover="Second and upper half specifier (field "Q")">{2}</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "immh") [2D,4S,8H,SEE(asimdimm)]"><Ta></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "immh:Q") [2S,4H,4S,8B,8H,16B,SEE(asimdimm)]"><Tb></a><text>, #</text><a link="sa_shift" hover="Left shift amount [0-the source element width in bits minus 1] (field "immh:immb")"><shift></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/left-long" mylink="aarch64.instrs.vector.shift.left-long" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if immh == '0000' then <a link="asimdimm" file="encodingindex.xml" hover="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
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if immh<3> == '1' then UNDEFINED;
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integer esize = 8 << <a link="impl-shared.HighestSetBit.1" file="shared_pseudocode.xml" hover="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
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integer datasize = 64;
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integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
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integer elements = datasize DIV esize;
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integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;
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boolean unsigned = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_2">2</symbol>
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<definition encodedin="Q">
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<intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol">2</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">[absent]</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">[present]</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="immh">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="symbol">2D</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_tb"><Tb></symbol>
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<definition encodedin="immh:Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Tb></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">4H</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">8H</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">2S</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">4S</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="SSHLL_asimdshf_L" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="immh:immb">
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<intro>Is the left shift amount, in the range 0 to the source element width in bits minus 1, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">immh</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol" iclasslink="asimdimm" iclasslinkfile="encodingindex.xml">SEE Advanced SIMD modified immediate</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">(UInt(immh:immb)-8)</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">(UInt(immh:immb)-16)</entry>
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</row>
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<row>
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<entry class="bitfield">01xx</entry>
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<entry class="symbol">(UInt(immh:immb)-32)</entry>
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</row>
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<row>
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<entry class="bitfield">1xxx</entry>
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<entry class="symbol">RESERVED</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/shift/left-long" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) operand = <a link="impl-aarch64.Vpart.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) Vpart[integer n, integer part, integer width]">Vpart</a>[n, part, datasize];
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bits(datasize*2) result;
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integer element;
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for e = 0 to elements-1
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element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], unsigned) << shift;
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 2*esize] = element<2*esize-1:0>;
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize*2] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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