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https://github.com/pound-emu/ballistic.git
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260 lines
16 KiB
XML
260 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="TBL_advsimd" title="TBL -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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</docvars>
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<heading>TBL</heading>
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<desc>
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<brief>
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<para>Table vector Lookup</para>
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</brief>
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<authored>
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<para>Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If PSTATE.DIT is 1:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="4" isa="A64">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/vector/transfer/vector/table" tworows="1">
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<box hibit="31" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="29" width="6" settings="6">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="op2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="21" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="2" name="len" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="12" name="op" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="TBL_asimdtbl_L2_2" oneofinclass="4" oneof="4" label="Two register table" bitdiffs="len == 01">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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<docvar key="no-reg-for-table" value="tbl2" />
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</docvars>
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<box hibit="14" width="2" name="len">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>TBL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a><text>, </text><text>{</text><text> </text><a link="sa_vn_1" hover="First SIMD&FP table register (field "Rn")"><Vn></a><text>.16B, </text><a link="sa_vn_plus_1" hover="Second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32 (field Rn)"><Vn+1></a><text>.16B </text><text>}</text><text>, </text><a link="sa_vm" hover="SIMD&FP index register (field "Rm")"><Vm></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a></asmtemplate>
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</encoding>
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<encoding name="TBL_asimdtbl_L3_3" oneofinclass="4" oneof="4" label="Three register table" bitdiffs="len == 10">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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<docvar key="no-reg-for-table" value="tbl3" />
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</docvars>
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<box hibit="14" width="2" name="len">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>TBL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a><text>, </text><text>{</text><text> </text><a link="sa_vn_1" hover="First SIMD&FP table register (field "Rn")"><Vn></a><text>.16B, </text><a link="sa_vn_plus_1" hover="Second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32 (field Rn)"><Vn+1></a><text>.16B, </text><a link="sa_vn_plus_2" hover="Third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32 (field Rn)"><Vn+2></a><text>.16B </text><text>}</text><text>, </text><a link="sa_vm" hover="SIMD&FP index register (field "Rm")"><Vm></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a></asmtemplate>
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</encoding>
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<encoding name="TBL_asimdtbl_L4_4" oneofinclass="4" oneof="4" label="Four register table" bitdiffs="len == 11">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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<docvar key="no-reg-for-table" value="tbl4" />
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</docvars>
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<box hibit="14" width="2" name="len">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>TBL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a><text>, </text><text>{</text><text> </text><a link="sa_vn_1" hover="First SIMD&FP table register (field "Rn")"><Vn></a><text>.16B, </text><a link="sa_vn_plus_1" hover="Second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32 (field Rn)"><Vn+1></a><text>.16B, </text><a link="sa_vn_plus_2" hover="Third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32 (field Rn)"><Vn+2></a><text>.16B, </text><a link="sa_vn_plus_3" hover="Fourth SIMD&FP table register, encoded as "Rn" plus 3 modulo 32 (field Rn)"><Vn+3></a><text>.16B </text><text>}</text><text>, </text><a link="sa_vm" hover="SIMD&FP index register (field "Rm")"><Vm></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a></asmtemplate>
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</encoding>
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<encoding name="TBL_asimdtbl_L1_1" oneofinclass="4" oneof="4" label="Single register table" bitdiffs="len == 00">
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<docvars>
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<docvar key="instr-class" value="advsimd" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="TBL" />
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<docvar key="no-reg-for-table" value="tbl1" />
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</docvars>
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<box hibit="14" width="2" name="len">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>TBL </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a><text>, </text><text>{</text><text> </text><a link="sa_vn" hover="SIMD&FP table register (field "Rn")"><Vn></a><text>.16B </text><text>}</text><text>, </text><a link="sa_vm" hover="SIMD&FP index register (field "Rm")"><Vm></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "Q") [8B,16B]"><Ta></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/transfer/vector/table" mylink="aarch64.instrs.vector.transfer.vector.table" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer datasize = if Q == '1' then 128 else 64;
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integer elements = datasize DIV 8;
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integer regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(len) + 1;
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boolean is_tbl = (op == '0');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="TBL_asimdtbl_L1_1, TBL_asimdtbl_L2_2, TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vd"><Vd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L1_1, TBL_asimdtbl_L2_2, TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_ta"><Ta></symbol>
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<definition encodedin="Q">
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<intro>Is an arrangement specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><Ta></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">8B</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">16B</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L2_2, TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vn_1"><Vn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>For the four register table, three register table and two register table variant: is the name of the first SIMD&FP table register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L1_1" symboldefcount="2">
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<symbol link="sa_vn"><Vn></symbol>
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<account encodedin="Rn">
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<docvars>
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<docvar key="no-reg-for-table" value="tbl1" />
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</docvars>
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<intro>
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<para>For the single register table variant: is the name of the SIMD&FP table register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L2_2, TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vn_plus_1"><Vn+1></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vn_plus_2"><Vn+2></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vn_plus_3"><Vn+3></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the name of the fourth SIMD&FP table register, encoded as "Rn" plus 3 modulo 32.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBL_asimdtbl_L1_1, TBL_asimdtbl_L2_2, TBL_asimdtbl_L3_3, TBL_asimdtbl_L4_4" symboldefcount="1">
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<symbol link="sa_vm"><Vm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the name of the SIMD&FP index register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/transfer/vector/table" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
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bits(datasize) indices = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
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bits(128*regs) table = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128*regs);
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bits(datasize) result;
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integer index;
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// Create table from registers
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for i = 0 to regs - 1
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table<128*i+127:128*i> = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
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n = (n + 1) MOD 32;
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result = if is_tbl then <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(datasize) else <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
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for i = 0 to elements - 1
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index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[indices, i, 8]);
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if index < 16 * regs then
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, i, 8] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[table, index, 8];
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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