mirror of
https://github.com/pound-emu/ballistic.git
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134 lines
6.6 KiB
XML
134 lines
6.6 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="BFCVT_float" title="BFCVT -- A64" type="instruction">
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<docvars>
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<docvar key="convert-type" value="single-to-bf16" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFCVT" />
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</docvars>
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<heading>BFCVT</heading>
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<desc>
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<brief>
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<para>Floating-point convert from single-precision to BFloat16 format (scalar)</para>
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</brief>
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<authored>
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<para>Floating-point convert from single-precision to BFloat16 format (scalar) converts the single-precision floating-point value in the 32-bit SIMD&FP source register to BFloat16 format and writes the result in the 16-bit SIMD&FP destination register.</para>
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<para><xref linkend="AArch64.id_aa64isar1_el1">ID_AA64ISAR1_EL1</xref>.BF16 indicates whether this instruction is supported.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Single-precision to BFloat16" oneof="1" id="iclass_single_to_bf16" no_encodings="1" isa="A64">
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<docvars>
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<docvar key="convert-type" value="single-to-bf16" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFCVT" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_BF16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch64/instrs/vector/cvt_bf16/scalar">
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<box hibit="31" name="M" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ptype" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="6" name="opcode" settings="6">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="14" width="5" settings="5">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="BFCVT_BS_floatdp1" oneofinclass="1" oneof="1" label="">
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<docvars>
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<docvar key="convert-type" value="single-to-bf16" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="BFCVT" />
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</docvars>
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<asmtemplate><text>BFCVT </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP source register (field "Rn")"><Sn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/cvt_bf16/scalar" mylink="aarch64.instrs.vector.cvt_bf16.scalar" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveBF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="BFCVT_BS_floatdp1" symboldefcount="1">
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<symbol link="sa_hd"><Hd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="BFCVT_BS_floatdp1" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/vector/cvt_bf16/scalar" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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bits(32) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 32];
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<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
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boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
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bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, 16] = <a link="impl-shared.FPConvertBF.2" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</a>(operand, fpcr);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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