mirror of
https://github.com/pound-emu/ballistic.git
synced 2026-01-31 01:15:21 +01:00
118185 lines
4.3 MiB
118185 lines
4.3 MiB
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="encodingindex-splitmaintable.xsl" version="1.0"?>
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<!DOCTYPE encodingindex PUBLIC "-//ARM//DTD encodingindex //EN" "encodingindex.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<encodingindex instructionset="A64">
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<hierarchy>
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<regdiagram form="32">
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<box hibit="31" width="1" name="op0" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="30" width="2">
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<c colspan="2" />
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</box>
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<box hibit="28" width="4" name="op1" usename="1">
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<c colspan="4" />
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</box>
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<box hibit="24" width="25">
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<c colspan="25" />
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</box>
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</regdiagram>
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<node groupname="reserved">
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<header>Reserved</header>
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<decode>
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<box hibit="31" width="1" name="op0" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="28" width="4" name="op1" usename="1">
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<c colspan="4">0000</c>
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</box>
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</decode>
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<regdiagram form="32">
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<box hibit="31" width="1">
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<c colspan="1" />
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</box>
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<box hibit="30" width="2" name="op0" usename="1">
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|
<c colspan="2" />
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</box>
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<box hibit="28" width="4">
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<c colspan="4">0000</c>
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</box>
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<box hibit="24" width="9" name="op1" usename="1">
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<c colspan="9" />
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</box>
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<box hibit="15" width="16">
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<c colspan="16" />
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</box>
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</regdiagram>
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<node iclass="perm_undef">
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<header>Reserved</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">00</c>
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</box>
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<box hibit="24" width="9" name="op1" usename="1">
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<c colspan="9">000000000</c>
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</box>
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</decode>
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</node>
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<node iclass="unallocate3" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2" />
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</box>
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<box hibit="24" width="9" name="op1" usename="1">
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<c colspan="9">!= 000000000</c>
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</box>
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</decode>
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</node>
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<node iclass="unallocate4" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">!= 00</c>
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</box>
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<box hibit="24" width="9" name="op1" usename="1">
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<c colspan="9" />
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</box>
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</decode>
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</node>
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</node>
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<node groupname="sme">
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<header>SME encodings</header>
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<decode>
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<box hibit="31" width="1" name="op0" usename="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="28" width="4" name="op1" usename="1">
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<c colspan="4">0000</c>
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</box>
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</decode>
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<regdiagram form="32">
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<box hibit="31" width="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2" />
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</box>
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<box hibit="28" width="4">
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<c colspan="4">0000</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15" />
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</box>
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<box hibit="9" width="5">
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<c colspan="5" />
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3" />
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</box>
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<box hibit="1" width="2">
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<c colspan="2" />
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</box>
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</regdiagram>
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<node groupname="mortlach_64bit_prod">
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<header>SME Outer Product - 64 bit</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">0x</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">x11xxxxxxxxxxxx</c>
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3">x0x</c>
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</box>
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</decode>
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<regdiagram form="32">
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<box hibit="31" width="2">
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<c colspan="2">10</c>
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</box>
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<box hibit="29" width="1" name="op0" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="28" width="4">
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<c colspan="4">0000</c>
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</box>
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<box hibit="24" width="1" name="op1" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="23" width="2">
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<c colspan="2">11</c>
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</box>
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<box hibit="21" width="1" name="op2" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="20" width="17">
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<c colspan="17" />
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</box>
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<box hibit="3" width="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="2" width="3">
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<c colspan="3" />
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</box>
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</regdiagram>
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<node iclass="mortlach_f64f64_prod">
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<header>SME FP64 outer product</header>
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<decode>
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<box hibit="29" width="1" name="op0" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="24" width="1" name="op1" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="21" width="1" name="op2" usename="1">
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<c colspan="1">0</c>
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</box>
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</decode>
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</node>
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<node iclass="UNALLOCATED_51" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="29" width="1" name="op0" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="24" width="1" name="op1" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="21" width="1" name="op2" usename="1">
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<c colspan="1">1</c>
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</box>
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</decode>
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</node>
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<node iclass="UNALLOCATED_53" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="29" width="1" name="op0" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="24" width="1" name="op1" usename="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="21" width="1" name="op2" usename="1">
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<c colspan="1" />
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</box>
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</decode>
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</node>
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<node iclass="mortlach_i16i64_prod">
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<header>SME Int16 outer product</header>
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<decode>
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<box hibit="29" width="1" name="op0" usename="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="24" width="1" name="op1" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="21" width="1" name="op2" usename="1">
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<c colspan="1" />
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</box>
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</decode>
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</node>
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</node>
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<node iclass="unalloc_4" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">0x</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">x11xxxxxxxxxxxx</c>
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3">x1x</c>
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</box>
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</decode>
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</node>
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<node iclass="unalloc_1" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">00</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">x0xxxxxxxxxxxxx</c>
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3" />
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</box>
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</decode>
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</node>
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<node groupname="mortlach_32bit_fp_prod">
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<header>SME FP Outer Product - 32 bit</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">00</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">x10xxxxxxxxxxxx</c>
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3">x00</c>
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</box>
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</decode>
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<regdiagram form="32">
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<box hibit="31" width="7">
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<c colspan="7">1000000</c>
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</box>
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<box hibit="24" width="1" name="op0" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="23" width="2">
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<c colspan="2">10</c>
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</box>
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<box hibit="21" width="1" name="op1" usename="1">
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<c colspan="1" />
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</box>
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<box hibit="20" width="17">
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<c colspan="17" />
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</box>
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<box hibit="3" width="2">
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<c colspan="2">00</c>
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</box>
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<box hibit="1" width="2">
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<c colspan="2" />
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</box>
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</regdiagram>
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<node iclass="mortlach_f32f32_prod">
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<header>SME FP32 outer product</header>
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<decode>
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<box hibit="24" width="1" name="op0" usename="1">
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<c colspan="1">0</c>
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</box>
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<box hibit="21" width="1" name="op1" usename="1">
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<c colspan="1">0</c>
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</box>
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</decode>
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</node>
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<node iclass="mortlach_b16f32_prod">
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<header>SME widening BF16 outer product</header>
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<decode>
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<box hibit="24" width="1" name="op0" usename="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="21" width="1" name="op1" usename="1">
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<c colspan="1">0</c>
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</box>
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</decode>
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</node>
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<node iclass="mortlach_f16f32_prod">
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<header>SME FP16 widening outer product</header>
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<decode>
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<box hibit="24" width="1" name="op0" usename="1">
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<c colspan="1">1</c>
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</box>
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<box hibit="21" width="1" name="op1" usename="1">
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<c colspan="1">1</c>
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</box>
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</decode>
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</node>
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</node>
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<node iclass="unalloc_0" unallocated="1">
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<header>UNALLOCATED</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">00</c>
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</box>
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<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">010xxxxxxxxxxxx</c>
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</box>
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<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3">xx1</c>
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</box>
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</decode>
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</node>
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<node groupname="mortlach_32bit_bin_prod">
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<header>SME2 Binary Outer Product - 32 bit</header>
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<decode>
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<box hibit="30" width="2" name="op0" usename="1">
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<c colspan="2">00</c>
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</box>
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|
<box hibit="24" width="15" name="op1" usename="1">
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<c colspan="15">010xxxxxxxxxxxx</c>
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</box>
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|
<box hibit="4" width="3" name="op2" usename="1">
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<c colspan="3">x10</c>
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|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="10">
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<c colspan="10">1000000010</c>
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</box>
|
|
<box hibit="21" width="1" name="op0" usename="1">
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<c colspan="1" />
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</box>
|
|
<box hibit="20" width="17">
|
|
<c colspan="17" />
|
|
</box>
|
|
<box hibit="3" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
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<node iclass="mortlach_bini32_prod">
|
|
<header>SME2 32-bit binary outer product</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_50" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_2" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">110xxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_16bit_fp_prod">
|
|
<header>SME FP Outer Product - 16 bit</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">110xxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">x1x</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="10">
|
|
<c colspan="10">1000000110</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="17">
|
|
<c colspan="17" />
|
|
</box>
|
|
<box hibit="3" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="0" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_f16f16_prod">
|
|
<header>SME FP16 non-widening outer product</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_b16b16_prod">
|
|
<header>SME non-widening BF16 outer product</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_52" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_32bit_int_prod">
|
|
<header>SME Integer Outer Product - 32 bit</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">x10xxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">xx0</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1010000</c>
|
|
</box>
|
|
<box hibit="24" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="17">
|
|
<c colspan="17" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_i16i32_prod">
|
|
<header>SME2 Int16 two-way outer product</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_62" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_i8i32_prod">
|
|
<header>SME Int8 outer product</header>
|
|
<decode>
|
|
<box hibit="21" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_3" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">x10xxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_multi_mem_ctg">
|
|
<header>SME2 Multi-vector - Memory (Contiguous)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">00xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">101000000</c>
|
|
</box>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="0" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_cld_cldnt_ss_ctg">
|
|
<header>SME2 multi-vec contiguous load (scalar plus scalar, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cld_cldnt_ss_ctg">
|
|
<header>SME2 multi-vec contiguous load (scalar plus scalar, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cst_cstnt_ss_ctg">
|
|
<header>SME2 multi-vec contiguous store (scalar plus scalar, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cst_cstnt_ss_ctg">
|
|
<header>SME2 multi-vec contiguous store (scalar plus scalar, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_59" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cld_cldnt_si_ctg">
|
|
<header>SME2 multi-vec contiguous load (scalar plus immediate, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cld_cldnt_si_ctg">
|
|
<header>SME2 multi-vec contiguous load (scalar plus immediate, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cst_cstnt_si_ctg">
|
|
<header>SME2 multi-vec contiguous store (scalar plus immediate, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cst_cstnt_si_ctg">
|
|
<header>SME2 multi-vec contiguous store (scalar plus immediate, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_60" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">1x0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_61" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">1x1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="1" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_mem_nctg">
|
|
<header>SME2 Multi-vector - Memory (Strided)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">10xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">101000010</c>
|
|
</box>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="12">
|
|
<c colspan="12" />
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_cld_cldnt_ss_nctg">
|
|
<header>SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cld_cldnt_ss_nctg">
|
|
<header>SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cst_cstnt_ss_nctg">
|
|
<header>SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cst_cstnt_ss_nctg">
|
|
<header>SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_63" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cld_cldnt_si_nctg">
|
|
<header>SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cld_cldnt_si_nctg">
|
|
<header>SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_cst_cstnt_si_nctg">
|
|
<header>SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_cst_cstnt_si_nctg">
|
|
<header>SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_64" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">1x0</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_65" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="3" name="op0" usename="1">
|
|
<c colspan="3">1x1</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_ins">
|
|
<header>SME Move into Array</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx000x0xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000000</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_za_insert_ctg">
|
|
<header>SME2 move vector to array, two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_za_insert_ctg">
|
|
<header>SME2 move vector to array, four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_67" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_68" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_69" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_238" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_71" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_72" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_73" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_239" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_74" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_240" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_241" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_242" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_243" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_244" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_245" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_insert_pred">
|
|
<header>SME move vector to array</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_insert_ctg">
|
|
<header>SME2 move vector to tile, two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_insert_ctg">
|
|
<header>SME2 move vector to tile, four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_70" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_75" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_6" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx000x0xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_ext">
|
|
<header>SME Move from Array</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx000x1xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000000</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="7" width="6">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_za_extract_ctg">
|
|
<header>SME2 move array to vector, two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_za_extract_zero">
|
|
<header>mortlach_multi2_za_extract_zero</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_za_extract_ctg">
|
|
<header>SME2 move array to vector, four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_za_extract_zero">
|
|
<header>mortlach_multi4_za_extract_zero</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_76" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_231" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_77" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_79" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_232" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_80" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_81" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_233" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_235" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_236" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_234" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_237" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_extract_zero">
|
|
<header>SME zeroing move array to vector</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_230" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_extract_pred">
|
|
<header>SME move array to vector</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_extract_ctg">
|
|
<header>SME2 move tile to vector, two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_extract_zero">
|
|
<header>SME2 zeroing move tile to vector, two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_extract_ctg">
|
|
<header>SME2 move tile to vector, four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_extract_zero">
|
|
<header>SME2 zeroing move tile to vector, four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_78" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_82" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op5" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_hvadd">
|
|
<header>SME Add Vector to Array</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx010xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">x0x</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000000</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="12">
|
|
<c colspan="12" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_83" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_addhv">
|
|
<header>SME add vector to array</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_86" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_248" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_7" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx010xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3">x1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_9" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_5" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">00x011xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_zero">
|
|
<header>SME Zero</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0000010xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="14">
|
|
<c colspan="14">11000000000010</c>
|
|
</box>
|
|
<box hibit="17" width="10" name="op0" usename="1">
|
|
<c colspan="10" />
|
|
</box>
|
|
<box hibit="7" width="8">
|
|
<c colspan="8" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_zero">
|
|
<header>SME zero array</header>
|
|
<decode>
|
|
<box hibit="17" width="10" name="op0" usename="1">
|
|
<c colspan="10">0000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_246" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="10" name="op0" usename="1">
|
|
<c colspan="10">!= 0000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multizero">
|
|
<header>SME2 Multiple Zero</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0000011xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="14">
|
|
<c colspan="14">11000000000011</c>
|
|
</box>
|
|
<box hibit="17" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="12" width="10" name="op0" usename="1">
|
|
<c colspan="10" />
|
|
</box>
|
|
<box hibit="2" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi_zero">
|
|
<header>SME multiple vectors zero array</header>
|
|
<decode>
|
|
<box hibit="12" width="10" name="op0" usename="1">
|
|
<c colspan="10">0000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_247" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="12" width="10" name="op0" usename="1">
|
|
<c colspan="10">!= 0000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_zero_zt">
|
|
<header>SME2 Zero Lookup Table</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0010010xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="14">
|
|
<c colspan="14">11000000010010</c>
|
|
</box>
|
|
<box hibit="17" width="14" name="op0" usename="1">
|
|
<c colspan="14" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_zero_zt">
|
|
<header>SME2 zero lookup table</header>
|
|
<decode>
|
|
<box hibit="17" width="14" name="op0" usename="1">
|
|
<c colspan="14">00000000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_249" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="14" name="op0" usename="1">
|
|
<c colspan="14">!= 00000000000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_mov_zt">
|
|
<header>SME2 Move Lookup Table</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0010011xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="14">
|
|
<c colspan="14">11000000010011</c>
|
|
</box>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="16" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="15">
|
|
<c colspan="15" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_extract_zt">
|
|
<header>SME2 move from lookup table</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_insert_zt">
|
|
<header>SME2 move into lookup table</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="16" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_250" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="16" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_zt_expand_ctg">
|
|
<header>SME2 Expand Lookup Table (Contiguous)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">01x001xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">110000001</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="13" width="12">
|
|
<c colspan="12" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_84" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_expand_4dst_ctg">
|
|
<header>SME2 lookup table expand four contiguous registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_251" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_expand_2dst_ctg">
|
|
<header>SME2 lookup table expand two contiguous registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_85" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_expand_1dst">
|
|
<header>SME2 lookup table expand one register</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_zt_expand_nctg">
|
|
<header>SME2 Expand Lookup Table (Non-contiguous)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">010011xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="13">
|
|
<c colspan="13">1100000010011</c>
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="13" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_87" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_expand_4dst_nctg">
|
|
<header>SME2 lookup table expand four non-contiguous registers</header>
|
|
<decode>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_88" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_252" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_expand_2dst_nctg">
|
|
<header>SME2 lookup table expand two non-contiguous registers</header>
|
|
<decode>
|
|
<box hibit="15" width="2" name="op0" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="3" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_8" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">011011xxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_multi_indexed_1">
|
|
<header>SME2 Multi-vector - Indexed (One register)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx00xxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="19" width="7">
|
|
<c colspan="7" />
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="11" width="9">
|
|
<c colspan="9" />
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi1_mla_long_long_idx_s">
|
|
<header>SME2 multi-vec indexed long long MLA one source 32-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_122" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_mla_long_long_idx_d">
|
|
<header>SME2 multi-vec indexed long long MLA one source 64-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_126" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_fma_long_idx">
|
|
<header>SME2 multi-vec indexed long FMA one source</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_155" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_mla_long_idx">
|
|
<header>SME2 multi-vec indexed long MLA one source</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="2" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_indexed_2">
|
|
<header>SME2 Multi-vector - Indexed (Two registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx01xxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="10" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_mla_long_long_idx_s">
|
|
<header>SME2 multi-vec indexed long long MLA two sources 32-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zza_idx_h">
|
|
<header>SME2 multi-vec ternary indexed two registers 16-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zza_idx_s">
|
|
<header>SME2 multi-vec ternary indexed two registers 32-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_mla_long_long_idx_d">
|
|
<header>SME2 multi-vec indexed long long MLA two sources 64-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_127" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_128" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_fma_long_idx">
|
|
<header>SME2 multi-vec indexed long FMA two sources</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_129" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zza_idx_d">
|
|
<header>SME2 multi-vec ternary indexed two registers 64-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_156" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_mla_long_idx">
|
|
<header>SME2 multi-vec indexed long MLA two sources</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_indexed_3">
|
|
<header>SME2 Multi-vector - Indexed (Four registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx01xxxx1xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="10" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi4_mla_long_long_idx_s">
|
|
<header>SME2 multi-vec indexed long long MLA four sources 32-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zza_idx_h">
|
|
<header>SME2 multi-vec ternary indexed four registers 16-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zza_idx_s">
|
|
<header>SME2 multi-vec ternary indexed four registers 32-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_89" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_mla_long_long_idx_d">
|
|
<header>SME2 multi-vec indexed long long MLA four sources 64-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_253" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_130" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_fma_long_idx">
|
|
<header>SME2 multi-vec indexed long FMA four sources</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_254" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zza_idx_d">
|
|
<header>SME2 multi-vec ternary indexed four registers 64-bit</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_157" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_mla_long_idx">
|
|
<header>SME2 multi-vec indexed long MLA four sources</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_158" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_1">
|
|
<header>SME2 Multi-vector - SVE Select</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="12" width="6">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi4_select_int">
|
|
<header>SME2 multi-vec select four registers</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_255" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_256" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_110" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_select_int">
|
|
<header>SME2 multi-vec select two registers</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_93" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_94" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="2" name="op0" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_3">
|
|
<header>SME2 Multi-vector - SVE Constructive Binary</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx110xxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="8">
|
|
<c colspan="8" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_z_z_long_zip">
|
|
<header>SME2 multi-vec quadwords ZIP two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_123" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_139" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_qrshr">
|
|
<header>SME2 multi-vec saturating shift right narrow two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_fclamp">
|
|
<header>SME2 multi-vec FCLAMP two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_104" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_clamp_int">
|
|
<header>SME2 multi-vec CLAMP two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_fclamp">
|
|
<header>SME2 multi-vec FCLAMP four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_105" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_clamp_int">
|
|
<header>SME2 multi-vec CLAMP four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_106" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_zip">
|
|
<header>SME2 multi-vec ZIP two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_qrshr">
|
|
<header>SME2 multi-vec saturating shift right narrow four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_4">
|
|
<header>SME2 Multi-vector - SVE Constructive Unary</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx111000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="6">
|
|
<c colspan="6">111000</c>
|
|
</box>
|
|
<box hibit="9" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_fpint_cvrt">
|
|
<header>SME2 multi-vec FP to int convert two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_107" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_intfp_cvrt">
|
|
<header>SME2 multi-vec int to FP two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_109" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_112" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_fpint_cvrt">
|
|
<header>SME2 multi-vec FP to int convert four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_270" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_116" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_intfp_cvrt">
|
|
<header>SME2 multi-vec int to FP four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_271" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_117" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_long_zip">
|
|
<header>SME2 multi-vec quadwords ZIP four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_121" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_272" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_124" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_125" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">x00</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_narrow_fp_cvrt">
|
|
<header>SME2 multi-vec FP down convert two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_narrow_int_cvrt">
|
|
<header>SME2 multi-vec int down convert two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_111" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_118" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_wide_fp_cvrt">
|
|
<header>SME2 multi-vec convert two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_280" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_159" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_154" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_152" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_276" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_277" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_278" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_279" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_275" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_wide_int">
|
|
<header>SME2 multi-vec unpack two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_frint">
|
|
<header>SME2 multi-vec FRINT two registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_113" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_114" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_narrow_int_cvrt">
|
|
<header>SME2 multi-vec int down convert four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_wide_int">
|
|
<header>SME2 multi-vec unpack four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_119" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_120" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_zip">
|
|
<header>SME2 multi-vec ZIP four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_frint">
|
|
<header>SME2 multi-vec FRINT four registers</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_273" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_274" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op3" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_14" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx111001</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_15" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx11101x</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_2c">
|
|
<header>SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxx010110x</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="16" width="6">
|
|
<c colspan="6">010110</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_z_z_minmax_mm">
|
|
<header>SME2 multiple vectors int min/max two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0000x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_fminmax_mm">
|
|
<header>SME2 multiple vectors FP min/max two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0100x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_265" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0x!= 00x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_shift_mm">
|
|
<header>SME2 multiple vectors shift two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_99" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11xxx</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_sqdmulh_mm">
|
|
<header>SME2 multi-vector signed saturating doubling multiply high two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_100" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_266" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_2d">
|
|
<header>SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxx010111x</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="16" width="6">
|
|
<c colspan="6">010111</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi4_z_z_minmax_mm">
|
|
<header>SME2 multiple vectors int min/max four registers</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">0000x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_fminmax_mm">
|
|
<header>SME2 multiple vectors FP min/max four registers</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">0100x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_101" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">0x00x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_267" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">0x!= 00x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_shift_mm">
|
|
<header>SME2 multiple vectors shift four registers</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_102" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_103" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">11xxx</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_sqdmulh_mm">
|
|
<header>SME2 multi-vector signed saturating doubling multiply high four registers</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_268" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_269" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_108" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="17" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_2a">
|
|
<header>SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx10xxxx10100x</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="5">
|
|
<c colspan="5">10100</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_z_z_minmax_sm">
|
|
<header>SME2 single-multi int min/max two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0000x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_fminmax_sm">
|
|
<header>SME2 single-multi FP min/max two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0100x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_257" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0x!= 00x</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_shift_sm">
|
|
<header>SME2 single-multi shift two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_add_sm">
|
|
<header>SME2 single-multi add two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_95" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_258" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11!= 000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_z_sqdmulh_sm">
|
|
<header>SME2 single-multi signed saturating doubling multiply high two registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_96" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_259" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="0" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_sve_2b">
|
|
<header>SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx10xxxx10101x</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">11000001</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="5">
|
|
<c colspan="5">10101</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi4_z_z_minmax_sm">
|
|
<header>SME2 single-multi int min/max four registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0000x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_fminmax_sm">
|
|
<header>SME2 single-multi FP min/max four registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0100x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_97" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0x00x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_260" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">0x!= 00x</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_shift_sm">
|
|
<header>SME2 single-multi shift four registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_98" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_add_sm">
|
|
<header>SME2 single-multi add four registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_261" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_262" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">11!= 000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_z_sqdmulh_sm">
|
|
<header>SME2 single-multi signed saturating doubling multiply high four registers</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_263" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_264" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="10" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op1" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_10" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx10xxx01111xx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_11" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx10xxx11x11xx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_16" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx11xxxx1111xx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_12" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx11xxx01010xx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_13" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx11xxx1101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="mortlach_multi_array_1">
|
|
<header>SME2 Multi-vector - Multiple and Single Array Vectors</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">10x1xxxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">110000010</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="0" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_zz_za_fma_long_sm">
|
|
<header>SME2 single-multi long FMA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_zz_za_fma_long_sm">
|
|
<header>SME2 multiple and single vector long FMA one source</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_mixed_dot_sm">
|
|
<header>SME2 single-multi mixed dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_fma_long_sm">
|
|
<header>SME2 single-multi long FMA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_mixed_dot_sm">
|
|
<header>SME2 single-multi mixed dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_mla_long_sm">
|
|
<header>SME2 single-multi long MLA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_zz_za_mla_long_sm">
|
|
<header>SME2 multiple and single vector long MLA one source</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_2way_dot_sm">
|
|
<header>SME2 single-multi two-way dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_mla_long_sm">
|
|
<header>SME2 single-multi long MLA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_2way_dot_sm">
|
|
<header>SME2 single-multi two-way dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_mla_long_long_sm">
|
|
<header>SME2 single-multi long long MLA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi1_zz_za_mla_long_long_sm">
|
|
<header>SME2 multiple and single vector long long FMA one source</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_fpdot_sm">
|
|
<header>SME2 single-multi FP dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_4way_dot_sm">
|
|
<header>SME2 single-multi four-way dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_float_sm">
|
|
<header>SME2 single-multi ternary FP two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_int_sm">
|
|
<header>SME2 single-multi ternary int two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_f16_sm">
|
|
<header>SME2 single-multi ternary FP16 two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_mla_long_long_sm">
|
|
<header>SME2 single-multi long long MLA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_115" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_fpdot_sm">
|
|
<header>SME2 single-multi FP dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_4way_dot_sm">
|
|
<header>SME2 single-multi four-way dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_float_sm">
|
|
<header>SME2 single-multi ternary FP four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_int_sm">
|
|
<header>SME2 single-multi ternary int four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_f16_sm">
|
|
<header>SME2 single-multi ternary FP16 four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_90" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_91" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_92" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op3" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_array_2a">
|
|
<header>SME2 Multi-vector - Multiple Array Vectors (Two registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">11x1xxxx00xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">110000011</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="0" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi2_zz_za_fma_long_mm">
|
|
<header>SME2 multiple vectors long FMA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_mixed_dot_mm">
|
|
<header>SME2 multiple vectors mixed dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">001xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_136" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">011xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_mla_long_mm">
|
|
<header>SME2 multiple vectors long MLA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_2way_dot_mm">
|
|
<header>SME2 multiple vectors two-way dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_float_mm">
|
|
<header>SME2 multiple vectors binary FP two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">00xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_int_mm">
|
|
<header>SME2 multiple vectors binary int two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">01xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_f16_mm">
|
|
<header>SME2 multiple vectors binary FP16 two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">00xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_151" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">01xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_138" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_148" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_149" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_281" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_282" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_mla_long_long_mm">
|
|
<header>SME2 multiple vectors long long MLA two sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0xxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_131" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_134" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0xx1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_132" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x0</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_133" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_f16_mm">
|
|
<header>SME2 multiple vectors ternary FP16 two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_135" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_fpdot_mm">
|
|
<header>SME2 multiple vectors FP dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">xx0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_z_za_4way_dot_mm">
|
|
<header>SME2 multiple vectors four-way dot product two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">0x0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_137" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">1xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_float_mm">
|
|
<header>SME2 multiple vectors ternary FP two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">00xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi2_zz_za_int_mm">
|
|
<header>SME2 multiple vectors ternary int two registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="5" width="5" name="op4" usename="1">
|
|
<c colspan="5">01xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_multi_array_2b">
|
|
<header>SME2 Multi-vector - Multiple Array Vectors (Four registers)</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">11x1xxxx10xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">110000011</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="14" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="0" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_multi4_zz_za_fma_long_mm">
|
|
<header>SME2 multiple vectors long FMA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_mixed_dot_mm">
|
|
<header>SME2 multiple vectors mixed dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">01xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_145" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">11xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_mla_long_mm">
|
|
<header>SME2 multiple vectors long MLA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">xx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_2way_dot_mm">
|
|
<header>SME2 multiple vectors two-way dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_float_mm">
|
|
<header>SME2 multiple vectors binary FP four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_int_mm">
|
|
<header>SME2 multiple vectors binary int four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_f16_mm">
|
|
<header>SME2 multiple vectors binary FP16 four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_153" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_147" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_144" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_284" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_285" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_286" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_287" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_mla_long_long_mm">
|
|
<header>SME2 multiple vectors long long MLA four sources</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">xxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_140" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_142" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">xx1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_283" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x0</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_141" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_f16_mm">
|
|
<header>SME2 multiple vectors ternary FP16 four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_143" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_fpdot_mm">
|
|
<header>SME2 multiple vectors FP dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_z_za_4way_dot_mm">
|
|
<header>SME2 multiple vectors four-way dot product four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_146" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_float_mm">
|
|
<header>SME2 multiple vectors ternary FP four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_multi4_zz_za_int_mm">
|
|
<header>SME2 multiple vectors ternary int four registers</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_150" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op3" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="6" width="2" name="op4" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="4" width="4" name="op5" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="mortlach_mem">
|
|
<header>SME Memory</header>
|
|
<decode>
|
|
<box hibit="30" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110000</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="9" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="1" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="mortlach_contig_load">
|
|
<header>SME load array vector (elements)</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_contig_store">
|
|
<header>SME store array vector (elements)</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_163" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_ctxt_ldst">
|
|
<header>SME save and restore array</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">xx000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_164" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">xx000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_289" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">xx!= 000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_292" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_zt_ldst">
|
|
<header>SME2 lookup table load/store</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_290" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_291" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_165" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">101x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_166" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">110x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_contig_qload">
|
|
<header>SME load array vector (quadwords)</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">1110</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="mortlach_contig_qstore">
|
|
<header>SME store array vector (quadwords)</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">1111</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_167" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="4" name="op0" usename="1">
|
|
<c colspan="4">111x</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="3" name="op4" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
</node>
|
|
<node iclass="unallocate1" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">0001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve">
|
|
<header>SVE encodings</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="28" width="4">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="9" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node groupname="sve_int_muladd_pred">
|
|
<header>SVE Integer Multiply-Add - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxxx1xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="14">
|
|
<c colspan="14" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_mlas_vvv_pred">
|
|
<header>SVE integer multiply-accumulate writing addend (predicated)</header>
|
|
<decode>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_mladdsub_vvv_pred">
|
|
<header>SVE integer multiply-add writing multiplicand (predicated)</header>
|
|
<decode>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_pred_bin">
|
|
<header>SVE Integer Binary Arithmetic - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx000xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_bin_pred_arit_0">
|
|
<header>SVE integer add/subtract vectors (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_arit_1">
|
|
<header>SVE integer min/max/difference (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_arit_2">
|
|
<header>SVE integer multiply vectors (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_div">
|
|
<header>SVE integer divide vectors (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_log">
|
|
<header>SVE bitwise logical operations (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_pred_red">
|
|
<header>SVE Integer Reduction</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_reduce_0">
|
|
<header>SVE integer add reduction (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_reduce_0q">
|
|
<header>SVE integer add reduction (quadwords)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_reduce_1">
|
|
<header>SVE integer min/max reduction (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_reduce_1q">
|
|
<header>SVE integer min/max reduction (quadwords)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_movprfx_pred">
|
|
<header>SVE constructive prefix (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_reduce_2">
|
|
<header>SVE bitwise logical reduction (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_reduce_2q">
|
|
<header>SVE bitwise logical reduction (quadwords)</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_pred_shift">
|
|
<header>SVE Bitwise Shift - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_bin_pred_shift_0">
|
|
<header>SVE bitwise shift by immediate (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_shift_1">
|
|
<header>SVE bitwise shift by vector (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_pred_shift_2">
|
|
<header>SVE bitwise shift by wide elements (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_pred_un">
|
|
<header>SVE Integer Unary Arithmetic - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_0" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_un_pred_arit_0">
|
|
<header>SVE integer unary operations (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_un_pred_arit_1">
|
|
<header>SVE bitwise unary operations (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_arit_0">
|
|
<header>SVE integer add/subtract vectors (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx000xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_int_unpred_logical">
|
|
<header>SVE Bitwise Logical - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_1" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_log">
|
|
<header>SVE bitwise logical operations (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_rotate_imm">
|
|
<header>sve_int_rotate_imm</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_tern_log">
|
|
<header>SVE2 bitwise ternary operations</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_index">
|
|
<header>SVE Index Generation</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0100xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">0100</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_index_ii">
|
|
<header>SVE index generation (immediate start, immediate increment)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_index_ri">
|
|
<header>SVE index generation (register start, immediate increment)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_index_ir">
|
|
<header>SVE index generation (immediate start, register increment)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_index_rr">
|
|
<header>SVE index generation (register start, register increment)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_alloca">
|
|
<header>SVE Stack Allocation</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0101xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">0101</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_arith_vl">
|
|
<header>SVE stack frame adjustment</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_arith_svl">
|
|
<header>Streaming SVE stack frame adjustment</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_read_vl_a">
|
|
<header>SVE stack frame size</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_read_svl_a">
|
|
<header>Streaming SVE stack frame size</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_unpred_arit_b">
|
|
<header>SVE2 Integer Multiply - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx011xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_mul_b">
|
|
<header>SVE2 integer multiply vectors (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="12" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_sqdmulh">
|
|
<header>SVE2 signed saturating doubling multiply high (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="12" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_2" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="12" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_int_unpred_shift">
|
|
<header>SVE Bitwise Shift - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="12" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="11" width="12">
|
|
<c colspan="12" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_bin_cons_shift_a">
|
|
<header>SVE bitwise shift by wide elements (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="12" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_shift_b">
|
|
<header>SVE bitwise shift by immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="12" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_misc_0_a">
|
|
<header>SVE address generation</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx1010xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_int_unpred_misc">
|
|
<header>SVE Integer Misc - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx1011xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">1011</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_bin_cons_misc_0_b">
|
|
<header>SVE floating-point trig select coefficient</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_misc_0_c">
|
|
<header>SVE floating-point exponential accelerator</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_bin_cons_misc_0_d">
|
|
<header>SVE constructive prefix (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_countelt">
|
|
<header>SVE Element Count</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_countvlv0">
|
|
<header>SVE saturating inc/dec vector by element count</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_count">
|
|
<header>SVE element count</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_4" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_countvlv1">
|
|
<header>SVE inc/dec vector by element count</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pred_pattern_a">
|
|
<header>SVE inc/dec register by element count</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_5" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_3" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pred_pattern_b">
|
|
<header>SVE saturating inc/dec register by element count</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_maskimm">
|
|
<header>SVE Bitwise Immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx00xxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="19" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="17" width="18">
|
|
<c colspan="18" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_dup_mask_imm">
|
|
<header>SVE broadcast bitmask immediate</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="19" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_log_imm">
|
|
<header>SVE bitwise logical with immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 11</c>
|
|
</box>
|
|
<box hibit="19" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_203" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="19" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_wideimm_pred">
|
|
<header>SVE Integer Wide Immediate - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx01xxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_dup_imm_pred">
|
|
<header>SVE copy integer immediate (predicated)</header>
|
|
<decode>
|
|
<box hibit="15" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_6" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="3" name="op0" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_dup_fpimm_pred">
|
|
<header>SVE copy floating-point immediate (predicated)</header>
|
|
<decode>
|
|
<box hibit="15" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_7" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_perm_dup_i">
|
|
<header>SVE broadcast indexed element</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_perm_quads_a">
|
|
<header>SVE Permute Vector - Quadwords</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001001</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="6">
|
|
<c colspan="6">001001</c>
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_dupq_i">
|
|
<header>sve_int_perm_dupq_i</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_extq">
|
|
<header>sve_int_perm_extq</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_18" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_19" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_perm_tbl_3src">
|
|
<header>SVE table lookup (three sources)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx00101x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_tbl">
|
|
<header>SVE table lookup</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001100</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_tbxquads">
|
|
<header>sve_int_perm_tbxquads</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001101</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_perm_unpred_d">
|
|
<header>SVE Permute Vector - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001110</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="6">
|
|
<c colspan="6">001110</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="8" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_dup_r">
|
|
<header>SVE broadcast general register</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_insrs">
|
|
<header>SVE insert general register</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_175" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">x10</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_174" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_mov_v2p">
|
|
<header>SVE move predicate from vector</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx0</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_10" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx0</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_mov_p2v">
|
|
<header>SVE move predicate into vector</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_11" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_unpk">
|
|
<header>SVE unpack vector elements</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_insrv">
|
|
<header>SVE insert SIMD&FP scalar register</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_183" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_182" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">1x1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_reverse_z">
|
|
<header>SVE reverse vector elements</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_205" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_0" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx001111</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_perm_predicates">
|
|
<header>SVE Permute Predicate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx010xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="8" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_punpk">
|
|
<header>SVE unpack predicate elements</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">1000x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_184" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">1000x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_185" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">1000x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_186" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">1000x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_bin_perm_pp">
|
|
<header>SVE permute predicate elements</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">0xxxx</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">xxx0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_173" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">0xxxx</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_reverse_p">
|
|
<header>SVE reverse predicate elements</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10100</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_16" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10101</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_181" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10x0x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_180" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10x0x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">x100</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_179" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10x0x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">xx10</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_178" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10x0x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_15" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">10x1x</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_17" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5">11xxx</c>
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_172" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5" name="op1" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="12" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_perm_bin_perm_zz">
|
|
<header>SVE permute vector elements</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx011xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_perm_pred">
|
|
<header>SVE Permute Vector - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx10xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_cpy_v">
|
|
<header>SVE copy SIMD&FP scalar register to vector (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_compact">
|
|
<header>SVE compress active elements</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_last_r">
|
|
<header>SVE extract element to general register</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_last_v">
|
|
<header>SVE extract element to SIMD&FP scalar register</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_rev">
|
|
<header>SVE reverse within elements</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_9" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_cpy_r">
|
|
<header>SVE copy general register to vector (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_12" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_clast_zz">
|
|
<header>SVE conditionally broadcast element to vector</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_clast_vz">
|
|
<header>SVE conditionally extract element to SIMD&FP scalar</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_splice">
|
|
<header>SVE vector splice (destructive)</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_perm_splice">
|
|
<header>SVE2 vector splice (constructive)</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_13" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_revd">
|
|
<header>SVE reverse doublewords</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_176" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_177" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_8" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_14" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_clast_rz">
|
|
<header>SVE conditionally extract element to general register</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_204" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="19" width="3" name="op1" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_sel_vvv">
|
|
<header>SVE select vector elements (predicated)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_perm_extract">
|
|
<header>SVE Permute Vector - Extract</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">10x1xxxxx000xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">000001010</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_extract_i">
|
|
<header>SVE extract vector (immediate offset, destructive)</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_perm_extract_i">
|
|
<header>SVE2 extract vector (immediate offset, constructive)</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_perm_inter_long">
|
|
<header>SVE Permute Vector - Segments</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">11x1xxxxx000xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="9">
|
|
<c colspan="9">000001011</c>
|
|
</box>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_perm_bin_long_perm_zz">
|
|
<header>SVE permute vector segments</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_20" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_cmpvec">
|
|
<header>SVE Integer Compare - Vectors</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="6">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="14">
|
|
<c colspan="14" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_cmp_0">
|
|
<header>SVE integer compare vectors</header>
|
|
<decode>
|
|
<box hibit="14" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_cmp_1">
|
|
<header>SVE integer compare with wide elements</header>
|
|
<decode>
|
|
<box hibit="14" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_ucmp_vi">
|
|
<header>SVE integer compare with unsigned immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_scmp_vi">
|
|
<header>SVE integer compare with signed immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxxx0xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pred_log">
|
|
<header>SVE predicate logical operations</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx00xxxx01xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_pred_gen_b">
|
|
<header>SVE Propagate Break</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx00xxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="13" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="9" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="8" width="9">
|
|
<c colspan="9" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_brkp">
|
|
<header>SVE propagate break from previous partition</header>
|
|
<decode>
|
|
<box hibit="9" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_21" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="9" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_pred_gen_c">
|
|
<header>SVE Partition Break</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx01xxxx01xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="13" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="8" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_brkn">
|
|
<header>SVE propagate break to next partition</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_23" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_22" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">x000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_193" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_191" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">xx1x</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_189" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_29" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_206" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_break">
|
|
<header>SVE partition break condition</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4" name="op1" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_pred_gen_d">
|
|
<header>SVE Predicate Misc</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx01xxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_ptest">
|
|
<header>SVE predicate test</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_194" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">0100</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_192" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x10</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_190" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx1</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_188" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pfirst">
|
|
<header>SVE predicate first active</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_207" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pfalse">
|
|
<header>SVE predicate zero</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_208" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_rdffr">
|
|
<header>SVE predicate read from FFR (predicated)</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_25" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pnext">
|
|
<header>SVE predicate next active</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_26" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_27" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_rdffr_2">
|
|
<header>SVE predicate read from FFR (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_210" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_24" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_ptrue">
|
|
<header>SVE predicate initialize</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_196" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_209" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_195" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_198" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">110x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_197" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4">1x1x</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_187" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="19" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op4" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_cmpgpr">
|
|
<header>SVE Integer Compare - Scalars</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx00xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="9" width="6">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_while_rr">
|
|
<header>SVE integer compare scalar count and limit</header>
|
|
<decode>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_cterm">
|
|
<header>SVE conditionally terminate scalars</header>
|
|
<decode>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_211" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_whilenc">
|
|
<header>SVE pointer conflict compare</header>
|
|
<decode>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_212" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="13" width="2" name="op0" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_int_pred_dup">
|
|
<header>SVE broadcast predicate element</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx01xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_while_pn">
|
|
<header>SVE Scalar Integer Compare - Predicate-as-counter</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx01xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="4" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="2" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_ctr_to_mask">
|
|
<header>SVE extract mask predicate from predicate-as-counter</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pn_ptrue">
|
|
<header>sve_int_pn_ptrue</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6">000000</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_28" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6">000000</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_213" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6">!= 000000</c>
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_214" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_while_rr_pair">
|
|
<header>SVE integer compare scalar count and limit (predicate pair)</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">01x</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_while_rr_pn">
|
|
<header>SVE integer compare scalar count and limit (predicate-as-counter)</header>
|
|
<decode>
|
|
<box hibit="20" width="5" name="op0" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">x0x</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="op2" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="3" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_wideimm_unpred">
|
|
<header>SVE Integer Wide Immediate - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="13" width="14">
|
|
<c colspan="14" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_arith_imm0">
|
|
<header>SVE integer add/subtract immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_arith_imm1">
|
|
<header>SVE integer min/max immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_arith_imm2">
|
|
<header>SVE integer multiply immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_dup_imm">
|
|
<header>SVE broadcast integer immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_dup_fpimm">
|
|
<header>SVE broadcast floating-point immediate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_pred_count_a">
|
|
<header>SVE Predicate Count</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx100xxx10xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="8" width="9">
|
|
<c colspan="9" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_pcount_pn">
|
|
<header>SVE predicate count (predicate-as-counter)</header>
|
|
<decode>
|
|
<box hibit="13" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_215" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="13" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_pcount_pred">
|
|
<header>SVE predicate count</header>
|
|
<decode>
|
|
<box hibit="13" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_pred_count_b">
|
|
<header>SVE Inc/Dec by Predicate Count</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx101xxx1000xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_count_v_sat">
|
|
<header>SVE saturating inc/dec vector by predicate count</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_count_r_sat">
|
|
<header>SVE saturating inc/dec register by predicate count</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_count_v">
|
|
<header>SVE inc/dec vector by predicate count</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_count_r">
|
|
<header>SVE inc/dec register by predicate count</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="11" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_pred_wrffr">
|
|
<header>SVE Write FFR</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx101xxx1001xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">00100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">1001</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_int_wrffr">
|
|
<header>SVE FFR write from predicate</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_setffr">
|
|
<header>SVE FFR initialise</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_202" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_201" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_200" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">xx1x</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_199" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4">xxx1</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_216" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_217" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_218" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="11" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="8" width="4" name="op3" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_1" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx101xxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_2" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx11xxxx10xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_intx_muladd_unpred">
|
|
<header>SVE Integer Multiply-Add - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_dot">
|
|
<header>SVE integer dot product (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">0000x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qdmlalbt">
|
|
<header>SVE2 saturating multiply-add interleaved long</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">0001x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cdot">
|
|
<header>SVE2 complex integer dot product</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">001xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cmla">
|
|
<header>SVE2 complex integer multiply-add</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">01xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mlal_long">
|
|
<header>SVE2 integer multiply-add long</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">10xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qdmlal_long">
|
|
<header>SVE2 saturating multiply-add long</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">110xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qrdmlah">
|
|
<header>SVE2 saturating multiply-add high</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">1110x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mixed_dot">
|
|
<header>SVE mixed sign dot product</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">11110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_30" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="14" width="5" name="op0" usename="1">
|
|
<c colspan="5">11111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_intx_predicated">
|
|
<header>SVE2 Integer - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx10xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="16" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_accumulate_long_pairs">
|
|
<header>SVE2 integer pairwise add and accumulate long</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_31" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">0011</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_32" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">011x</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_pred_arith_unary">
|
|
<header>SVE2 integer unary operations (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x0x</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_bin_pred_shift_sat_round">
|
|
<header>SVE2 saturating/rounding bitwise shift left (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_pred_arith_binary">
|
|
<header>SVE2 integer halving add/subtract (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_arith_binary_pairs">
|
|
<header>SVE2 integer pairwise arithmetic</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_pred_arith_binary_sat">
|
|
<header>SVE2 saturating add/subtract</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">11xx</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_33" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">11xx</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_intx_clamp">
|
|
<header>SVE integer clamp</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx11000x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_4" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx1101xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_int_perm_binquads">
|
|
<header>SVE permute vector elements (quadwords)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx111xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_intx_by_indexed_elem">
|
|
<header>SVE Multiply - Indexed</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000100</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_dot_by_indexed_elem">
|
|
<header>SVE integer dot product (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">00000x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mla_by_indexed_elem">
|
|
<header>SVE2 integer multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">00001x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qrdmlah_by_indexed_elem">
|
|
<header>SVE2 saturating multiply-add high (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">00010x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mixed_dot_by_indexed_elem">
|
|
<header>SVE mixed sign dot product (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">00011x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qdmla_long_by_indexed_elem">
|
|
<header>SVE2 saturating multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">001xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cdot_by_indexed_elem">
|
|
<header>SVE2 complex integer dot product (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">0100xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_34" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">0101xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cmla_by_indexed_elem">
|
|
<header>SVE2 complex integer multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">0110xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qrdcmla_by_indexed_elem">
|
|
<header>SVE2 complex saturating multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">0111xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mla_long_by_indexed_elem">
|
|
<header>SVE2 integer multiply-add long (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">10xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mul_long_by_indexed_elem">
|
|
<header>SVE2 integer multiply long (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">110xxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qdmul_long_by_indexed_elem">
|
|
<header>SVE2 saturating multiply (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">1110xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_qdmulh_by_indexed_elem">
|
|
<header>SVE2 saturating multiply high (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">11110x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mul_by_indexed_elem">
|
|
<header>SVE2 integer multiply (indexed)</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">111110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_35" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="15" width="6" name="op0" usename="1">
|
|
<c colspan="6">111111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_3" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0x10xxxxx11001x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_dot2">
|
|
<header>SVE two-way dot product</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0000xxxxx11001x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_dot2_by_indexed_elem">
|
|
<header>SVE two-way dot product (indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0100xxxxx11001x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_intx_cons_widening">
|
|
<header>SVE2 Widening Integer Arithmetic</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_cons_arith_long">
|
|
<header>SVE2 integer add/subtract long</header>
|
|
<decode>
|
|
<box hibit="14" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cons_arith_wide">
|
|
<header>SVE2 integer add/subtract wide</header>
|
|
<decode>
|
|
<box hibit="14" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_cons_mul_long">
|
|
<header>SVE2 integer multiply long</header>
|
|
<decode>
|
|
<box hibit="14" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_intx_constructive">
|
|
<header>SVE Misc</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx10xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_shift_long">
|
|
<header>SVE2 bitwise shift left long</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_43" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_clong">
|
|
<header>SVE2 integer add/subtract interleaved long</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_eorx">
|
|
<header>SVE2 bitwise exclusive-or interleaved</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">010x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_mmla">
|
|
<header>SVE integer matrix multiply accumulate</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">0110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_36" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_perm_bit">
|
|
<header>SVE2 bitwise permute</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="4" name="op1" usename="1">
|
|
<c colspan="4">11xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_intx_acc">
|
|
<header>SVE2 Accumulate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="16" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_cadd">
|
|
<header>SVE2 complex integer add</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_219" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_aba_long">
|
|
<header>SVE2 integer absolute difference and accumulate long</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_adc_long">
|
|
<header>SVE2 integer add/subtract long with carry</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_sra">
|
|
<header>SVE2 bitwise shift right and accumulate</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_shift_insert">
|
|
<header>SVE2 bitwise shift and insert</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_aba">
|
|
<header>SVE2 integer absolute difference and accumulate</header>
|
|
<decode>
|
|
<box hibit="20" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="13" width="3" name="op1" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_intx_narrowing">
|
|
<header>SVE2 Narrowing</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="4" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_extract_narrow">
|
|
<header>SVE2 saturating extract narrow</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_multi_extract_narrow">
|
|
<header>SME2 multi-vec extract narrow</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_38" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_39" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_224" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_shift_narrow">
|
|
<header>SVE2 bitwise shift right narrow</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_multi_shift_narrow">
|
|
<header>SME2 multi-vec shift narrow</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_44" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_45" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_46" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_intx_arith_narrow">
|
|
<header>SVE2 integer add/subtract narrow high part</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="18" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="16" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="2" name="op3" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="10" width="1" name="op4" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="5" width="1" name="op5" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_intx_match">
|
|
<header>SVE2 character match</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_intx_histseg">
|
|
<header>SVE2 Histogram Computation - Segment</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_intx_histseg">
|
|
<header>SVE2 histogram generation (segment)</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_220" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="12" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_intx_histcnt">
|
|
<header>SVE2 histogram generation (vector)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx110xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_intx_crypto">
|
|
<header>SVE2 Crypto Extensions</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxx111xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01000101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="10" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="4" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_crypto_unary">
|
|
<header>SVE2 crypto unary operations</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5">00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_221" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5">!= 00000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_37" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_40" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_41" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_crypto_binary_dest">
|
|
<header>SVE2 crypto destructive binary operations</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_42" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_222" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_223" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_crypto_binary_const">
|
|
<header>SVE2 crypto constructive binary operations</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="12" width="2" name="op2" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="op3" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_fp_fcmla">
|
|
<header>SVE floating-point complex multiply-add (predicated)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0xxxxx0xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fcadd">
|
|
<header>SVE floating-point complex add (predicated)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00000x100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_5" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00000x101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_6" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00000x11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_7" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00001x1xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_8" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0001xx1xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_9" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0010xx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fcvt2">
|
|
<header>SVE floating-point convert precision odd elements</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0010xx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_10" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0010xx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_11" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx001100100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_12" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00110011xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_13" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx0011011xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_14" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx00111x1xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_pairwise">
|
|
<header>SVE2 floating-point pairwise operations</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx010xxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fast_redq">
|
|
<header>SVE floating-point recursive reduction (quadwords)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx010xxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_15" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx010xxx11xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_16" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx011xxx1xxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fma_by_indexed_elem">
|
|
<header>SVE floating-point multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0000xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fcmla_by_indexed_elem">
|
|
<header>SVE floating-point complex multiply-add (indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0001xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fmul_by_indexed_elem">
|
|
<header>SVE floating-point multiply (indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0010x0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_clamp">
|
|
<header>SVE FP clamp</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx001001</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_17" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx001011</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_18" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx0011xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_fp_fma_w_by_indexed_elem">
|
|
<header>SVE Floating Point Widening Multiply-Add - Indexed</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx01x0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100100</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="11" width="12">
|
|
<c colspan="12" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_fdot_by_indexed_elem">
|
|
<header>SVE BFloat16 floating-point dot product (indexed)</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_47" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fma_long_by_indexed_elem">
|
|
<header>SVE floating-point multiply-add long (indexed)</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="13" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_19" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx01x1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_fp_fma_w">
|
|
<header>SVE Floating Point Widening Multiply-Add</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx10x00x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100100</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="22" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="2">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="13" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="12" width="2">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="10" width="11">
|
|
<c colspan="11" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_fdot">
|
|
<header>SVE BFloat16 floating-point dot product</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fma_long">
|
|
<header>SVE floating-point multiply-add long</header>
|
|
<decode>
|
|
<box hibit="23" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="unalloc_20" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx10x01x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_21" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx10x1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_22" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx110xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_23" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx111000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_fmmla">
|
|
<header>SVE floating point matrix multiply accumulate</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx111001</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_24" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx11101x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_25" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">0xx1xxxxx1111xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_3op_p_pd">
|
|
<header>SVE floating-point compare vectors</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxxx1xxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_3op_u_zd">
|
|
<header>SVE floating-point arithmetic (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx000xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_fp_pred">
|
|
<header>SVE Floating Point Arithmetic - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx100xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="5" width="6">
|
|
<c colspan="6" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_2op_p_zds">
|
|
<header>SVE floating-point arithmetic (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_ftmad">
|
|
<header>SVE floating-point trig multiply-add coefficient</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_226" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_2op_i_p_zds">
|
|
<header>SVE floating-point arithmetic with immediate (predicated)</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_227" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="20" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="op1" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="9" width="4" name="op2" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_fp_unary">
|
|
<header>SVE Floating Point Unary Operations - Predicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx0xxxxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_2op_p_zd_a">
|
|
<header>SVE floating-point round to integral value</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">00x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_2op_p_zd_b_0">
|
|
<header>SVE floating-point convert precision</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_2op_p_zd_b_1">
|
|
<header>SVE floating-point unary operations</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_2op_p_zd_c">
|
|
<header>SVE integer convert to floating-point</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_2op_p_zd_d">
|
|
<header>SVE floating-point convert to integer</header>
|
|
<decode>
|
|
<box hibit="20" width="3" name="op0" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node iclass="sve_fp_fast_red">
|
|
<header>SVE floating-point recursive reduction</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx000xxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="unalloc_26" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx001xxx0010xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="sve_fp_unary_unpred">
|
|
<header>SVE Floating Point Unary Operations - Unpredicated</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx001xxx0011xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="18" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="15" width="4">
|
|
<c colspan="4">0011</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_2op_u_zd">
|
|
<header>SVE floating-point reciprocal estimate (unpredicated)</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_225" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="11" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_fp_cmpzero">
|
|
<header>SVE Floating Point Compare - with Zero</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx010xxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_2op_p_pd">
|
|
<header>SVE floating-point compare with zero</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_48" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_fp_slowreduce">
|
|
<header>SVE Floating Point Accumulating Reduction</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx011xxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="3">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="17" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_2op_p_vd">
|
|
<header>SVE floating-point serial reduction (predicated)</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_49" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="18" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_fp_fma">
|
|
<header>SVE Floating Point Multiply-Add</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">1xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="8">
|
|
<c colspan="8">01100101</c>
|
|
</box>
|
|
<box hibit="23" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="21" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="14" width="15">
|
|
<c colspan="15" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_fp_3op_p_zds_a">
|
|
<header>SVE floating-point multiply-accumulate writing addend</header>
|
|
<decode>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_fp_3op_p_zds_b">
|
|
<header>SVE floating-point multiply-accumulate writing multiplicand</header>
|
|
<decode>
|
|
<box hibit="15" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_mem32">
|
|
<header>SVE Memory - 32-bit Gather and Unsized Contiguous</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1000010</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="12" width="8">
|
|
<c colspan="8" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_32b_prfm_sv">
|
|
<header>SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_55" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_gld_sv_a">
|
|
<header>SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_gld_sv_b">
|
|
<header>SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_pfill">
|
|
<header>SVE load predicate register</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_56" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_fill">
|
|
<header>SVE load vector register</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_57" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0x1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_prfm_si">
|
|
<header>SVE contiguous prefetch (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_58" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_gld_vs">
|
|
<header>SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 11</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_gldnt_vs">
|
|
<header>SVE2 32-bit gather non-temporal load (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_prfm_ss">
|
|
<header>SVE contiguous prefetch (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_prfm_vi">
|
|
<header>SVE 32-bit gather prefetch (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_54" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">11x</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_32b_gld_vi">
|
|
<header>SVE 32-bit gather load (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_ld_dup">
|
|
<header>SVE load and broadcast element</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memcld">
|
|
<header>SVE Memory - Contiguous Load</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1010010</c>
|
|
</box>
|
|
<box hibit="24" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_cldnt_si">
|
|
<header>SVE contiguous non-temporal load (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cld_si_q">
|
|
<header>SVE contiguous load (quadwords, scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_eldq_si">
|
|
<header>SVE load multiple structures (quadwords, scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cld_ss_q">
|
|
<header>SVE contiguous load (quadwords, scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cldnt_ss">
|
|
<header>SVE contiguous non-temporal load (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_eldq_ss">
|
|
<header>SVE load multiple structures (quadwords, scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_66" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_eld_si">
|
|
<header>SVE load multiple structures (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_228" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_229" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_eld_ss">
|
|
<header>SVE load multiple structures (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_ldqr_si">
|
|
<header>SVE load and broadcast quadword (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cld_si">
|
|
<header>SVE contiguous load (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cldnf_si">
|
|
<header>SVE contiguous non-fault load (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_ldqr_ss">
|
|
<header>SVE load and broadcast quadword (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cld_ss">
|
|
<header>SVE contiguous load (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cldff_ss">
|
|
<header>SVE contiguous first-fault load (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_mem64">
|
|
<header>SVE Memory - 64-bit Gather</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1100010</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="12" width="8">
|
|
<c colspan="8" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_64b_gldq_vs">
|
|
<header>SVE2 128-bit gather load (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_161" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_prfm_sv2">
|
|
<header>SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_162" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_prfm_sv">
|
|
<header>SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_288" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gld_sv2">
|
|
<header>SVE 64-bit gather load (scalar plus 64-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gld_sv">
|
|
<header>SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x1</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_prfm_vi">
|
|
<header>SVE 64-bit gather prefetch (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_160" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gldnt_vs">
|
|
<header>SVE2 64-bit gather non-temporal load (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1x0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gld_vi">
|
|
<header>SVE 64-bit gather load (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gld_vs2">
|
|
<header>SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">1xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_64b_gld_vs">
|
|
<header>SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="24" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op1" usename="1">
|
|
<c colspan="2">x0</c>
|
|
</box>
|
|
<box hibit="15" width="3" name="op2" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memst_cs">
|
|
<header>SVE Memory - Contiguous Store and Unsized Contiguous</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx0x0xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="8">
|
|
<c colspan="8" />
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="3" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_estq_si">
|
|
<header>SVE store multiple structures (quadwords, scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_168" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_estq_ss">
|
|
<header>SVE store multiple structures (quadwords, scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">0xx</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_169" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">10x</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_pspill">
|
|
<header>SVE store predicate register</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_170" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_spill">
|
|
<header>SVE store vector register</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_171" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cst_ss">
|
|
<header>SVE contiguous store (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 110</c>
|
|
</box>
|
|
<box hibit="21" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="14" width="1" name="op2" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op3" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memsst_nt">
|
|
<header>SVE Memory - Non-temporal and Quadword Scatter Store</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx001xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="21" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">001</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_sstq_64b_vs">
|
|
<header>SVE2 128-bit scatter store (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">000</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_293" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">!= 000</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sstnt_64b_vs">
|
|
<header>SVE2 64-bit scatter non-temporal store (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">xx0</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sstnt_32b_vs">
|
|
<header>SVE2 32-bit scatter non-temporal store (vector plus scalar)</header>
|
|
<decode>
|
|
<box hibit="24" width="3" name="op0" usename="1">
|
|
<c colspan="3">xx1</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memcst_nt">
|
|
<header>SVE Memory - Non-temporal and Multi-register Contiguous Store</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx011xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">011</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_cstnt_ss">
|
|
<header>SVE contiguous non-temporal store (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_est_ss">
|
|
<header>SVE store multiple structures (scalar plus scalar)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memst_ss">
|
|
<header>SVE Memory - Scatter with Optional Sign Extend</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx1x0xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="14" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="13" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_sst_vs_a">
|
|
<header>SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_sv_a">
|
|
<header>SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_vs_b">
|
|
<header>SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_sv_b">
|
|
<header>SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memst_ss2">
|
|
<header>SVE Memory - Scatter</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx101xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_sst_vs2">
|
|
<header>SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_sv2">
|
|
<header>SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_vi_a">
|
|
<header>SVE 64-bit scatter store (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_sst_vi_b">
|
|
<header>SVE 32-bit scatter store (vector plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="sve_memst_si">
|
|
<header>SVE Memory - Contiguous Store with Immediate Offset</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op1" usename="1">
|
|
<c colspan="15">xxxxxxxxx111xxx</c>
|
|
</box>
|
|
<box hibit="4" width="1" name="op2" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="7">
|
|
<c colspan="7">1110010</c>
|
|
</box>
|
|
<box hibit="24" width="2">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="19" width="4">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="15" width="3">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="12" width="13">
|
|
<c colspan="13" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="sve_mem_cstnt_si">
|
|
<header>SVE contiguous non-temporal store (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_est_si">
|
|
<header>SVE store multiple structures (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="sve_mem_cst_si">
|
|
<header>SVE contiguous store (scalar plus immediate)</header>
|
|
<decode>
|
|
<box hibit="22" width="2" name="op0" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="20" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
</node>
|
|
<node iclass="unallocate2" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">0011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node groupname="dpimm">
|
|
<header>Data Processing -- Immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="3">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="28" width="3">
|
|
<c colspan="3">100</c>
|
|
</box>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="21" width="22">
|
|
<c colspan="22" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="pcreladdr">
|
|
<header>PC-rel. addressing</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="addsub_imm">
|
|
<header>Add/subtract (immediate)</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">010x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="addsub_immtags">
|
|
<header>Add/subtract (immediate, with tags)</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">0110</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="minmax_imm">
|
|
<header>Min/max (immediate)</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="log_imm">
|
|
<header>Logical (immediate)</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">100x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="movewide">
|
|
<header>Move wide (immediate)</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">101x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="bitfield">
|
|
<header>Bitfield</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">110x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="extract">
|
|
<header>Extract</header>
|
|
<decode>
|
|
<box hibit="25" width="4" name="op0" usename="1">
|
|
<c colspan="4">111x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="control">
|
|
<header>Branches, Exception Generating and System instructions</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">101x</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3" />
|
|
</box>
|
|
<box hibit="28" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14" />
|
|
</box>
|
|
<box hibit="11" width="7">
|
|
<c colspan="7" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="condbranch">
|
|
<header>Conditional branch (immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">010</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="exception">
|
|
<header>Exception generation</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">00xxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="systeminstrswithreg">
|
|
<header>System instructions with register argument</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">01000000110001</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="hints">
|
|
<header>Hints</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">01000000110010</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5">11111</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="barriers">
|
|
<header>Barriers</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">01000000110011</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="pstate">
|
|
<header>PSTATE</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0100000xxx0100</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="systemresult">
|
|
<header>System with result</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0100100xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="systeminstrs">
|
|
<header>System instructions</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0100x01xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="systemmove">
|
|
<header>System register move</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0100x1xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="syspairinstrs">
|
|
<header>System pair instructions</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0101x01xxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="systemmovepr">
|
|
<header>System register pair move</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0101x1xxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="branch_reg">
|
|
<header>Unconditional branch (register)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">110</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">1xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="branch_imm">
|
|
<header>Unconditional branch (immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">x00</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14" />
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="compbranch">
|
|
<header>Compare and branch (immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">0xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="testbranch">
|
|
<header>Test and branch (immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="3" name="op0" usename="1">
|
|
<c colspan="3">x01</c>
|
|
</box>
|
|
<box hibit="25" width="14" name="op1" usename="1">
|
|
<c colspan="14">1xxxxxxxxxxxxx</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op2" usename="1">
|
|
<c colspan="5" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="ldst">
|
|
<header>Loads and Stores</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">x1x0</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="27" width="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="25" width="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="comswappr">
|
|
<header>Compare and swap pair</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00x1xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdlse">
|
|
<header>Advanced SIMD load/store multiple structures</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00x000000xxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_90" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00xxxxxx1xxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdlsep">
|
|
<header>Advanced SIMD load/store multiple structures (post-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">01x0xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_85" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdlso">
|
|
<header>Advanced SIMD load/store single structure</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">10xx0000xxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdlsop">
|
|
<header>Advanced SIMD load/store single structure (post-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">11xxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_94" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">x0xx1xxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_93" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">x0xxx1xxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_92" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">x0xxxx1xxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_91" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">x0xxxxx1xxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="rcwcomswap">
|
|
<header>RCW compare and swap</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx1xxxxx000010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="rcwcomswappr">
|
|
<header>RCW compare and swap pair</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx1xxxxx000011</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="memop_128">
|
|
<header>128-bit atomic memory operations</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx1xxxxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_gcs">
|
|
<header>GCS load/store</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1101</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1000111110xxx11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldsttags">
|
|
<header>Load/store memory tags</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1101</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx1xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstexclp">
|
|
<header>Load/store exclusive pair</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00x1xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_83" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1x00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstexclr">
|
|
<header>Load/store exclusive register</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00x0xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstord">
|
|
<header>Load/store ordered</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">01x0xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="comswap">
|
|
<header>Compare and swap</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx00</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">01x1xxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldiappstilp">
|
|
<header>LDIAPP/STILP</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">10x0xxxxxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldapstl_writeback">
|
|
<header>LDAPR/STLR (writeback)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">11x000000000010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldapstl_unscaled">
|
|
<header>LDAPR/STLR (unscaled immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx0xxxxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldapstl_simd">
|
|
<header>LDAPR/STLR (SIMD&FP)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx0xxxxxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="loadlit">
|
|
<header>Load register (literal)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xxxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="memcms">
|
|
<header>Memory Copy and Memory Set</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx01</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xx0xxxxxxxxx01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstnapair_offs">
|
|
<header>Load/store no-allocate pair (offset)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx10</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">00xxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstpair_post">
|
|
<header>Load/store register pair (post-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx10</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">01xxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstpair_off">
|
|
<header>Load/store register pair (offset)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx10</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">10xxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldstpair_pre">
|
|
<header>Load/store register pair (pre-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx10</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">11xxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_unscaled">
|
|
<header>Load/store register (unscaled immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx0xxxxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_immpost">
|
|
<header>Load/store register (immediate post-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx0xxxxxxxxx01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_unpriv">
|
|
<header>Load/store register (unprivileged)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx0xxxxxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_immpre">
|
|
<header>Load/store register (immediate pre-indexed)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx0xxxxxxxxx11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="memop">
|
|
<header>Atomic memory operations</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_regoff">
|
|
<header>Load/store register (register offset)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_pac">
|
|
<header>Load/store register (pac)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">0xx1xxxxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="ldst_pos">
|
|
<header>Load/store register (unsigned immediate)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">xx11</c>
|
|
</box>
|
|
<box hibit="26" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="24" width="15" name="op2" usename="1">
|
|
<c colspan="15">1xxxxxxxxxxxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="dpreg">
|
|
<header>Data Processing -- Register</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="29" width="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="27" width="3">
|
|
<c colspan="3">101</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="20" width="5">
|
|
<c colspan="5" />
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="dp_2src">
|
|
<header>Data-processing (2 source)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0110</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="dp_1src">
|
|
<header>Data-processing (1 source)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0110</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="log_shift">
|
|
<header>Logical (shifted register)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0xxx</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="addsub_shift">
|
|
<header>Add/subtract (shifted register)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">1xx0</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="addsub_ext">
|
|
<header>Add/subtract (extended register)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">1xx1</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="addsub_carry">
|
|
<header>Add/subtract (with carry)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6">000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="rmif">
|
|
<header>Rotate right into flags</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6">x00001</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="setf">
|
|
<header>Evaluate into flags</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6">xx0010</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="condcmp_reg">
|
|
<header>Conditional compare (register)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6">xxxx0x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="condcmp_imm">
|
|
<header>Conditional compare (immediate)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6">xxxx1x</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="condsel">
|
|
<header>Conditional select</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">0100</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="dp_3src">
|
|
<header>Data-processing (3 source)</header>
|
|
<decode>
|
|
<box hibit="30" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="1" name="op1" usename="1">
|
|
<c colspan="1">1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="op2" usename="1">
|
|
<c colspan="4">1xxx</c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
<node groupname="simd-dp">
|
|
<header>Data Processing -- Scalar Floating-Point and Advanced SIMD</header>
|
|
<decode>
|
|
<box hibit="31" width="1" name="op0" usename="1">
|
|
<c colspan="1" />
|
|
</box>
|
|
<box hibit="28" width="4" name="op1" usename="1">
|
|
<c colspan="4">x111</c>
|
|
</box>
|
|
</decode>
|
|
<regdiagram form="32">
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="27" width="3">
|
|
<c colspan="3">111</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2" />
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9" />
|
|
</box>
|
|
<box hibit="9" width="10">
|
|
<c colspan="10" />
|
|
</box>
|
|
</regdiagram>
|
|
<node iclass="UNALLOCATED_advsimd_26" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_27" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0010</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="cryptoaes">
|
|
<header>Cryptographic AES</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="cryptosha3">
|
|
<header>Cryptographic three-register SHA</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0101</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_52" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0101</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="cryptosha2">
|
|
<header>Cryptographic two-register SHA</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0101</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_29" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0110</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_53" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_63" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x101</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdone">
|
|
<header>Advanced SIMD scalar copy</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_55" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_65" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdsamefp16">
|
|
<header>Advanced SIMD scalar three same FP16</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx00xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_57" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx01xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdmiscfp16">
|
|
<header>Advanced SIMD scalar two-register miscellaneous FP16</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">1111</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_49" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx1xxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdsame2">
|
|
<header>Advanced SIMD scalar three same extra</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx1xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdmisc">
|
|
<header>Advanced SIMD scalar two-register miscellaneous</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x100</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdpair">
|
|
<header>Advanced SIMD scalar pairwise</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x110</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_67" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">1xxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_68" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">x1xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisddiff">
|
|
<header>Advanced SIMD scalar three different</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdsame">
|
|
<header>Advanced SIMD scalar three same</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdshf">
|
|
<header>Advanced SIMD scalar shift by immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_70" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asisdelem">
|
|
<header>Advanced SIMD scalar x indexed element</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">01x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdtbl">
|
|
<header>Advanced SIMD table lookup</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdperm">
|
|
<header>Advanced SIMD permute</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x00</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdext">
|
|
<header>Advanced SIMD extract</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0x10</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdins">
|
|
<header>Advanced SIMD copy</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_19" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_31" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">0111</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdsamefp16">
|
|
<header>Advanced SIMD three same (FP16)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx00xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_21" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx01xxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdmiscfp16">
|
|
<header>Advanced SIMD two-register miscellaneous (FP16)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">1111</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_13" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx1xxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdsame2">
|
|
<header>Advanced SIMD three-register extension</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx1xxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdmisc">
|
|
<header>Advanced SIMD two-register miscellaneous</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x100</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdall">
|
|
<header>Advanced SIMD across lanes</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x110</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">00xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_33" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">1xxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_34" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">x1xxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimddiff">
|
|
<header>Advanced SIMD three different</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxx00</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdsame">
|
|
<header>Advanced SIMD three same</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdimm">
|
|
<header>Advanced SIMD modified immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">0000</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdshf">
|
|
<header>Advanced SIMD shift by immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">10</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_36" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">11</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx1</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="asimdelem">
|
|
<header>Advanced SIMD vector x indexed element</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">0xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxxx0</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="crypto3_imm2">
|
|
<header>Cryptographic three-register, imm2</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">10xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx10xxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="cryptosha512_3">
|
|
<header>Cryptographic three-register SHA 512</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">11xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx1x00xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="crypto4">
|
|
<header>Cryptographic four-register</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">00</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx0xxxxx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="crypto3_imm6">
|
|
<header>Cryptographic three-register, imm6</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">00xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="cryptosha512_2">
|
|
<header>Cryptographic two-register SHA 512</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1100</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">01</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">1000</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">0001000xx</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="UNALLOCATED_advsimd_11" unallocated="1">
|
|
<header>UNALLOCATED</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">1xx0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="float2fix">
|
|
<header>Conversion between floating-point and fixed-point</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x0xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="float2int">
|
|
<header>Conversion between floating-point and integer</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxx000000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatdp1">
|
|
<header>Floating-point data-processing (1 source)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxx10000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatcmp">
|
|
<header>Floating-point compare</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxx1000</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatimm">
|
|
<header>Floating-point immediate</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxx100</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatccmp">
|
|
<header>Floating-point conditional compare</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxx01</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatdp2">
|
|
<header>Floating-point data-processing (2 source)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxx10</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatsel">
|
|
<header>Floating-point conditional select</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">0x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4">x1xx</c>
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9">xxxxxxx11</c>
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
<node iclass="floatdp3">
|
|
<header>Floating-point data-processing (3 source)</header>
|
|
<decode>
|
|
<box hibit="31" width="4" name="op0" usename="1">
|
|
<c colspan="4">x0x1</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="op1" usename="1">
|
|
<c colspan="2">1x</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="op2" usename="1">
|
|
<c colspan="4" />
|
|
</box>
|
|
<box hibit="18" width="9" name="op3" usename="1">
|
|
<c colspan="9" />
|
|
</box>
|
|
</decode>
|
|
</node>
|
|
</node>
|
|
</hierarchy>
|
|
<groups heading="Top-level Encoding Groups">
|
|
<maintable class="grouptable" size="32" howmanybits="32">
|
|
<col bitno="31" colno="1" printwidth="0.019in" />
|
|
<col bitno="30" colno="2" printwidth="0.019in" />
|
|
<col bitno="29" colno="3" printwidth="0.019in" />
|
|
<col bitno="28" colno="4" printwidth="0.019in" />
|
|
<col bitno="27" colno="5" printwidth="0.019in" />
|
|
<col bitno="26" colno="6" printwidth="0.019in" />
|
|
<col bitno="25" colno="7" printwidth="0.019in" />
|
|
<col bitno="24" colno="8" printwidth="0.019in" />
|
|
<col bitno="23" colno="9" printwidth="0.019in" />
|
|
<col bitno="22" colno="10" printwidth="0.019in" />
|
|
<col bitno="21" colno="11" printwidth="0.019in" />
|
|
<col bitno="20" colno="12" printwidth="0.019in" />
|
|
<col bitno="19" colno="13" printwidth="0.019in" />
|
|
<col bitno="18" colno="14" printwidth="0.019in" />
|
|
<col bitno="17" colno="15" printwidth="0.019in" />
|
|
<col bitno="16" colno="16" printwidth="0.019in" />
|
|
<col bitno="15" colno="17" printwidth="0.019in" />
|
|
<col bitno="14" colno="18" printwidth="0.019in" />
|
|
<col bitno="13" colno="19" printwidth="0.019in" />
|
|
<col bitno="12" colno="20" printwidth="0.019in" />
|
|
<col bitno="11" colno="21" printwidth="0.019in" />
|
|
<col bitno="10" colno="22" printwidth="0.019in" />
|
|
<col bitno="9" colno="23" printwidth="0.019in" />
|
|
<col bitno="8" colno="24" printwidth="0.019in" />
|
|
<col bitno="7" colno="25" printwidth="0.019in" />
|
|
<col bitno="6" colno="26" printwidth="0.019in" />
|
|
<col bitno="5" colno="27" printwidth="0.019in" />
|
|
<col bitno="4" colno="28" printwidth="0.019in" />
|
|
<col bitno="3" colno="29" printwidth="0.019in" />
|
|
<col bitno="2" colno="30" printwidth="0.019in" />
|
|
<col bitno="1" colno="31" printwidth="0.019in" />
|
|
<col bitno="0" colno="32" printwidth="0.019in" />
|
|
<col colno="33" printwidth="0.400in" />
|
|
<tableheader>
|
|
<tr class="header1">
|
|
<th colno="1" colspan="32">Instruction bits</th>
|
|
<th colno="33" rowspan="2">Encoding Group</th>
|
|
</tr>
|
|
<tr class="header2-morebits">
|
|
<th class="boxleft">31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th class="boxright">0</th>
|
|
</tr>
|
|
</tableheader>
|
|
<tablebody>
|
|
<tr class="maintable" size="32" groupid="main" groupname="reserved">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a>Reserved</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" groupname="sme">
|
|
<td class="boxleft">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a>SME encodings</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="main" iclass="unallocate1">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" groupname="sve">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a>SVE encodings</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="main" iclass="unallocate2">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" iclass="dpimm">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="dpimm">Data Processing -- Immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" iclass="control">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="control">Branches, Exception Generating and System instructions</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" iclass="ldst">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst">Loads and Stores</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" iclass="dpreg">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="dpreg">Data Processing -- Register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="main" iclass="simd-dp">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="simd-dp">Data Processing -- Scalar Floating-Point and Advanced SIMD</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="reserved" iclass="perm_undef">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="perm_undef">Reserved / UDF</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="reserved" iclass="unallocate3">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td colspan="9">!= 000000000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">Reserved / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="reserved" iclass="unallocate4">
|
|
<td class="boxleft"></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">Reserved / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_pred_bin">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_bin">SVE encodings / SVE Integer Binary Arithmetic - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_pred_red">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_red">SVE encodings / SVE Integer Reduction</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_pred_shift">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_shift">SVE encodings / SVE Bitwise Shift - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_pred_un">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_un">SVE encodings / SVE Integer Unary Arithmetic - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_muladd_pred">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_muladd_pred">SVE encodings / SVE Integer Multiply-Add - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_unpred_arit">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_unpred_arit">SVE encodings / SVE Integer Arithmetic - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_unpred_logical">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_unpred_logical">SVE encodings / SVE Bitwise Logical - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_index">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_index">SVE encodings / SVE Index Generation</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_alloca">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_alloca">SVE encodings / SVE Stack Allocation</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_unpred_arit_b">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_unpred_arit_b">SVE encodings / SVE2 Integer Multiply - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_unpred_shift">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_unpred_shift">SVE encodings / SVE Bitwise Shift - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_adr">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_adr">SVE encodings / SVE Address Generation</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_unpred_misc">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_unpred_misc">SVE encodings / SVE Integer Misc - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_countelt">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_countelt">SVE encodings / SVE Element Count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_extract">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_extract">SVE encodings / SVE Permute Vector - Extract</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_inter_long">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_inter_long">SVE encodings / SVE Permute Vector - Segments</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_maskimm">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_maskimm">SVE encodings / SVE Bitwise Immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_wideimm_pred">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_wideimm_pred">SVE encodings / SVE Integer Wide Immediate - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_unpred_a">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_unpred_a">SVE encodings / SVE Permute Vector - Indexed DUP</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_quads_a">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_quads_a">SVE encodings / SVE Permute Vector - Quadwords</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_unpred_b">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_unpred_b">SVE encodings / SVE Permute Vector - Three Sources TBL</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_unpred_c">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_unpred_c">SVE encodings / SVE Permute Vector - Two Sources TBL</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_quads_c">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_quads_c">SVE encodings / sve_perm_quads_c</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_unpred_d">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_unpred_d">SVE encodings / SVE Permute Vector - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_0">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_predicates">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_predicates">SVE encodings / SVE Permute Predicate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_inter">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_inter">SVE encodings / SVE Permute Vector - Interleaving</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_pred">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_pred">SVE encodings / SVE Permute Vector - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_int_select">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_select">SVE encodings / SVE Vector Select</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_cmpvec">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_cmpvec">SVE encodings / SVE Integer Compare - Vectors</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_cmpuimm">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_cmpuimm">SVE encodings / SVE Integer Compare - Unsigned Immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_gen_a">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_gen_a">SVE encodings / SVE Predicate Logical Operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_gen_b">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_gen_b">SVE encodings / SVE Propagate Break</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_gen_c">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_gen_c">SVE encodings / SVE Partition Break</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_gen_d">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_gen_d">SVE encodings / SVE Predicate Misc</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_cmpsimm">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_cmpsimm">SVE encodings / SVE Integer Compare - Signed Immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_count_a">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_count_a">SVE encodings / SVE Predicate Count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_count_b">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_count_b">SVE encodings / SVE Inc/Dec by Predicate Count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_wrffr">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_wrffr">SVE encodings / SVE Write FFR</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_1">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_2">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_cmpgpr">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_cmpgpr">SVE encodings / SVE Integer Compare - Scalars</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_pred_dup">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_pred_dup">SVE encodings / sve_pred_dup</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_while_pn">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_while_pn">SVE encodings / SVE Scalar Integer Compare - Predicate-as-counter</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_wideimm_unpred">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_wideimm_unpred">SVE encodings / SVE Integer Wide Immediate - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_dot2">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot2">SVE encodings / SVE Dot Product - Two-way</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_dot2_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot2_by_indexed_elem">SVE encodings / SVE Dot Product - Two-way Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_3">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_muladd_unpred">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_muladd_unpred">SVE encodings / SVE Integer Multiply-Add - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_predicated">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_predicated">SVE encodings / SVE2 Integer - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_clamp">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_clamp">SVE encodings / sve_intx_clamp</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_4">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_perm_quads_b">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_perm_quads_b">SVE encodings / sve_perm_quads_b</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_by_indexed_elem">SVE encodings / SVE Multiply - Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_cons_widening">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cons_widening">SVE encodings / SVE2 Widening Integer Arithmetic</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_constructive">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_constructive">SVE encodings / SVE Misc</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_acc">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_acc">SVE encodings / SVE2 Accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_narrowing">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_narrowing">SVE encodings / SVE2 Narrowing</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_string">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_string">SVE encodings / SVE2 String Processing</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_histseg">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_histseg">SVE encodings / SVE2 Histogram Computation - Segment</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_histcnt">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_histcnt">SVE encodings / SVE2 Histogram Computation - Vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_intx_crypto">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_crypto">SVE encodings / SVE2 Crypto Extensions</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fcadd">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcadd">SVE encodings / SVE Floating Point Complex Addition</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_5">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_6">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_7">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_8">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_9">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fcvt2">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcvt2">SVE encodings / SVE Floating Point Convert Precision Odd Elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_10">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_11">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_12">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_13">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_14">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_pairwise">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_pairwise">SVE encodings / SVE2 Floating Point Pairwise</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fastreduceq">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fastreduceq">SVE encodings / sve_fp_fastreduceq</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_15">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_16">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fcmla">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcmla">SVE encodings / SVE Floating Point Complex Multiply-Add</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fma_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_by_indexed_elem">SVE encodings / SVE Floating Point Multiply-Add - Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fcmla_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcmla_by_indexed_elem">SVE encodings / SVE Floating Point Complex Multiply-Add - Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_clamp">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_clamp">SVE encodings / sve_fp_clamp</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_17">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fmul_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fmul_by_indexed_elem">SVE encodings / SVE Floating Point Multiply - Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_18">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fma_w_by_indexed_elem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_w_by_indexed_elem">SVE encodings / SVE Floating Point Widening Multiply-Add - Indexed</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_19">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fma_w">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_w">SVE encodings / SVE Floating Point Widening Multiply-Add</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_20">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_21">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_22">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_23">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fmmla">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fmmla">SVE encodings / SVE Floating Point Matrix Multiply Accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_24">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_25">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fastreduce">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fastreduce">SVE encodings / SVE Floating Point Fast Reduction</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sve" iclass="unalloc_26">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SVE encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_unary_unpred">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_unary_unpred">SVE encodings / SVE Floating Point Unary Operations - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_cmpzero">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_cmpzero">SVE encodings / SVE Floating Point Compare - with Zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_slowreduce">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_slowreduce">SVE encodings / SVE Floating Point Accumulating Reduction</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_unpred">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_unpred">SVE encodings / SVE Floating Point Arithmetic - Unpredicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_pred">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_pred">SVE encodings / SVE Floating Point Arithmetic - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_unary">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_unary">SVE encodings / SVE Floating Point Unary Operations - Predicated</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_cmpvev">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_cmpvev">SVE encodings / SVE Floating Point Compare - Vectors</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_fp_fma">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma">SVE encodings / SVE Floating Point Multiply-Add</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_mem32">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem32">SVE encodings / SVE Memory - 32-bit Gather and Unsized Contiguous</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memcld">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memcld">SVE encodings / SVE Memory - Contiguous Load</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_mem64">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem64">SVE encodings / SVE Memory - 64-bit Gather</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memsst_nt">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memsst_nt">SVE encodings / SVE Memory - Non-temporal and Quadword Scatter Store</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memcst_nt">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memcst_nt">SVE encodings / SVE Memory - Non-temporal and Multi-register Contiguous Store</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memst_cs">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memst_cs">SVE encodings / SVE Memory - Contiguous Store and Unsized Contiguous</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memst_ss2">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memst_ss2">SVE encodings / SVE Memory - Scatter</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memst_si">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memst_si">SVE encodings / SVE Memory - Contiguous Store with Immediate Offset</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve" iclass="sve_memst_ss">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_memst_ss">SVE encodings / SVE Memory - Scatter with Optional Sign Extend</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_32bit_bin_prod">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_32bit_bin_prod">SME encodings / SME2 Binary Outer Product - 32 bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_0">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_2">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_16bit_fp_prod">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_16bit_fp_prod">SME encodings / SME FP Outer Product - 16 bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_1">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_32bit_fp_prod">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_32bit_fp_prod">SME encodings / SME FP Outer Product - 32 bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_mem_ctg">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_mem_ctg">SME encodings / SME2 Multi-vector - Memory (Contiguous)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_mem_nctg">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_mem_nctg">SME encodings / SME2 Multi-vector - Memory (Strided)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_32bit_int_prod">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_32bit_int_prod">SME encodings / SME Integer Outer Product - 32 bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_3">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_64bit_prod">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_64bit_prod">SME encodings / SME Outer Product - 64 bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_4">
|
|
<td class="boxleft">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_zero">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zero">SME encodings / SME Zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multizero">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multizero">SME encodings / SME2 Multiple Zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_zero_zt">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zero_zt">SME encodings / SME2 Zero Lookup Table</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_mov_zt">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_mov_zt">SME encodings / SME2 Move Lookup Table</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_5">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_zt_expand_nctg">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zt_expand_nctg">SME encodings / SME2 Expand Lookup Table (Non-contiguous)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_8">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_zt_expand_ctg">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zt_expand_ctg">SME encodings / SME2 Expand Lookup Table (Contiguous)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_ins">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_ins">SME encodings / SME Move into Array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_6">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_ext">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_ext">SME encodings / SME Move from Array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_hvadd">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_hvadd">SME encodings / SME Add Vector to Array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_7">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_9">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_array_1">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_array_1">SME encodings / SME2 Multi-vector - Multiple and Single Array Vectors</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_array_2a">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_array_2a">SME encodings / SME2 Multi-vector - Multiple Array Vectors (Two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_array_2b">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_array_2b">SME encodings / SME2 Multi-vector - Multiple Array Vectors (Four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_indexed_1">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_indexed_1">SME encodings / SME2 Multi-vector - Indexed (One register)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_indexed_2">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_indexed_2">SME encodings / SME2 Multi-vector - Indexed (Two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_indexed_3">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_indexed_3">SME encodings / SME2 Multi-vector - Indexed (Four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_10">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_11">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_2a">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_2a">SME encodings / SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_2b">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_2b">SME encodings / SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_12">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_13">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_16">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_2c">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_2c">SME encodings / SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_2d">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_2d">SME encodings / SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_1">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_1">SME encodings / SME2 Multi-vector - SVE Select</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_3">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_3">SME encodings / SME2 Multi-vector - SVE Constructive Binary</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_multi_sve_4">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_sve_4">SME encodings / SME2 Multi-vector - SVE Constructive Unary</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_14">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" undef="1" groupid="sme" iclass="unalloc_15">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">SME encodings / UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sme" iclass="mortlach_mem">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_mem">SME encodings / SME Memory</a>
|
|
</td>
|
|
</tr>
|
|
</tablebody>
|
|
</maintable>
|
|
</groups>
|
|
<maintable class="allclasses" size="32" howmanybits="32">
|
|
<col bitno="31" colno="1" printwidth="0.019in" />
|
|
<col bitno="30" colno="2" printwidth="0.019in" />
|
|
<col bitno="29" colno="3" printwidth="0.019in" />
|
|
<col bitno="28" colno="4" printwidth="0.019in" />
|
|
<col bitno="27" colno="5" printwidth="0.019in" />
|
|
<col bitno="26" colno="6" printwidth="0.019in" />
|
|
<col bitno="25" colno="7" printwidth="0.019in" />
|
|
<col bitno="24" colno="8" printwidth="0.019in" />
|
|
<col bitno="23" colno="9" printwidth="0.019in" />
|
|
<col bitno="22" colno="10" printwidth="0.019in" />
|
|
<col bitno="21" colno="11" printwidth="0.019in" />
|
|
<col bitno="20" colno="12" printwidth="0.019in" />
|
|
<col bitno="19" colno="13" printwidth="0.019in" />
|
|
<col bitno="18" colno="14" printwidth="0.019in" />
|
|
<col bitno="17" colno="15" printwidth="0.019in" />
|
|
<col bitno="16" colno="16" printwidth="0.019in" />
|
|
<col bitno="15" colno="17" printwidth="0.019in" />
|
|
<col bitno="14" colno="18" printwidth="0.019in" />
|
|
<col bitno="13" colno="19" printwidth="0.019in" />
|
|
<col bitno="12" colno="20" printwidth="0.019in" />
|
|
<col bitno="11" colno="21" printwidth="0.019in" />
|
|
<col bitno="10" colno="22" printwidth="0.019in" />
|
|
<col bitno="9" colno="23" printwidth="0.019in" />
|
|
<col bitno="8" colno="24" printwidth="0.019in" />
|
|
<col bitno="7" colno="25" printwidth="0.019in" />
|
|
<col bitno="6" colno="26" printwidth="0.019in" />
|
|
<col bitno="5" colno="27" printwidth="0.019in" />
|
|
<col bitno="4" colno="28" printwidth="0.019in" />
|
|
<col bitno="3" colno="29" printwidth="0.019in" />
|
|
<col bitno="2" colno="30" printwidth="0.019in" />
|
|
<col bitno="1" colno="31" printwidth="0.019in" />
|
|
<col bitno="0" colno="32" printwidth="0.019in" />
|
|
<col colno="33" printwidth="0.400in" />
|
|
<tableheader>
|
|
<tr class="header1">
|
|
<th colno="1" colspan="32">Instruction bits</th>
|
|
<th colno="33" rowspan="2">Instruction class</th>
|
|
</tr>
|
|
<tr class="header2-morebits">
|
|
<th class="boxleft">31</th>
|
|
<th>30</th>
|
|
<th>29</th>
|
|
<th>28</th>
|
|
<th>27</th>
|
|
<th>26</th>
|
|
<th>25</th>
|
|
<th>24</th>
|
|
<th>23</th>
|
|
<th>22</th>
|
|
<th>21</th>
|
|
<th>20</th>
|
|
<th>19</th>
|
|
<th>18</th>
|
|
<th>17</th>
|
|
<th>16</th>
|
|
<th>15</th>
|
|
<th>14</th>
|
|
<th>13</th>
|
|
<th>12</th>
|
|
<th>11</th>
|
|
<th>10</th>
|
|
<th>9</th>
|
|
<th>8</th>
|
|
<th>7</th>
|
|
<th>6</th>
|
|
<th>5</th>
|
|
<th>4</th>
|
|
<th>3</th>
|
|
<th>2</th>
|
|
<th>1</th>
|
|
<th class="boxright">0</th>
|
|
</tr>
|
|
</tableheader>
|
|
<tablebody>
|
|
<maintablesect sect="Data Processing -- Immediate" linkref="dpimm" />
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="pcreladdr">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="pcreladdr">PC-rel. addressing</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="addsub_imm">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="addsub_imm">Add/subtract (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="addsub_immtags">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="addsub_immtags">Add/subtract (immediate, with tags)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="minmax_imm">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="minmax_imm">Min/max (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="log_imm">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="log_imm">Logical (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="movewide">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="movewide">Move wide (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="bitfield">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="bitfield">Bitfield</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpimm" iclass="extract">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="extract">Extract</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="Branches, Exception Generating and System instructions" linkref="control" />
|
|
<tr class="maintable" size="32" groupid="control" iclass="branch_imm">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="branch_imm">Unconditional branch (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="compbranch">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="compbranch">Compare and branch (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="testbranch">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="testbranch">Test and branch (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="condbranch">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="condbranch">Conditional branch (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="exception">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="exception">Exception generation</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="systeminstrs">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="systeminstrs">System instructions</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="systemmove">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="systemmove">System register move</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="pstate">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="pstate">PSTATE</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="systeminstrswithreg">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="systeminstrswithreg">System instructions with register argument</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="hints">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">
|
|
<a classid="hints">Hints</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="barriers">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="barriers">Barriers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="systemresult">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="systemresult">System with result</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="syspairinstrs">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="syspairinstrs">System pair instructions</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="systemmovepr">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="systemmovepr">System register pair move</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="control" iclass="branch_reg">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="branch_reg">Unconditional branch (register)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="Loads and Stores" linkref="ldst" />
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstexclr">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstexclr">Load/store exclusive register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstord">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstord">Load/store ordered</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="comswap">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="comswap">Compare and swap</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="loadlit">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="loadlit">Load register (literal)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="memcms">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="memcms">Memory Copy and Memory Set</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldapstl_unscaled">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldapstl_unscaled">LDAPR/STLR (unscaled immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldiappstilp">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldiappstilp">LDIAPP/STILP</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldapstl_writeback">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldapstl_writeback">LDAPR/STLR (writeback)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldapstl_simd">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldapstl_simd">LDAPR/STLR (SIMD&FP)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstnapair_offs">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstnapair_offs">Load/store no-allocate pair (offset)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstpair_post">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstpair_post">Load/store register pair (post-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstpair_off">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstpair_off">Load/store register pair (offset)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstpair_pre">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstpair_pre">Load/store register pair (pre-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_unscaled">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_unscaled">Load/store register (unscaled immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_immpost">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_immpost">Load/store register (immediate post-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_unpriv">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_unpriv">Load/store register (unprivileged)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_immpre">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_immpre">Load/store register (immediate pre-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_pac">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_pac">Load/store register (pac)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="memop">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="memop">Atomic memory operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_regoff">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_regoff">Load/store register (register offset)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_pos">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_pos">Load/store register (unsigned immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="comswappr">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="comswappr">Compare and swap pair</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_91">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_92">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_93">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_94">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_85">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_90">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="asisdlse">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdlse">Advanced SIMD load/store multiple structures</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="asisdlsep">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdlsep">Advanced SIMD load/store multiple structures (post-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="asisdlso">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdlso">Advanced SIMD load/store single structure</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="asisdlsop">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdlsop">Advanced SIMD load/store single structure (post-indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="memop_128">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="memop_128">128-bit atomic memory operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="rcwcomswap">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="rcwcomswap">RCW compare and swap</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="rcwcomswappr">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="rcwcomswappr">RCW compare and swap pair</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldstexclp">
|
|
<td class="boxleft">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldstexclp">Load/store exclusive pair</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="ldst" iclass="UNALLOCATED_advsimd_83">
|
|
<td class="boxleft">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldsttags">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldsttags">Load/store memory tags</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="ldst" iclass="ldst_gcs">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="ldst_gcs">GCS load/store</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="Data Processing -- Register" linkref="dpreg" />
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="log_shift">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="log_shift">Logical (shifted register)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="addsub_shift">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="addsub_shift">Add/subtract (shifted register)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="addsub_ext">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="addsub_ext">Add/subtract (extended register)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="setf">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="setf">Evaluate into flags</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="rmif">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="rmif">Rotate right into flags</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="addsub_carry">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="addsub_carry">Add/subtract (with carry)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="condcmp_reg">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="condcmp_reg">Conditional compare (register)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="condcmp_imm">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="condcmp_imm">Conditional compare (immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="condsel">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="condsel">Conditional select</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="dp_3src">
|
|
<td class="boxleft"></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="dp_3src">Data-processing (3 source)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="dp_2src">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="dp_2src">Data-processing (2 source)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="dpreg" iclass="dp_1src">
|
|
<td class="boxleft"></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="dp_1src">Data-processing (1 source)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="Data Processing -- Scalar Floating-Point and Advanced SIMD" linkref="simd-dp" />
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="float2fix">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="float2fix">Conversion between floating-point and fixed-point</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatccmp">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatccmp">Floating-point conditional compare</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatdp2">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatdp2">Floating-point data-processing (2 source)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatsel">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatsel">Floating-point conditional select</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatimm">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatimm">Floating-point immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatcmp">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatcmp">Floating-point compare</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatdp1">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatdp1">Floating-point data-processing (1 source)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="float2int">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="float2int">Conversion between floating-point and integer</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="floatdp3">
|
|
<td class="boxleft"></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="floatdp3">Floating-point data-processing (3 source)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_13">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdsame2">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdsame2">Advanced SIMD three-register extension</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdsame">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdsame">Advanced SIMD three same</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimddiff">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimddiff">Advanced SIMD three different</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_34">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_33">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdmisc">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdmisc">Advanced SIMD two-register miscellaneous</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdall">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdall">Advanced SIMD across lanes</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_31">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdsamefp16">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdsamefp16">Advanced SIMD three same (FP16)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_21">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdmiscfp16">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdmiscfp16">Advanced SIMD two-register miscellaneous (FP16)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdins">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdins">Advanced SIMD copy</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_19">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdelem">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdelem">Advanced SIMD vector x indexed element</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdimm">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdimm">Advanced SIMD modified immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdshf">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdshf">Advanced SIMD shift by immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_36">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdtbl">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdtbl">Advanced SIMD table lookup</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdperm">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdperm">Advanced SIMD permute</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asimdext">
|
|
<td class="boxleft">0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asimdext">Advanced SIMD extract</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_26">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_27">
|
|
<td class="boxleft">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_49">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdsame2">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdsame2">Advanced SIMD scalar three same extra</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdsame">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdsame">Advanced SIMD scalar three same</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisddiff">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisddiff">Advanced SIMD scalar three different</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_68">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_67">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdmisc">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdmisc">Advanced SIMD scalar two-register miscellaneous</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdpair">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdpair">Advanced SIMD scalar pairwise</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_65">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdsamefp16">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdsamefp16">Advanced SIMD scalar three same FP16</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_57">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdmiscfp16">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdmiscfp16">Advanced SIMD scalar two-register miscellaneous FP16</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdone">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdone">Advanced SIMD scalar copy</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_55">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdelem">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdelem">Advanced SIMD scalar x indexed element</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="asisdshf">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="asisdshf">Advanced SIMD scalar shift by immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_70">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="cryptoaes">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="cryptoaes">Cryptographic AES</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="cryptosha3">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="cryptosha3">Cryptographic three-register SHA</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_52">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="cryptosha2">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="cryptosha2">Cryptographic two-register SHA</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_29">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_53">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_63">
|
|
<td class="boxleft">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="simd-dp" iclass="UNALLOCATED_advsimd_11">
|
|
<td class="boxleft">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="crypto4">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="crypto4">Cryptographic four-register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="crypto3_imm2">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="crypto3_imm2">Cryptographic three-register, imm2</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="cryptosha512_3">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="cryptosha512_3">Cryptographic three-register SHA 512</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="crypto3_imm6">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="crypto3_imm6">Cryptographic three-register, imm6</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="simd-dp" iclass="cryptosha512_2">
|
|
<td class="boxleft">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="cryptosha512_2">Cryptographic two-register SHA 512</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="UDF" linkref="perm_undef" />
|
|
<tr class="maintable" size="32" groupid="perm_undef" iclass="perm_undef">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="perm_undef">Reserved</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Binary Arithmetic - Predicated" linkref="sve_int_pred_bin" />
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_bin" iclass="sve_int_bin_pred_arit_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_arit_0">SVE integer add/subtract vectors (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_bin" iclass="sve_int_bin_pred_arit_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_arit_1">SVE integer min/max/difference (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_bin" iclass="sve_int_bin_pred_arit_2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_arit_2">SVE integer multiply vectors (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_bin" iclass="sve_int_bin_pred_div">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_div">SVE integer divide vectors (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_bin" iclass="sve_int_bin_pred_log">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_log">SVE bitwise logical operations (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Reduction" linkref="sve_int_pred_red" />
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_0">SVE integer add reduction (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_0q">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_0q">SVE integer add reduction (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_1">SVE integer min/max reduction (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_1q">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_1q">SVE integer min/max reduction (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_movprfx_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_movprfx_pred">SVE constructive prefix (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_2">SVE bitwise logical reduction (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_red" iclass="sve_int_reduce_2q">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_reduce_2q">SVE bitwise logical reduction (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Bitwise Shift - Predicated" linkref="sve_int_pred_shift" />
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_shift" iclass="sve_int_bin_pred_shift_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_shift_0">SVE bitwise shift by immediate (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_shift" iclass="sve_int_bin_pred_shift_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_shift_1">SVE bitwise shift by vector (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_shift" iclass="sve_int_bin_pred_shift_2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_pred_shift_2">SVE bitwise shift by wide elements (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Unary Arithmetic - Predicated" linkref="sve_int_pred_un" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_int_pred_un" iclass="UNALLOCATED_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_un" iclass="sve_int_un_pred_arit_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_un_pred_arit_0">SVE integer unary operations (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_pred_un" iclass="sve_int_un_pred_arit_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_un_pred_arit_1">SVE bitwise unary operations (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Multiply-Add - Predicated" linkref="sve_int_muladd_pred" />
|
|
<tr class="maintable" size="32" groupid="sve_int_muladd_pred" iclass="sve_int_mlas_vvv_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_mlas_vvv_pred">SVE integer multiply-accumulate writing addend (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_muladd_pred" iclass="sve_int_mladdsub_vvv_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_mladdsub_vvv_pred">SVE integer multiply-add writing multiplicand (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Arithmetic - Unpredicated" linkref="sve_int_unpred_arit" />
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_arit" iclass="sve_int_bin_cons_arit_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_arit_0">SVE integer add/subtract vectors (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Bitwise Logical - Unpredicated" linkref="sve_int_unpred_logical" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_int_unpred_logical" iclass="UNALLOCATED_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_logical" iclass="sve_int_bin_cons_log">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_log">SVE bitwise logical operations (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_logical" iclass="sve_int_rotate_imm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_rotate_imm">sve_int_rotate_imm</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_logical" iclass="sve_int_tern_log">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_tern_log">SVE2 bitwise ternary operations</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Index Generation" linkref="sve_index" />
|
|
<tr class="maintable" size="32" groupid="sve_index" iclass="sve_int_index_ii">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_index_ii">SVE index generation (immediate start, immediate increment)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_index" iclass="sve_int_index_ri">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_index_ri">SVE index generation (register start, immediate increment)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_index" iclass="sve_int_index_ir">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_index_ir">SVE index generation (immediate start, register increment)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_index" iclass="sve_int_index_rr">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_index_rr">SVE index generation (register start, register increment)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Stack Allocation" linkref="sve_alloca" />
|
|
<tr class="maintable" size="32" groupid="sve_alloca" iclass="sve_int_arith_vl">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_arith_vl">SVE stack frame adjustment</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_alloca" iclass="sve_int_arith_svl">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_arith_svl">Streaming SVE stack frame adjustment</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_alloca" iclass="sve_int_read_vl_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_read_vl_a">SVE stack frame size</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_alloca" iclass="sve_int_read_svl_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_read_svl_a">Streaming SVE stack frame size</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Integer Multiply - Unpredicated" linkref="sve_int_unpred_arit_b" />
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_arit_b" iclass="sve_int_mul_b">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_mul_b">SVE2 integer multiply vectors (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_arit_b" iclass="sve_int_sqdmulh">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_sqdmulh">SVE2 signed saturating doubling multiply high (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_int_unpred_arit_b" iclass="UNALLOCATED_2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Bitwise Shift - Unpredicated" linkref="sve_int_unpred_shift" />
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_shift" iclass="sve_int_bin_cons_shift_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_shift_a">SVE bitwise shift by wide elements (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_shift" iclass="sve_int_bin_cons_shift_b">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_shift_b">SVE bitwise shift by immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Address Generation" linkref="sve_int_adr" />
|
|
<tr class="maintable" size="32" groupid="sve_int_adr" iclass="sve_int_bin_cons_misc_0_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_misc_0_a">SVE address generation</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Misc - Unpredicated" linkref="sve_int_unpred_misc" />
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_misc" iclass="sve_int_bin_cons_misc_0_b">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_misc_0_b">SVE floating-point trig select coefficient</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_misc" iclass="sve_int_bin_cons_misc_0_c">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_misc_0_c">SVE floating-point exponential accelerator</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_int_unpred_misc" iclass="sve_int_bin_cons_misc_0_d">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_bin_cons_misc_0_d">SVE constructive prefix (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Element Count" linkref="sve_countelt" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_countelt" iclass="UNALLOCATED_3">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_countelt" iclass="sve_int_pred_pattern_b">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_pattern_b">SVE saturating inc/dec register by element count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_countelt" iclass="sve_int_countvlv0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_countvlv0">SVE saturating inc/dec vector by element count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_countelt" iclass="sve_int_count">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_count">SVE element count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_countelt" iclass="UNALLOCATED_4">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_countelt" iclass="UNALLOCATED_5">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_countelt" iclass="sve_int_countvlv1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_countvlv1">SVE inc/dec vector by element count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_countelt" iclass="sve_int_pred_pattern_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_pattern_a">SVE inc/dec register by element count</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Extract" linkref="sve_perm_extract" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_extract" iclass="sve_int_perm_extract_i">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_extract_i">SVE extract vector (immediate offset, destructive)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_extract" iclass="sve_intx_perm_extract_i">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_perm_extract_i">SVE2 extract vector (immediate offset, constructive)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Segments" linkref="sve_perm_inter_long" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_inter_long" iclass="sve_int_perm_bin_long_perm_zz">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_bin_long_perm_zz">SVE permute vector segments</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_inter_long" iclass="UNALLOCATED_20">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Bitwise Immediate" linkref="sve_maskimm" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_maskimm" iclass="UNALLOCATED_203">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_maskimm" iclass="sve_int_dup_mask_imm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_dup_mask_imm">SVE broadcast bitmask immediate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_maskimm" iclass="sve_int_log_imm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 11</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_log_imm">SVE bitwise logical with immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Wide Immediate - Predicated" linkref="sve_wideimm_pred" />
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_pred" iclass="sve_int_dup_imm_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_dup_imm_pred">SVE copy integer immediate (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_wideimm_pred" iclass="UNALLOCATED_6">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_pred" iclass="sve_int_dup_fpimm_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_dup_fpimm_pred">SVE copy floating-point immediate (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_wideimm_pred" iclass="UNALLOCATED_7">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Indexed DUP" linkref="sve_perm_unpred_a" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_a" iclass="sve_int_perm_dup_i">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_dup_i">SVE broadcast indexed element</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Quadwords" linkref="sve_perm_quads_a" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_quads_a" iclass="sve_int_perm_dupq_i">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_dupq_i">sve_int_perm_dupq_i</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_quads_a" iclass="sve_int_perm_extq">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_extq">sve_int_perm_extq</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_quads_a" iclass="UNALLOCATED_18">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_quads_a" iclass="UNALLOCATED_19">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Three Sources TBL" linkref="sve_perm_unpred_b" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_b" iclass="sve_int_perm_tbl_3src">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_tbl_3src">SVE table lookup (three sources)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Two Sources TBL" linkref="sve_perm_unpred_c" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_c" iclass="sve_int_perm_tbl">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_tbl">SVE table lookup</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="sve_perm_quads_c" linkref="sve_perm_quads_c" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_quads_c" iclass="sve_int_perm_tbxquads">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_tbxquads">sve_int_perm_tbxquads</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Unpredicated" linkref="sve_perm_unpred_d" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_174">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_175">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_perm_dup_r">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_dup_r">SVE broadcast general register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_perm_insrs">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_insrs">SVE insert general register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_mov_v2p">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_mov_v2p">SVE move predicate from vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_10">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_mov_p2v">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_mov_p2v">SVE move predicate into vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_11">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_perm_unpk">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_unpk">SVE unpack vector elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_182">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_perm_insrv">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_insrv">SVE insert SIMD&FP scalar register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_183">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_unpred_d" iclass="sve_int_perm_reverse_z">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_reverse_z">SVE reverse vector elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_unpred_d" iclass="UNALLOCATED_205">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Predicate" linkref="sve_perm_predicates" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_172">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_predicates" iclass="sve_int_perm_bin_perm_pp">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_bin_perm_pp">SVE permute predicate elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_173">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_178">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_179">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_180">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_181">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_15">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_predicates" iclass="sve_int_perm_reverse_p">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_reverse_p">SVE reverse predicate elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_16">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_17">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_predicates" iclass="sve_int_perm_punpk">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_punpk">SVE unpack predicate elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_184">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_185">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_predicates" iclass="UNALLOCATED_186">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Interleaving" linkref="sve_perm_inter" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_inter" iclass="sve_int_perm_bin_perm_zz">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_bin_perm_zz">SVE permute vector elements</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Permute Vector - Predicated" linkref="sve_perm_pred" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_8">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_last_r">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_last_r">SVE extract element to general register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_cpy_v">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_cpy_v">SVE copy SIMD&FP scalar register to vector (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_compact">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_compact">SVE compress active elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_last_v">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_last_v">SVE extract element to SIMD&FP scalar register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_rev">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_rev">SVE reverse within elements</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_9">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_clast_zz">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_clast_zz">SVE conditionally broadcast element to vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_cpy_r">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_cpy_r">SVE copy general register to vector (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_12">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_clast_vz">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_clast_vz">SVE conditionally extract element to SIMD&FP scalar</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_13">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_splice">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_splice">SVE vector splice (destructive)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_intx_perm_splice">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_perm_splice">SVE2 vector splice (constructive)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_revd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_revd">SVE reverse doublewords</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_176">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_177">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_14">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_perm_pred" iclass="sve_int_perm_clast_rz">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_clast_rz">SVE conditionally extract element to general register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_perm_pred" iclass="UNALLOCATED_204">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Vector Select" linkref="sve_int_select" />
|
|
<tr class="maintable" size="32" groupid="sve_int_select" iclass="sve_int_sel_vvv">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_sel_vvv">SVE select vector elements (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Compare - Vectors" linkref="sve_cmpvec" />
|
|
<tr class="maintable" size="32" groupid="sve_cmpvec" iclass="sve_int_cmp_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_cmp_0">SVE integer compare vectors</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_cmpvec" iclass="sve_int_cmp_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_cmp_1">SVE integer compare with wide elements</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Compare - Unsigned Immediate" linkref="sve_cmpuimm" />
|
|
<tr class="maintable" size="32" groupid="sve_cmpuimm" iclass="sve_int_ucmp_vi">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_ucmp_vi">SVE integer compare with unsigned immediate</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Predicate Logical Operations" linkref="sve_pred_gen_a" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_a" iclass="sve_int_pred_log">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_log">SVE predicate logical operations</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Propagate Break" linkref="sve_pred_gen_b" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_b" iclass="sve_int_brkp">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_brkp">SVE propagate break from previous partition</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_b" iclass="UNALLOCATED_21">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Partition Break" linkref="sve_pred_gen_c" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_c" iclass="sve_int_break">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_break">SVE partition break condition</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_189">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_191">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_22">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_193">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_c" iclass="sve_int_brkn">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_brkn">SVE propagate break to next partition</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_23">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_29">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_c" iclass="UNALLOCATED_206">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Predicate Misc" linkref="sve_pred_gen_d" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_187">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_188">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_190">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_192">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_ptest">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_ptest">SVE predicate test</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_194">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_197">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_195">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_24">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_ptrue">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_ptrue">SVE predicate initialize</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_196">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_209">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_pfirst">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pfirst">SVE predicate first active</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_207">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_pfalse">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pfalse">SVE predicate zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_208">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_rdffr">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_rdffr">SVE predicate read from FFR (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_25">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_pnext">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pnext">SVE predicate next active</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_26">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_27">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_gen_d" iclass="sve_int_rdffr_2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_rdffr_2">SVE predicate read from FFR (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_210">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_gen_d" iclass="UNALLOCATED_198">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Compare - Signed Immediate" linkref="sve_cmpsimm" />
|
|
<tr class="maintable" size="32" groupid="sve_cmpsimm" iclass="sve_int_scmp_vi">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_scmp_vi">SVE integer compare with signed immediate</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Predicate Count" linkref="sve_pred_count_a" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_a" iclass="sve_int_pcount_pred">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pcount_pred">SVE predicate count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_a" iclass="sve_int_pcount_pn">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pcount_pn">SVE predicate count (predicate-as-counter)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_count_a" iclass="UNALLOCATED_215">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Inc/Dec by Predicate Count" linkref="sve_pred_count_b" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_b" iclass="sve_int_count_v_sat">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_count_v_sat">SVE saturating inc/dec vector by predicate count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_b" iclass="sve_int_count_r_sat">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_count_r_sat">SVE saturating inc/dec register by predicate count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_b" iclass="sve_int_count_v">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_count_v">SVE inc/dec vector by predicate count</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_count_b" iclass="sve_int_count_r">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_count_r">SVE inc/dec register by predicate count</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Write FFR" linkref="sve_pred_wrffr" />
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_216">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="5" class="boxright">!= 00000</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_217">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_218">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_wrffr" iclass="sve_int_wrffr">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_wrffr">SVE FFR write from predicate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_199">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_200">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_201">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_pred_wrffr" iclass="sve_int_setffr">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_setffr">SVE FFR initialise</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_pred_wrffr" iclass="UNALLOCATED_202">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Compare - Scalars" linkref="sve_cmpgpr" />
|
|
<tr class="maintable" size="32" groupid="sve_cmpgpr" iclass="sve_int_while_rr">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_while_rr">SVE integer compare scalar count and limit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_cmpgpr" iclass="UNALLOCATED_212">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_cmpgpr" iclass="sve_int_cterm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_cterm">SVE conditionally terminate scalars</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_cmpgpr" iclass="UNALLOCATED_211">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="4" class="boxright">!= 0000</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_cmpgpr" iclass="sve_int_whilenc">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_whilenc">SVE pointer conflict compare</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="sve_pred_dup" linkref="sve_pred_dup" />
|
|
<tr class="maintable" size="32" groupid="sve_pred_dup" iclass="sve_int_pred_dup">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pred_dup">SVE broadcast predicate element</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Scalar Integer Compare - Predicate-as-counter" linkref="sve_while_pn" />
|
|
<tr class="maintable" size="32" groupid="sve_while_pn" iclass="sve_int_while_rr_pn">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_while_rr_pn">SVE integer compare scalar count and limit (predicate-as-counter)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_while_pn" iclass="sve_int_while_rr_pair">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_while_rr_pair">SVE integer compare scalar count and limit (predicate pair)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_while_pn" iclass="sve_int_ctr_to_mask">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_ctr_to_mask">SVE extract mask predicate from predicate-as-counter</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_while_pn" iclass="sve_int_pn_ptrue">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_pn_ptrue">sve_int_pn_ptrue</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_while_pn" iclass="UNALLOCATED_28">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_while_pn" iclass="UNALLOCATED_213">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td colspan="6">!= 000000</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_while_pn" iclass="UNALLOCATED_214">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Wide Immediate - Unpredicated" linkref="sve_wideimm_unpred" />
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_unpred" iclass="sve_int_arith_imm0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_arith_imm0">SVE integer add/subtract immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_unpred" iclass="sve_int_arith_imm1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_arith_imm1">SVE integer min/max immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_unpred" iclass="sve_int_arith_imm2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_arith_imm2">SVE integer multiply immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_unpred" iclass="sve_int_dup_imm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_dup_imm">SVE broadcast integer immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_wideimm_unpred" iclass="sve_int_dup_fpimm">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_dup_fpimm">SVE broadcast floating-point immediate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Dot Product - Two-way" linkref="sve_intx_dot2" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_dot2" iclass="sve_intx_dot2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot2">SVE two-way dot product</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Dot Product - Two-way Indexed" linkref="sve_intx_dot2_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_dot2_by_indexed_elem" iclass="sve_intx_dot2_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot2_by_indexed_elem">SVE two-way dot product (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Integer Multiply-Add - Unpredicated" linkref="sve_intx_muladd_unpred" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_dot">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot">SVE integer dot product (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_qdmlalbt">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qdmlalbt">SVE2 saturating multiply-add interleaved long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_cdot">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cdot">SVE2 complex integer dot product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_cmla">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cmla">SVE2 complex integer multiply-add</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_mlal_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mlal_long">SVE2 integer multiply-add long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_qdmlal_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qdmlal_long">SVE2 saturating multiply-add long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_qrdmlah">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qrdmlah">SVE2 saturating multiply-add high</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_muladd_unpred" iclass="sve_intx_mixed_dot">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mixed_dot">SVE mixed sign dot product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_muladd_unpred" iclass="UNALLOCATED_30">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Integer - Predicated" linkref="sve_intx_predicated" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_bin_pred_shift_sat_round">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_bin_pred_shift_sat_round">SVE2 saturating/rounding bitwise shift left (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_pred_arith_unary">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_pred_arith_unary">SVE2 integer unary operations (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_accumulate_long_pairs">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_accumulate_long_pairs">SVE2 integer pairwise add and accumulate long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_predicated" iclass="UNALLOCATED_31">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_predicated" iclass="UNALLOCATED_32">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_pred_arith_binary">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_pred_arith_binary">SVE2 integer halving add/subtract (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_arith_binary_pairs">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_arith_binary_pairs">SVE2 integer pairwise arithmetic</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_predicated" iclass="sve_intx_pred_arith_binary_sat">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_pred_arith_binary_sat">SVE2 saturating add/subtract</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_predicated" iclass="UNALLOCATED_33">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="sve_intx_clamp" linkref="sve_intx_clamp" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_clamp" iclass="sve_intx_clamp">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_clamp">SVE integer clamp</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="sve_perm_quads_b" linkref="sve_perm_quads_b" />
|
|
<tr class="maintable" size="32" groupid="sve_perm_quads_b" iclass="sve_int_perm_binquads">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_int_perm_binquads">SVE permute vector elements (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Multiply - Indexed" linkref="sve_intx_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_dot_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_dot_by_indexed_elem">SVE integer dot product (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_mla_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mla_by_indexed_elem">SVE2 integer multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_qrdmlah_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qrdmlah_by_indexed_elem">SVE2 saturating multiply-add high (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_mixed_dot_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mixed_dot_by_indexed_elem">SVE mixed sign dot product (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_qdmla_long_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qdmla_long_by_indexed_elem">SVE2 saturating multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_cdot_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cdot_by_indexed_elem">SVE2 complex integer dot product (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_by_indexed_elem" iclass="UNALLOCATED_34">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_cmla_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cmla_by_indexed_elem">SVE2 complex integer multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_qrdcmla_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qrdcmla_by_indexed_elem">SVE2 complex saturating multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_mla_long_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mla_long_by_indexed_elem">SVE2 integer multiply-add long (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_mul_long_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mul_long_by_indexed_elem">SVE2 integer multiply long (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_qdmul_long_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qdmul_long_by_indexed_elem">SVE2 saturating multiply (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_qdmulh_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_qdmulh_by_indexed_elem">SVE2 saturating multiply high (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_by_indexed_elem" iclass="sve_intx_mul_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mul_by_indexed_elem">SVE2 integer multiply (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_by_indexed_elem" iclass="UNALLOCATED_35">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Widening Integer Arithmetic" linkref="sve_intx_cons_widening" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_cons_widening" iclass="sve_intx_cons_arith_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cons_arith_long">SVE2 integer add/subtract long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_cons_widening" iclass="sve_intx_cons_arith_wide">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cons_arith_wide">SVE2 integer add/subtract wide</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_cons_widening" iclass="sve_intx_cons_mul_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cons_mul_long">SVE2 integer multiply long</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Misc" linkref="sve_intx_constructive" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_constructive" iclass="sve_intx_clong">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_clong">SVE2 integer add/subtract interleaved long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_constructive" iclass="sve_intx_eorx">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_eorx">SVE2 bitwise exclusive-or interleaved</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_constructive" iclass="sve_intx_mmla">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_mmla">SVE integer matrix multiply accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_constructive" iclass="UNALLOCATED_36">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_constructive" iclass="sve_intx_perm_bit">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_perm_bit">SVE2 bitwise permute</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_constructive" iclass="sve_intx_shift_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_shift_long">SVE2 bitwise shift left long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_constructive" iclass="UNALLOCATED_43">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Accumulate" linkref="sve_intx_acc" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_aba_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_aba_long">SVE2 integer absolute difference and accumulate long</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_adc_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_adc_long">SVE2 integer add/subtract long with carry</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_sra">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_sra">SVE2 bitwise shift right and accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_shift_insert">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_shift_insert">SVE2 bitwise shift and insert</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_aba">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_aba">SVE2 integer absolute difference and accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_acc" iclass="sve_intx_cadd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_cadd">SVE2 complex integer add</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_acc" iclass="UNALLOCATED_219">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Narrowing" linkref="sve_intx_narrowing" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_narrowing" iclass="sve_intx_arith_narrow">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_arith_narrow">SVE2 integer add/subtract narrow high part</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_narrowing" iclass="sve_intx_shift_narrow">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_shift_narrow">SVE2 bitwise shift right narrow</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_narrowing" iclass="sve_intx_extract_narrow">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_extract_narrow">SVE2 saturating extract narrow</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_narrowing" iclass="sve_intx_multi_extract_narrow">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_multi_extract_narrow">SME2 multi-vec extract narrow</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_38">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_39">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_224">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_narrowing" iclass="sve_intx_multi_shift_narrow">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_multi_shift_narrow">SME2 multi-vec shift narrow</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_44">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_45">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_narrowing" iclass="UNALLOCATED_46">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 String Processing" linkref="sve_intx_string" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_string" iclass="sve_intx_match">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_match">SVE2 character match</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Histogram Computation - Segment" linkref="sve_intx_histseg" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_histseg" iclass="sve_intx_histseg">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_histseg">SVE2 histogram generation (segment)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_histseg" iclass="UNALLOCATED_220">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Histogram Computation - Vector" linkref="sve_intx_histcnt" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_histcnt" iclass="sve_intx_histcnt">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_intx_histcnt">SVE2 histogram generation (vector)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Crypto Extensions" linkref="sve_intx_crypto" />
|
|
<tr class="maintable" size="32" groupid="sve_intx_crypto" iclass="sve_crypto_binary_const">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_crypto_binary_const">SVE2 crypto constructive binary operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_37">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_crypto" iclass="sve_crypto_unary">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_crypto_unary">SVE2 crypto unary operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_221">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_40">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_41">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_42">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_intx_crypto" iclass="sve_crypto_binary_dest">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_crypto_binary_dest">SVE2 crypto destructive binary operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_222">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_intx_crypto" iclass="UNALLOCATED_223">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Complex Addition" linkref="sve_fp_fcadd" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fcadd" iclass="sve_fp_fcadd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcadd">SVE floating-point complex add (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Convert Precision Odd Elements" linkref="sve_fp_fcvt2" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fcvt2" iclass="sve_fp_fcvt2">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcvt2">SVE floating-point convert precision odd elements</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE2 Floating Point Pairwise" linkref="sve_fp_pairwise" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_pairwise" iclass="sve_fp_pairwise">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_pairwise">SVE2 floating-point pairwise operations</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="sve_fp_fastreduceq" linkref="sve_fp_fastreduceq" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fastreduceq" iclass="sve_fp_fast_redq">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fast_redq">SVE floating-point recursive reduction (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Complex Multiply-Add" linkref="sve_fp_fcmla" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fcmla" iclass="sve_fp_fcmla">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcmla">SVE floating-point complex multiply-add (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Multiply-Add - Indexed" linkref="sve_fp_fma_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma_by_indexed_elem" iclass="sve_fp_fma_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_by_indexed_elem">SVE floating-point multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Complex Multiply-Add - Indexed" linkref="sve_fp_fcmla_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fcmla_by_indexed_elem" iclass="sve_fp_fcmla_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fcmla_by_indexed_elem">SVE floating-point complex multiply-add (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="sve_fp_clamp" linkref="sve_fp_clamp" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_clamp" iclass="sve_fp_clamp">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_clamp">SVE FP clamp</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Multiply - Indexed" linkref="sve_fp_fmul_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fmul_by_indexed_elem" iclass="sve_fp_fmul_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fmul_by_indexed_elem">SVE floating-point multiply (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Widening Multiply-Add - Indexed" linkref="sve_fp_fma_w_by_indexed_elem" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma_w_by_indexed_elem" iclass="sve_fp_fdot_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fdot_by_indexed_elem">SVE BFloat16 floating-point dot product (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_fma_w_by_indexed_elem" iclass="UNALLOCATED_47">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma_w_by_indexed_elem" iclass="sve_fp_fma_long_by_indexed_elem">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_long_by_indexed_elem">SVE floating-point multiply-add long (indexed)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Widening Multiply-Add" linkref="sve_fp_fma_w" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma_w" iclass="sve_fp_fdot">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fdot">SVE BFloat16 floating-point dot product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma_w" iclass="sve_fp_fma_long">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fma_long">SVE floating-point multiply-add long</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Matrix Multiply Accumulate" linkref="sve_fp_fmmla" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fmmla" iclass="sve_fp_fmmla">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fmmla">SVE floating point matrix multiply accumulate</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Fast Reduction" linkref="sve_fp_fastreduce" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fastreduce" iclass="sve_fp_fast_red">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_fast_red">SVE floating-point recursive reduction</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Unary Operations - Unpredicated" linkref="sve_fp_unary_unpred" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary_unpred" iclass="sve_fp_2op_u_zd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_u_zd">SVE floating-point reciprocal estimate (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_unary_unpred" iclass="UNALLOCATED_225">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Compare - with Zero" linkref="sve_fp_cmpzero" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_cmpzero" iclass="sve_fp_2op_p_pd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_pd">SVE floating-point compare with zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_cmpzero" iclass="UNALLOCATED_48">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Accumulating Reduction" linkref="sve_fp_slowreduce" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_slowreduce" iclass="sve_fp_2op_p_vd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_vd">SVE floating-point serial reduction (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_slowreduce" iclass="UNALLOCATED_49">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Arithmetic - Unpredicated" linkref="sve_fp_unpred" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_unpred" iclass="sve_fp_3op_u_zd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_3op_u_zd">SVE floating-point arithmetic (unpredicated)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Arithmetic - Predicated" linkref="sve_fp_pred" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_pred" iclass="sve_fp_2op_p_zds">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zds">SVE floating-point arithmetic (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_pred" iclass="sve_fp_ftmad">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_ftmad">SVE floating-point trig multiply-add coefficient</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_pred" iclass="UNALLOCATED_226">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_pred" iclass="sve_fp_2op_i_p_zds">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_i_p_zds">SVE floating-point arithmetic with immediate (predicated)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_fp_pred" iclass="UNALLOCATED_227">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="4">!= 0000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Unary Operations - Predicated" linkref="sve_fp_unary" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary" iclass="sve_fp_2op_p_zd_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zd_a">SVE floating-point round to integral value</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary" iclass="sve_fp_2op_p_zd_b_0">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zd_b_0">SVE floating-point convert precision</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary" iclass="sve_fp_2op_p_zd_b_1">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zd_b_1">SVE floating-point unary operations</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary" iclass="sve_fp_2op_p_zd_c">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zd_c">SVE integer convert to floating-point</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_unary" iclass="sve_fp_2op_p_zd_d">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_2op_p_zd_d">SVE floating-point convert to integer</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Compare - Vectors" linkref="sve_fp_cmpvev" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_cmpvev" iclass="sve_fp_3op_p_pd">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_3op_p_pd">SVE floating-point compare vectors</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Floating Point Multiply-Add" linkref="sve_fp_fma" />
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma" iclass="sve_fp_3op_p_zds_a">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_3op_p_zds_a">SVE floating-point multiply-accumulate writing addend</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_fp_fma" iclass="sve_fp_3op_p_zds_b">
|
|
<td class="boxleft" ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_fp_3op_p_zds_b">SVE floating-point multiply-accumulate writing multiplicand</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - 32-bit Gather and Unsized Contiguous" linkref="sve_mem32" />
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_gldnt_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_gldnt_vs">SVE2 32-bit gather non-temporal load (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem32" iclass="UNALLOCATED_54">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_prfm_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_prfm_ss">SVE contiguous prefetch (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_prfm_vi">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_prfm_vi">SVE 32-bit gather prefetch (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_gld_vi">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_gld_vi">SVE 32-bit gather load (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_ld_dup">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_ld_dup">SVE load and broadcast element</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_prfm_sv">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_prfm_sv">SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem32" iclass="UNALLOCATED_55">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_gld_sv_a">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_gld_sv_a">SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_gld_sv_b">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_gld_sv_b">SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem32" iclass="UNALLOCATED_57">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_pfill">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_pfill">SVE load predicate register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem32" iclass="UNALLOCATED_56">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_fill">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_fill">SVE load vector register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_prfm_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_prfm_si">SVE contiguous prefetch (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem32" iclass="UNALLOCATED_58">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem32" iclass="sve_mem_32b_gld_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 11</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_32b_gld_vs">SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Contiguous Load" linkref="sve_memcld" />
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_ldqr_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_ldqr_ss">SVE load and broadcast quadword (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cld_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cld_ss">SVE contiguous load (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cldff_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cldff_ss">SVE contiguous first-fault load (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_ldqr_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_ldqr_si">SVE load and broadcast quadword (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cld_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cld_si">SVE contiguous load (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cldnf_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cldnf_si">SVE contiguous non-fault load (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cld_ss_q">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cld_ss_q">SVE contiguous load (quadwords, scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cldnt_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cldnt_ss">SVE contiguous non-temporal load (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cldnt_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cldnt_si">SVE contiguous non-temporal load (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_cld_si_q">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cld_si_q">SVE contiguous load (quadwords, scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_eldq_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_eldq_si">SVE load multiple structures (quadwords, scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_eldq_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_eldq_ss">SVE load multiple structures (quadwords, scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memcld" iclass="UNALLOCATED_66">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_eld_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_eld_ss">SVE load multiple structures (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcld" iclass="sve_mem_eld_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_eld_si">SVE load multiple structures (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memcld" iclass="UNALLOCATED_228">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memcld" iclass="UNALLOCATED_229">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - 64-bit Gather" linkref="sve_mem64" />
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gld_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gld_vs">SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gldnt_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gldnt_vs">SVE2 64-bit gather non-temporal load (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_prfm_vi">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_prfm_vi">SVE 64-bit gather prefetch (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem64" iclass="UNALLOCATED_160">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gld_vi">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gld_vi">SVE 64-bit gather load (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gld_vs2">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gld_vs2">SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_prfm_sv">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_prfm_sv">SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gldq_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gldq_vs">SVE2 128-bit gather load (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem64" iclass="UNALLOCATED_161">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem64" iclass="UNALLOCATED_162">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_prfm_sv2">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_prfm_sv2">SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gld_sv">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gld_sv">SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_mem64" iclass="UNALLOCATED_288">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_mem64" iclass="sve_mem_64b_gld_sv2">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_64b_gld_sv2">SVE 64-bit gather load (scalar plus 64-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Non-temporal and Quadword Scatter Store" linkref="sve_memsst_nt" />
|
|
<tr class="maintable" size="32" groupid="sve_memsst_nt" iclass="sve_mem_sstnt_64b_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sstnt_64b_vs">SVE2 64-bit scatter non-temporal store (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memsst_nt" iclass="sve_mem_sstnt_32b_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sstnt_32b_vs">SVE2 32-bit scatter non-temporal store (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memsst_nt" iclass="sve_mem_sstq_64b_vs">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sstq_64b_vs">SVE2 128-bit scatter store (vector plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memsst_nt" iclass="UNALLOCATED_293">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Non-temporal and Multi-register Contiguous Store" linkref="sve_memcst_nt" />
|
|
<tr class="maintable" size="32" groupid="sve_memcst_nt" iclass="sve_mem_cstnt_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cstnt_ss">SVE contiguous non-temporal store (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memcst_nt" iclass="sve_mem_est_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_est_ss">SVE store multiple structures (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Contiguous Store and Unsized Contiguous" linkref="sve_memst_cs" />
|
|
<tr class="maintable" size="32" groupid="sve_memst_cs" iclass="sve_mem_estq_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_estq_si">SVE store multiple structures (quadwords, scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memst_cs" iclass="UNALLOCATED_168">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_cs" iclass="sve_mem_estq_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_estq_ss">SVE store multiple structures (quadwords, scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memst_cs" iclass="UNALLOCATED_169">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_cs" iclass="sve_mem_pspill">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_pspill">SVE store predicate register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memst_cs" iclass="UNALLOCATED_170">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_cs" iclass="sve_mem_spill">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_spill">SVE store vector register</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="sve_memst_cs" iclass="UNALLOCATED_171">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_cs" iclass="sve_mem_cst_ss">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="3">!= 110</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cst_ss">SVE contiguous store (scalar plus scalar)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Scatter" linkref="sve_memst_ss2" />
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss2" iclass="sve_mem_sst_vs2">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_vs2">SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss2" iclass="sve_mem_sst_sv2">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_sv2">SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss2" iclass="sve_mem_sst_vi_a">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_vi_a">SVE 64-bit scatter store (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss2" iclass="sve_mem_sst_vi_b">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_vi_b">SVE 32-bit scatter store (vector plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Contiguous Store with Immediate Offset" linkref="sve_memst_si" />
|
|
<tr class="maintable" size="32" groupid="sve_memst_si" iclass="sve_mem_cst_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cst_si">SVE contiguous store (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_si" iclass="sve_mem_cstnt_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_cstnt_si">SVE contiguous non-temporal store (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_si" iclass="sve_mem_est_si">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_est_si">SVE store multiple structures (scalar plus immediate)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SVE Memory - Scatter with Optional Sign Extend" linkref="sve_memst_ss" />
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss" iclass="sve_mem_sst_vs_a">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_vs_a">SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss" iclass="sve_mem_sst_sv_a">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_sv_a">SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss" iclass="sve_mem_sst_vs_b">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_vs_b">SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="sve_memst_ss" iclass="sve_mem_sst_sv_b">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="sve_mem_sst_sv_b">SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Binary Outer Product - 32 bit" linkref="mortlach_32bit_bin_prod" />
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_bin_prod" iclass="mortlach_bini32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_bini32_prod">SME2 32-bit binary outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_32bit_bin_prod" iclass="UNALLOCATED_50">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME FP Outer Product - 16 bit" linkref="mortlach_16bit_fp_prod" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_16bit_fp_prod" iclass="UNALLOCATED_52">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_16bit_fp_prod" iclass="mortlach_f16f16_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_f16f16_prod">SME FP16 non-widening outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_16bit_fp_prod" iclass="mortlach_b16b16_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_b16b16_prod">SME non-widening BF16 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME FP Outer Product - 32 bit" linkref="mortlach_32bit_fp_prod" />
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_fp_prod" iclass="mortlach_f32f32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_f32f32_prod">SME FP32 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_fp_prod" iclass="mortlach_b16f32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_b16f32_prod">SME widening BF16 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_fp_prod" iclass="mortlach_f16f32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_f16f32_prod">SME FP16 widening outer product</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Memory (Contiguous)" linkref="mortlach_multi_mem_ctg" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_ctg" iclass="UNALLOCATED_59">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi2_cld_cldnt_ss_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cld_cldnt_ss_ctg">SME2 multi-vec contiguous load (scalar plus scalar, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi4_cld_cldnt_ss_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cld_cldnt_ss_ctg">SME2 multi-vec contiguous load (scalar plus scalar, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi2_cst_cstnt_ss_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cst_cstnt_ss_ctg">SME2 multi-vec contiguous store (scalar plus scalar, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi4_cst_cstnt_ss_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cst_cstnt_ss_ctg">SME2 multi-vec contiguous store (scalar plus scalar, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_ctg" iclass="UNALLOCATED_60">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_ctg" iclass="UNALLOCATED_61">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi2_cld_cldnt_si_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cld_cldnt_si_ctg">SME2 multi-vec contiguous load (scalar plus immediate, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi4_cld_cldnt_si_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cld_cldnt_si_ctg">SME2 multi-vec contiguous load (scalar plus immediate, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi2_cst_cstnt_si_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cst_cstnt_si_ctg">SME2 multi-vec contiguous store (scalar plus immediate, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_ctg" iclass="mortlach_multi4_cst_cstnt_si_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cst_cstnt_si_ctg">SME2 multi-vec contiguous store (scalar plus immediate, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Memory (Strided)" linkref="mortlach_multi_mem_nctg" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_nctg" iclass="UNALLOCATED_63">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi2_cld_cldnt_ss_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cld_cldnt_ss_nctg">SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi4_cld_cldnt_ss_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cld_cldnt_ss_nctg">SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi2_cst_cstnt_ss_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cst_cstnt_ss_nctg">SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi4_cst_cstnt_ss_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cst_cstnt_ss_nctg">SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_nctg" iclass="UNALLOCATED_64">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_mem_nctg" iclass="UNALLOCATED_65">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi2_cld_cldnt_si_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cld_cldnt_si_nctg">SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi4_cld_cldnt_si_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cld_cldnt_si_nctg">SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi2_cst_cstnt_si_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_cst_cstnt_si_nctg">SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_mem_nctg" iclass="mortlach_multi4_cst_cstnt_si_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_cst_cstnt_si_nctg">SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME Integer Outer Product - 32 bit" linkref="mortlach_32bit_int_prod" />
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_int_prod" iclass="mortlach_i8i32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_i8i32_prod">SME Int8 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_32bit_int_prod" iclass="mortlach_i16i32_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_i16i32_prod">SME2 Int16 two-way outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_32bit_int_prod" iclass="UNALLOCATED_62">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME Outer Product - 64 bit" linkref="mortlach_64bit_prod" />
|
|
<tr class="maintable" size="32" groupid="mortlach_64bit_prod" iclass="mortlach_f64f64_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_f64f64_prod">SME FP64 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_64bit_prod" iclass="UNALLOCATED_51">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_64bit_prod" iclass="UNALLOCATED_53">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_64bit_prod" iclass="mortlach_i16i64_prod">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_i16i64_prod">SME Int16 outer product</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME Zero" linkref="mortlach_zero" />
|
|
<tr class="maintable" size="32" groupid="mortlach_zero" iclass="mortlach_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zero">SME zero array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zero" iclass="UNALLOCATED_246">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="10">!= 0000000000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multiple Zero" linkref="mortlach_multizero" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multizero" iclass="mortlach_multi_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi_zero">SME multiple vectors zero array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multizero" iclass="UNALLOCATED_247">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="10">!= 0000000000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Zero Lookup Table" linkref="mortlach_zero_zt" />
|
|
<tr class="maintable" size="32" groupid="mortlach_zero_zt" iclass="mortlach_zero_zt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zero_zt">SME2 zero lookup table</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zero_zt" iclass="UNALLOCATED_249">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="14">!= 00000000000000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Move Lookup Table" linkref="mortlach_mov_zt" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mov_zt" iclass="UNALLOCATED_250">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mov_zt" iclass="mortlach_extract_zt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_extract_zt">SME2 move from lookup table</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mov_zt" iclass="mortlach_insert_zt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_insert_zt">SME2 move into lookup table</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Expand Lookup Table (Non-contiguous)" linkref="mortlach_zt_expand_nctg" />
|
|
<tr class="maintable" size="32" groupid="mortlach_zt_expand_nctg" iclass="mortlach_expand_2dst_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_expand_2dst_nctg">SME2 lookup table expand two non-contiguous registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_nctg" iclass="UNALLOCATED_87">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_zt_expand_nctg" iclass="mortlach_expand_4dst_nctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_expand_4dst_nctg">SME2 lookup table expand four non-contiguous registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_nctg" iclass="UNALLOCATED_88">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_nctg" iclass="UNALLOCATED_252">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Expand Lookup Table (Contiguous)" linkref="mortlach_zt_expand_ctg" />
|
|
<tr class="maintable" size="32" groupid="mortlach_zt_expand_ctg" iclass="mortlach_expand_2dst_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_expand_2dst_ctg">SME2 lookup table expand two contiguous registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_ctg" iclass="UNALLOCATED_85">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_ctg" iclass="UNALLOCATED_84">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_zt_expand_ctg" iclass="mortlach_expand_4dst_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_expand_4dst_ctg">SME2 lookup table expand four contiguous registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_zt_expand_ctg" iclass="UNALLOCATED_251">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_zt_expand_ctg" iclass="mortlach_expand_1dst">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_expand_1dst">SME2 lookup table expand one register</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME Move into Array" linkref="mortlach_ins" />
|
|
<tr class="maintable" size="32" groupid="mortlach_ins" iclass="mortlach_insert_pred">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_insert_pred">SME move vector to array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ins" iclass="mortlach_multi2_insert_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_insert_ctg">SME2 move vector to tile, two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ins" iclass="mortlach_multi4_insert_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_insert_ctg">SME2 move vector to tile, four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_70">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_75">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_67">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_68">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_69">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_238">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ins" iclass="mortlach_multi2_za_insert_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_za_insert_ctg">SME2 move vector to array, two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ins" iclass="mortlach_multi4_za_insert_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_za_insert_ctg">SME2 move vector to array, four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_71">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_72">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_73">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_239">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_74">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_240">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_241">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_242">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_243">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_244">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ins" iclass="UNALLOCATED_245">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME Move from Array" linkref="mortlach_ext" />
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_extract_pred">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_extract_pred">SME move array to vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_extract_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_extract_zero">SME zeroing move array to vector</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_230">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="3">!= 000</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi2_extract_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_extract_ctg">SME2 move tile to vector, two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi2_extract_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_extract_zero">SME2 zeroing move tile to vector, two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi4_extract_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_extract_ctg">SME2 move tile to vector, four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi4_extract_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_extract_zero">SME2 zeroing move tile to vector, four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_78">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_82">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_77">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_76">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_231">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi2_za_extract_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_za_extract_ctg">SME2 move array to vector, two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi2_za_extract_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_za_extract_zero">mortlach_multi2_za_extract_zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi4_za_extract_ctg">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_za_extract_ctg">SME2 move array to vector, four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_ext" iclass="mortlach_multi4_za_extract_zero">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_za_extract_zero">mortlach_multi4_za_extract_zero</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_80">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_79">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_232">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_81">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_234">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_233">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_235">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_236">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_ext" iclass="UNALLOCATED_237">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME Add Vector to Array" linkref="mortlach_hvadd" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_hvadd" iclass="UNALLOCATED_83">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_hvadd" iclass="mortlach_addhv">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_addhv">SME add vector to array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_hvadd" iclass="UNALLOCATED_86">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_hvadd" iclass="UNALLOCATED_248">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple and Single Array Vectors" linkref="mortlach_multi_array_1" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_1" iclass="UNALLOCATED_90">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_1" iclass="UNALLOCATED_91">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_1" iclass="UNALLOCATED_92">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_mla_long_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_mla_long_long_sm">SME2 single-multi long long MLA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi1_zz_za_mla_long_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_zz_za_mla_long_long_sm">SME2 multiple and single vector long long FMA one source</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_z_za_fpdot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_fpdot_sm">SME2 single-multi FP dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_z_za_4way_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_4way_dot_sm">SME2 single-multi four-way dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_float_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_float_sm">SME2 single-multi ternary FP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_int_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_int_sm">SME2 single-multi ternary int two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_f16_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_f16_sm">SME2 single-multi ternary FP16 two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_1" iclass="UNALLOCATED_115">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_mla_long_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_mla_long_long_sm">SME2 single-multi long long MLA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_z_za_fpdot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_fpdot_sm">SME2 single-multi FP dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_z_za_4way_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_4way_dot_sm">SME2 single-multi four-way dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_float_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_float_sm">SME2 single-multi ternary FP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_int_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_int_sm">SME2 single-multi ternary int four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_f16_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_f16_sm">SME2 single-multi ternary FP16 four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_fma_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_fma_long_sm">SME2 single-multi long FMA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi1_zz_za_fma_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_zz_za_fma_long_sm">SME2 multiple and single vector long FMA one source</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_z_za_mixed_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_mixed_dot_sm">SME2 single-multi mixed dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_fma_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_fma_long_sm">SME2 single-multi long FMA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_z_za_mixed_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_mixed_dot_sm">SME2 single-multi mixed dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_zz_za_mla_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_mla_long_sm">SME2 single-multi long MLA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi1_zz_za_mla_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_zz_za_mla_long_sm">SME2 multiple and single vector long MLA one source</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi2_z_za_2way_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_2way_dot_sm">SME2 single-multi two-way dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_zz_za_mla_long_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_mla_long_sm">SME2 single-multi long MLA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_1" iclass="mortlach_multi4_z_za_2way_dot_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_2way_dot_sm">SME2 single-multi two-way dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple Array Vectors (Two registers)" linkref="mortlach_multi_array_2a" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_132">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_133">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_mla_long_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_mla_long_long_mm">SME2 multiple vectors long long MLA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_131">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_134">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_fpdot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_fpdot_mm">SME2 multiple vectors FP dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_f16_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_f16_mm">SME2 multiple vectors ternary FP16 two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_135">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_4way_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_4way_dot_mm">SME2 multiple vectors four-way dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_137">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_float_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_float_mm">SME2 multiple vectors ternary FP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_int_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_int_mm">SME2 multiple vectors ternary int two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_138">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_148">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_149">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_float_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_float_mm">SME2 multiple vectors binary FP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_int_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_int_mm">SME2 multiple vectors binary int two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_f16_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_f16_mm">SME2 multiple vectors binary FP16 two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_151">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_281">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_282">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_fma_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_fma_long_mm">SME2 multiple vectors long FMA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_mixed_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_mixed_dot_mm">SME2 multiple vectors mixed dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2a" iclass="UNALLOCATED_136">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_zz_za_mla_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zz_za_mla_long_mm">SME2 multiple vectors long MLA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2a" iclass="mortlach_multi2_z_za_2way_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_za_2way_dot_mm">SME2 multiple vectors two-way dot product two registers</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple Array Vectors (Four registers)" linkref="mortlach_multi_array_2b" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_283">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_141">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_mla_long_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_mla_long_long_mm">SME2 multiple vectors long long MLA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_140">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_142">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_fpdot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_fpdot_mm">SME2 multiple vectors FP dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_f16_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_f16_mm">SME2 multiple vectors ternary FP16 four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_143">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_4way_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_4way_dot_mm">SME2 multiple vectors four-way dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_146">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_float_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_float_mm">SME2 multiple vectors ternary FP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_int_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_int_mm">SME2 multiple vectors ternary int four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_150">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_144">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_147">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_float_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_float_mm">SME2 multiple vectors binary FP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_int_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_int_mm">SME2 multiple vectors binary int four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_f16_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_f16_mm">SME2 multiple vectors binary FP16 four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_153">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_284">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_285">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_286">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_287">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_fma_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_fma_long_mm">SME2 multiple vectors long FMA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_mixed_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_mixed_dot_mm">SME2 multiple vectors mixed dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_array_2b" iclass="UNALLOCATED_145">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_zz_za_mla_long_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zz_za_mla_long_mm">SME2 multiple vectors long MLA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_array_2b" iclass="mortlach_multi4_z_za_2way_dot_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_za_2way_dot_mm">SME2 multiple vectors two-way dot product four registers</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Indexed (One register)" linkref="mortlach_multi_indexed_1" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_1" iclass="mortlach_multi1_mla_long_long_idx_s">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_mla_long_long_idx_s">SME2 multi-vec indexed long long MLA one source 32-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_1" iclass="UNALLOCATED_122">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_1" iclass="mortlach_multi1_mla_long_long_idx_d">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_mla_long_long_idx_d">SME2 multi-vec indexed long long MLA one source 64-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_1" iclass="UNALLOCATED_126">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_1" iclass="mortlach_multi1_fma_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_fma_long_idx">SME2 multi-vec indexed long FMA one source</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_1" iclass="UNALLOCATED_155">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_1" iclass="mortlach_multi1_mla_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi1_mla_long_idx">SME2 multi-vec indexed long MLA one source</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Indexed (Two registers)" linkref="mortlach_multi_indexed_2" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_mla_long_long_idx_s">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_mla_long_long_idx_s">SME2 multi-vec indexed long long MLA two sources 32-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_zza_idx_h">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zza_idx_h">SME2 multi-vec ternary indexed two registers 16-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_zza_idx_s">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zza_idx_s">SME2 multi-vec ternary indexed two registers 32-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_mla_long_long_idx_d">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_mla_long_long_idx_d">SME2 multi-vec indexed long long MLA two sources 64-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_2" iclass="UNALLOCATED_127">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_2" iclass="UNALLOCATED_128">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_fma_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_fma_long_idx">SME2 multi-vec indexed long FMA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_2" iclass="UNALLOCATED_129">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_zza_idx_d">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_zza_idx_d">SME2 multi-vec ternary indexed two registers 64-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_2" iclass="UNALLOCATED_156">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_2" iclass="mortlach_multi2_mla_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_mla_long_idx">SME2 multi-vec indexed long MLA two sources</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Indexed (Four registers)" linkref="mortlach_multi_indexed_3" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_89">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_mla_long_long_idx_s">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_mla_long_long_idx_s">SME2 multi-vec indexed long long MLA four sources 32-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_zza_idx_h">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zza_idx_h">SME2 multi-vec ternary indexed four registers 16-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_zza_idx_s">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zza_idx_s">SME2 multi-vec ternary indexed four registers 32-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_mla_long_long_idx_d">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_mla_long_long_idx_d">SME2 multi-vec indexed long long MLA four sources 64-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_253">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_130">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_fma_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_fma_long_idx">SME2 multi-vec indexed long FMA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_254">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_158">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_zza_idx_d">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_zza_idx_d">SME2 multi-vec ternary indexed four registers 64-bit</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_indexed_3" iclass="UNALLOCATED_157">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_indexed_3" iclass="mortlach_multi4_mla_long_idx">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_mla_long_idx">SME2 multi-vec indexed long MLA four sources</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)" linkref="mortlach_multi_sve_2a" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2a" iclass="UNALLOCATED_257">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2a" iclass="mortlach_multi2_z_z_minmax_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_minmax_sm">SME2 single-multi int min/max two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2a" iclass="mortlach_multi2_z_z_fminmax_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_fminmax_sm">SME2 single-multi FP min/max two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2a" iclass="mortlach_multi2_z_z_shift_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_shift_sm">SME2 single-multi shift two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2a" iclass="mortlach_multi2_z_z_add_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_add_sm">SME2 single-multi add two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2a" iclass="UNALLOCATED_95">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2a" iclass="UNALLOCATED_258">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2a" iclass="mortlach_multi2_z_z_sqdmulh_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_sqdmulh_sm">SME2 single-multi signed saturating doubling multiply high two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2a" iclass="UNALLOCATED_96">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2a" iclass="UNALLOCATED_259">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)" linkref="mortlach_multi_sve_2b" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_97">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_260">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2b" iclass="mortlach_multi4_z_z_minmax_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_minmax_sm">SME2 single-multi int min/max four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2b" iclass="mortlach_multi4_z_z_fminmax_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_fminmax_sm">SME2 single-multi FP min/max four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2b" iclass="mortlach_multi4_z_z_shift_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_shift_sm">SME2 single-multi shift four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_98">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2b" iclass="mortlach_multi4_z_z_add_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_add_sm">SME2 single-multi add four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_261">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_262">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2b" iclass="mortlach_multi4_z_z_sqdmulh_sm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_sqdmulh_sm">SME2 single-multi signed saturating doubling multiply high four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_263">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2b" iclass="UNALLOCATED_264">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)" linkref="mortlach_multi_sve_2c" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2c" iclass="UNALLOCATED_265">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2c" iclass="mortlach_multi2_z_z_minmax_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_minmax_mm">SME2 multiple vectors int min/max two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2c" iclass="mortlach_multi2_z_z_fminmax_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_fminmax_mm">SME2 multiple vectors FP min/max two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2c" iclass="mortlach_multi2_z_z_shift_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_shift_mm">SME2 multiple vectors shift two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2c" iclass="UNALLOCATED_99">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2c" iclass="mortlach_multi2_z_z_sqdmulh_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_sqdmulh_mm">SME2 multi-vector signed saturating doubling multiply high two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2c" iclass="UNALLOCATED_100">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2c" iclass="UNALLOCATED_266">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)" linkref="mortlach_multi_sve_2d" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_101">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_267">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2d" iclass="mortlach_multi4_z_z_minmax_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_minmax_mm">SME2 multiple vectors int min/max four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2d" iclass="mortlach_multi4_z_z_fminmax_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_fminmax_mm">SME2 multiple vectors FP min/max four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2d" iclass="mortlach_multi4_z_z_shift_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_shift_mm">SME2 multiple vectors shift four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_102">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_103">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_2d" iclass="mortlach_multi4_z_z_sqdmulh_mm">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_sqdmulh_mm">SME2 multi-vector signed saturating doubling multiply high four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_268">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_269">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_2d" iclass="UNALLOCATED_108">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - SVE Select" linkref="mortlach_multi_sve_1" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_1" iclass="mortlach_multi2_select_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_select_int">SME2 multi-vec select two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_1" iclass="UNALLOCATED_93">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_1" iclass="UNALLOCATED_94">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_1" iclass="mortlach_multi4_select_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_select_int">SME2 multi-vec select four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_1" iclass="UNALLOCATED_255">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_1" iclass="UNALLOCATED_256">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_1" iclass="UNALLOCATED_110">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - SVE Constructive Binary" linkref="mortlach_multi_sve_3" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi2_fclamp">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_fclamp">SME2 multi-vec FCLAMP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_3" iclass="UNALLOCATED_104">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi2_clamp_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_clamp_int">SME2 multi-vec CLAMP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_3" iclass="UNALLOCATED_106">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi4_fclamp">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_fclamp">SME2 multi-vec FCLAMP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_3" iclass="UNALLOCATED_105">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi4_clamp_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_clamp_int">SME2 multi-vec CLAMP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi2_z_z_zip">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_zip">SME2 multi-vec ZIP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi4_qrshr">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_qrshr">SME2 multi-vec saturating shift right narrow four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi2_z_z_long_zip">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_z_z_long_zip">SME2 multi-vec quadwords ZIP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_3" iclass="UNALLOCATED_123">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_3" iclass="UNALLOCATED_139">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_3" iclass="mortlach_multi2_qrshr">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_qrshr">SME2 multi-vec saturating shift right narrow two registers</a>
|
|
</td>
|
|
</tr>
|
|
<maintablesect sect="SME2 Multi-vector - SVE Constructive Unary" linkref="mortlach_multi_sve_4" />
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_wide_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_wide_int">SME2 multi-vec unpack two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_frint">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_frint">SME2 multi-vec FRINT two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_113">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_114">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_narrow_int_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_narrow_int_cvrt">SME2 multi-vec int down convert four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_wide_int">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_wide_int">SME2 multi-vec unpack four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_119">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_120">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_z_z_zip">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_zip">SME2 multi-vec ZIP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_frint">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_frint">SME2 multi-vec FRINT four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_273">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_274">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_narrow_fp_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_narrow_fp_cvrt">SME2 multi-vec FP down convert two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_narrow_int_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_narrow_int_cvrt">SME2 multi-vec int down convert two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_111">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_118">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_fpint_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_fpint_cvrt">SME2 multi-vec FP to int convert two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_107">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_intfp_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_intfp_cvrt">SME2 multi-vec int to FP two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_109">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_112">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_116">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_fpint_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_fpint_cvrt">SME2 multi-vec FP to int convert four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_270">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_intfp_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_intfp_cvrt">SME2 multi-vec int to FP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_271">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2" class="boxright">!= 00</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_117">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_121">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_272">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="2">!= 00</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi4_z_z_long_zip">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">0</td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi4_z_z_long_zip">SME2 multi-vec quadwords ZIP four registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_125">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_124">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_152">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_154">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_multi_sve_4" iclass="mortlach_multi2_wide_fp_cvrt">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_multi2_wide_fp_cvrt">SME2 multi-vec convert two registers</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_280">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_159">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_275">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_276">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_277">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright">1</td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_278">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_multi_sve_4" iclass="UNALLOCATED_279">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">1</td>
|
|
<td colspan="2">!= 00</td>
|
|
<td ingroup="1">1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<maintablesect sect="SME Memory" linkref="mortlach_mem" />
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_163">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_contig_load">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_contig_load">SME load array vector (elements)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_contig_store">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_contig_store">SME store array vector (elements)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_zt_ldst">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_zt_ldst">SME2 lookup table load/store</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_290">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_291">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_ctxt_ldst">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_ctxt_ldst">SME save and restore array</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_164">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_289">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td colspan="3">!= 000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_292">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td colspan="5">!= 00000</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_165">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_166">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" undef="1" groupid="mortlach_mem" iclass="UNALLOCATED_167">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_contig_qload">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_contig_qload">SME load array vector (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
<tr class="maintable" size="32" groupid="mortlach_mem" iclass="mortlach_contig_qstore">
|
|
<td class="boxleft" ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">1</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td ingroup="1">0</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td>1</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>0</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="boxright"></td>
|
|
<td class="iclassname">
|
|
<a classid="mortlach_contig_qstore">SME store array vector (quadwords)</a>
|
|
</td>
|
|
</tr>
|
|
</tablebody>
|
|
</maintable>
|
|
<funcgroupheader id="control">Branches, Exception Generating and System instructions</funcgroupheader>
|
|
<iclass_sect id="barriers" title="Barriers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="20" settings="20">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="barriers" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">CRm</th>
|
|
<th class="bitfields">op2</th>
|
|
<th class="bitfields">Rt</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLREX_BN_barriers" iformfile="clrex.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CLREX">CLREX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DSB_BO_barriers" iformfile="dsb.xml" label="memory barrier" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="DSB">DSB</td>
|
|
<td class="enctags">Memory barrier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DMB_BO_barriers" iformfile="dmb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="DMB">DMB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ISB_BI_barriers" iformfile="isb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="ISB">ISB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SB_only_barriers" arch_version="FEAT_SB" iformfile="sb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="SB">SB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">xx0x</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DSB_BOn_barriers" arch_version="FEAT_XS" iformfile="dsb.xml" label="Memory nXS barrier" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">xx10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="DSB">DSB</td>
|
|
<td class="enctags">Memory nXS barrier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">xx11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TCOMMIT_only_barriers" arch_version="FEAT_TME" iformfile="tcommit.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="TCOMMIT">TCOMMIT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">001x</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_barriers" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="compbranch" title="Compare and branch (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/branch/conditional/compare">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="19" name="imm19" usename="1">
|
|
<c colspan="19"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="compbranch" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="CBZ_32_compbranch" iformfile="cbz.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CBZ">CBZ</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CBNZ_32_compbranch" iformfile="cbnz.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="CBNZ">CBNZ</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CBZ_64_compbranch" iformfile="cbz.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CBZ">CBZ</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CBNZ_64_compbranch" iformfile="cbnz.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="CBNZ">CBNZ</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="condbranch" title="Conditional branch (immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="19" name="imm19" usename="1">
|
|
<c colspan="19"></c>
|
|
</box>
|
|
<box hibit="4" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="condbranch" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">o1</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="B_only_condbranch" iformfile="b_cond.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="B_cond">B.cond</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BC_only_condbranch" arch_version="FEAT_HBC" iformfile="bc_cond.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="BC_cond">BC.cond</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_condbranch" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="exception" title="Exception generation">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="20" width="16" name="imm16" usename="1">
|
|
<c colspan="16"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="LL" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="exception" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">op2</th>
|
|
<th class="bitfields">LL</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SVC_EX_exception" iformfile="svc.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="SVC">SVC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="HVC_EX_exception" iformfile="hvc.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="HVC">HVC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMC_EX_exception" iformfile="smc.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="SMC">SMC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BRK_EX_exception" iformfile="brk.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="BRK">BRK</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="HLT_EX_exception" iformfile="hlt.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="HLT">HLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TCANCEL_EX_exception" arch_version="FEAT_TME" iformfile="tcancel.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="TCANCEL">TCANCEL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DCPS1_DC_exception" iformfile="dcps1.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="DCPS1">DCPS1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DCPS2_DC_exception" iformfile="dcps2.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="DCPS2">DCPS2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DCPS3_DC_exception" iformfile="dcps3.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="DCPS3">DCPS3</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_exception" undef="1" oneofthismnem="14" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="hints" title="Hints">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="20" settings="20">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="hints" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="43*" />
|
|
<col colno="4" printwidth="19*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">CRm</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="HINT_HM_hints" iformfile="hint.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="HINT">HINT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="NOP_HI_hints" iformfile="nop.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="NOP">NOP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="YIELD_HI_hints" iformfile="yield.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="YIELD">YIELD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="WFE_HI_hints" iformfile="wfe.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="WFE">WFE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="WFI_HI_hints" iformfile="wfi.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="WFI">WFI</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SEV_HI_hints" iformfile="sev.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="SEV">SEV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SEVL_HI_hints" iformfile="sevl.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="SEVL">SEVL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DGH_HI_hints" arch_version="FEAT_DGH" iformfile="dgh.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="DGH">DGH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="XPACLRI_HI_hints" arch_version="FEAT_PAuth" iformfile="xpac.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="XPAC">XPACD, XPACI, XPACLRI</td>
|
|
<td class="enctags">System</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIA1716_HI_hints" arch_version="FEAT_PAuth" iformfile="pacia.xml" label="PACIA1716" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="PACIA">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA</td>
|
|
<td class="enctags">System, PACIA1716</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIB1716_HI_hints" arch_version="FEAT_PAuth" iformfile="pacib.xml" label="PACIB1716" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="PACIB">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB</td>
|
|
<td class="enctags">System, PACIB1716</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIA1716_HI_hints" arch_version="FEAT_PAuth" iformfile="autia.xml" label="AUTIA1716" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="AUTIA">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</td>
|
|
<td class="enctags">System, AUTIA1716</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIB1716_HI_hints" arch_version="FEAT_PAuth" iformfile="autib.xml" label="AUTIB1716" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="AUTIB">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</td>
|
|
<td class="enctags">System, AUTIB1716</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ESB_HI_hints" arch_version="FEAT_RAS" iformfile="esb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="ESB">ESB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PSB_HC_hints" arch_version="FEAT_SPE" iformfile="psb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="PSB">PSB CSYNC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TSB_HC_hints" arch_version="FEAT_TRF" iformfile="tsb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="TSB">TSB CSYNC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="GCSB_HD_hints" arch_version="FEAT_GCS" iformfile="gcsb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="GCSB">GCSB DSYNC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSDB_HI_hints" iformfile="csdb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="CSDB">CSDB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLRBHB_HI_hints" arch_version="FEAT_CLRBHB" iformfile="clrbhb.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="CLRBHB">CLRBHB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIAZ_HI_hints" arch_version="FEAT_PAuth" iformfile="pacia.xml" label="PACIAZ" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="PACIA">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA</td>
|
|
<td class="enctags">System, PACIAZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIASP_HI_hints" arch_version="FEAT_PAuth" iformfile="pacia.xml" label="PACIASP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="PACIA">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA</td>
|
|
<td class="enctags">System, PACIASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIBZ_HI_hints" arch_version="FEAT_PAuth" iformfile="pacib.xml" label="PACIBZ" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="PACIB">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB</td>
|
|
<td class="enctags">System, PACIBZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIBSP_HI_hints" arch_version="FEAT_PAuth" iformfile="pacib.xml" label="PACIBSP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="PACIB">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB</td>
|
|
<td class="enctags">System, PACIBSP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIAZ_HI_hints" arch_version="FEAT_PAuth" iformfile="autia.xml" label="AUTIAZ" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="AUTIA">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</td>
|
|
<td class="enctags">System, AUTIAZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIASP_HI_hints" arch_version="FEAT_PAuth" iformfile="autia.xml" label="AUTIASP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="AUTIA">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</td>
|
|
<td class="enctags">System, AUTIASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIBZ_HI_hints" arch_version="FEAT_PAuth" iformfile="autib.xml" label="AUTIBZ" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="AUTIB">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</td>
|
|
<td class="enctags">System, AUTIBZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIBSP_HI_hints" arch_version="FEAT_PAuth" iformfile="autib.xml" label="AUTIBSP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="AUTIB">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</td>
|
|
<td class="enctags">System, AUTIBSP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BTI_HB_hints" arch_version="FEAT_BTI" iformfile="bti.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="3" class="bitfield">xx0</td>
|
|
<td class="iformname" iformid="BTI">BTI</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CHKFEAT_HI_hints" arch_version="FEAT_CHK" iformfile="chkfeat.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="CHKFEAT">CHKFEAT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="pstate" title="PSTATE">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="13" settings="13">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="pstate" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op1</th>
|
|
<th class="bitfields">op2</th>
|
|
<th class="bitfields">Rt</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_pstate" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MSR_SI_pstate" iformfile="msr_imm.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="MSR_imm">MSR (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CFINV_M_pstate" arch_version="FEAT_FlagM" iformfile="cfinv.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CFINV">CFINV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="XAFLAG_M_pstate" arch_version="FEAT_FlagM2" iformfile="xaflag.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="XAFLAG">XAFLAG</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AXFLAG_M_pstate" arch_version="FEAT_FlagM2" iformfile="axflag.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="AXFLAG">AXFLAG</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="systeminstrs" title="System instructions">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="CRn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="systeminstrs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SYS_CR_systeminstrs" iformfile="sys.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SYS">SYS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SYSL_RC_systeminstrs" iformfile="sysl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SYSL">SYSL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="systeminstrswithreg" title="System instructions with register argument">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="20" settings="20">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="systeminstrswithreg" cols="4">
|
|
<col colno="1" printwidth="9*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">CRm</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_systeminstrswithreg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="WFET_only_systeminstrswithreg" arch_version="FEAT_WFxT" iformfile="wfet.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="WFET">WFET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="WFIT_only_systeminstrswithreg" arch_version="FEAT_WFxT" iformfile="wfit.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="WFIT">WFIT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_systeminstrswithreg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_systeminstrswithreg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="syspairinstrs" title="System pair instructions">
|
|
<regdiagram form="32" psname="aarch64/instrs/system/sysops_128">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="CRn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="syspairinstrs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SYSP_CR_syspairinstrs" arch_version="FEAT_SYSINSTR128" iformfile="sysp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SYSP">SYSP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_syspairinstrs" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="systemmove" title="System register move">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="CRn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="systemmove" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="MSR_SR_systemmove" iformfile="msr_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MSR_reg">MSR (register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MRS_RS_systemmove" iformfile="mrs.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="MRS">MRS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="systemmovepr" title="System register pair move">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="CRn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="systemmovepr" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="MSRR_SR_systemmovepr" arch_version="FEAT_SYSREG128" iformfile="msrr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MSRR">MSRR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MRRS_RS_systemmovepr" arch_version="FEAT_SYSREG128" iformfile="mrrs.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="MRRS">MRRS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="systemresult" title="System with result">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="13" settings="13">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="op1" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="CRn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="CRm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="op2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="systemresult" cols="6">
|
|
<col colno="1" printwidth="8*" />
|
|
<col colno="2" printwidth="9*" />
|
|
<col colno="3" printwidth="9*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op1</th>
|
|
<th class="bitfields">CRn</th>
|
|
<th class="bitfields">CRm</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_systemresult" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">!= 011</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_systemresult" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="4" class="bitfield">!= 0011</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_systemresult" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">!= 011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_systemresult" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="4" class="bitfield">!= 000x</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TSTART_BR_systemresult" arch_version="FEAT_TME" iformfile="tstart.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="TSTART">TSTART</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TTEST_BR_systemresult" arch_version="FEAT_TME" iformfile="ttest.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="TTEST">TTEST</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="testbranch" title="Test and branch (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/branch/conditional/test">
|
|
<box hibit="31" name="b5" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="5" name="b40" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="18" width="14" name="imm14" usename="1">
|
|
<c colspan="14"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="testbranch" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="TBZ_only_testbranch" iformfile="tbz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="TBZ">TBZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBNZ_only_testbranch" iformfile="tbnz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="TBNZ">TBNZ</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="branch_imm" title="Unconditional branch (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/branch/unconditional/immediate">
|
|
<box hibit="31" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="25" width="26" name="imm26" usename="1">
|
|
<c colspan="26"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="branch_imm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="B_only_branch_imm" iformfile="b_uncond.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="B_uncond">B</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BL_only_branch_imm" iformfile="bl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="BL">BL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="branch_reg" title="Unconditional branch (register)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="op2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="op3" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="op4" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="branch_reg" cols="7">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<col colno="3" printwidth="11*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<col colno="6" printwidth="30*" />
|
|
<col colno="7" printwidth="26*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">op2</th>
|
|
<th class="bitfields">op3</th>
|
|
<th class="bitfields">Rn</th>
|
|
<th class="bitfields">op4</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BR_64_branch_reg" iformfile="br.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="BR">BR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BRAAZ_64_branch_reg" arch_version="FEAT_PAuth" iformfile="bra.xml" label="key A, zero modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="BRA">BRAA, BRAAZ, BRAB, BRABZ</td>
|
|
<td class="enctags">Key A, zero modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BRABZ_64_branch_reg" arch_version="FEAT_PAuth" iformfile="bra.xml" label="key B, zero modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="BRA">BRAA, BRAAZ, BRAB, BRABZ</td>
|
|
<td class="enctags">Key B, zero modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BLR_64_branch_reg" iformfile="blr.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="BLR">BLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BLRAAZ_64_branch_reg" arch_version="FEAT_PAuth" iformfile="blra.xml" label="key A, zero modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="BLRA">BLRAA, BLRAAZ, BLRAB, BLRABZ</td>
|
|
<td class="enctags">Key A, zero modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BLRABZ_64_branch_reg" arch_version="FEAT_PAuth" iformfile="blra.xml" label="key B, zero modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="BLRA">BLRAA, BLRAAZ, BLRAB, BLRABZ</td>
|
|
<td class="enctags">Key B, zero modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RET_64R_branch_reg" iformfile="ret.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="RET">RET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RETAA_64E_branch_reg" arch_version="FEAT_PAuth" iformfile="reta.xml" label="RETAA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="RETA">RETAA, RETAB</td>
|
|
<td class="enctags">RETAA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_43_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RETAB_64E_branch_reg" arch_version="FEAT_PAuth" iformfile="reta.xml" label="RETAB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="RETA">RETAA, RETAB</td>
|
|
<td class="enctags">RETAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_44_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_47_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_52_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_50_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_51_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ERET_64E_branch_reg" iformfile="eret.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="ERET">ERET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_53_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_57_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_56_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_55_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ERETAA_64E_branch_reg" arch_version="FEAT_PAuth" iformfile="ereta.xml" label="ERETAA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="ERETA">ERETAA, ERETAB</td>
|
|
<td class="enctags">ERETAA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_61_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_60_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_59_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ERETAB_64E_branch_reg" arch_version="FEAT_PAuth" iformfile="ereta.xml" label="ERETAB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="ERETA">ERETAA, ERETAB</td>
|
|
<td class="enctags">ERETAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_62_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_63_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_64_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_65_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_70_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">!= 000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_69_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_67_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_68_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">!= 00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DRPS_64E_branch_reg" iformfile="drps.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="DRPS">DRPS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_71_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">011x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_72_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">00000x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BRAA_64P_branch_reg" arch_version="FEAT_PAuth" iformfile="bra.xml" label="key A, register modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="BRA">BRAA, BRAAZ, BRAB, BRABZ</td>
|
|
<td class="enctags">Key A, register modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BRAB_64P_branch_reg" arch_version="FEAT_PAuth" iformfile="bra.xml" label="key B, register modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="BRA">BRAA, BRAAZ, BRAB, BRABZ</td>
|
|
<td class="enctags">Key B, register modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_75_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_76_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_77_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_78_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_79_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">00000x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BLRAA_64P_branch_reg" arch_version="FEAT_PAuth" iformfile="blra.xml" label="key A, register modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="BLRA">BLRAA, BLRAAZ, BLRAB, BLRABZ</td>
|
|
<td class="enctags">Key A, register modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BLRAB_64P_branch_reg" arch_version="FEAT_PAuth" iformfile="blra.xml" label="key B, register modifier" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="BLRA">BLRAA, BLRAAZ, BLRAB, BLRABZ</td>
|
|
<td class="enctags">Key B, register modifier</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_82_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_83_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_84_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_85_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_86_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">101x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_87_branch_reg" undef="1" oneofthismnem="61" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="ldst">Loads and Stores</funcgroupheader>
|
|
<iclass_sect id="memop_128" title="128-bit atomic memory operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="A" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="memop_128" cols="7">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="5*" />
|
|
<col colno="6" printwidth="44*" />
|
|
<col colno="7" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">A</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">o3</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_memop_128" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_memop_128" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">0x0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRP_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldclrp.xml" label="LDCLRP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRP">LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL</td>
|
|
<td class="enctags">LDCLRP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETP_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldsetp.xml" label="LDSETP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETP">LDSETP, LDSETPA, LDSETPAL, LDSETPL</td>
|
|
<td class="enctags">LDSETP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPP_128_memop_128" arch_version="FEAT_LSE128" iformfile="swpp.xml" label="SWPP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPP">SWPP, SWPPA, SWPPAL, SWPPL</td>
|
|
<td class="enctags">SWPP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwclrp.xml" label="RCWCLRP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLRP">RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPAL</td>
|
|
<td class="enctags">RCWCLRP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwswpp.xml" label="RCWSWPP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWPP">RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPAL</td>
|
|
<td class="enctags">RCWSWPP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsetp.xml" label="RCWSETP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSETP">RCWSETP, RCWSETPA, RCWSETPL, RCWSETPAL</td>
|
|
<td class="enctags">RCWSETP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRPL_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldclrp.xml" label="LDCLRPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRP">LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL</td>
|
|
<td class="enctags">LDCLRPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETPL_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldsetp.xml" label="LDSETPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETP">LDSETP, LDSETPA, LDSETPAL, LDSETPL</td>
|
|
<td class="enctags">LDSETPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPPL_128_memop_128" arch_version="FEAT_LSE128" iformfile="swpp.xml" label="SWPPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPP">SWPP, SWPPA, SWPPAL, SWPPL</td>
|
|
<td class="enctags">SWPPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwclrp.xml" label="RCWCLRPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLRP">RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPAL</td>
|
|
<td class="enctags">RCWCLRPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwswpp.xml" label="RCWSWPPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWPP">RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPAL</td>
|
|
<td class="enctags">RCWSWPPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsetp.xml" label="RCWSETPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSETP">RCWSETP, RCWSETPA, RCWSETPL, RCWSETPAL</td>
|
|
<td class="enctags">RCWSETPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRPA_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldclrp.xml" label="LDCLRPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRP">LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL</td>
|
|
<td class="enctags">LDCLRPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETPA_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldsetp.xml" label="LDSETPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETP">LDSETP, LDSETPA, LDSETPAL, LDSETPL</td>
|
|
<td class="enctags">LDSETPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPPA_128_memop_128" arch_version="FEAT_LSE128" iformfile="swpp.xml" label="SWPPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPP">SWPP, SWPPA, SWPPAL, SWPPL</td>
|
|
<td class="enctags">SWPPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwclrp.xml" label="RCWCLRPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLRP">RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPAL</td>
|
|
<td class="enctags">RCWCLRPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwswpp.xml" label="RCWSWPPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWPP">RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPAL</td>
|
|
<td class="enctags">RCWSWPPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsetp.xml" label="RCWSETPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSETP">RCWSETP, RCWSETPA, RCWSETPL, RCWSETPAL</td>
|
|
<td class="enctags">RCWSETPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRPAL_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldclrp.xml" label="LDCLRPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRP">LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL</td>
|
|
<td class="enctags">LDCLRPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETPAL_128_memop_128" arch_version="FEAT_LSE128" iformfile="ldsetp.xml" label="LDSETPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETP">LDSETP, LDSETPA, LDSETPAL, LDSETPL</td>
|
|
<td class="enctags">LDSETPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPPAL_128_memop_128" arch_version="FEAT_LSE128" iformfile="swpp.xml" label="SWPPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPP">SWPP, SWPPA, SWPPAL, SWPPL</td>
|
|
<td class="enctags">SWPPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwclrp.xml" label="RCWCLRPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLRP">RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPAL</td>
|
|
<td class="enctags">RCWCLRPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwswpp.xml" label="RCWSWPPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWPP">RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPAL</td>
|
|
<td class="enctags">RCWSWPPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsetp.xml" label="RCWSETPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSETP">RCWSETP, RCWSETPA, RCWSETPL, RCWSETPAL</td>
|
|
<td class="enctags">RCWSETPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_memop_128" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_memop_128" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_50_memop_128" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsclrp.xml" label="RCWSCLRP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLRP">RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPAL</td>
|
|
<td class="enctags">RCWSCLRP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsswpp.xml" label="RCWSSWPP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWPP">RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPAL</td>
|
|
<td class="enctags">RCWSSWPP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETP_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwssetp.xml" label="RCWSSETP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSETP">RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPAL</td>
|
|
<td class="enctags">RCWSSETP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsclrp.xml" label="RCWSCLRPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLRP">RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPAL</td>
|
|
<td class="enctags">RCWSCLRPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsswpp.xml" label="RCWSSWPPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWPP">RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPAL</td>
|
|
<td class="enctags">RCWSSWPPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETPL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwssetp.xml" label="RCWSSETPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSETP">RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPAL</td>
|
|
<td class="enctags">RCWSSETPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsclrp.xml" label="RCWSCLRPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLRP">RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPAL</td>
|
|
<td class="enctags">RCWSCLRPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsswpp.xml" label="RCWSSWPPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWPP">RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPAL</td>
|
|
<td class="enctags">RCWSSWPPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETPA_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwssetp.xml" label="RCWSSETPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSETP">RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPAL</td>
|
|
<td class="enctags">RCWSSETPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsclrp.xml" label="RCWSCLRPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLRP">RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPAL</td>
|
|
<td class="enctags">RCWSCLRPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwsswpp.xml" label="RCWSSWPPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWPP">RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPAL</td>
|
|
<td class="enctags">RCWSSWPPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETPAL_128_memop_128" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwssetp.xml" label="RCWSSETPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSETP">RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPAL</td>
|
|
<td class="enctags">RCWSSETPAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdlse" title="Advanced SIMD load/store multiple structures">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/vector/multiple/no-wb">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdlse" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="28*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ST4_asisdlse_R4" iformfile="st4_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ST4_advsimd_mult">ST4 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlse_R4_4v" iformfile="st1_advsimd_mult.xml" label="four registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlse_R3" iformfile="st3_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ST3_advsimd_mult">ST3 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlse_R3_3v" iformfile="st1_advsimd_mult.xml" label="three registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Three registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlse_R1_1v" iformfile="st1_advsimd_mult.xml" label="one register" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">No offset, One register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlse_R2" iformfile="st2_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ST2_advsimd_mult">ST2 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlse_R2_2v" iformfile="st1_advsimd_mult.xml" label="two registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlse_R4" iformfile="ld4_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="LD4_advsimd_mult">LD4 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlse_R4_4v" iformfile="ld1_advsimd_mult.xml" label="four registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlse_R3" iformfile="ld3_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="LD3_advsimd_mult">LD3 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlse_R3_3v" iformfile="ld1_advsimd_mult.xml" label="three registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Three registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlse_R1_1v" iformfile="ld1_advsimd_mult.xml" label="one register" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">No offset, One register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlse_R2" iformfile="ld2_advsimd_mult.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="LD2_advsimd_mult">LD2 (multiple structures)</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlse_R2_2v" iformfile="ld1_advsimd_mult.xml" label="two registers" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">No offset, Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_asisdlse" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdlsep" title="Advanced SIMD load/store multiple structures (post-indexed)">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/vector/multiple/post-inc">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdlsep" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="27*" />
|
|
<col colno="5" printwidth="47*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">Rm</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsep_R4_r" iformfile="st4_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ST4_advsimd_mult">ST4 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_R4_r4" iformfile="st1_advsimd_mult.xml" label="four registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Four registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsep_R3_r" iformfile="st3_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ST3_advsimd_mult">ST3 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_R3_r3" iformfile="st1_advsimd_mult.xml" label="three registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Three registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_R1_r1" iformfile="st1_advsimd_mult.xml" label="one register, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, One register, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsep_R2_r" iformfile="st2_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ST2_advsimd_mult">ST2 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_R2_r2" iformfile="st1_advsimd_mult.xml" label="two registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Two registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsep_I4_i" iformfile="st4_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ST4_advsimd_mult">ST4 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_I4_i4" iformfile="st1_advsimd_mult.xml" label="four registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Four registers, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsep_I3_i" iformfile="st3_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ST3_advsimd_mult">ST3 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_I3_i3" iformfile="st1_advsimd_mult.xml" label="three registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Three registers, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_I1_i1" iformfile="st1_advsimd_mult.xml" label="one register, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, One register, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsep_I2_i" iformfile="st2_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ST2_advsimd_mult">ST2 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsep_I2_i2" iformfile="st1_advsimd_mult.xml" label="two registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ST1_advsimd_mult">ST1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Two registers, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_50_asisdlsep" undef="1" oneofthismnem="12" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsep_R4_r" iformfile="ld4_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="LD4_advsimd_mult">LD4 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_R4_r4" iformfile="ld1_advsimd_mult.xml" label="four registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Four registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsep_R3_r" iformfile="ld3_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="LD3_advsimd_mult">LD3 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_R3_r3" iformfile="ld1_advsimd_mult.xml" label="three registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Three registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_R1_r1" iformfile="ld1_advsimd_mult.xml" label="one register, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, One register, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsep_R2_r" iformfile="ld2_advsimd_mult.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="LD2_advsimd_mult">LD2 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_R2_r2" iformfile="ld1_advsimd_mult.xml" label="two registers, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Two registers, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsep_I4_i" iformfile="ld4_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="LD4_advsimd_mult">LD4 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_I4_i4" iformfile="ld1_advsimd_mult.xml" label="four registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Four registers, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsep_I3_i" iformfile="ld3_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="LD3_advsimd_mult">LD3 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_I3_i3" iformfile="ld1_advsimd_mult.xml" label="three registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Three registers, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_I1_i1" iformfile="ld1_advsimd_mult.xml" label="one register, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, One register, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsep_I2_i" iformfile="ld2_advsimd_mult.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="LD2_advsimd_mult">LD2 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsep_I2_i2" iformfile="ld1_advsimd_mult.xml" label="two registers, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="LD1_advsimd_mult">LD1 (multiple structures)</td>
|
|
<td class="enctags">Post-index, Two registers, immediate offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdlso" title="Advanced SIMD load/store single structure">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/vector/single/no-wb">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdlso" cols="8">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="3*" />
|
|
<col colno="6" printwidth="6*" />
|
|
<col colno="7" printwidth="24*" />
|
|
<col colno="8" printwidth="19*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">opcode</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_82_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">x00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_88_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">x00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_87_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">x00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_86_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">x01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_85_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">x1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_89_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlso_B1_1b" iformfile="st1_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlso_B3_3b" iformfile="st3_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlso_H1_1h" iformfile="st1_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlso_H3_3h" iformfile="st3_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlso_S1_1s" iformfile="st1_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlso_D1_1d" iformfile="st1_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlso_S3_3s" iformfile="st3_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlso_D3_3d" iformfile="st3_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STL1_asisdlso_D1" arch_version="FEAT_LRCPC3" iformfile="stl1_advsimd_sngl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="STL1_advsimd_sngl">STL1 (SIMD&FP)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlso_B2_2b" iformfile="st2_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlso_B4_4b" iformfile="st4_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlso_H2_2h" iformfile="st2_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlso_H4_4h" iformfile="st4_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlso_S2_2s" iformfile="st2_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlso_D2_2d" iformfile="st2_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlso_S4_4s" iformfile="st4_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlso_D4_4d" iformfile="st4_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlso_B1_1b" iformfile="ld1_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlso_B3_3b" iformfile="ld3_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlso_H1_1h" iformfile="ld1_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlso_H3_3h" iformfile="ld3_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_64_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlso_S1_1s" iformfile="ld1_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlso_D1_1d" iformfile="ld1_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlso_S3_3s" iformfile="ld3_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_66_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlso_D3_3d" iformfile="ld3_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_68_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_69_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1R_asisdlso_R1" iformfile="ld1r_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1R_advsimd">LD1R</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_51_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3R_asisdlso_R3" iformfile="ld3r_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3R_advsimd">LD3R</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_71_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAP1_asisdlso_D1" arch_version="FEAT_LRCPC3" iformfile="ldap1_advsimd_sngl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAP1_advsimd_sngl">LDAP1 (SIMD&FP)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlso_B2_2b" iformfile="ld2_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlso_B4_4b" iformfile="ld4_advsimd_sngl.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">No offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlso_H2_2h" iformfile="ld2_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_54_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlso_H4_4h" iformfile="ld4_advsimd_sngl.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">No offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_74_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlso_S2_2s" iformfile="ld2_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_56_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlso_D2_2d" iformfile="ld2_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_58_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_59_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlso_S4_4s" iformfile="ld4_advsimd_sngl.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_76_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlso_D4_4d" iformfile="ld4_advsimd_sngl.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_78_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_79_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2R_asisdlso_R2" iformfile="ld2r_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2R_advsimd">LD2R</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_61_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4R_asisdlso_R4" iformfile="ld4r_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4R_advsimd">LD4R</td>
|
|
<td class="enctags">No offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_81_asisdlso" undef="1" oneofthismnem="41" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdlsop" title="Advanced SIMD load/store single structure (post-indexed)">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/vector/single/post-inc">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdlsop" cols="8">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="3*" />
|
|
<col colno="6" printwidth="6*" />
|
|
<col colno="7" printwidth="24*" />
|
|
<col colno="8" printwidth="38*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">Rm</th>
|
|
<th class="bitfields">opcode</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_BX1_r1b" iformfile="st1_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_BX3_r3b" iformfile="st3_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_HX1_r1h" iformfile="st1_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_HX3_r3h" iformfile="st3_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_SX1_r1s" iformfile="st1_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_DX1_r1d" iformfile="st1_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_SX3_r3s" iformfile="st3_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_DX3_r3d" iformfile="st3_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_B1_i1b" iformfile="st1_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_B3_i3b" iformfile="st3_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_H1_i1h" iformfile="st1_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_H3_i3h" iformfile="st3_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_S1_i1s" iformfile="st1_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST1_asisdlsop_D1_i1d" iformfile="st1_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST1_advsimd_sngl">ST1 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_S3_i3s" iformfile="st3_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST3_asisdlsop_D3_i3d" iformfile="st3_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST3_advsimd_sngl">ST3 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_BX2_r2b" iformfile="st2_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_BX4_r4b" iformfile="st4_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_HX2_r2h" iformfile="st2_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_HX4_r4h" iformfile="st4_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_SX2_r2s" iformfile="st2_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_DX2_r2d" iformfile="st2_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_SX4_r4s" iformfile="st4_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_DX4_r4d" iformfile="st4_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_B2_i2b" iformfile="st2_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_B4_i4b" iformfile="st4_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_H2_i2h" iformfile="st2_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_H4_i4h" iformfile="st4_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_S2_i2s" iformfile="st2_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2_asisdlsop_D2_i2d" iformfile="st2_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST2_advsimd_sngl">ST2 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_S4_i4s" iformfile="st4_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST4_asisdlsop_D4_i4d" iformfile="st4_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST4_advsimd_sngl">ST4 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_64_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_66_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_68_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_69_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_51_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_71_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_BX1_r1b" iformfile="ld1_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_BX3_r3b" iformfile="ld3_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_HX1_r1h" iformfile="ld1_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_HX3_r3h" iformfile="ld3_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_SX1_r1s" iformfile="ld1_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_DX1_r1d" iformfile="ld1_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_SX3_r3s" iformfile="ld3_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_DX3_r3d" iformfile="ld3_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1R_asisdlsop_RX1_r" iformfile="ld1r_advsimd.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1R_advsimd">LD1R</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3R_asisdlsop_RX3_r" iformfile="ld3r_advsimd.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3R_advsimd">LD3R</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_B1_i1b" iformfile="ld1_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_B3_i3b" iformfile="ld3_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_H1_i1h" iformfile="ld1_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_H3_i3h" iformfile="ld3_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_S1_i1s" iformfile="ld1_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1_asisdlsop_D1_i1d" iformfile="ld1_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD1_advsimd_sngl">LD1 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_S3_i3s" iformfile="ld3_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3_asisdlsop_D3_i3d" iformfile="ld3_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD3_advsimd_sngl">LD3 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD1R_asisdlsop_R1_i" iformfile="ld1r_advsimd.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD1R_advsimd">LD1R</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD3R_asisdlsop_R3_i" iformfile="ld3r_advsimd.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD3R_advsimd">LD3R</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_54_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_74_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_56_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_58_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_59_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_76_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_78_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_79_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_61_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_81_asisdlsop" undef="1" oneofthismnem="35" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_BX2_r2b" iformfile="ld2_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_BX4_r4b" iformfile="ld4_advsimd_sngl.xml" label="8-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_HX2_r2h" iformfile="ld2_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_HX4_r4h" iformfile="ld4_advsimd_sngl.xml" label="16-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_SX2_r2s" iformfile="ld2_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_DX2_r2d" iformfile="ld2_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_SX4_r4s" iformfile="ld4_advsimd_sngl.xml" label="32-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_DX4_r4d" iformfile="ld4_advsimd_sngl.xml" label="64-bit, register offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2R_asisdlsop_RX2_r" iformfile="ld2r_advsimd.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2R_advsimd">LD2R</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4R_asisdlsop_RX4_r" iformfile="ld4r_advsimd.xml" label="register offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4R_advsimd">LD4R</td>
|
|
<td class="enctags">Post-index, Register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_B2_i2b" iformfile="ld2_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_B4_i4b" iformfile="ld4_advsimd_sngl.xml" label="8-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 8-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_H2_i2h" iformfile="ld2_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_H4_i4h" iformfile="ld4_advsimd_sngl.xml" label="16-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 16-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_S2_i2s" iformfile="ld2_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2_asisdlsop_D2_i2d" iformfile="ld2_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD2_advsimd_sngl">LD2 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_S4_i4s" iformfile="ld4_advsimd_sngl.xml" label="32-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 32-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4_asisdlsop_D4_i4d" iformfile="ld4_advsimd_sngl.xml" label="64-bit, immediate offset" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LD4_advsimd_sngl">LD4 (single structure)</td>
|
|
<td class="enctags">Post-index, 64-bit, immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD2R_asisdlsop_R2_i" iformfile="ld2r_advsimd.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD2R_advsimd">LD2R</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD4R_asisdlsop_R4_i" iformfile="ld4r_advsimd.xml" label="immediate offset" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="LD4R_advsimd">LD4R</td>
|
|
<td class="enctags">Post-index, Immediate offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="memop" title="Atomic memory operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="A" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="memop" cols="9">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="7*" />
|
|
<col colno="6" printwidth="4*" />
|
|
<col colno="7" printwidth="5*" />
|
|
<col colno="8" printwidth="40*" />
|
|
<col colno="9" printwidth="19*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="7">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">A</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">Rs</th>
|
|
<th class="bitfields">o3</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_206_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_193_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_203_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_204_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_198_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_205_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_207_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDB_32_memop" arch_version="FEAT_LSE" iformfile="ldaddb.xml" label="LDADDB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDB">LDADDB, LDADDAB, LDADDALB, LDADDLB</td>
|
|
<td class="enctags">LDADDB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRB_32_memop" arch_version="FEAT_LSE" iformfile="ldclrb.xml" label="LDCLRB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRB">LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB</td>
|
|
<td class="enctags">LDCLRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORB_32_memop" arch_version="FEAT_LSE" iformfile="ldeorb.xml" label="LDEORB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORB">LDEORB, LDEORAB, LDEORALB, LDEORLB</td>
|
|
<td class="enctags">LDEORB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETB_32_memop" arch_version="FEAT_LSE" iformfile="ldsetb.xml" label="LDSETB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETB">LDSETB, LDSETAB, LDSETALB, LDSETLB</td>
|
|
<td class="enctags">LDSETB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXB_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxb.xml" label="LDSMAXB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXB">LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB</td>
|
|
<td class="enctags">LDSMAXB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINB_32_memop" arch_version="FEAT_LSE" iformfile="ldsminb.xml" label="LDSMINB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINB">LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB</td>
|
|
<td class="enctags">LDSMINB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXB_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxb.xml" label="LDUMAXB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXB">LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB</td>
|
|
<td class="enctags">LDUMAXB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINB_32_memop" arch_version="FEAT_LSE" iformfile="lduminb.xml" label="LDUMINB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINB">LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB</td>
|
|
<td class="enctags">LDUMINB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPB_32_memop" arch_version="FEAT_LSE" iformfile="swpb.xml" label="SWPB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPB">SWPB, SWPAB, SWPALB, SWPLB</td>
|
|
<td class="enctags">SWPB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLR_64_memop" arch_version="FEAT_THE" iformfile="rcwclr.xml" label="RCWCLR" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLR">RCWCLR, RCWCLRA, RCWCLRL, RCWCLRAL</td>
|
|
<td class="enctags">RCWCLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWP_64_memop" arch_version="FEAT_THE" iformfile="rcwswp.xml" label="RCWSWP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWP">RCWSWP, RCWSWPA, RCWSWPL, RCWSWPAL</td>
|
|
<td class="enctags">RCWSWP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSET_64_memop" arch_version="FEAT_THE" iformfile="rcwset.xml" label="RCWSET" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSET">RCWSET, RCWSETA, RCWSETL, RCWSETAL</td>
|
|
<td class="enctags">RCWSET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_199_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDLB_32_memop" arch_version="FEAT_LSE" iformfile="ldaddb.xml" label="LDADDLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDB">LDADDB, LDADDAB, LDADDALB, LDADDLB</td>
|
|
<td class="enctags">LDADDLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRLB_32_memop" arch_version="FEAT_LSE" iformfile="ldclrb.xml" label="LDCLRLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRB">LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB</td>
|
|
<td class="enctags">LDCLRLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORLB_32_memop" arch_version="FEAT_LSE" iformfile="ldeorb.xml" label="LDEORLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORB">LDEORB, LDEORAB, LDEORALB, LDEORLB</td>
|
|
<td class="enctags">LDEORLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETLB_32_memop" arch_version="FEAT_LSE" iformfile="ldsetb.xml" label="LDSETLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETB">LDSETB, LDSETAB, LDSETALB, LDSETLB</td>
|
|
<td class="enctags">LDSETLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXLB_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxb.xml" label="LDSMAXLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXB">LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB</td>
|
|
<td class="enctags">LDSMAXLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINLB_32_memop" arch_version="FEAT_LSE" iformfile="ldsminb.xml" label="LDSMINLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINB">LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB</td>
|
|
<td class="enctags">LDSMINLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXLB_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxb.xml" label="LDUMAXLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXB">LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB</td>
|
|
<td class="enctags">LDUMAXLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINLB_32_memop" arch_version="FEAT_LSE" iformfile="lduminb.xml" label="LDUMINLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINB">LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB</td>
|
|
<td class="enctags">LDUMINLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPLB_32_memop" arch_version="FEAT_LSE" iformfile="swpb.xml" label="SWPLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPB">SWPB, SWPAB, SWPALB, SWPLB</td>
|
|
<td class="enctags">SWPLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRL_64_memop" arch_version="FEAT_THE" iformfile="rcwclr.xml" label="RCWCLRL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLR">RCWCLR, RCWCLRA, RCWCLRL, RCWCLRAL</td>
|
|
<td class="enctags">RCWCLRL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPL_64_memop" arch_version="FEAT_THE" iformfile="rcwswp.xml" label="RCWSWPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWP">RCWSWP, RCWSWPA, RCWSWPL, RCWSWPAL</td>
|
|
<td class="enctags">RCWSWPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETL_64_memop" arch_version="FEAT_THE" iformfile="rcwset.xml" label="RCWSETL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSET">RCWSET, RCWSETA, RCWSETL, RCWSETAL</td>
|
|
<td class="enctags">RCWSETL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDAB_32_memop" arch_version="FEAT_LSE" iformfile="ldaddb.xml" label="LDADDAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDB">LDADDB, LDADDAB, LDADDALB, LDADDLB</td>
|
|
<td class="enctags">LDADDAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRAB_32_memop" arch_version="FEAT_LSE" iformfile="ldclrb.xml" label="LDCLRAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRB">LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB</td>
|
|
<td class="enctags">LDCLRAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORAB_32_memop" arch_version="FEAT_LSE" iformfile="ldeorb.xml" label="LDEORAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORB">LDEORB, LDEORAB, LDEORALB, LDEORLB</td>
|
|
<td class="enctags">LDEORAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETAB_32_memop" arch_version="FEAT_LSE" iformfile="ldsetb.xml" label="LDSETAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETB">LDSETB, LDSETAB, LDSETALB, LDSETLB</td>
|
|
<td class="enctags">LDSETAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXAB_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxb.xml" label="LDSMAXAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXB">LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB</td>
|
|
<td class="enctags">LDSMAXAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINAB_32_memop" arch_version="FEAT_LSE" iformfile="ldsminb.xml" label="LDSMINAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINB">LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB</td>
|
|
<td class="enctags">LDSMINAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXAB_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxb.xml" label="LDUMAXAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXB">LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB</td>
|
|
<td class="enctags">LDUMAXAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINAB_32_memop" arch_version="FEAT_LSE" iformfile="lduminb.xml" label="LDUMINAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINB">LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB</td>
|
|
<td class="enctags">LDUMINAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPAB_32_memop" arch_version="FEAT_LSE" iformfile="swpb.xml" label="SWPAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPB">SWPB, SWPAB, SWPALB, SWPLB</td>
|
|
<td class="enctags">SWPAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRA_64_memop" arch_version="FEAT_THE" iformfile="rcwclr.xml" label="RCWCLRA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLR">RCWCLR, RCWCLRA, RCWCLRL, RCWCLRAL</td>
|
|
<td class="enctags">RCWCLRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPA_64_memop" arch_version="FEAT_THE" iformfile="rcwswp.xml" label="RCWSWPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWP">RCWSWP, RCWSWPA, RCWSWPL, RCWSWPAL</td>
|
|
<td class="enctags">RCWSWPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETA_64_memop" arch_version="FEAT_THE" iformfile="rcwset.xml" label="RCWSETA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSET">RCWSET, RCWSETA, RCWSETL, RCWSETAL</td>
|
|
<td class="enctags">RCWSETA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPRB_32L_memop" arch_version="FEAT_LRCPC" iformfile="ldaprb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDAPRB">LDAPRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDALB_32_memop" arch_version="FEAT_LSE" iformfile="ldaddb.xml" label="LDADDALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDB">LDADDB, LDADDAB, LDADDALB, LDADDLB</td>
|
|
<td class="enctags">LDADDALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRALB_32_memop" arch_version="FEAT_LSE" iformfile="ldclrb.xml" label="LDCLRALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRB">LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB</td>
|
|
<td class="enctags">LDCLRALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORALB_32_memop" arch_version="FEAT_LSE" iformfile="ldeorb.xml" label="LDEORALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORB">LDEORB, LDEORAB, LDEORALB, LDEORLB</td>
|
|
<td class="enctags">LDEORALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETALB_32_memop" arch_version="FEAT_LSE" iformfile="ldsetb.xml" label="LDSETALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETB">LDSETB, LDSETAB, LDSETALB, LDSETLB</td>
|
|
<td class="enctags">LDSETALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXALB_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxb.xml" label="LDSMAXALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXB">LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB</td>
|
|
<td class="enctags">LDSMAXALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINALB_32_memop" arch_version="FEAT_LSE" iformfile="ldsminb.xml" label="LDSMINALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINB">LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB</td>
|
|
<td class="enctags">LDSMINALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXALB_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxb.xml" label="LDUMAXALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXB">LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB</td>
|
|
<td class="enctags">LDUMAXALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINALB_32_memop" arch_version="FEAT_LSE" iformfile="lduminb.xml" label="LDUMINALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINB">LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB</td>
|
|
<td class="enctags">LDUMINALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPALB_32_memop" arch_version="FEAT_LSE" iformfile="swpb.xml" label="SWPALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPB">SWPB, SWPAB, SWPALB, SWPLB</td>
|
|
<td class="enctags">SWPALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCLRAL_64_memop" arch_version="FEAT_THE" iformfile="rcwclr.xml" label="RCWCLRAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWCLR">RCWCLR, RCWCLRA, RCWCLRL, RCWCLRAL</td>
|
|
<td class="enctags">RCWCLRAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSWPAL_64_memop" arch_version="FEAT_THE" iformfile="rcwswp.xml" label="RCWSWPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSWP">RCWSWP, RCWSWPA, RCWSWPL, RCWSWPAL</td>
|
|
<td class="enctags">RCWSWPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSETAL_64_memop" arch_version="FEAT_THE" iformfile="rcwset.xml" label="RCWSETAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSET">RCWSET, RCWSETA, RCWSETL, RCWSETAL</td>
|
|
<td class="enctags">RCWSETAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDH_32_memop" arch_version="FEAT_LSE" iformfile="ldaddh.xml" label="LDADDH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDH">LDADDH, LDADDAH, LDADDALH, LDADDLH</td>
|
|
<td class="enctags">LDADDH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRH_32_memop" arch_version="FEAT_LSE" iformfile="ldclrh.xml" label="LDCLRH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRH">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH</td>
|
|
<td class="enctags">LDCLRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORH_32_memop" arch_version="FEAT_LSE" iformfile="ldeorh.xml" label="LDEORH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORH">LDEORH, LDEORAH, LDEORALH, LDEORLH</td>
|
|
<td class="enctags">LDEORH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETH_32_memop" arch_version="FEAT_LSE" iformfile="ldseth.xml" label="LDSETH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETH">LDSETH, LDSETAH, LDSETALH, LDSETLH</td>
|
|
<td class="enctags">LDSETH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXH_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxh.xml" label="LDSMAXH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXH">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH</td>
|
|
<td class="enctags">LDSMAXH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINH_32_memop" arch_version="FEAT_LSE" iformfile="ldsminh.xml" label="LDSMINH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINH">LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH</td>
|
|
<td class="enctags">LDSMINH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXH_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxh.xml" label="LDUMAXH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXH">LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH</td>
|
|
<td class="enctags">LDUMAXH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINH_32_memop" arch_version="FEAT_LSE" iformfile="lduminh.xml" label="LDUMINH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINH">LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH</td>
|
|
<td class="enctags">LDUMINH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPH_32_memop" arch_version="FEAT_LSE" iformfile="swph.xml" label="SWPH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPH">SWPH, SWPAH, SWPALH, SWPLH</td>
|
|
<td class="enctags">SWPH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLR_64_memop" arch_version="FEAT_THE" iformfile="rcwsclr.xml" label="RCWSCLR" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLR">RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRAL</td>
|
|
<td class="enctags">RCWSCLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWP_64_memop" arch_version="FEAT_THE" iformfile="rcwsswp.xml" label="RCWSSWP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWP">RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPAL</td>
|
|
<td class="enctags">RCWSSWP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSET_64_memop" arch_version="FEAT_THE" iformfile="rcwsset.xml" label="RCWSSET" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSET">RCWSSET, RCWSSETA, RCWSSETL, RCWSSETAL</td>
|
|
<td class="enctags">RCWSSET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_200_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDLH_32_memop" arch_version="FEAT_LSE" iformfile="ldaddh.xml" label="LDADDLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDH">LDADDH, LDADDAH, LDADDALH, LDADDLH</td>
|
|
<td class="enctags">LDADDLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRLH_32_memop" arch_version="FEAT_LSE" iformfile="ldclrh.xml" label="LDCLRLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRH">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH</td>
|
|
<td class="enctags">LDCLRLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORLH_32_memop" arch_version="FEAT_LSE" iformfile="ldeorh.xml" label="LDEORLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORH">LDEORH, LDEORAH, LDEORALH, LDEORLH</td>
|
|
<td class="enctags">LDEORLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETLH_32_memop" arch_version="FEAT_LSE" iformfile="ldseth.xml" label="LDSETLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETH">LDSETH, LDSETAH, LDSETALH, LDSETLH</td>
|
|
<td class="enctags">LDSETLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXLH_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxh.xml" label="LDSMAXLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXH">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH</td>
|
|
<td class="enctags">LDSMAXLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINLH_32_memop" arch_version="FEAT_LSE" iformfile="ldsminh.xml" label="LDSMINLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINH">LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH</td>
|
|
<td class="enctags">LDSMINLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXLH_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxh.xml" label="LDUMAXLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXH">LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH</td>
|
|
<td class="enctags">LDUMAXLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINLH_32_memop" arch_version="FEAT_LSE" iformfile="lduminh.xml" label="LDUMINLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINH">LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH</td>
|
|
<td class="enctags">LDUMINLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPLH_32_memop" arch_version="FEAT_LSE" iformfile="swph.xml" label="SWPLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPH">SWPH, SWPAH, SWPALH, SWPLH</td>
|
|
<td class="enctags">SWPLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRL_64_memop" arch_version="FEAT_THE" iformfile="rcwsclr.xml" label="RCWSCLRL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLR">RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRAL</td>
|
|
<td class="enctags">RCWSCLRL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPL_64_memop" arch_version="FEAT_THE" iformfile="rcwsswp.xml" label="RCWSSWPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWP">RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPAL</td>
|
|
<td class="enctags">RCWSSWPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETL_64_memop" arch_version="FEAT_THE" iformfile="rcwsset.xml" label="RCWSSETL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSET">RCWSSET, RCWSSETA, RCWSSETL, RCWSSETAL</td>
|
|
<td class="enctags">RCWSSETL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDAH_32_memop" arch_version="FEAT_LSE" iformfile="ldaddh.xml" label="LDADDAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDH">LDADDH, LDADDAH, LDADDALH, LDADDLH</td>
|
|
<td class="enctags">LDADDAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRAH_32_memop" arch_version="FEAT_LSE" iformfile="ldclrh.xml" label="LDCLRAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRH">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH</td>
|
|
<td class="enctags">LDCLRAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORAH_32_memop" arch_version="FEAT_LSE" iformfile="ldeorh.xml" label="LDEORAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORH">LDEORH, LDEORAH, LDEORALH, LDEORLH</td>
|
|
<td class="enctags">LDEORAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETAH_32_memop" arch_version="FEAT_LSE" iformfile="ldseth.xml" label="LDSETAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETH">LDSETH, LDSETAH, LDSETALH, LDSETLH</td>
|
|
<td class="enctags">LDSETAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXAH_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxh.xml" label="LDSMAXAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXH">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH</td>
|
|
<td class="enctags">LDSMAXAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINAH_32_memop" arch_version="FEAT_LSE" iformfile="ldsminh.xml" label="LDSMINAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINH">LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH</td>
|
|
<td class="enctags">LDSMINAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXAH_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxh.xml" label="LDUMAXAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXH">LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH</td>
|
|
<td class="enctags">LDUMAXAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINAH_32_memop" arch_version="FEAT_LSE" iformfile="lduminh.xml" label="LDUMINAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINH">LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH</td>
|
|
<td class="enctags">LDUMINAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPAH_32_memop" arch_version="FEAT_LSE" iformfile="swph.xml" label="SWPAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPH">SWPH, SWPAH, SWPALH, SWPLH</td>
|
|
<td class="enctags">SWPAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRA_64_memop" arch_version="FEAT_THE" iformfile="rcwsclr.xml" label="RCWSCLRA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLR">RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRAL</td>
|
|
<td class="enctags">RCWSCLRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPA_64_memop" arch_version="FEAT_THE" iformfile="rcwsswp.xml" label="RCWSSWPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWP">RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPAL</td>
|
|
<td class="enctags">RCWSSWPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETA_64_memop" arch_version="FEAT_THE" iformfile="rcwsset.xml" label="RCWSSETA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSET">RCWSSET, RCWSSETA, RCWSSETL, RCWSSETAL</td>
|
|
<td class="enctags">RCWSSETA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPRH_32L_memop" arch_version="FEAT_LRCPC" iformfile="ldaprh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDAPRH">LDAPRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDALH_32_memop" arch_version="FEAT_LSE" iformfile="ldaddh.xml" label="LDADDALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADDH">LDADDH, LDADDAH, LDADDALH, LDADDLH</td>
|
|
<td class="enctags">LDADDALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRALH_32_memop" arch_version="FEAT_LSE" iformfile="ldclrh.xml" label="LDCLRALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLRH">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH</td>
|
|
<td class="enctags">LDCLRALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORALH_32_memop" arch_version="FEAT_LSE" iformfile="ldeorh.xml" label="LDEORALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEORH">LDEORH, LDEORAH, LDEORALH, LDEORLH</td>
|
|
<td class="enctags">LDEORALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETALH_32_memop" arch_version="FEAT_LSE" iformfile="ldseth.xml" label="LDSETALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSETH">LDSETH, LDSETAH, LDSETALH, LDSETLH</td>
|
|
<td class="enctags">LDSETALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXALH_32_memop" arch_version="FEAT_LSE" iformfile="ldsmaxh.xml" label="LDSMAXALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAXH">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH</td>
|
|
<td class="enctags">LDSMAXALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINALH_32_memop" arch_version="FEAT_LSE" iformfile="ldsminh.xml" label="LDSMINALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMINH">LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH</td>
|
|
<td class="enctags">LDSMINALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXALH_32_memop" arch_version="FEAT_LSE" iformfile="ldumaxh.xml" label="LDUMAXALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAXH">LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH</td>
|
|
<td class="enctags">LDUMAXALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINALH_32_memop" arch_version="FEAT_LSE" iformfile="lduminh.xml" label="LDUMINALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMINH">LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH</td>
|
|
<td class="enctags">LDUMINALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPALH_32_memop" arch_version="FEAT_LSE" iformfile="swph.xml" label="SWPALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWPH">SWPH, SWPAH, SWPALH, SWPLH</td>
|
|
<td class="enctags">SWPALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCLRAL_64_memop" arch_version="FEAT_THE" iformfile="rcwsclr.xml" label="RCWSCLRAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="RCWSCLR">RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRAL</td>
|
|
<td class="enctags">RCWSCLRAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSWPAL_64_memop" arch_version="FEAT_THE" iformfile="rcwsswp.xml" label="RCWSSWPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="RCWSSWP">RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPAL</td>
|
|
<td class="enctags">RCWSSWPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSSETAL_64_memop" arch_version="FEAT_THE" iformfile="rcwsset.xml" label="RCWSSETAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="RCWSSET">RCWSSET, RCWSSETA, RCWSSETL, RCWSSETAL</td>
|
|
<td class="enctags">RCWSSETAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_160_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_173_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_186_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_163_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_176_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_189_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_166_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_179_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_192_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADD_32_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="32-bit LDADD" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">32-bit LDADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLR_32_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="32-bit LDCLR" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">32-bit LDCLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEOR_32_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="32-bit LDEOR" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">32-bit LDEOR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSET_32_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="32-bit LDSET" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">32-bit LDSET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAX_32_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="32-bit LDSMAX" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">32-bit LDSMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMIN_32_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="32-bit LDSMIN" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">32-bit LDSMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAX_32_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="32-bit LDUMAX" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">32-bit LDUMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMIN_32_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="32-bit LDUMIN" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">32-bit LDUMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWP_32_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="32-bit SWP" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">32-bit SWP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_156_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_169_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_182_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_201_memop" undef="1" oneofthismnem="22" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDL_32_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="32-bit LDADDL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">32-bit LDADDL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRL_32_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="32-bit LDCLRL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">32-bit LDCLRL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORL_32_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="32-bit LDEORL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">32-bit LDEORL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETL_32_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="32-bit LDSETL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">32-bit LDSETL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXL_32_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="32-bit LDSMAXL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">32-bit LDSMAXL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINL_32_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="32-bit LDSMINL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">32-bit LDSMINL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXL_32_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="32-bit LDUMAXL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">32-bit LDUMAXL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINL_32_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="32-bit LDUMINL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">32-bit LDUMINL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPL_32_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="32-bit SWPL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">32-bit SWPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDA_32_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="32-bit LDADDA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">32-bit LDADDA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRA_32_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="32-bit LDCLRA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">32-bit LDCLRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORA_32_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="32-bit LDEORA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">32-bit LDEORA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETA_32_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="32-bit LDSETA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">32-bit LDSETA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXA_32_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="32-bit LDSMAXA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">32-bit LDSMAXA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINA_32_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="32-bit LDSMINA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">32-bit LDSMINA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXA_32_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="32-bit LDUMAXA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">32-bit LDUMAXA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINA_32_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="32-bit LDUMINA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">32-bit LDUMINA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPA_32_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="32-bit SWPA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">32-bit SWPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPR_32L_memop" arch_version="FEAT_LRCPC" iformfile="ldapr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDAPR">LDAPR</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDAL_32_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="32-bit LDADDAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">32-bit LDADDAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRAL_32_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="32-bit LDCLRAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">32-bit LDCLRAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORAL_32_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="32-bit LDEORAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">32-bit LDEORAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETAL_32_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="32-bit LDSETAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">32-bit LDSETAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXAL_32_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="32-bit LDSMAXAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">32-bit LDSMAXAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINAL_32_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="32-bit LDSMINAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">32-bit LDSMINAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXAL_32_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="32-bit LDUMAXAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">32-bit LDUMAXAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINAL_32_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="32-bit LDUMINAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">32-bit LDUMINAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPAL_32_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="32-bit SWPAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">32-bit SWPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADD_64_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="64-bit LDADD" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">64-bit LDADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLR_64_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="64-bit LDCLR" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">64-bit LDCLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEOR_64_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="64-bit LDEOR" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">64-bit LDEOR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSET_64_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="64-bit LDSET" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">64-bit LDSET</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAX_64_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="64-bit LDSMAX" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">64-bit LDSMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMIN_64_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="64-bit LDSMIN" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">64-bit LDSMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAX_64_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="64-bit LDUMAX" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">64-bit LDUMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMIN_64_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="64-bit LDUMIN" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">64-bit LDUMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWP_64_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="64-bit SWP" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">64-bit SWP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST64BV0_64_memop" arch_version="FEAT_LS64_ACCDATA" iformfile="st64bv0.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="ST64BV0">ST64BV0</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST64BV_64_memop" arch_version="FEAT_LS64_V" iformfile="st64bv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="ST64BV">ST64BV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST64B_64L_memop" arch_version="FEAT_LS64" iformfile="st64b.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="ST64B">ST64B</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LD64B_64L_memop" arch_version="FEAT_LS64" iformfile="ld64b.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LD64B">LD64B</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDL_64_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="64-bit LDADDL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">64-bit LDADDL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRL_64_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="64-bit LDCLRL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">64-bit LDCLRL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORL_64_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="64-bit LDEORL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">64-bit LDEORL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETL_64_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="64-bit LDSETL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">64-bit LDSETL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXL_64_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="64-bit LDSMAXL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">64-bit LDSMAXL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINL_64_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="64-bit LDSMINL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">64-bit LDSMINL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXL_64_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="64-bit LDUMAXL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">64-bit LDUMAXL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINL_64_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="64-bit LDUMINL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">64-bit LDUMINL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPL_64_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="64-bit SWPL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">64-bit SWPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDA_64_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="64-bit LDADDA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">64-bit LDADDA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRA_64_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="64-bit LDCLRA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">64-bit LDCLRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORA_64_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="64-bit LDEORA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">64-bit LDEORA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETA_64_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="64-bit LDSETA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">64-bit LDSETA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXA_64_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="64-bit LDSMAXA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">64-bit LDSMAXA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINA_64_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="64-bit LDSMINA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">64-bit LDSMINA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXA_64_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="64-bit LDUMAXA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">64-bit LDUMAXA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINA_64_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="64-bit LDUMINA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">64-bit LDUMINA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPA_64_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="64-bit SWPA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">64-bit SWPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPR_64L_memop" arch_version="FEAT_LRCPC" iformfile="ldapr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDAPR">LDAPR</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDADDAL_64_memop" arch_version="FEAT_LSE" iformfile="ldadd.xml" label="64-bit LDADDAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="LDADD">LDADD, LDADDA, LDADDAL, LDADDL</td>
|
|
<td class="enctags">64-bit LDADDAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDCLRAL_64_memop" arch_version="FEAT_LSE" iformfile="ldclr.xml" label="64-bit LDCLRAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="LDCLR">LDCLR, LDCLRA, LDCLRAL, LDCLRL</td>
|
|
<td class="enctags">64-bit LDCLRAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDEORAL_64_memop" arch_version="FEAT_LSE" iformfile="ldeor.xml" label="64-bit LDEORAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="LDEOR">LDEOR, LDEORA, LDEORAL, LDEORL</td>
|
|
<td class="enctags">64-bit LDEORAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSETAL_64_memop" arch_version="FEAT_LSE" iformfile="ldset.xml" label="64-bit LDSETAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="LDSET">LDSET, LDSETA, LDSETAL, LDSETL</td>
|
|
<td class="enctags">64-bit LDSETAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMAXAL_64_memop" arch_version="FEAT_LSE" iformfile="ldsmax.xml" label="64-bit LDSMAXAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="LDSMAX">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL</td>
|
|
<td class="enctags">64-bit LDSMAXAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDSMINAL_64_memop" arch_version="FEAT_LSE" iformfile="ldsmin.xml" label="64-bit LDSMINAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="LDSMIN">LDSMIN, LDSMINA, LDSMINAL, LDSMINL</td>
|
|
<td class="enctags">64-bit LDSMINAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMAXAL_64_memop" arch_version="FEAT_LSE" iformfile="ldumax.xml" label="64-bit LDUMAXAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="LDUMAX">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL</td>
|
|
<td class="enctags">64-bit LDUMAXAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUMINAL_64_memop" arch_version="FEAT_LSE" iformfile="ldumin.xml" label="64-bit LDUMINAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="LDUMIN">LDUMIN, LDUMINA, LDUMINAL, LDUMINL</td>
|
|
<td class="enctags">64-bit LDUMINAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SWPAL_64_memop" arch_version="FEAT_LSE" iformfile="swp.xml" label="64-bit SWPAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SWP">SWP, SWPA, SWPAL, SWPL</td>
|
|
<td class="enctags">64-bit SWPAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="comswap" title="Compare and swap">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="comswap" cols="6">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<col colno="6" printwidth="14*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">o0</th>
|
|
<th class="bitfields">Rt2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_comswap" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASB_C32_comswap" arch_version="FEAT_LSE" iformfile="casb.xml" label="CASB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASB">CASB, CASAB, CASALB, CASLB</td>
|
|
<td class="enctags">CASB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASLB_C32_comswap" arch_version="FEAT_LSE" iformfile="casb.xml" label="CASLB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASB">CASB, CASAB, CASALB, CASLB</td>
|
|
<td class="enctags">CASLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASAB_C32_comswap" arch_version="FEAT_LSE" iformfile="casb.xml" label="CASAB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASB">CASB, CASAB, CASALB, CASLB</td>
|
|
<td class="enctags">CASAB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASALB_C32_comswap" arch_version="FEAT_LSE" iformfile="casb.xml" label="CASALB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASB">CASB, CASAB, CASALB, CASLB</td>
|
|
<td class="enctags">CASALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASH_C32_comswap" arch_version="FEAT_LSE" iformfile="cash.xml" label="CASH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASH">CASH, CASAH, CASALH, CASLH</td>
|
|
<td class="enctags">CASH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASLH_C32_comswap" arch_version="FEAT_LSE" iformfile="cash.xml" label="CASLH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASH">CASH, CASAH, CASALH, CASLH</td>
|
|
<td class="enctags">CASLH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASAH_C32_comswap" arch_version="FEAT_LSE" iformfile="cash.xml" label="CASAH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASH">CASH, CASAH, CASALH, CASLH</td>
|
|
<td class="enctags">CASAH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASALH_C32_comswap" arch_version="FEAT_LSE" iformfile="cash.xml" label="CASALH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASH">CASH, CASAH, CASALH, CASLH</td>
|
|
<td class="enctags">CASALH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CAS_C32_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="32-bit CAS" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">32-bit CAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASL_C32_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="32-bit CASL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">32-bit CASL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASA_C32_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="32-bit CASA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">32-bit CASA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASAL_C32_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="32-bit CASAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">32-bit CASAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CAS_C64_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="64-bit CAS" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">64-bit CAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASL_C64_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="64-bit CASL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">64-bit CASL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASA_C64_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="64-bit CASA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">64-bit CASA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASAL_C64_comswap" arch_version="FEAT_LSE" iformfile="cas.xml" label="64-bit CASAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CAS">CAS, CASA, CASAL, CASL</td>
|
|
<td class="enctags">64-bit CASAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="comswappr" title="Compare and swap pair">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="comswappr" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<col colno="6" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">o0</th>
|
|
<th class="bitfields">Rt2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_comswappr" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">!= 11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASP_CP32_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="32-bit CASP" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">32-bit CASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPL_CP32_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="32-bit CASPL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">32-bit CASPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPA_CP32_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="32-bit CASPA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">32-bit CASPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPAL_CP32_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="32-bit CASPAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">32-bit CASPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASP_CP64_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="64-bit CASP" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">64-bit CASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPL_CP64_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="64-bit CASPL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">64-bit CASPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPA_CP64_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="64-bit CASPA" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">64-bit CASPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CASPAL_CP64_comswappr" arch_version="FEAT_LSE" iformfile="casp.xml" label="64-bit CASPAL" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="CASP">CASP, CASPA, CASPAL, CASPL</td>
|
|
<td class="enctags">64-bit CASPAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_gcs" title="GCS load/store">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_gcs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="GCSSTR_64_ldst_gcs" arch_version="FEAT_GCS" iformfile="gcsstr.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="GCSSTR">GCSSTR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="GCSSTTR_64_ldst_gcs" arch_version="FEAT_GCS" iformfile="gcssttr.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="GCSSTTR">GCSSTTR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_ldst_gcs" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_ldst_gcs" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldapstl_simd" title="LDAPR/STLR (SIMD&FP)">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/single/simdfp/immediate/signed/offset/ordered">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldapstl_simd" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STLUR_B_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="stlur_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_fpsimd">STLUR (SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_B_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="ldapur_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_fpsimd">LDAPUR (SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_Q_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="stlur_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STLUR_fpsimd">STLUR (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_Q_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="ldapur_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDAPUR_fpsimd">LDAPUR (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_H_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="stlur_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_fpsimd">STLUR (SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_H_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="ldapur_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_fpsimd">LDAPUR (SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_ldapstl_simd" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_ldapstl_simd" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_S_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="stlur_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_fpsimd">STLUR (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_S_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="ldapur_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_fpsimd">LDAPUR (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_D_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="stlur_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_fpsimd">STLUR (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_D_ldapstl_simd" arch_version="FEAT_LRCPC3" iformfile="ldapur_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_fpsimd">LDAPUR (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldapstl_unscaled" title="LDAPR/STLR (unscaled immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/memory/single/general/immediate/signed/offset/lda_stl">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldapstl_unscaled" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STLURB_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="stlurb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLURB">STLURB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURB_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapurb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPURB">LDAPURB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURSB_64_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapursb.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDAPURSB">LDAPURSB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURSB_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapursb.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDAPURSB">LDAPURSB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLURH_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="stlurh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLURH">STLURH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURH_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapurh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPURH">LDAPURH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURSH_64_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapursh.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDAPURSH">LDAPURSH</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURSH_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapursh.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDAPURSH">LDAPURSH</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldapstl_unscaled" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="stlur_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_gen">STLUR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_32_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapur_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_gen">LDAPUR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPURSW_64_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapursw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDAPURSW">LDAPURSW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLUR_64_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="stlur_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STLUR_gen">STLUR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPUR_64_ldapstl_unscaled" arch_version="FEAT_LRCPC2" iformfile="ldapur_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDAPUR_gen">LDAPUR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_ldapstl_unscaled" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldapstl_writeback" title="LDAPR/STLR (writeback)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldapstl_writeback" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_ldapstl_writeback" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLR_32S_ldapstl_writeback" arch_version="FEAT_LRCPC3" iformfile="stlr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLR">STLR</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPR_32L_ldapstl_writeback" arch_version="FEAT_LRCPC3" iformfile="ldapr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAPR">LDAPR</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLR_64S_ldapstl_writeback" arch_version="FEAT_LRCPC3" iformfile="stlr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLR">STLR</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAPR_64L_ldapstl_writeback" arch_version="FEAT_LRCPC3" iformfile="ldapr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAPR">LDAPR</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldiappstilp" title="LDIAPP/STILP">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opc2" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldiappstilp" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="19*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_ldiappstilp" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_ldiappstilp" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_ldiappstilp" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_ldiappstilp" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STILP_32SE_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="stilp.xml" label="32-bit pre-index" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="STILP">STILP</td>
|
|
<td class="enctags">32-bit pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STILP_32S_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="stilp.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="STILP">STILP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDIAPP_32LE_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="ldiapp.xml" label="32-bit post-index" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="LDIAPP">LDIAPP</td>
|
|
<td class="enctags">32-bit post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDIAPP_32L_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="ldiapp.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="LDIAPP">LDIAPP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STILP_64SS_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="stilp.xml" label="64-bit pre-index" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="STILP">STILP</td>
|
|
<td class="enctags">64-bit pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STILP_64S_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="stilp.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="STILP">STILP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDIAPP_64LS_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="ldiapp.xml" label="64-bit post-index" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="LDIAPP">LDIAPP</td>
|
|
<td class="enctags">64-bit post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDIAPP_64L_ldiappstilp" arch_version="FEAT_LRCPC3" iformfile="ldiapp.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="LDIAPP">LDIAPP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="loadlit" title="Load register (literal)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="19" name="imm19" usename="1">
|
|
<c colspan="19"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="loadlit" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">V</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="LDR_32_loadlit" iformfile="ldr_lit_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDR_lit_gen">LDR (literal)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_S_loadlit" iformfile="ldr_lit_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDR_lit_fpsimd">LDR (literal, SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_64_loadlit" iformfile="ldr_lit_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDR_lit_gen">LDR (literal)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_D_loadlit" iformfile="ldr_lit_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDR_lit_fpsimd">LDR (literal, SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSW_64_loadlit" iformfile="ldrsw_lit.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDRSW_lit">LDRSW (literal)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_Q_loadlit" iformfile="ldr_lit_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDR_lit_fpsimd">LDR (literal, SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PRFM_P_loadlit" iformfile="prfm_lit.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="PRFM_lit">PRFM (literal)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_loadlit" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstexclp" title="Load/store exclusive pair">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="30" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstexclp" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STXP_SP32_ldstexclp" iformfile="stxp.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXP">STXP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXP_SP32_ldstexclp" iformfile="stlxp.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXP">STLXP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXP_LP32_ldstexclp" iformfile="ldxp.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXP">LDXP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXP_LP32_ldstexclp" iformfile="ldaxp.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXP">LDAXP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STXP_SP64_ldstexclp" iformfile="stxp.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXP">STXP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXP_SP64_ldstexclp" iformfile="stlxp.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXP">STLXP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXP_LP64_ldstexclp" iformfile="ldxp.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXP">LDXP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXP_LP64_ldstexclp" iformfile="ldaxp.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXP">LDAXP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstexclr" title="Load/store exclusive register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstexclr" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STXRB_SR32_ldstexclr" iformfile="stxrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXRB">STXRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXRB_SR32_ldstexclr" iformfile="stlxrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXRB">STLXRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXRB_LR32_ldstexclr" iformfile="ldxrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXRB">LDXRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXRB_LR32_ldstexclr" iformfile="ldaxrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXRB">LDAXRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STXRH_SR32_ldstexclr" iformfile="stxrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXRH">STXRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXRH_SR32_ldstexclr" iformfile="stlxrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXRH">STLXRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXRH_LR32_ldstexclr" iformfile="ldxrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXRH">LDXRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXRH_LR32_ldstexclr" iformfile="ldaxrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXRH">LDAXRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STXR_SR32_ldstexclr" iformfile="stxr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXR">STXR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXR_SR32_ldstexclr" iformfile="stlxr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXR">STLXR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXR_LR32_ldstexclr" iformfile="ldxr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXR">LDXR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXR_LR32_ldstexclr" iformfile="ldaxr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXR">LDAXR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STXR_SR64_ldstexclr" iformfile="stxr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STXR">STXR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLXR_SR64_ldstexclr" iformfile="stlxr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLXR">STLXR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDXR_LR64_ldstexclr" iformfile="ldxr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDXR">LDXR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAXR_LR64_ldstexclr" iformfile="ldaxr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAXR">LDAXR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldsttags" title="Load/store memory tags">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldsttags" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="14*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">imm9</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STG_64Spost_ldsttags" arch_version="FEAT_MTE" iformfile="stg.xml" label="post-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="STG">STG</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STG_64Soffset_ldsttags" arch_version="FEAT_MTE" iformfile="stg.xml" label="signed offset" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STG">STG</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STG_64Spre_ldsttags" arch_version="FEAT_MTE" iformfile="stg.xml" label="pre-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="STG">STG</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZGM_64bulk_ldsttags" arch_version="FEAT_MTE2" iformfile="stzgm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="9" class="bitfield">000000000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STZGM">STZGM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDG_64Loffset_ldsttags" arch_version="FEAT_MTE" iformfile="ldg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LDG">LDG</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZG_64Spost_ldsttags" arch_version="FEAT_MTE" iformfile="stzg.xml" label="post-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="STZG">STZG</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZG_64Soffset_ldsttags" arch_version="FEAT_MTE" iformfile="stzg.xml" label="signed offset" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STZG">STZG</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZG_64Spre_ldsttags" arch_version="FEAT_MTE" iformfile="stzg.xml" label="pre-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="STZG">STZG</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2G_64Spost_ldsttags" arch_version="FEAT_MTE" iformfile="st2g.xml" label="post-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ST2G">ST2G</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2G_64Soffset_ldsttags" arch_version="FEAT_MTE" iformfile="st2g.xml" label="signed offset" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ST2G">ST2G</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ST2G_64Spre_ldsttags" arch_version="FEAT_MTE" iformfile="st2g.xml" label="pre-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ST2G">ST2G</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_ldsttags" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="9" class="bitfield">!= 000000000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STGM_64bulk_ldsttags" arch_version="FEAT_MTE2" iformfile="stgm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="9" class="bitfield">000000000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STGM">STGM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZ2G_64Spost_ldsttags" arch_version="FEAT_MTE" iformfile="stz2g.xml" label="post-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="STZ2G">STZ2G</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZ2G_64Soffset_ldsttags" arch_version="FEAT_MTE" iformfile="stz2g.xml" label="signed offset" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STZ2G">STZ2G</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STZ2G_64Spre_ldsttags" arch_version="FEAT_MTE" iformfile="stz2g.xml" label="pre-index" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="9" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="STZ2G">STZ2G</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_ldsttags" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="9" class="bitfield">!= 000000000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDGM_64bulk_ldsttags" arch_version="FEAT_MTE2" iformfile="ldgm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="9" class="bitfield">000000000</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="LDGM">LDGM</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstnapair_offs" title="Load/store no-allocate pair (offset)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" name="imm7" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstnapair_offs" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STNP_32_ldstnapair_offs" iformfile="stnp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STNP_gen">STNP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDNP_32_ldstnapair_offs" iformfile="ldnp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDNP_gen">LDNP</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STNP_S_ldstnapair_offs" iformfile="stnp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STNP_fpsimd">STNP (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDNP_S_ldstnapair_offs" iformfile="ldnp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDNP_fpsimd">LDNP (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_ldstnapair_offs" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STNP_D_ldstnapair_offs" iformfile="stnp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STNP_fpsimd">STNP (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDNP_D_ldstnapair_offs" iformfile="ldnp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDNP_fpsimd">LDNP (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STNP_64_ldstnapair_offs" iformfile="stnp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STNP_gen">STNP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDNP_64_ldstnapair_offs" iformfile="ldnp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDNP_gen">LDNP</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STNP_Q_ldstnapair_offs" iformfile="stnp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STNP_fpsimd">STNP (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDNP_Q_ldstnapair_offs" iformfile="ldnp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDNP_fpsimd">LDNP (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_ldstnapair_offs" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstord" title="Load/store ordered">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstord" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="19*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STLLRB_SL32_ldstord" arch_version="FEAT_LOR" iformfile="stllrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLLRB">STLLRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLRB_SL32_ldstord" iformfile="stlrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLRB">STLRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDLARB_LR32_ldstord" arch_version="FEAT_LOR" iformfile="ldlarb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDLARB">LDLARB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDARB_LR32_ldstord" iformfile="ldarb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDARB">LDARB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLLRH_SL32_ldstord" arch_version="FEAT_LOR" iformfile="stllrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLLRH">STLLRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLRH_SL32_ldstord" iformfile="stlrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLRH">STLRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDLARH_LR32_ldstord" arch_version="FEAT_LOR" iformfile="ldlarh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDLARH">LDLARH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDARH_LR32_ldstord" iformfile="ldarh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDARH">LDARH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLLR_SL32_ldstord" arch_version="FEAT_LOR" iformfile="stllr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLLR">STLLR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLR_SL32_ldstord" iformfile="stlr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLR">STLR</td>
|
|
<td class="enctags">No offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDLAR_LR32_ldstord" arch_version="FEAT_LOR" iformfile="ldlar.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDLAR">LDLAR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAR_LR32_ldstord" iformfile="ldar.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAR">LDAR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLLR_SL64_ldstord" arch_version="FEAT_LOR" iformfile="stllr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STLLR">STLLR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STLR_SL64_ldstord" iformfile="stlr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="STLR">STLR</td>
|
|
<td class="enctags">No offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDLAR_LR64_ldstord" arch_version="FEAT_LOR" iformfile="ldlar.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDLAR">LDLAR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDAR_LR64_ldstord" iformfile="ldar.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDAR">LDAR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_immpost" title="Load/store register (immediate post-indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_immpost" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="21*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_ldst_immpost" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRB_32_ldst_immpost" iformfile="strb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRB_imm">STRB (immediate)</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRB_32_ldst_immpost" iformfile="ldrb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRB_imm">LDRB (immediate)</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_64_ldst_immpost" iformfile="ldrsb_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_32_ldst_immpost" iformfile="ldrsb_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_B_ldst_immpost" iformfile="str_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_B_ldst_immpost" iformfile="ldr_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_Q_ldst_immpost" iformfile="str_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_Q_ldst_immpost" iformfile="ldr_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRH_32_ldst_immpost" iformfile="strh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRH_imm">STRH (immediate)</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRH_32_ldst_immpost" iformfile="ldrh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRH_imm">LDRH (immediate)</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_64_ldst_immpost" iformfile="ldrsh_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_32_ldst_immpost" iformfile="ldrsh_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_H_ldst_immpost" iformfile="str_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_H_ldst_immpost" iformfile="ldr_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldst_immpost" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_ldst_immpost" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_32_ldst_immpost" iformfile="str_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_32_ldst_immpost" iformfile="ldr_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSW_64_ldst_immpost" iformfile="ldrsw_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSW_imm">LDRSW (immediate)</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_S_ldst_immpost" iformfile="str_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_S_ldst_immpost" iformfile="ldr_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_64_ldst_immpost" iformfile="str_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_64_ldst_immpost" iformfile="ldr_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_ldst_immpost" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_D_ldst_immpost" iformfile="str_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_D_ldst_immpost" iformfile="ldr_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_immpre" title="Load/store register (immediate pre-indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_immpre" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_ldst_immpre" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRB_32_ldst_immpre" iformfile="strb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRB_imm">STRB (immediate)</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRB_32_ldst_immpre" iformfile="ldrb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRB_imm">LDRB (immediate)</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_64_ldst_immpre" iformfile="ldrsb_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_32_ldst_immpre" iformfile="ldrsb_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_B_ldst_immpre" iformfile="str_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_B_ldst_immpre" iformfile="ldr_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_Q_ldst_immpre" iformfile="str_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_Q_ldst_immpre" iformfile="ldr_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRH_32_ldst_immpre" iformfile="strh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRH_imm">STRH (immediate)</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRH_32_ldst_immpre" iformfile="ldrh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRH_imm">LDRH (immediate)</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_64_ldst_immpre" iformfile="ldrsh_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_32_ldst_immpre" iformfile="ldrsh_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_H_ldst_immpre" iformfile="str_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_H_ldst_immpre" iformfile="ldr_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldst_immpre" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_ldst_immpre" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_32_ldst_immpre" iformfile="str_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_32_ldst_immpre" iformfile="ldr_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSW_64_ldst_immpre" iformfile="ldrsw_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSW_imm">LDRSW (immediate)</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_S_ldst_immpre" iformfile="str_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_S_ldst_immpre" iformfile="ldr_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_64_ldst_immpre" iformfile="str_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_64_ldst_immpre" iformfile="ldr_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_ldst_immpre" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_D_ldst_immpre" iformfile="str_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_D_ldst_immpre" iformfile="ldr_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_pac" title="Load/store register (pac)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" name="W" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_pac" cols="6">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">W</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_ldst_pac" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRAA_64_ldst_pac" arch_version="FEAT_PAuth" iformfile="ldra.xml" label="key A, offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDRA">LDRAA, LDRAB</td>
|
|
<td class="enctags">Key A, offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRAA_64W_ldst_pac" arch_version="FEAT_PAuth" iformfile="ldra.xml" label="key A, pre-indexed" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDRA">LDRAA, LDRAB</td>
|
|
<td class="enctags">Key A, pre-indexed</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRAB_64_ldst_pac" arch_version="FEAT_PAuth" iformfile="ldra.xml" label="key B, offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="LDRA">LDRAA, LDRAB</td>
|
|
<td class="enctags">Key B, offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRAB_64W_ldst_pac" arch_version="FEAT_PAuth" iformfile="ldra.xml" label="key B, pre-indexed" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDRA">LDRAA, LDRAB</td>
|
|
<td class="enctags">Key B, pre-indexed</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_ldst_pac" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_regoff" title="Load/store register (register offset)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="option" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_regoff" cols="7">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<col colno="6" printwidth="25*" />
|
|
<col colno="7" printwidth="38*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">option</th>
|
|
<th class="bitfields">Rt</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_43_ldst_regoff" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRB_32B_ldst_regoff" iformfile="strb_reg.xml" label="extended register" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STRB_reg">STRB (register)</td>
|
|
<td class="enctags">Extended register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRB_32BL_ldst_regoff" iformfile="strb_reg.xml" label="shifted register" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STRB_reg">STRB (register)</td>
|
|
<td class="enctags">Shifted register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRB_32B_ldst_regoff" iformfile="ldrb_reg.xml" label="extended register" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRB_reg">LDRB (register)</td>
|
|
<td class="enctags">Extended register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRB_32BL_ldst_regoff" iformfile="ldrb_reg.xml" label="shifted register" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRB_reg">LDRB (register)</td>
|
|
<td class="enctags">Shifted register</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_64B_ldst_regoff" iformfile="ldrsb_reg.xml" label="64-bit with extended register offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSB_reg">LDRSB (register)</td>
|
|
<td class="enctags">64-bit with extended register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_64BL_ldst_regoff" iformfile="ldrsb_reg.xml" label="64-bit with shifted register offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSB_reg">LDRSB (register)</td>
|
|
<td class="enctags">64-bit with shifted register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_32B_ldst_regoff" iformfile="ldrsb_reg.xml" label="32-bit with extended register offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSB_reg">LDRSB (register)</td>
|
|
<td class="enctags">32-bit with extended register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_32BL_ldst_regoff" iformfile="ldrsb_reg.xml" label="32-bit with shifted register offset" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSB_reg">LDRSB (register)</td>
|
|
<td class="enctags">32-bit with shifted register offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_B_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_BL_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_B_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">!= 011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_BL_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_Q_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_Q_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRH_32_ldst_regoff" iformfile="strh_reg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STRH_reg">STRH (register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRH_32_ldst_regoff" iformfile="ldrh_reg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRH_reg">LDRH (register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_64_ldst_regoff" iformfile="ldrsh_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSH_reg">LDRSH (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_32_ldst_regoff" iformfile="ldrsh_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSH_reg">LDRSH (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_H_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_H_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_ldst_regoff" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_44_ldst_regoff" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_32_ldst_regoff" iformfile="str_reg_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_gen">STR (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_32_ldst_regoff" iformfile="ldr_reg_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_gen">LDR (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSW_64_ldst_regoff" iformfile="ldrsw_reg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDRSW_reg">LDRSW (register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_S_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_S_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_64_ldst_regoff" iformfile="str_reg_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_gen">STR (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_64_ldst_regoff" iformfile="ldr_reg_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_gen">LDR (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_ldst_regoff" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">x0x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PRFM_P_ldst_regoff" iformfile="prfm_reg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">x1x</td>
|
|
<td bitwidth="5" class="bitfield">!= 11xxx</td>
|
|
<td class="iformname" iformid="PRFM_reg">PRFM (register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RPRFM_R_ldst_regoff" arch_version="FEAT_RPRFM" iformfile="rprfm_reg.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">x1x</td>
|
|
<td bitwidth="5" class="bitfield">11xxx</td>
|
|
<td class="iformname" iformid="RPRFM_reg">RPRFM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_D_ldst_regoff" iformfile="str_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="STR_reg_fpsimd">STR (register, SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_D_ldst_regoff" iformfile="ldr_reg_fpsimd.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="LDR_reg_fpsimd">LDR (register, SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_unpriv" title="Load/store register (unprivileged)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_unpriv" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_ldst_unpriv" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STTRB_32_ldst_unpriv" iformfile="sttrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STTRB">STTRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRB_32_ldst_unpriv" iformfile="ldtrb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDTRB">LDTRB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRSB_64_ldst_unpriv" iformfile="ldtrsb.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDTRSB">LDTRSB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRSB_32_ldst_unpriv" iformfile="ldtrsb.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDTRSB">LDTRSB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STTRH_32_ldst_unpriv" iformfile="sttrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STTRH">STTRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRH_32_ldst_unpriv" iformfile="ldtrh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDTRH">LDTRH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRSH_64_ldst_unpriv" iformfile="ldtrsh.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDTRSH">LDTRSH</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRSH_32_ldst_unpriv" iformfile="ldtrsh.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDTRSH">LDTRSH</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldst_unpriv" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STTR_32_ldst_unpriv" iformfile="sttr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STTR">STTR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTR_32_ldst_unpriv" iformfile="ldtr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDTR">LDTR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTRSW_64_ldst_unpriv" iformfile="ldtrsw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDTRSW">LDTRSW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STTR_64_ldst_unpriv" iformfile="sttr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STTR">STTR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDTR_64_ldst_unpriv" iformfile="ldtr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDTR">LDTR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_ldst_unpriv" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_unscaled" title="Load/store register (unscaled immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="9" name="imm9" usename="1">
|
|
<c colspan="9"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_unscaled" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_ldst_unscaled" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STURB_32_ldst_unscaled" iformfile="sturb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STURB">STURB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURB_32_ldst_unscaled" iformfile="ldurb.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDURB">LDURB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURSB_64_ldst_unscaled" iformfile="ldursb.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDURSB">LDURSB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURSB_32_ldst_unscaled" iformfile="ldursb.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDURSB">LDURSB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_B_ldst_unscaled" iformfile="stur_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_fpsimd">STUR (SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_B_ldst_unscaled" iformfile="ldur_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_fpsimd">LDUR (SIMD&FP)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_Q_ldst_unscaled" iformfile="stur_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STUR_fpsimd">STUR (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_Q_ldst_unscaled" iformfile="ldur_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDUR_fpsimd">LDUR (SIMD&FP)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STURH_32_ldst_unscaled" iformfile="sturh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STURH">STURH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURH_32_ldst_unscaled" iformfile="ldurh.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDURH">LDURH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURSH_64_ldst_unscaled" iformfile="ldursh.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDURSH">LDURSH</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURSH_32_ldst_unscaled" iformfile="ldursh.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDURSH">LDURSH</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_H_ldst_unscaled" iformfile="stur_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_fpsimd">STUR (SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_H_ldst_unscaled" iformfile="ldur_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_fpsimd">LDUR (SIMD&FP)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldst_unscaled" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_ldst_unscaled" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_32_ldst_unscaled" iformfile="stur_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_gen">STUR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_32_ldst_unscaled" iformfile="ldur_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_gen">LDUR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDURSW_64_ldst_unscaled" iformfile="ldursw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDURSW">LDURSW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_S_ldst_unscaled" iformfile="stur_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_fpsimd">STUR (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_S_ldst_unscaled" iformfile="ldur_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_fpsimd">LDUR (SIMD&FP)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_64_ldst_unscaled" iformfile="stur_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_gen">STUR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_64_ldst_unscaled" iformfile="ldur_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_gen">LDUR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PRFUM_P_ldst_unscaled" iformfile="prfum.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="PRFUM">PRFUM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STUR_D_ldst_unscaled" iformfile="stur_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STUR_fpsimd">STUR (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDUR_D_ldst_unscaled" iformfile="ldur_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDUR_fpsimd">LDUR (SIMD&FP)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldst_pos" title="Load/store register (unsigned immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" name="imm12" usename="1">
|
|
<c colspan="12"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldst_pos" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="26*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_ldst_pos" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRB_32_ldst_pos" iformfile="strb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRB_imm">STRB (immediate)</td>
|
|
<td class="enctags">Unsigned offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRB_32_ldst_pos" iformfile="ldrb_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRB_imm">LDRB (immediate)</td>
|
|
<td class="enctags">Unsigned offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_64_ldst_pos" iformfile="ldrsb_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSB_32_ldst_pos" iformfile="ldrsb_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSB_imm">LDRSB (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_B_ldst_pos" iformfile="str_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_B_ldst_pos" iformfile="ldr_imm_fpsimd.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_Q_ldst_pos" iformfile="str_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_Q_ldst_pos" iformfile="ldr_imm_fpsimd.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STRH_32_ldst_pos" iformfile="strh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STRH_imm">STRH (immediate)</td>
|
|
<td class="enctags">Unsigned offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRH_32_ldst_pos" iformfile="ldrh_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDRH_imm">LDRH (immediate)</td>
|
|
<td class="enctags">Unsigned offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_64_ldst_pos" iformfile="ldrsh_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSH_32_ldst_pos" iformfile="ldrsh_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="LDRSH_imm">LDRSH (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_H_ldst_pos" iformfile="str_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_H_ldst_pos" iformfile="ldr_imm_fpsimd.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_ldst_pos" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_ldst_pos" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_32_ldst_pos" iformfile="str_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_32_ldst_pos" iformfile="ldr_imm_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDRSW_64_ldst_pos" iformfile="ldrsw_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="LDRSW_imm">LDRSW (immediate)</td>
|
|
<td class="enctags">Unsigned offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_S_ldst_pos" iformfile="str_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_S_ldst_pos" iformfile="ldr_imm_fpsimd.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_64_ldst_pos" iformfile="str_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_gen">STR (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_64_ldst_pos" iformfile="ldr_imm_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_gen">LDR (immediate)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PRFM_P_ldst_pos" iformfile="prfm_imm.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="PRFM_imm">PRFM (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STR_D_ldst_pos" iformfile="str_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="STR_imm_fpsimd">STR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDR_D_ldst_pos" iformfile="ldr_imm_fpsimd.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="LDR_imm_fpsimd">LDR (immediate, SIMD&FP)</td>
|
|
<td class="enctags">Unsigned offset, 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstpair_off" title="Load/store register pair (offset)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" name="imm7" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstpair_off" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STP_32_ldstpair_off" iformfile="stp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Signed offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_32_ldstpair_off" iformfile="ldp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Signed offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_S_ldstpair_off" iformfile="stp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_S_ldstpair_off" iformfile="ldp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STGP_64_ldstpair_off" arch_version="FEAT_MTE" iformfile="stgp.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STGP">STGP</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDPSW_64_ldstpair_off" iformfile="ldpsw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDPSW">LDPSW</td>
|
|
<td class="enctags">Signed offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_D_ldstpair_off" iformfile="stp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_D_ldstpair_off" iformfile="ldp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_64_ldstpair_off" iformfile="stp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Signed offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_64_ldstpair_off" iformfile="ldp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Signed offset, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_Q_ldstpair_off" iformfile="stp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_Q_ldstpair_off" iformfile="ldp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Signed offset, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_ldstpair_off" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstpair_post" title="Load/store register pair (post-indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" name="imm7" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstpair_post" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="21*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STP_32_ldstpair_post" iformfile="stp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_32_ldstpair_post" iformfile="ldp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_S_ldstpair_post" iformfile="stp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_S_ldstpair_post" iformfile="ldp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STGP_64_ldstpair_post" arch_version="FEAT_MTE" iformfile="stgp.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STGP">STGP</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDPSW_64_ldstpair_post" iformfile="ldpsw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDPSW">LDPSW</td>
|
|
<td class="enctags">Post-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_D_ldstpair_post" iformfile="stp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_D_ldstpair_post" iformfile="ldp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_64_ldstpair_post" iformfile="stp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_64_ldstpair_post" iformfile="ldp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Post-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_Q_ldstpair_post" iformfile="stp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_Q_ldstpair_post" iformfile="ldp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Post-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_ldstpair_post" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="ldstpair_pre" title="Load/store register pair (pre-indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" name="imm7" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Rt2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="ldstpair_pre" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="STP_32_ldstpair_pre" iformfile="stp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_32_ldstpair_pre" iformfile="ldp_gen.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_S_ldstpair_pre" iformfile="stp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_S_ldstpair_pre" iformfile="ldp_fpsimd.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STGP_64_ldstpair_pre" arch_version="FEAT_MTE" iformfile="stgp.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STGP">STGP</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDPSW_64_ldstpair_pre" iformfile="ldpsw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDPSW">LDPSW</td>
|
|
<td class="enctags">Pre-index</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_D_ldstpair_pre" iformfile="stp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_D_ldstpair_pre" iformfile="ldp_fpsimd.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_64_ldstpair_pre" iformfile="stp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_gen">STP</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_64_ldstpair_pre" iformfile="ldp_gen.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_gen">LDP</td>
|
|
<td class="enctags">Pre-index, 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="STP_Q_ldstpair_pre" iformfile="stp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="STP_fpsimd">STP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LDP_Q_ldstpair_pre" iformfile="ldp_fpsimd.xml" label="128-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="LDP_fpsimd">LDP (SIMD&FP)</td>
|
|
<td class="enctags">Pre-index, 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_ldstpair_pre" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="memcms" title="Memory Copy and Memory Set">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="29" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="26" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="25" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op1" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="op2" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="memcms" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="33*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">o0</th>
|
|
<th class="bitfields">op1</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="CPYFP_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfp.xml" label="CPYFP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYFP">CPYFP, CPYFM, CPYFE</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwt.xml" label="CPYFPWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYFPWT">CPYFPWT, CPYFMWT, CPYFEWT</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPRT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprt.xml" label="CPYFPRT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYFPRT">CPYFPRT, CPYFMRT, CPYFERT</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpt.xml" label="CPYFPT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYFPT">CPYFPT, CPYFMT, CPYFET</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwn.xml" label="CPYFPWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYFPWN">CPYFPWN, CPYFMWN, CPYFEWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtwn.xml" label="CPYFPWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYFPWTWN">CPYFPWTWN, CPYFMWTWN, CPYFEWTWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPRTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtwn.xml" label="CPYFPRTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYFPRTWN">CPYFPRTWN, CPYFMRTWN, CPYFERTWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptwn.xml" label="CPYFPTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYFPTWN">CPYFPTWN, CPYFMTWN, CPYFETWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprn.xml" label="CPYFPRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYFPRN">CPYFPRN, CPYFMRN, CPYFERN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtrn.xml" label="CPYFPWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYFPWTRN">CPYFPWTRN, CPYFMWTRN, CPYFEWTRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPRTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtrn.xml" label="CPYFPRTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYFPRTRN">CPYFPRTRN, CPYFMRTRN, CPYFERTRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptrn.xml" label="CPYFPTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYFPTRN">CPYFPTRN, CPYFMTRN, CPYFETRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpn.xml" label="CPYFPN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYFPN">CPYFPN, CPYFMN, CPYFEN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtn.xml" label="CPYFPWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYFPWTN">CPYFPWTN, CPYFMWTN, CPYFEWTN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPRTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtn.xml" label="CPYFPRTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYFPRTN">CPYFPRTN, CPYFMRTN, CPYFERTN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFPTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptn.xml" label="CPYFPTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYFPTN">CPYFPTN, CPYFMTN, CPYFETN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFM_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfp.xml" label="CPYFM" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYFP">CPYFP, CPYFM, CPYFE</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwt.xml" label="CPYFMWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYFPWT">CPYFPWT, CPYFMWT, CPYFEWT</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMRT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprt.xml" label="CPYFMRT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYFPRT">CPYFPRT, CPYFMRT, CPYFERT</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpt.xml" label="CPYFMT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYFPT">CPYFPT, CPYFMT, CPYFET</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwn.xml" label="CPYFMWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYFPWN">CPYFPWN, CPYFMWN, CPYFEWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtwn.xml" label="CPYFMWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYFPWTWN">CPYFPWTWN, CPYFMWTWN, CPYFEWTWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMRTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtwn.xml" label="CPYFMRTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYFPRTWN">CPYFPRTWN, CPYFMRTWN, CPYFERTWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptwn.xml" label="CPYFMTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYFPTWN">CPYFPTWN, CPYFMTWN, CPYFETWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprn.xml" label="CPYFMRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYFPRN">CPYFPRN, CPYFMRN, CPYFERN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtrn.xml" label="CPYFMWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYFPWTRN">CPYFPWTRN, CPYFMWTRN, CPYFEWTRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMRTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtrn.xml" label="CPYFMRTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYFPRTRN">CPYFPRTRN, CPYFMRTRN, CPYFERTRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptrn.xml" label="CPYFMTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYFPTRN">CPYFPTRN, CPYFMTRN, CPYFETRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpn.xml" label="CPYFMN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYFPN">CPYFPN, CPYFMN, CPYFEN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtn.xml" label="CPYFMWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYFPWTN">CPYFPWTN, CPYFMWTN, CPYFEWTN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMRTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtn.xml" label="CPYFMRTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYFPRTN">CPYFPRTN, CPYFMRTN, CPYFERTN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFMTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptn.xml" label="CPYFMTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYFPTN">CPYFPTN, CPYFMTN, CPYFETN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFE_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfp.xml" label="CPYFE" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYFP">CPYFP, CPYFM, CPYFE</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwt.xml" label="CPYFEWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYFPWT">CPYFPWT, CPYFMWT, CPYFEWT</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFERT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprt.xml" label="CPYFERT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYFPRT">CPYFPRT, CPYFMRT, CPYFERT</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFET_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpt.xml" label="CPYFET" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYFPT">CPYFPT, CPYFMT, CPYFET</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwn.xml" label="CPYFEWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYFPWN">CPYFPWN, CPYFMWN, CPYFEWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtwn.xml" label="CPYFEWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYFPWTWN">CPYFPWTWN, CPYFMWTWN, CPYFEWTWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFERTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtwn.xml" label="CPYFERTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYFPRTWN">CPYFPRTWN, CPYFMRTWN, CPYFERTWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFETWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptwn.xml" label="CPYFETWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYFPTWN">CPYFPTWN, CPYFMTWN, CPYFETWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFERN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprn.xml" label="CPYFERN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYFPRN">CPYFPRN, CPYFMRN, CPYFERN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtrn.xml" label="CPYFEWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYFPWTRN">CPYFPWTRN, CPYFMWTRN, CPYFEWTRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFERTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtrn.xml" label="CPYFERTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYFPRTRN">CPYFPRTRN, CPYFMRTRN, CPYFERTRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFETRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptrn.xml" label="CPYFETRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYFPTRN">CPYFPTRN, CPYFMTRN, CPYFETRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpn.xml" label="CPYFEN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYFPN">CPYFPN, CPYFMN, CPYFEN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFEWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfpwtn.xml" label="CPYFEWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYFPWTN">CPYFPWTN, CPYFMWTN, CPYFEWTN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFERTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfprtn.xml" label="CPYFERTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYFPRTN">CPYFPRTN, CPYFMRTN, CPYFERTN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYFETN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyfptn.xml" label="CPYFETN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYFPTN">CPYFPTN, CPYFMTN, CPYFETN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETP_SET_memcms" arch_version="FEAT_MOPS" iformfile="setp.xml" label="SETP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SETP">SETP, SETM, SETE</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETPT_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpt.xml" label="SETPT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="SETPT">SETPT, SETMT, SETET</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETPN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpn.xml" label="SETPN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SETPN">SETPN, SETMN, SETEN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETPTN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setptn.xml" label="SETPTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="SETPTN">SETPTN, SETMTN, SETETN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETM_SET_memcms" arch_version="FEAT_MOPS" iformfile="setp.xml" label="SETM" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="SETP">SETP, SETM, SETE</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETMT_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpt.xml" label="SETMT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="SETPT">SETPT, SETMT, SETET</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETMN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpn.xml" label="SETMN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="SETPN">SETPN, SETMN, SETEN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETMTN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setptn.xml" label="SETMTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="SETPTN">SETPTN, SETMTN, SETETN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETE_SET_memcms" arch_version="FEAT_MOPS" iformfile="setp.xml" label="SETE" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="SETP">SETP, SETM, SETE</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETET_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpt.xml" label="SETET" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="SETPT">SETPT, SETMT, SETET</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETEN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setpn.xml" label="SETEN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="SETPN">SETPN, SETMN, SETEN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETETN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setptn.xml" label="SETETN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SETPTN">SETPTN, SETMTN, SETETN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_70_memcms" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYP_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyp.xml" label="CPYP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYP">CPYP, CPYM, CPYE</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwt.xml" label="CPYPWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYPWT">CPYPWT, CPYMWT, CPYEWT</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPRT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprt.xml" label="CPYPRT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYPRT">CPYPRT, CPYMRT, CPYERT</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypt.xml" label="CPYPT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYPT">CPYPT, CPYMT, CPYET</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwn.xml" label="CPYPWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYPWN">CPYPWN, CPYMWN, CPYEWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtwn.xml" label="CPYPWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYPWTWN">CPYPWTWN, CPYMWTWN, CPYEWTWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPRTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtwn.xml" label="CPYPRTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYPRTWN">CPYPRTWN, CPYMRTWN, CPYERTWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptwn.xml" label="CPYPTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYPTWN">CPYPTWN, CPYMTWN, CPYETWN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprn.xml" label="CPYPRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYPRN">CPYPRN, CPYMRN, CPYERN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtrn.xml" label="CPYPWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYPWTRN">CPYPWTRN, CPYMWTRN, CPYEWTRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPRTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtrn.xml" label="CPYPRTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYPRTRN">CPYPRTRN, CPYMRTRN, CPYERTRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptrn.xml" label="CPYPTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYPTRN">CPYPTRN, CPYMTRN, CPYETRN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypn.xml" label="CPYPN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYPN">CPYPN, CPYMN, CPYEN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtn.xml" label="CPYPWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYPWTN">CPYPWTN, CPYMWTN, CPYEWTN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPRTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtn.xml" label="CPYPRTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYPRTN">CPYPRTN, CPYMRTN, CPYERTN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYPTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptn.xml" label="CPYPTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYPTN">CPYPTN, CPYMTN, CPYETN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYM_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyp.xml" label="CPYM" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYP">CPYP, CPYM, CPYE</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwt.xml" label="CPYMWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYPWT">CPYPWT, CPYMWT, CPYEWT</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMRT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprt.xml" label="CPYMRT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYPRT">CPYPRT, CPYMRT, CPYERT</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypt.xml" label="CPYMT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYPT">CPYPT, CPYMT, CPYET</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwn.xml" label="CPYMWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYPWN">CPYPWN, CPYMWN, CPYEWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtwn.xml" label="CPYMWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYPWTWN">CPYPWTWN, CPYMWTWN, CPYEWTWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMRTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtwn.xml" label="CPYMRTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYPRTWN">CPYPRTWN, CPYMRTWN, CPYERTWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptwn.xml" label="CPYMTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYPTWN">CPYPTWN, CPYMTWN, CPYETWN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprn.xml" label="CPYMRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYPRN">CPYPRN, CPYMRN, CPYERN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtrn.xml" label="CPYMWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYPWTRN">CPYPWTRN, CPYMWTRN, CPYEWTRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMRTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtrn.xml" label="CPYMRTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYPRTRN">CPYPRTRN, CPYMRTRN, CPYERTRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptrn.xml" label="CPYMTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYPTRN">CPYPTRN, CPYMTRN, CPYETRN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypn.xml" label="CPYMN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYPN">CPYPN, CPYMN, CPYEN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtn.xml" label="CPYMWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYPWTN">CPYPWTN, CPYMWTN, CPYEWTN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMRTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtn.xml" label="CPYMRTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYPRTN">CPYPRTN, CPYMRTN, CPYERTN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYMTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptn.xml" label="CPYMTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYPTN">CPYPTN, CPYMTN, CPYETN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYE_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyp.xml" label="CPYE" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="CPYP">CPYP, CPYM, CPYE</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEWT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwt.xml" label="CPYEWT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="CPYPWT">CPYPWT, CPYMWT, CPYEWT</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYERT_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprt.xml" label="CPYERT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="CPYPRT">CPYPRT, CPYMRT, CPYERT</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYET_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypt.xml" label="CPYET" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="CPYPT">CPYPT, CPYMT, CPYET</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwn.xml" label="CPYEWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="CPYPWN">CPYPWN, CPYMWN, CPYEWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEWTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtwn.xml" label="CPYEWTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="CPYPWTWN">CPYPWTWN, CPYMWTWN, CPYEWTWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYERTWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtwn.xml" label="CPYERTWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="CPYPRTWN">CPYPRTWN, CPYMRTWN, CPYERTWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYETWN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptwn.xml" label="CPYETWN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="CPYPTWN">CPYPTWN, CPYMTWN, CPYETWN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYERN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprn.xml" label="CPYERN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="CPYPRN">CPYPRN, CPYMRN, CPYERN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEWTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtrn.xml" label="CPYEWTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="CPYPWTRN">CPYPWTRN, CPYMWTRN, CPYEWTRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYERTRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtrn.xml" label="CPYERTRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="CPYPRTRN">CPYPRTRN, CPYMRTRN, CPYERTRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYETRN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptrn.xml" label="CPYETRN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="CPYPTRN">CPYPTRN, CPYMTRN, CPYETRN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypn.xml" label="CPYEN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="CPYPN">CPYPN, CPYMN, CPYEN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYEWTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpypwtn.xml" label="CPYEWTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="CPYPWTN">CPYPWTN, CPYMWTN, CPYEWTN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYERTN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyprtn.xml" label="CPYERTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="CPYPRTN">CPYPRTN, CPYMRTN, CPYERTN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CPYETN_CPY_memcms" arch_version="FEAT_MOPS" iformfile="cpyptn.xml" label="CPYETN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="CPYPTN">CPYPTN, CPYMTN, CPYETN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGP_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgp.xml" label="SETGP" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SETGP">SETGP, SETGM, SETGE</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGPT_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpt.xml" label="SETGPT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="SETGPT">SETGPT, SETGMT, SETGET</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGPN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpn.xml" label="SETGPN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SETGPN">SETGPN, SETGMN, SETGEN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGPTN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgptn.xml" label="SETGPTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="SETGPTN">SETGPTN, SETGMTN, SETGETN</td>
|
|
<td class="enctags">Prologue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGM_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgp.xml" label="SETGM" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="SETGP">SETGP, SETGM, SETGE</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGMT_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpt.xml" label="SETGMT" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="SETGPT">SETGPT, SETGMT, SETGET</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGMN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpn.xml" label="SETGMN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="SETGPN">SETGPN, SETGMN, SETGEN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGMTN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgptn.xml" label="SETGMTN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="SETGPTN">SETGPTN, SETGMTN, SETGETN</td>
|
|
<td class="enctags">Main</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGE_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgp.xml" label="SETGE" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="SETGP">SETGP, SETGM, SETGE</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGET_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpt.xml" label="SETGET" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="SETGPT">SETGPT, SETGMT, SETGET</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGEN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgpn.xml" label="SETGEN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="SETGPN">SETGPN, SETGMN, SETGEN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETGETN_SET_memcms" arch_version="FEAT_MOPS" iformfile="setgptn.xml" label="SETGETN" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SETGPTN">SETGPTN, SETGMTN, SETGETN</td>
|
|
<td class="enctags">Epilogue</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_131_memcms" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="rcwcomswap" title="RCW compare and swap">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="A" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="rcwcomswap" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="40*" />
|
|
<col colno="5" printwidth="11*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">A</th>
|
|
<th class="bitfields">R</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="RCWCAS_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwcas.xml" label="RCWCAS" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWCAS">RCWCAS, RCWCASA, RCWCASL, RCWCASAL</td>
|
|
<td class="enctags">RCWCAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASL_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwcas.xml" label="RCWCASL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWCAS">RCWCAS, RCWCASA, RCWCASL, RCWCASAL</td>
|
|
<td class="enctags">RCWCASL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASA_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwcas.xml" label="RCWCASA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWCAS">RCWCAS, RCWCASA, RCWCASL, RCWCASAL</td>
|
|
<td class="enctags">RCWCASA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASAL_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwcas.xml" label="RCWCASAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWCAS">RCWCAS, RCWCASA, RCWCASL, RCWCASAL</td>
|
|
<td class="enctags">RCWCASAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCAS_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwscas.xml" label="RCWSCAS" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWSCAS">RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASAL</td>
|
|
<td class="enctags">RCWSCAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASL_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwscas.xml" label="RCWSCASL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWSCAS">RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASAL</td>
|
|
<td class="enctags">RCWSCASL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASA_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwscas.xml" label="RCWSCASA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWSCAS">RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASAL</td>
|
|
<td class="enctags">RCWSCASA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASAL_C64_rcwcomswap" arch_version="FEAT_THE" iformfile="rcwscas.xml" label="RCWSCASAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWSCAS">RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASAL</td>
|
|
<td class="enctags">RCWSCASAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="rcwcomswappr" title="RCW compare and swap pair">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="A" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rs" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="rcwcomswappr" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="44*" />
|
|
<col colno="5" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">A</th>
|
|
<th class="bitfields">R</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="RCWCASP_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwcasp.xml" label="RCWCASP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWCASP">RCWCASP, RCWCASPA, RCWCASPL, RCWCASPAL</td>
|
|
<td class="enctags">RCWCASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASPL_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwcasp.xml" label="RCWCASPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWCASP">RCWCASP, RCWCASPA, RCWCASPL, RCWCASPAL</td>
|
|
<td class="enctags">RCWCASPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASPA_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwcasp.xml" label="RCWCASPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWCASP">RCWCASP, RCWCASPA, RCWCASPL, RCWCASPAL</td>
|
|
<td class="enctags">RCWCASPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWCASPAL_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwcasp.xml" label="RCWCASPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWCASP">RCWCASP, RCWCASPA, RCWCASPL, RCWCASPAL</td>
|
|
<td class="enctags">RCWCASPAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASP_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwscasp.xml" label="RCWSCASP" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWSCASP">RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPAL</td>
|
|
<td class="enctags">RCWSCASP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASPL_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwscasp.xml" label="RCWSCASPL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWSCASP">RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPAL</td>
|
|
<td class="enctags">RCWSCASPL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASPA_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwscasp.xml" label="RCWSCASPA" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RCWSCASP">RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPAL</td>
|
|
<td class="enctags">RCWSCASPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RCWSCASPAL_C64_rcwcomswappr" arch_version="FEAT_D128 && FEAT_THE" iformfile="rcwscasp.xml" label="RCWSCASPAL" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="RCWSCASP">RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPAL</td>
|
|
<td class="enctags">RCWSCASPAL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="dpimm">Data Processing -- Immediate</funcgroupheader>
|
|
<iclass_sect id="addsub_imm" title="Add/subtract (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/immediate">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" name="imm12" usename="1">
|
|
<c colspan="12"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="addsub_imm" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ADD_32_addsub_imm" iformfile="add_addsub_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADD_addsub_imm">ADD (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_32S_addsub_imm" iformfile="adds_addsub_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ADDS_addsub_imm">ADDS (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_32_addsub_imm" iformfile="sub_addsub_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SUB_addsub_imm">SUB (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_32S_addsub_imm" iformfile="subs_addsub_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SUBS_addsub_imm">SUBS (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_64_addsub_imm" iformfile="add_addsub_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADD_addsub_imm">ADD (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_64S_addsub_imm" iformfile="adds_addsub_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ADDS_addsub_imm">ADDS (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_64_addsub_imm" iformfile="sub_addsub_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SUB_addsub_imm">SUB (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_64S_addsub_imm" iformfile="subs_addsub_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SUBS_addsub_imm">SUBS (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="addsub_immtags" title="Add/subtract (immediate, with tags)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="uimm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op3" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="13" width="4" name="uimm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="addsub_immtags" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_addsub_immtags" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_addsub_immtags" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDG_64_addsub_immtags" arch_version="FEAT_MTE" iformfile="addg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADDG">ADDG</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBG_64_addsub_immtags" arch_version="FEAT_MTE" iformfile="subg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SUBG">SUBG</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="bitfield" title="Bitfield">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/bitfield">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="6" name="immr" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imms" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="bitfield" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_bitfield" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_bitfield" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBFM_32M_bitfield" iformfile="sbfm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SBFM">SBFM</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFM_32M_bitfield" iformfile="bfm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="BFM">BFM</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UBFM_32M_bitfield" iformfile="ubfm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="UBFM">UBFM</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_bitfield" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBFM_64M_bitfield" iformfile="sbfm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SBFM">SBFM</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFM_64M_bitfield" iformfile="bfm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="BFM">BFM</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UBFM_64M_bitfield" iformfile="ubfm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="UBFM">UBFM</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="extract" title="Extract">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="op21" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imms" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="extract" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="8*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op21</th>
|
|
<th class="bitfields">N</th>
|
|
<th class="bitfields">o0</th>
|
|
<th class="bitfields">imms</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EXTR_32_extract" iformfile="extr.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">0xxxxx</td>
|
|
<td class="iformname" iformid="EXTR">EXTR</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_extract" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EXTR_64_extract" iformfile="extr.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="EXTR">EXTR</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="log_imm" title="Logical (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="6" name="immr" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imms" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="log_imm" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_log_imm" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AND_32_log_imm" iformfile="and_log_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="AND_log_imm">AND (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_32_log_imm" iformfile="orr_log_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ORR_log_imm">ORR (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EOR_32_log_imm" iformfile="eor_log_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="EOR_log_imm">EOR (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ANDS_32S_log_imm" iformfile="ands_log_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ANDS_log_imm">ANDS (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AND_64_log_imm" iformfile="and_log_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="AND_log_imm">AND (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_64_log_imm" iformfile="orr_log_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="ORR_log_imm">ORR (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EOR_64_log_imm" iformfile="eor_log_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="EOR_log_imm">EOR (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ANDS_64S_log_imm" iformfile="ands_log_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="ANDS_log_imm">ANDS (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="minmax_imm" title="Min/max (immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="17" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="minmax_imm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="6*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_minmax_imm" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_minmax_imm" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_minmax_imm" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">00xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_minmax_imm" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAX_32_minmax_imm" arch_version="FEAT_CSSC" iformfile="smax_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SMAX_imm">SMAX (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAX_32U_minmax_imm" arch_version="FEAT_CSSC" iformfile="umax_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="UMAX_imm">UMAX (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMIN_32_minmax_imm" arch_version="FEAT_CSSC" iformfile="smin_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SMIN_imm">SMIN (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMIN_32U_minmax_imm" arch_version="FEAT_CSSC" iformfile="umin_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="UMIN_imm">UMIN (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAX_64_minmax_imm" arch_version="FEAT_CSSC" iformfile="smax_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SMAX_imm">SMAX (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAX_64U_minmax_imm" arch_version="FEAT_CSSC" iformfile="umax_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="UMAX_imm">UMAX (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMIN_64_minmax_imm" arch_version="FEAT_CSSC" iformfile="smin_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SMIN_imm">SMIN (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMIN_64U_minmax_imm" arch_version="FEAT_CSSC" iformfile="umin_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="UMIN_imm">UMIN (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="movewide" title="Move wide (immediate)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/ins-ext/insert/movewide">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="hw" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" width="16" name="imm16" usename="1">
|
|
<c colspan="16"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="movewide" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">hw</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_movewide" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_movewide" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVN_32_movewide" iformfile="movn.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname" iformid="MOVN">MOVN</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVZ_32_movewide" iformfile="movz.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname" iformid="MOVZ">MOVZ</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVK_32_movewide" iformfile="movk.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname" iformid="MOVK">MOVK</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVN_64_movewide" iformfile="movn.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="MOVN">MOVN</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVZ_64_movewide" iformfile="movz.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="MOVZ">MOVZ</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVK_64_movewide" iformfile="movk.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="MOVK">MOVK</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="pcreladdr" title="PC-rel. addressing">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/address/pc-rel">
|
|
<box hibit="31" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="immlo" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="19" name="immhi" usename="1">
|
|
<c colspan="19"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="pcreladdr" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ADR_only_pcreladdr" iformfile="adr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADR">ADR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADRP_only_pcreladdr" iformfile="adrp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ADRP">ADRP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="dpreg">Data Processing -- Register</funcgroupheader>
|
|
<iclass_sect id="addsub_ext" title="Add/subtract (extended register)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opt" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="option" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="addsub_ext" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="5*" />
|
|
<col colno="5" printwidth="6*" />
|
|
<col colno="6" printwidth="26*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opt</th>
|
|
<th class="bitfields">imm3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_addsub_ext" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">1x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_addsub_ext" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_addsub_ext" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_addsub_ext" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_32_addsub_ext" iformfile="add_addsub_ext.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADD_addsub_ext">ADD (extended register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_32S_addsub_ext" iformfile="adds_addsub_ext.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADDS_addsub_ext">ADDS (extended register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_32_addsub_ext" iformfile="sub_addsub_ext.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUB_addsub_ext">SUB (extended register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_32S_addsub_ext" iformfile="subs_addsub_ext.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUBS_addsub_ext">SUBS (extended register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_64_addsub_ext" iformfile="add_addsub_ext.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADD_addsub_ext">ADD (extended register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_64S_addsub_ext" iformfile="adds_addsub_ext.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADDS_addsub_ext">ADDS (extended register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_64_addsub_ext" iformfile="sub_addsub_ext.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUB_addsub_ext">SUB (extended register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_64S_addsub_ext" iformfile="subs_addsub_ext.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUBS_addsub_ext">SUBS (extended register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="addsub_shift" title="Add/subtract (shifted register)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="shift" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="addsub_shift" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="7*" />
|
|
<col colno="5" printwidth="8*" />
|
|
<col colno="6" printwidth="25*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">shift</th>
|
|
<th class="bitfields">imm6</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_addsub_shift" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_addsub_shift" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_32_addsub_shift" iformfile="add_addsub_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADD_addsub_shift">ADD (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_32_addsub_shift" iformfile="adds_addsub_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADDS_addsub_shift">ADDS (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_32_addsub_shift" iformfile="sub_addsub_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUB_addsub_shift">SUB (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_32_addsub_shift" iformfile="subs_addsub_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUBS_addsub_shift">SUBS (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_64_addsub_shift" iformfile="add_addsub_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADD_addsub_shift">ADD (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDS_64_addsub_shift" iformfile="adds_addsub_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ADDS_addsub_shift">ADDS (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_64_addsub_shift" iformfile="sub_addsub_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUB_addsub_shift">SUB (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBS_64_addsub_shift" iformfile="subs_addsub_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SUBS_addsub_shift">SUBS (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="addsub_carry" title="Add/subtract (with carry)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/carry">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="addsub_carry" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ADC_32_addsub_carry" iformfile="adc.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADC">ADC</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADCS_32_addsub_carry" iformfile="adcs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ADCS">ADCS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBC_32_addsub_carry" iformfile="sbc.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SBC">SBC</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBCS_32_addsub_carry" iformfile="sbcs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SBCS">SBCS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADC_64_addsub_carry" iformfile="adc.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ADC">ADC</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADCS_64_addsub_carry" iformfile="adcs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ADCS">ADCS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBC_64_addsub_carry" iformfile="sbc.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SBC">SBC</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SBCS_64_addsub_carry" iformfile="sbcs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SBCS">SBCS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="condcmp_imm" title="Conditional compare (immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="nzcv" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="condcmp_imm" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="4*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">o3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_condcmp_imm" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_condcmp_imm" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_condcmp_imm" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMN_32_condcmp_imm" iformfile="ccmn_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMN_imm">CCMN (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMP_32_condcmp_imm" iformfile="ccmp_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMP_imm">CCMP (immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMN_64_condcmp_imm" iformfile="ccmn_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMN_imm">CCMN (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMP_64_condcmp_imm" iformfile="ccmp_imm.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMP_imm">CCMP (immediate)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="condcmp_reg" title="Conditional compare (register)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="nzcv" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="condcmp_reg" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="4*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">o3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_condcmp_reg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_condcmp_reg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_condcmp_reg" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMN_32_condcmp_reg" iformfile="ccmn_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMN_reg">CCMN (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMP_32_condcmp_reg" iformfile="ccmp_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMP_reg">CCMP (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMN_64_condcmp_reg" iformfile="ccmn_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMN_reg">CCMN (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CCMP_64_condcmp_reg" iformfile="ccmp_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="CCMP_reg">CCMP (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="condsel" title="Conditional select">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="op2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="condsel" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="5*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_condsel" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_condsel" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSEL_32_condsel" iformfile="csel.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="CSEL">CSEL</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSINC_32_condsel" iformfile="csinc.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="CSINC">CSINC</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSINV_32_condsel" iformfile="csinv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="CSINV">CSINV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSNEG_32_condsel" iformfile="csneg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="CSNEG">CSNEG</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSEL_64_condsel" iformfile="csel.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="CSEL">CSEL</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSINC_64_condsel" iformfile="csinc.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="CSINC">CSINC</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSINV_64_condsel" iformfile="csinv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="CSINV">CSINV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CSNEG_64_condsel" iformfile="csneg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="CSNEG">CSNEG</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="dp_1src" title="Data-processing (1 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opcode2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="opcode" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="dp_1src" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="9*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="7*" />
|
|
<col colno="6" printwidth="43*" />
|
|
<col colno="7" printwidth="17*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opcode2</th>
|
|
<th class="bitfields">opcode</th>
|
|
<th class="bitfields">Rn</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xxx1x</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xx1xx</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">x1xxx</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">00101x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">0011xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RBIT_32_dp_1src" iformfile="rbit_int.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="RBIT_int">RBIT</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV16_32_dp_1src" iformfile="rev16_int.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="REV16_int">REV16</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV_32_dp_1src" iformfile="rev.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="REV">REV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLZ_32_dp_1src" iformfile="clz_int.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CLZ_int">CLZ</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLS_32_dp_1src" iformfile="cls_int.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CLS_int">CLS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CTZ_32_dp_1src" arch_version="FEAT_CSSC" iformfile="ctz.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000110</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CTZ">CTZ</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CNT_32_dp_1src" arch_version="FEAT_CSSC" iformfile="cnt.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000111</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CNT">CNT</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ABS_32_dp_1src" arch_version="FEAT_CSSC" iformfile="abs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="ABS">ABS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RBIT_64_dp_1src" iformfile="rbit_int.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="RBIT_int">RBIT</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV16_64_dp_1src" iformfile="rev16_int.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="REV16_int">REV16</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV32_64_dp_1src" iformfile="rev32_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="REV32_int">REV32</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV_64_dp_1src" iformfile="rev.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="REV">REV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLZ_64_dp_1src" iformfile="clz_int.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CLZ_int">CLZ</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLS_64_dp_1src" iformfile="cls_int.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CLS_int">CLS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CTZ_64_dp_1src" arch_version="FEAT_CSSC" iformfile="ctz.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000110</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CTZ">CTZ</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CNT_64_dp_1src" arch_version="FEAT_CSSC" iformfile="cnt.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">000111</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="CNT">CNT</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ABS_64_dp_1src" arch_version="FEAT_CSSC" iformfile="abs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="ABS">ABS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIA_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="pacia.xml" label="PACIA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="PACIA">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA</td>
|
|
<td class="enctags">Integer, PACIA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIB_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="pacib.xml" label="PACIB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="PACIB">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB</td>
|
|
<td class="enctags">Integer, PACIB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACDA_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="pacda.xml" label="PACDA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="PACDA">PACDA, PACDZA</td>
|
|
<td class="enctags">PACDA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACDB_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="pacdb.xml" label="PACDB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="PACDB">PACDB, PACDZB</td>
|
|
<td class="enctags">PACDB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIA_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="autia.xml" label="AUTIA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="AUTIA">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</td>
|
|
<td class="enctags">Integer, AUTIA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIB_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="autib.xml" label="AUTIB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="AUTIB">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</td>
|
|
<td class="enctags">Integer, AUTIB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTDA_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="autda.xml" label="AUTDA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000110</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="AUTDA">AUTDA, AUTDZA</td>
|
|
<td class="enctags">AUTDA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTDB_64P_dp_1src" arch_version="FEAT_PAuth" iformfile="autdb.xml" label="AUTDB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">000111</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname" iformid="AUTDB">AUTDB, AUTDZB</td>
|
|
<td class="enctags">AUTDB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIZA_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="pacia.xml" label="PACIZA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="PACIA">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA</td>
|
|
<td class="enctags">Integer, PACIZA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACIZB_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="pacib.xml" label="PACIZB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="PACIB">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB</td>
|
|
<td class="enctags">Integer, PACIZB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACDZA_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="pacda.xml" label="PACDZA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="PACDA">PACDA, PACDZA</td>
|
|
<td class="enctags">PACDZA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACDZB_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="pacdb.xml" label="PACDZB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="PACDB">PACDB, PACDZB</td>
|
|
<td class="enctags">PACDZB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIZA_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="autia.xml" label="AUTIZA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="AUTIA">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</td>
|
|
<td class="enctags">Integer, AUTIZA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTIZB_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="autib.xml" label="AUTIZB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001101</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="AUTIB">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</td>
|
|
<td class="enctags">Integer, AUTIZB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTDZA_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="autda.xml" label="AUTDZA" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001110</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="AUTDA">AUTDA, AUTDZA</td>
|
|
<td class="enctags">AUTDZA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AUTDZB_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="autdb.xml" label="AUTDZB" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">001111</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="AUTDB">AUTDB, AUTDZB</td>
|
|
<td class="enctags">AUTDZB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="XPACI_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="xpac.xml" label="XPACI" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">010000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="XPAC">XPACD, XPACI, XPACLRI</td>
|
|
<td class="enctags">Integer, XPACI</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="XPACD_64Z_dp_1src" arch_version="FEAT_PAuth" iformfile="xpac.xml" label="XPACD" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">010001</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="XPAC">XPACD, XPACI, XPACLRI</td>
|
|
<td class="enctags">Integer, XPACD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">01001x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">0101xx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_dp_1src" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td bitwidth="6" class="bitfield">011xxx</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="dp_2src" title="Data-processing (2 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="opcode" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="dp_2src" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="36*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_59_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">00011x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">00111x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_58_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">0111xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">00001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">0001xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">001xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UDIV_32_dp_2src" iformfile="udiv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td class="iformname" iformid="UDIV">UDIV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SDIV_32_dp_2src" iformfile="sdiv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td class="iformname" iformid="SDIV">SDIV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">00010x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LSLV_32_dp_2src" iformfile="lslv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td class="iformname" iformid="LSLV">LSLV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LSRV_32_dp_2src" iformfile="lsrv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td class="iformname" iformid="LSRV">LSRV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ASRV_32_dp_2src" iformfile="asrv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td class="iformname" iformid="ASRV">ASRV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RORV_32_dp_2src" iformfile="rorv.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td class="iformname" iformid="RORV">RORV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_47_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010x11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32B_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32B" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010000</td>
|
|
<td class="iformname" iformid="CRC32">CRC32B, CRC32H, CRC32W, CRC32X</td>
|
|
<td class="enctags">CRC32B</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32H_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32H" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010001</td>
|
|
<td class="iformname" iformid="CRC32">CRC32B, CRC32H, CRC32W, CRC32X</td>
|
|
<td class="enctags">CRC32H</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32W_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32W" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010010</td>
|
|
<td class="iformname" iformid="CRC32">CRC32B, CRC32H, CRC32W, CRC32X</td>
|
|
<td class="enctags">CRC32W</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32CB_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010100</td>
|
|
<td class="iformname" iformid="CRC32C">CRC32CB, CRC32CH, CRC32CW, CRC32CX</td>
|
|
<td class="enctags">CRC32CB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32CH_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010101</td>
|
|
<td class="iformname" iformid="CRC32C">CRC32CB, CRC32CH, CRC32CW, CRC32CX</td>
|
|
<td class="enctags">CRC32CH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32CW_32C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CW" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010110</td>
|
|
<td class="iformname" iformid="CRC32C">CRC32CB, CRC32CH, CRC32CW, CRC32CX</td>
|
|
<td class="enctags">CRC32CW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAX_32_dp_2src" arch_version="FEAT_CSSC" iformfile="smax_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011000</td>
|
|
<td class="iformname" iformid="SMAX_reg">SMAX (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAX_32_dp_2src" arch_version="FEAT_CSSC" iformfile="umax_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011001</td>
|
|
<td class="iformname" iformid="UMAX_reg">UMAX (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMIN_32_dp_2src" arch_version="FEAT_CSSC" iformfile="smin_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011010</td>
|
|
<td class="iformname" iformid="SMIN_reg">SMIN (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMIN_32_dp_2src" arch_version="FEAT_CSSC" iformfile="umin_reg.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011011</td>
|
|
<td class="iformname" iformid="UMIN_reg">UMIN (register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBP_64S_dp_2src" arch_version="FEAT_MTE" iformfile="subp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname" iformid="SUBP">SUBP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UDIV_64_dp_2src" iformfile="udiv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td class="iformname" iformid="UDIV">UDIV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SDIV_64_dp_2src" iformfile="sdiv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td class="iformname" iformid="SDIV">SDIV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="IRG_64I_dp_2src" arch_version="FEAT_MTE" iformfile="irg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td class="iformname" iformid="IRG">IRG</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="GMI_64G_dp_2src" arch_version="FEAT_MTE" iformfile="gmi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td class="iformname" iformid="GMI">GMI</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LSLV_64_dp_2src" iformfile="lslv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td class="iformname" iformid="LSLV">LSLV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="LSRV_64_dp_2src" iformfile="lsrv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td class="iformname" iformid="LSRV">LSRV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ASRV_64_dp_2src" iformfile="asrv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td class="iformname" iformid="ASRV">ASRV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RORV_64_dp_2src" iformfile="rorv.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td class="iformname" iformid="RORV">RORV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PACGA_64P_dp_2src" arch_version="FEAT_PAuth" iformfile="pacga.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td class="iformname" iformid="PACGA">PACGA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010xx0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_dp_2src" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010x0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32X_64C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32.xml" label="CRC32X" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010011</td>
|
|
<td class="iformname" iformid="CRC32">CRC32B, CRC32H, CRC32W, CRC32X</td>
|
|
<td class="enctags">CRC32X</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CRC32CX_64C_dp_2src" arch_version="FEAT_CRC32" iformfile="crc32c.xml" label="CRC32CX" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">010111</td>
|
|
<td class="iformname" iformid="CRC32C">CRC32CB, CRC32CH, CRC32CW, CRC32CX</td>
|
|
<td class="enctags">CRC32CX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAX_64_dp_2src" arch_version="FEAT_CSSC" iformfile="smax_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011000</td>
|
|
<td class="iformname" iformid="SMAX_reg">SMAX (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAX_64_dp_2src" arch_version="FEAT_CSSC" iformfile="umax_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011001</td>
|
|
<td class="iformname" iformid="UMAX_reg">UMAX (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMIN_64_dp_2src" arch_version="FEAT_CSSC" iformfile="smin_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011010</td>
|
|
<td class="iformname" iformid="SMIN_reg">SMIN (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMIN_64_dp_2src" arch_version="FEAT_CSSC" iformfile="umin_reg.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield">011011</td>
|
|
<td class="iformname" iformid="UMIN_reg">UMIN (register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBPS_64S_dp_2src" arch_version="FEAT_MTE" iformfile="subps.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname" iformid="SUBPS">SUBPS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="dp_3src" title="Data-processing (3 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="op54" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="3" name="op31" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Ra" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="dp_3src" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op54</th>
|
|
<th class="bitfields">op31</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MADD_32A_dp_3src" iformfile="madd.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MADD">MADD</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MSUB_32A_dp_3src" iformfile="msub.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="MSUB">MSUB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_dp_3src" undef="1" oneofthismnem="13" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MADD_64A_dp_3src" iformfile="madd.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MADD">MADD</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MSUB_64A_dp_3src" iformfile="msub.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="MSUB">MSUB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMADDL_64WA_dp_3src" iformfile="smaddl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SMADDL">SMADDL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMSUBL_64WA_dp_3src" iformfile="smsubl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="SMSUBL">SMSUBL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMULH_64_dp_3src" iformfile="smulh.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="SMULH">SMULH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMADDL_64WA_dp_3src" iformfile="umaddl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="UMADDL">UMADDL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMSUBL_64WA_dp_3src" iformfile="umsubl.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="UMSUBL">UMSUBL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMULH_64_dp_3src" iformfile="umulh.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="UMULH">UMULH</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="setf" title="Evaluate into flags">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="6" name="opcode2" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="14" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="mask" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="setf" cols="9">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="11*" />
|
|
<col colno="5" printwidth="4*" />
|
|
<col colno="6" printwidth="4*" />
|
|
<col colno="7" printwidth="9*" />
|
|
<col colno="8" printwidth="18*" />
|
|
<col colno="9" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="7">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opcode2</th>
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">o3</th>
|
|
<th class="bitfields">mask</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">!= 000000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETF8_only_setf" arch_version="FEAT_FlagM" iformfile="setf.xml" label="SETF8" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SETF">SETF8, SETF16</td>
|
|
<td class="enctags">SETF8</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SETF16_only_setf" arch_version="FEAT_FlagM" iformfile="setf.xml" label="SETF16" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SETF">SETF8, SETF16</td>
|
|
<td class="enctags">SETF16</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_setf" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="log_shift" title="Logical (shifted register)">
|
|
<regdiagram form="32" psname="aarch64/instrs/integer/logical/shiftedreg">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="shift" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="log_shift" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="25*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">N</th>
|
|
<th class="bitfields">imm6</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_log_shift" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AND_32_log_shift" iformfile="and_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="AND_log_shift">AND (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIC_32_log_shift" iformfile="bic_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="BIC_log_shift">BIC (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_32_log_shift" iformfile="orr_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ORR_log_shift">ORR (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORN_32_log_shift" iformfile="orn_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ORN_log_shift">ORN (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EOR_32_log_shift" iformfile="eor_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="EOR_log_shift">EOR (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EON_32_log_shift" iformfile="eon.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="EON">EON (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ANDS_32_log_shift" iformfile="ands_log_shift.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ANDS_log_shift">ANDS (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BICS_32_log_shift" iformfile="bics.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="BICS">BICS (shifted register)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AND_64_log_shift" iformfile="and_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="AND_log_shift">AND (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIC_64_log_shift" iformfile="bic_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="BIC_log_shift">BIC (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_64_log_shift" iformfile="orr_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ORR_log_shift">ORR (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORN_64_log_shift" iformfile="orn_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ORN_log_shift">ORN (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EOR_64_log_shift" iformfile="eor_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="EOR_log_shift">EOR (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EON_64_log_shift" iformfile="eon.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="EON">EON (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ANDS_64_log_shift" iformfile="ands_log_shift.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="ANDS_log_shift">ANDS (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BICS_64_log_shift" iformfile="bics.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="BICS">BICS (shifted register)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="rmif" title="Rotate right into flags">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="14" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="mask" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="rmif" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_rmif" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_rmif" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RMIF_only_rmif" arch_version="FEAT_FlagM" iformfile="rmif.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="RMIF">RMIF</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_rmif" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_rmif" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="simd-dp">Data Processing -- Scalar Floating-Point and Advanced SIMD</funcgroupheader>
|
|
<iclass_sect id="asimdall" title="Advanced SIMD across lanes">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdall" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="39*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">0000x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">001xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">0100x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1100x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_40_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">111xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SADDLV_asimdall_only" iformfile="saddlv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="SADDLV_advsimd">SADDLV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAXV_asimdall_only" iformfile="smaxv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SMAXV_advsimd">SMAXV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMINV_asimdall_only" iformfile="sminv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="SMINV_advsimd">SMINV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDV_asimdall_only" iformfile="addv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="ADDV_advsimd">ADDV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMV_asimdall_only_H" arch_version="FEAT_FP16" iformfile="fmaxnmv_advsimd.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMAXNMV_advsimd">FMAXNMV</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXV_asimdall_only_H" arch_version="FEAT_FP16" iformfile="fmaxv_advsimd.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMAXV_advsimd">FMAXV</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMV_asimdall_only_H" arch_version="FEAT_FP16" iformfile="fminnmv_advsimd.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMINNMV_advsimd">FMINNMV</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINV_asimdall_only_H" arch_version="FEAT_FP16" iformfile="fminv_advsimd.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMINV_advsimd">FMINV</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UADDLV_asimdall_only" iformfile="uaddlv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="UADDLV_advsimd">UADDLV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAXV_asimdall_only" iformfile="umaxv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="UMAXV_advsimd">UMAXV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMINV_asimdall_only" iformfile="uminv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="UMINV_advsimd">UMINV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asimdall" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMV_asimdall_only_SD" iformfile="fmaxnmv_advsimd.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMAXNMV_advsimd">FMAXNMV</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXV_asimdall_only_SD" iformfile="fmaxv_advsimd.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMAXV_advsimd">FMAXV</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMV_asimdall_only_SD" iformfile="fminnmv_advsimd.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMINNMV_advsimd">FMINNMV</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINV_asimdall_only_SD" iformfile="fminv_advsimd.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMINV_advsimd">FMINV</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdins" title="Advanced SIMD copy">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdins" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="6*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Q</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">imm5</th>
|
|
<th class="bitfields">imm4</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">x0000</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DUP_asimdins_DV_v" iformfile="dup_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="DUP_advsimd_elt">DUP (element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DUP_asimdins_DR_r" iformfile="dup_advsimd_gen.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="DUP_advsimd_gen">DUP (general)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMOV_asimdins_W_w" iformfile="smov_advsimd.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="SMOV_advsimd">SMOV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMOV_asimdins_W_w" iformfile="umov_advsimd.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="UMOV_advsimd">UMOV</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asimdins" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="INS_asimdins_IR_r" iformfile="ins_advsimd_gen.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="INS_advsimd_gen">INS (general)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMOV_asimdins_X_x" iformfile="smov_advsimd.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="SMOV_advsimd">SMOV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMOV_asimdins_X_x" iformfile="umov_advsimd.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">x1000</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="UMOV_advsimd">UMOV</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="INS_asimdins_IV_v" iformfile="ins_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname" iformid="INS_advsimd_elt">INS (element)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdext" title="Advanced SIMD extract">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdext" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdext" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EXT_asimdext_only" iformfile="ext_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="EXT_advsimd">EXT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asimdext" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdimm" title="Advanced SIMD modified immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" name="a" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="b" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="c" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cmode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" name="d" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="8" name="e" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="7" name="f" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" name="g" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdimm" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="26*" />
|
|
<col colno="6" printwidth="57*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Q</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">cmode</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0xxx</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_L_sl" iformfile="movi_advsimd.xml" label="32-bit shifted immediate" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0xx0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">32-bit shifted immediate</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_asimdimm_L_sl" iformfile="orr_advsimd_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0xx1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ORR_advsimd_imm">ORR (vector, immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">10xx</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_L_hl" iformfile="movi_advsimd.xml" label="16-bit shifted immediate" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">10x0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">16-bit shifted immediate</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_asimdimm_L_hl" iformfile="orr_advsimd_imm.xml" label="16-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">10x1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ORR_advsimd_imm">ORR (vector, immediate)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_M_sm" iformfile="movi_advsimd.xml" label="32-bit shifting ones" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">110x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">32-bit shifting ones</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">110x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_N_b" iformfile="movi_advsimd.xml" label="8-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_asimdimm_S_s" iformfile="fmov_advsimd.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FMOV_advsimd">FMOV (vector, immediate)</td>
|
|
<td class="enctags">Single-precision and double-precision, Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_asimdimm_H_h" arch_version="FEAT_FP16" iformfile="fmov_advsimd.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FMOV_advsimd">FMOV (vector, immediate)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MVNI_asimdimm_L_sl" iformfile="mvni_advsimd.xml" label="32-bit shifted immediate" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0xx0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MVNI_advsimd">MVNI</td>
|
|
<td class="enctags">32-bit shifted immediate</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIC_asimdimm_L_sl" iformfile="bic_advsimd_imm.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0xx1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="BIC_advsimd_imm">BIC (vector, immediate)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MVNI_asimdimm_L_hl" iformfile="mvni_advsimd.xml" label="16-bit shifted immediate" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">10x0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MVNI_advsimd">MVNI</td>
|
|
<td class="enctags">16-bit shifted immediate</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIC_asimdimm_L_hl" iformfile="bic_advsimd_imm.xml" label="16-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">10x1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="BIC_advsimd_imm">BIC (vector, immediate)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MVNI_asimdimm_M_sm" iformfile="mvni_advsimd.xml" label="32-bit shifting ones" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">110x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MVNI_advsimd">MVNI</td>
|
|
<td class="enctags">32-bit shifting ones</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_D_ds" iformfile="movi_advsimd.xml" label="64-bit scalar" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">64-bit scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdimm" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MOVI_asimdimm_D2_d" iformfile="movi_advsimd.xml" label="64-bit vector" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="MOVI_advsimd">MOVI</td>
|
|
<td class="enctags">64-bit vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_asimdimm_D2_d" iformfile="fmov_advsimd.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FMOV_advsimd">FMOV (vector, immediate)</td>
|
|
<td class="enctags">Single-precision and double-precision, Double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdperm" title="Advanced SIMD permute">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdperm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdperm" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UZP1_asimdperm_only" iformfile="uzp1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="UZP1_advsimd">UZP1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TRN1_asimdperm_only" iformfile="trn1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="TRN1_advsimd">TRN1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ZIP1_asimdperm_only" iformfile="zip1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="ZIP1_advsimd">ZIP1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asimdperm" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UZP2_asimdperm_only" iformfile="uzp2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="UZP2_advsimd">UZP2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TRN2_asimdperm_only" iformfile="trn2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="TRN2_advsimd">TRN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ZIP2_asimdperm_only" iformfile="zip2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="ZIP2_advsimd">ZIP2</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdone" title="Advanced SIMD scalar copy">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdone" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">imm4</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asisdone" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">xxx1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdone" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">xx1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdone" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">x1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="DUP_asisdone_only" iformfile="dup_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="DUP_advsimd_elt">DUP (element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisdone" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asisdone" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdpair" title="Advanced SIMD scalar pairwise">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdpair" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="39*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">010xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1100x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">111xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDP_asisdpair_only" iformfile="addp_advsimd_pair.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="ADDP_advsimd_pair">ADDP (scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMP_asisdpair_only_H" arch_version="FEAT_FP16" iformfile="fmaxnmp_advsimd_pair.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMAXNMP_advsimd_pair">FMAXNMP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADDP_asisdpair_only_H" arch_version="FEAT_FP16" iformfile="faddp_advsimd_pair.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FADDP_advsimd_pair">FADDP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXP_asisdpair_only_H" arch_version="FEAT_FP16" iformfile="fmaxp_advsimd_pair.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMAXP_advsimd_pair">FMAXP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMP_asisdpair_only_H" arch_version="FEAT_FP16" iformfile="fminnmp_advsimd_pair.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMINNMP_advsimd_pair">FMINNMP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINP_asisdpair_only_H" arch_version="FEAT_FP16" iformfile="fminp_advsimd_pair.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMINP_advsimd_pair">FMINP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdpair" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMP_asisdpair_only_SD" iformfile="fmaxnmp_advsimd_pair.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMAXNMP_advsimd_pair">FMAXNMP (scalar)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADDP_asisdpair_only_SD" iformfile="faddp_advsimd_pair.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FADDP_advsimd_pair">FADDP (scalar)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXP_asisdpair_only_SD" iformfile="fmaxp_advsimd_pair.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMAXP_advsimd_pair">FMAXP (scalar)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMP_asisdpair_only_SD" iformfile="fminnmp_advsimd_pair.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FMINNMP_advsimd_pair">FMINNMP (scalar)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINP_asisdpair_only_SD" iformfile="fminp_advsimd_pair.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FMINP_advsimd_pair">FMINP (scalar)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdshf" title="Advanced SIMD scalar shift by immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="immh" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="immb" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdshf" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="9*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">immh</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_44_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">101xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSHR_asisdshf_R" iformfile="sshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="SSHR_advsimd">SSHR</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSRA_asisdshf_R" iformfile="ssra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="SSRA_advsimd">SSRA</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSHR_asisdshf_R" iformfile="srshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="SRSHR_advsimd">SRSHR</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSRA_asisdshf_R" iformfile="srsra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="SRSRA_advsimd">SRSRA</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHL_asisdshf_R" iformfile="shl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SHL_advsimd">SHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHL_asisdshf_R" iformfile="sqshl_advsimd_imm.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="SQSHL_advsimd_imm">SQSHL (immediate)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_asisdshf" undef="1" oneofthismnem="17" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHRN_asisdshf_N" iformfile="sqshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="SQSHRN_advsimd">SQSHRN, SQSHRN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHRN_asisdshf_N" iformfile="sqrshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="SQRSHRN_advsimd">SQRSHRN, SQRSHRN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asisdshf_C" iformfile="scvtf_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_fix">SCVTF (vector, fixed-point)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asisdshf_C" iformfile="fcvtzs_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_fix">FCVTZS (vector, fixed-point)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USHR_asisdshf_R" iformfile="ushr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="USHR_advsimd">USHR</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USRA_asisdshf_R" iformfile="usra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="USRA_advsimd">USRA</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSHR_asisdshf_R" iformfile="urshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="URSHR_advsimd">URSHR</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSRA_asisdshf_R" iformfile="ursra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="URSRA_advsimd">URSRA</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRI_asisdshf_R" iformfile="sri_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="SRI_advsimd">SRI</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SLI_asisdshf_R" iformfile="sli_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SLI_advsimd">SLI</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHLU_asisdshf_R" iformfile="sqshlu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="SQSHLU_advsimd">SQSHLU</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHL_asisdshf_R" iformfile="uqshl_advsimd_imm.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="UQSHL_advsimd_imm">UQSHL (immediate)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHRUN_asisdshf_N" iformfile="sqshrun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="SQSHRUN_advsimd">SQSHRUN, SQSHRUN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHRUN_asisdshf_N" iformfile="sqrshrun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="SQRSHRUN_advsimd">SQRSHRUN, SQRSHRUN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHRN_asisdshf_N" iformfile="uqshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="UQSHRN_advsimd">UQSHRN, UQSHRN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQRSHRN_asisdshf_N" iformfile="uqrshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="UQRSHRN_advsimd">UQRSHRN, UQRSHRN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asisdshf_C" iformfile="ucvtf_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_fix">UCVTF (vector, fixed-point)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asisdshf_C" iformfile="fcvtzu_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">!= 0000</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_fix">FCVTZU (vector, fixed-point)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisddiff" title="Advanced SIMD scalar three different">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisddiff" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="28*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">00xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">111x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLAL_asisddiff_only" iformfile="sqdmlal_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="SQDMLAL_advsimd_vec">SQDMLAL, SQDMLAL2 (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLSL_asisddiff_only" iformfile="sqdmlsl_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SQDMLSL_advsimd_vec">SQDMLSL, SQDMLSL2 (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULL_asisddiff_only" iformfile="sqdmull_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQDMULL_advsimd_vec">SQDMULL, SQDMULL2 (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asisddiff" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdsame" title="Advanced SIMD scalar three same">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdsame" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="19*" />
|
|
<col colno="5" printwidth="46*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">0001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_30_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">011xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_58_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQADD_asisdsame_only" iformfile="sqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="SQADD_advsimd">SQADD</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSUB_asisdsame_only" iformfile="sqsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="SQSUB_advsimd">SQSUB</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGT_asisdsame_only" iformfile="cmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="CMGT_advsimd_reg">CMGT (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGE_asisdsame_only" iformfile="cmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="CMGE_advsimd_reg">CMGE (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSHL_asisdsame_only" iformfile="sshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="SSHL_advsimd">SSHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHL_asisdsame_only" iformfile="sqshl_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="SQSHL_advsimd_reg">SQSHL (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSHL_asisdsame_only" iformfile="srshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SRSHL_advsimd">SRSHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHL_asisdsame_only" iformfile="sqrshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="SQRSHL_advsimd">SQRSHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_asisdsame_only" iformfile="add_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="ADD_advsimd">ADD (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMTST_asisdsame_only" iformfile="cmtst_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="CMTST_advsimd">CMTST</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_36_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_38_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULH_asisdsame_only" iformfile="sqdmulh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="SQDMULH_advsimd_vec">SQDMULH (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_42_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_44_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_48_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_52_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asisdsame_only" iformfile="fmulx_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_vec">FMULX</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asisdsame_only" iformfile="fcmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_reg">FCMEQ (register)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_63_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_67_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPS_asisdsame_only" iformfile="frecps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRECPS_advsimd">FRECPS</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_46_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_50_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_54_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_61_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_65_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_69_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTS_asisdsame_only" iformfile="frsqrts_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRSQRTS_advsimd">FRSQRTS</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQADD_asisdsame_only" iformfile="uqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="UQADD_advsimd">UQADD</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSUB_asisdsame_only" iformfile="uqsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="UQSUB_advsimd">UQSUB</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMHI_asisdsame_only" iformfile="cmhi_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="CMHI_advsimd">CMHI (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMHS_asisdsame_only" iformfile="cmhs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="CMHS_advsimd">CMHS (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USHL_asisdsame_only" iformfile="ushl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="USHL_advsimd">USHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHL_asisdsame_only" iformfile="uqshl_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="UQSHL_advsimd_reg">UQSHL (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSHL_asisdsame_only" iformfile="urshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="URSHL_advsimd">URSHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQRSHL_asisdsame_only" iformfile="uqrshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="UQRSHL_advsimd">UQRSHL</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_asisdsame_only" iformfile="sub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="SUB_advsimd">SUB (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMEQ_asisdsame_only" iformfile="cmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="CMEQ_advsimd_reg">CMEQ (register)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_37_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_39_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMULH_asisdsame_only" iformfile="sqrdmulh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="SQRDMULH_advsimd_vec">SQRDMULH (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_43_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_45_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_53_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_57_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asisdsame_only" iformfile="fcmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_reg">FCMGE (register)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGE_asisdsame_only" iformfile="facge_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FACGE_advsimd">FACGE</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_68_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_72_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_47_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_51_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABD_asisdsame_only" iformfile="fabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FABD_advsimd">FABD</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asisdsame_only" iformfile="fcmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_reg">FCMGT (register)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGT_asisdsame_only" iformfile="facgt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FACGT_advsimd">FACGT</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_70_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_74_asisdsame" undef="1" oneofthismnem="33" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdsamefp16" title="Advanced SIMD scalar three same FP16">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="a" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdsamefp16" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">a</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmulx_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_vec">FMULX</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_reg">FCMEQ (register)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPS_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="frecps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FRECPS_advsimd">FRECPS</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTS_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="frsqrts_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FRSQRTS_advsimd">FRSQRTS</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_reg">FCMGE (register)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGE_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="facge_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FACGE_advsimd">FACGE</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABD_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="fabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="FABD_advsimd">FABD</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_reg">FCMGT (register)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGT_asisdsamefp16_only" arch_version="FEAT_FP16" iformfile="facgt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FACGT_advsimd">FACGT</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asisdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdsame2" title="Advanced SIMD scalar three same extra">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdsame2" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="19*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asisdsame2" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdsame2" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asisdsame2" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdsame2" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdsame2" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLAH_asisdsame2_only" arch_version="FEAT_RDM" iformfile="sqrdmlah_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SQRDMLAH_advsimd_vec">SQRDMLAH (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLSH_asisdsame2_only" arch_version="FEAT_RDM" iformfile="sqrdmlsh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="SQRDMLSH_advsimd_vec">SQRDMLSH (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdmisc" title="Advanced SIMD scalar two-register miscellaneous">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdmisc" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="46*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">0000x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">0010x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1000x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1100x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_62_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">011xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_63_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_44_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_57_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUQADD_asisdmisc_R" iformfile="suqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="SUQADD_advsimd">SUQADD</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQABS_asisdmisc_R" iformfile="sqabs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="SQABS_advsimd">SQABS</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGT_asisdmisc_Z" iformfile="cmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="CMGT_advsimd_zero">CMGT (zero)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMEQ_asisdmisc_Z" iformfile="cmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="CMEQ_advsimd_zero">CMEQ (zero)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMLT_asisdmisc_Z" iformfile="cmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="CMLT_advsimd">CMLT (zero)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ABS_asisdmisc_R" iformfile="abs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="ABS_advsimd">ABS</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_36_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQXTN_asisdmisc_N" iformfile="sqxtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="SQXTN_advsimd">SQXTN, SQXTN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_asisdmisc_R" iformfile="fcvtns_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNS_advsimd">FCVTNS (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_asisdmisc_R" iformfile="fcvtms_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMS_advsimd">FCVTMS (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_asisdmisc_R" iformfile="fcvtas_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAS_advsimd">FCVTAS (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asisdmisc_R" iformfile="scvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_int">SCVTF (vector, integer)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asisdmisc_FZ" iformfile="fcmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_zero">FCMGT (zero)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asisdmisc_FZ" iformfile="fcmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_zero">FCMEQ (zero)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLT_asisdmisc_FZ" iformfile="fcmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="FCMLT_advsimd">FCMLT (zero)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_asisdmisc_R" iformfile="fcvtps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPS_advsimd">FCVTPS (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asisdmisc_R" iformfile="fcvtzs_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_int">FCVTZS (vector, integer)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPE_asisdmisc_R" iformfile="frecpe_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRECPE_advsimd">FRECPE</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPX_asisdmisc_R" iformfile="frecpx_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRECPX_advsimd">FRECPX</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USQADD_asisdmisc_R" iformfile="usqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="USQADD_advsimd">USQADD</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQNEG_asisdmisc_R" iformfile="sqneg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="SQNEG_advsimd">SQNEG</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGE_asisdmisc_Z" iformfile="cmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="CMGE_advsimd_zero">CMGE (zero)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMLE_asisdmisc_Z" iformfile="cmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="CMLE_advsimd">CMLE (zero)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="NEG_asisdmisc_R" iformfile="neg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="NEG_advsimd">NEG (vector)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQXTUN_asisdmisc_N" iformfile="sqxtun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="SQXTUN_advsimd">SQXTUN, SQXTUN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQXTN_asisdmisc_N" iformfile="uqxtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="UQXTN_advsimd">UQXTN, UQXTN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTXN_asisdmisc_N" iformfile="fcvtxn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="FCVTXN_advsimd">FCVTXN, FCVTXN2</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_asisdmisc_R" iformfile="fcvtnu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNU_advsimd">FCVTNU (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_asisdmisc_R" iformfile="fcvtmu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMU_advsimd">FCVTMU (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_asisdmisc_R" iformfile="fcvtau_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAU_advsimd">FCVTAU (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asisdmisc_R" iformfile="ucvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_int">UCVTF (vector, integer)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asisdmisc_FZ" iformfile="fcmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_zero">FCMGE (zero)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLE_asisdmisc_FZ" iformfile="fcmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMLE_advsimd">FCMLE (zero)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_asisdmisc_R" iformfile="fcvtpu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPU_advsimd">FCVTPU (vector)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asisdmisc_R" iformfile="fcvtzu_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_int">FCVTZU (vector, integer)</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTE_asisdmisc_R" iformfile="frsqrte_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRSQRTE_advsimd">FRSQRTE</td>
|
|
<td class="enctags">Scalar single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_65_asisdmisc" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdmiscfp16" title="Advanced SIMD scalar two-register miscellaneous FP16">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="a" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdmiscfp16" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">a</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">010xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1100x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">011xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtns_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNS_advsimd">FCVTNS (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtms_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMS_advsimd">FCVTMS (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtas_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAS_advsimd">FCVTAS (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="scvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_int">SCVTF (vector, integer)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asisdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_zero">FCMGT (zero)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asisdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_zero">FCMEQ (zero)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLT_asisdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="FCMLT_advsimd">FCMLT (zero)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPS_advsimd">FCVTPS (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtzs_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_int">FCVTZS (vector, integer)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPE_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frecpe_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRECPE_advsimd">FRECPE</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPX_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frecpx_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRECPX_advsimd">FRECPX</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtnu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNU_advsimd">FCVTNU (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtmu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMU_advsimd">FCVTMU (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtau_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAU_advsimd">FCVTAU (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="ucvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_int">UCVTF (vector, integer)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asisdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_zero">FCMGE (zero)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLE_asisdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMLE_advsimd">FCMLE (zero)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtpu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPU_advsimd">FCVTPU (vector)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtzu_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_int">FCVTZU (vector, integer)</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTE_asisdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frsqrte_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRSQRTE_advsimd">FRSQRTE</td>
|
|
<td class="enctags">Scalar half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asisdmiscfp16" undef="1" oneofthismnem="11" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asisdelem" title="Advanced SIMD scalar x indexed element">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asisdelem" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="32*" />
|
|
<col colno="5" printwidth="47*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLAL_asisdelem_L" iformfile="sqdmlal_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="SQDMLAL_advsimd_elt">SQDMLAL, SQDMLAL2 (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLSL_asisdelem_L" iformfile="sqdmlsl_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="SQDMLSL_advsimd_elt">SQDMLSL, SQDMLSL2 (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULL_asisdelem_L" iformfile="sqdmull_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SQDMULL_advsimd_elt">SQDMULL, SQDMULL2 (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULH_asisdelem_R" iformfile="sqdmulh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="SQDMULH_advsimd_elt">SQDMULH (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMULH_asisdelem_R" iformfile="sqrdmulh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQRDMULH_advsimd_elt">SQRDMULH (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_43_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asisdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmla_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_elt">FMLA (by element)</td>
|
|
<td class="enctags">Scalar, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asisdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmls_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_elt">FMLS (by element)</td>
|
|
<td class="enctags">Scalar, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asisdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmul_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_elt">FMUL (by element)</td>
|
|
<td class="enctags">Scalar, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asisdelem_R_SD" iformfile="fmla_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_elt">FMLA (by element)</td>
|
|
<td class="enctags">Scalar, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asisdelem_R_SD" iformfile="fmls_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_elt">FMLS (by element)</td>
|
|
<td class="enctags">Scalar, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asisdelem_R_SD" iformfile="fmul_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_elt">FMUL (by element)</td>
|
|
<td class="enctags">Scalar, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLAH_asisdelem_R" arch_version="FEAT_RDM" iformfile="sqrdmlah_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQRDMLAH_advsimd_elt">SQRDMLAH (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLSH_asisdelem_R" arch_version="FEAT_RDM" iformfile="sqrdmlsh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="SQRDMLSH_advsimd_elt">SQRDMLSH (by element)</td>
|
|
<td class="enctags">Scalar</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asisdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmulx_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_elt">FMULX (by element)</td>
|
|
<td class="enctags">Scalar, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asisdelem" undef="1" oneofthismnem="19" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asisdelem_R_SD" iformfile="fmulx_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_elt">FMULX (by element)</td>
|
|
<td class="enctags">Scalar, single-precision and double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdshf" title="Advanced SIMD shift by immediate">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="4" name="immh" usename="1" settings="4" constraint="!= 0000">
|
|
<c colspan="4">!= 0000</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="immb" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="immh" op="!=" val="0000" />
|
|
<decode_constraint name="immh" op="!=" val="0000" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="asimdshf" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="30*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_45_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1011x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_47_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_50_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_51_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSHR_asimdshf_R" iformfile="sshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="SSHR_advsimd">SSHR</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSRA_asimdshf_R" iformfile="ssra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="SSRA_advsimd">SSRA</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSHR_asimdshf_R" iformfile="srshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="SRSHR_advsimd">SRSHR</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSRA_asimdshf_R" iformfile="srsra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="SRSRA_advsimd">SRSRA</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_23_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHL_asimdshf_R" iformfile="shl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SHL_advsimd">SHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asimdshf" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHL_asimdshf_R" iformfile="sqshl_advsimd_imm.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="SQSHL_advsimd_imm">SQSHL (immediate)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHRN_asimdshf_N" iformfile="shrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="SHRN_advsimd">SHRN, SHRN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RSHRN_asimdshf_N" iformfile="rshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="RSHRN_advsimd">RSHRN, RSHRN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHRN_asimdshf_N" iformfile="sqshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="SQSHRN_advsimd">SQSHRN, SQSHRN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHRN_asimdshf_N" iformfile="sqrshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="SQRSHRN_advsimd">SQRSHRN, SQRSHRN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSHLL_asimdshf_L" iformfile="sshll_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="SSHLL_advsimd">SSHLL, SSHLL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asimdshf_C" iformfile="scvtf_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_fix">SCVTF (vector, fixed-point)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asimdshf_C" iformfile="fcvtzs_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_fix">FCVTZS (vector, fixed-point)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USHR_asimdshf_R" iformfile="ushr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="USHR_advsimd">USHR</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USRA_asimdshf_R" iformfile="usra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="USRA_advsimd">USRA</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSHR_asimdshf_R" iformfile="urshr_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="URSHR_advsimd">URSHR</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSRA_asimdshf_R" iformfile="ursra_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="URSRA_advsimd">URSRA</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRI_asimdshf_R" iformfile="sri_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="SRI_advsimd">SRI</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SLI_asimdshf_R" iformfile="sli_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SLI_advsimd">SLI</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHLU_asimdshf_R" iformfile="sqshlu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="SQSHLU_advsimd">SQSHLU</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHL_asimdshf_R" iformfile="uqshl_advsimd_imm.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="UQSHL_advsimd_imm">UQSHL (immediate)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHRUN_asimdshf_N" iformfile="sqshrun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="SQSHRUN_advsimd">SQSHRUN, SQSHRUN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHRUN_asimdshf_N" iformfile="sqrshrun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="SQRSHRUN_advsimd">SQRSHRUN, SQRSHRUN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHRN_asimdshf_N" iformfile="uqshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="UQSHRN_advsimd">UQSHRN, UQSHRN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQRSHRN_asimdshf_N" iformfile="uqrshrn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="UQRSHRN_advsimd">UQRSHRN, UQRSHRN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USHLL_asimdshf_L" iformfile="ushll_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="USHLL_advsimd">USHLL, USHLL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asimdshf_C" iformfile="ucvtf_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_fix">UCVTF (vector, fixed-point)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asimdshf_C" iformfile="fcvtzu_advsimd_fix.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_fix">FCVTZU (vector, fixed-point)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdtbl" title="Advanced SIMD table lookup">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="op2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="len" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdtbl" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op2</th>
|
|
<th class="bitfields">len</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdtbl" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBL_asimdtbl_L1_1" iformfile="tbl_advsimd.xml" label="single register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="TBL_advsimd">TBL</td>
|
|
<td class="enctags">Single register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBX_asimdtbl_L1_1" iformfile="tbx_advsimd.xml" label="single register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="TBX_advsimd">TBX</td>
|
|
<td class="enctags">Single register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBL_asimdtbl_L2_2" iformfile="tbl_advsimd.xml" label="two register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="TBL_advsimd">TBL</td>
|
|
<td class="enctags">Two register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBX_asimdtbl_L2_2" iformfile="tbx_advsimd.xml" label="two register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="TBX_advsimd">TBX</td>
|
|
<td class="enctags">Two register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBL_asimdtbl_L3_3" iformfile="tbl_advsimd.xml" label="three register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="TBL_advsimd">TBL</td>
|
|
<td class="enctags">Three register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBX_asimdtbl_L3_3" iformfile="tbx_advsimd.xml" label="three register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="TBX_advsimd">TBX</td>
|
|
<td class="enctags">Three register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBL_asimdtbl_L4_4" iformfile="tbl_advsimd.xml" label="four register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="TBL_advsimd">TBL</td>
|
|
<td class="enctags">Four register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="TBX_asimdtbl_L4_4" iformfile="tbx_advsimd.xml" label="four register table" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="TBX_advsimd">TBX</td>
|
|
<td class="enctags">Four register table</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asimdtbl" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimddiff" title="Advanced SIMD three different">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimddiff" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="28*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asimddiff" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SADDL_asimddiff_L" iformfile="saddl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SADDL_advsimd">SADDL, SADDL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SADDW_asimddiff_W" iformfile="saddw_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="SADDW_advsimd">SADDW, SADDW2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSUBL_asimddiff_L" iformfile="ssubl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SSUBL_advsimd">SSUBL, SSUBL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSUBW_asimddiff_W" iformfile="ssubw_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="SSUBW_advsimd">SSUBW, SSUBW2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDHN_asimddiff_N" iformfile="addhn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ADDHN_advsimd">ADDHN, ADDHN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SABAL_asimddiff_L" iformfile="sabal_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="SABAL_advsimd">SABAL, SABAL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUBHN_asimddiff_N" iformfile="subhn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="SUBHN_advsimd">SUBHN, SUBHN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SABDL_asimddiff_L" iformfile="sabdl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="SABDL_advsimd">SABDL, SABDL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMLAL_asimddiff_L" iformfile="smlal_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="SMLAL_advsimd_vec">SMLAL, SMLAL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLAL_asimddiff_L" iformfile="sqdmlal_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="SQDMLAL_advsimd_vec">SQDMLAL, SQDMLAL2 (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMLSL_asimddiff_L" iformfile="smlsl_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="SMLSL_advsimd_vec">SMLSL, SMLSL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLSL_asimddiff_L" iformfile="sqdmlsl_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SQDMLSL_advsimd_vec">SQDMLSL, SQDMLSL2 (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMULL_asimddiff_L" iformfile="smull_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="SMULL_advsimd_vec">SMULL, SMULL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULL_asimddiff_L" iformfile="sqdmull_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQDMULL_advsimd_vec">SQDMULL, SQDMULL2 (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PMULL_asimddiff_L" iformfile="pmull_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="PMULL_advsimd">PMULL, PMULL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UADDL_asimddiff_L" iformfile="uaddl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="UADDL_advsimd">UADDL, UADDL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UADDW_asimddiff_W" iformfile="uaddw_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="UADDW_advsimd">UADDW, UADDW2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USUBL_asimddiff_L" iformfile="usubl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="USUBL_advsimd">USUBL, USUBL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USUBW_asimddiff_W" iformfile="usubw_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="USUBW_advsimd">USUBW, USUBW2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RADDHN_asimddiff_N" iformfile="raddhn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="RADDHN_advsimd">RADDHN, RADDHN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UABAL_asimddiff_L" iformfile="uabal_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="UABAL_advsimd">UABAL, UABAL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RSUBHN_asimddiff_N" iformfile="rsubhn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="RSUBHN_advsimd">RSUBHN, RSUBHN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UABDL_asimddiff_L" iformfile="uabdl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="UABDL_advsimd">UABDL, UABDL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMLAL_asimddiff_L" iformfile="umlal_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="UMLAL_advsimd_vec">UMLAL, UMLAL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asimddiff" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMLSL_asimddiff_L" iformfile="umlsl_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="UMLSL_advsimd_vec">UMLSL, UMLSL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asimddiff" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMULL_asimddiff_L" iformfile="umull_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="UMULL_advsimd_vec">UMULL, UMULL2 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_asimddiff" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_40_asimddiff" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdsame" title="Advanced SIMD three same">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdsame" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<col colno="5" printwidth="46*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SHADD_asimdsame_only" iformfile="shadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="SHADD_advsimd">SHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQADD_asimdsame_only" iformfile="sqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="SQADD_advsimd">SQADD</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRHADD_asimdsame_only" iformfile="srhadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="SRHADD_advsimd">SRHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHSUB_asimdsame_only" iformfile="shsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="SHSUB_advsimd">SHSUB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSUB_asimdsame_only" iformfile="sqsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="SQSUB_advsimd">SQSUB</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGT_asimdsame_only" iformfile="cmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="CMGT_advsimd_reg">CMGT (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGE_asimdsame_only" iformfile="cmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="CMGE_advsimd_reg">CMGE (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SSHL_asimdsame_only" iformfile="sshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="SSHL_advsimd">SSHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQSHL_asimdsame_only" iformfile="sqshl_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="SQSHL_advsimd_reg">SQSHL (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SRSHL_asimdsame_only" iformfile="srshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="SRSHL_advsimd">SRSHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRSHL_asimdsame_only" iformfile="sqrshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="SQRSHL_advsimd">SQRSHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAX_asimdsame_only" iformfile="smax_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="SMAX_advsimd">SMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMIN_asimdsame_only" iformfile="smin_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="SMIN_advsimd">SMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SABD_asimdsame_only" iformfile="sabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="SABD_advsimd">SABD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SABA_asimdsame_only" iformfile="saba_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="SABA_advsimd">SABA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADD_asimdsame_only" iformfile="add_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="ADD_advsimd">ADD (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMTST_asimdsame_only" iformfile="cmtst_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="CMTST_advsimd">CMTST</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MLA_asimdsame_only" iformfile="mla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="MLA_advsimd_vec">MLA (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MUL_asimdsame_only" iformfile="mul_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="MUL_advsimd_vec">MUL (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMAXP_asimdsame_only" iformfile="smaxp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="SMAXP_advsimd">SMAXP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMINP_asimdsame_only" iformfile="sminp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname" iformid="SMINP_advsimd">SMINP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULH_asimdsame_only" iformfile="sqdmulh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="SQDMULH_advsimd_vec">SQDMULH (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ADDP_asimdsame_only" iformfile="addp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname" iformid="ADDP_advsimd_vec">ADDP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNM_asimdsame_only" iformfile="fmaxnm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FMAXNM_advsimd">FMAXNM (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asimdsame_only" iformfile="fmla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_vec">FMLA (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADD_asimdsame_only" iformfile="fadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FADD_advsimd">FADD (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asimdsame_only" iformfile="fmulx_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_vec">FMULX</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asimdsame_only" iformfile="fcmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_reg">FCMEQ (register)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAX_asimdsame_only" iformfile="fmax_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FMAX_advsimd">FMAX (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPS_asimdsame_only" iformfile="frecps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRECPS_advsimd">FRECPS</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AND_asimdsame_only" iformfile="and_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="AND_advsimd">AND (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLAL_asimdsame_F" arch_version="FEAT_FHM" iformfile="fmlal_advsimd_vec.xml" label="FMLAL" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FMLAL_advsimd_vec">FMLAL, FMLAL2 (vector)</td>
|
|
<td class="enctags">FMLAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIC_asimdsame_only" iformfile="bic_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="BIC_advsimd_reg">BIC (vector, register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_88_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNM_asimdsame_only" iformfile="fminnm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FMINNM_advsimd">FMINNM (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asimdsame_only" iformfile="fmls_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_vec">FMLS (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSUB_asimdsame_only" iformfile="fsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FSUB_advsimd">FSUB (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_81_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_85_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMIN_asimdsame_only" iformfile="fmin_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FMIN_advsimd">FMIN (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTS_asimdsame_only" iformfile="frsqrts_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRSQRTS_advsimd">FRSQRTS</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORR_asimdsame_only" iformfile="orr_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="ORR_advsimd_reg">ORR (vector, register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLSL_asimdsame_F" arch_version="FEAT_FHM" iformfile="fmlsl_advsimd_vec.xml" label="FMLSL" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FMLSL_advsimd_vec">FMLSL, FMLSL2 (vector)</td>
|
|
<td class="enctags">FMLSL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ORN_asimdsame_only" iformfile="orn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="ORN_advsimd">ORN (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_91_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UHADD_asimdsame_only" iformfile="uhadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="UHADD_advsimd">UHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQADD_asimdsame_only" iformfile="uqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="UQADD_advsimd">UQADD</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URHADD_asimdsame_only" iformfile="urhadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="URHADD_advsimd">URHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UHSUB_asimdsame_only" iformfile="uhsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="UHSUB_advsimd">UHSUB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSUB_asimdsame_only" iformfile="uqsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="UQSUB_advsimd">UQSUB</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMHI_asimdsame_only" iformfile="cmhi_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="CMHI_advsimd">CMHI (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMHS_asimdsame_only" iformfile="cmhs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="CMHS_advsimd">CMHS (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USHL_asimdsame_only" iformfile="ushl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="USHL_advsimd">USHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQSHL_asimdsame_only" iformfile="uqshl_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="UQSHL_advsimd_reg">UQSHL (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSHL_asimdsame_only" iformfile="urshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="URSHL_advsimd">URSHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQRSHL_asimdsame_only" iformfile="uqrshl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="UQRSHL_advsimd">UQRSHL</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAX_asimdsame_only" iformfile="umax_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="UMAX_advsimd">UMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMIN_asimdsame_only" iformfile="umin_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="UMIN_advsimd">UMIN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UABD_asimdsame_only" iformfile="uabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="UABD_advsimd">UABD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UABA_asimdsame_only" iformfile="uaba_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="UABA_advsimd">UABA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUB_asimdsame_only" iformfile="sub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="SUB_advsimd">SUB (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMEQ_asimdsame_only" iformfile="cmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10001</td>
|
|
<td class="iformname" iformid="CMEQ_advsimd_reg">CMEQ (register)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MLS_asimdsame_only" iformfile="mls_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="MLS_advsimd_vec">MLS (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="PMUL_asimdsame_only" iformfile="pmul_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="PMUL_advsimd">PMUL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMAXP_asimdsame_only" iformfile="umaxp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="UMAXP_advsimd">UMAXP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMINP_asimdsame_only" iformfile="uminp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname" iformid="UMINP_advsimd">UMINP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMULH_asimdsame_only" iformfile="sqrdmulh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="SQRDMULH_advsimd_vec">SQRDMULH (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_64_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMP_asimdsame_only" iformfile="fmaxnmp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FMAXNMP_advsimd_vec">FMAXNMP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADDP_asimdsame_only" iformfile="faddp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FADDP_advsimd_vec">FADDP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asimdsame_only" iformfile="fmul_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_vec">FMUL (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asimdsame_only" iformfile="fcmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_reg">FCMGE (register)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGE_asimdsame_only" iformfile="facge_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FACGE_advsimd">FACGE</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXP_asimdsame_only" iformfile="fmaxp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FMAXP_advsimd_vec">FMAXP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FDIV_asimdsame_only" iformfile="fdiv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FDIV_advsimd">FDIV (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="EOR_asimdsame_only" iformfile="eor_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="EOR_advsimd">EOR (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLAL2_asimdsame_F" arch_version="FEAT_FHM" iformfile="fmlal_advsimd_vec.xml" label="FMLAL2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FMLAL_advsimd_vec">FMLAL, FMLAL2 (vector)</td>
|
|
<td class="enctags">FMLAL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BSL_asimdsame_only" iformfile="bsl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="BSL_advsimd">BSL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_71_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMP_asimdsame_only" iformfile="fminnmp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FMINNMP_advsimd_vec">FMINNMP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABD_asimdsame_only" iformfile="fabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FABD_advsimd">FABD</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_82_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asimdsame_only" iformfile="fcmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_reg">FCMGT (register)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGT_asimdsame_only" iformfile="facgt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FACGT_advsimd">FACGT</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINP_asimdsame_only" iformfile="fminp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FMINP_advsimd_vec">FMINP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_100_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIT_asimdsame_only" iformfile="bit_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="BIT_advsimd">BIT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLSL2_asimdsame_F" arch_version="FEAT_FHM" iformfile="fmlsl_advsimd_vec.xml" label="FMLSL2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FMLSL_advsimd_vec">FMLSL, FMLSL2 (vector)</td>
|
|
<td class="enctags">FMLSL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BIF_asimdsame_only" iformfile="bif_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="BIF_advsimd">BIF</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_74_asimdsame" undef="1" oneofthismnem="9" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdsamefp16" title="Advanced SIMD three same (FP16)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="a" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdsamefp16" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">a</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="FMAXNM_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmaxnm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FMAXNM_advsimd">FMAXNM (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_vec">FMLA (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADD_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="FADD_advsimd">FADD (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmulx_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_vec">FMULX</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmeq_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_reg">FCMEQ (register)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAX_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmax_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMAX_advsimd">FMAX (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPS_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="frecps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FRECPS_advsimd">FRECPS</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNM_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fminnm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FMINNM_advsimd">FMINNM (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmls_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_vec">FMLS (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSUB_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fsub_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="FSUB_advsimd">FSUB (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMIN_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmin_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMIN_advsimd">FMIN (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTS_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="frsqrts_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FRSQRTS_advsimd">FRSQRTS</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNMP_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmaxnmp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FMAXNMP_advsimd_vec">FMAXNMP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADDP_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="faddp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="FADDP_advsimd_vec">FADDP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmul_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_vec">FMUL (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmge_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_reg">FCMGE (register)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGE_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="facge_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FACGE_advsimd">FACGE</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXP_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fmaxp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMAXP_advsimd_vec">FMAXP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FDIV_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fdiv_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FDIV_advsimd">FDIV (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNMP_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fminnmp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FMINNMP_advsimd_vec">FMINNMP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABD_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fabd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="FABD_advsimd">FABD</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fcmgt_advsimd_reg.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_reg">FCMGT (register)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FACGT_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="facgt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FACGT_advsimd">FACGT</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINP_asimdsamefp16_only" arch_version="FEAT_FP16" iformfile="fminp_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMINP_advsimd_vec">FMINP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asimdsamefp16" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdsame2" title="Advanced SIMD three-register extension">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdsame2" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="27*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Q</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SDOT_asimdsame2_D" arch_version="FEAT_DotProd" iformfile="sdot_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SDOT_advsimd_vec">SDOT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_28_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USDOT_asimdsame2_D" arch_version="FEAT_I8MM" iformfile="usdot_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="USDOT_advsimd_vec">USDOT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLAH_asimdsame2_only" arch_version="FEAT_RDM" iformfile="sqrdmlah_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="SQRDMLAH_advsimd_vec">SQRDMLAH (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLSH_asimdsame2_only" arch_version="FEAT_RDM" iformfile="sqrdmlsh_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="SQRDMLSH_advsimd_vec">SQRDMLSH (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UDOT_asimdsame2_D" arch_version="FEAT_DotProd" iformfile="udot_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="UDOT_advsimd_vec">UDOT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLA_asimdsame2_C" arch_version="FEAT_FCMA" iformfile="fcmla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">10xx</td>
|
|
<td class="iformname" iformid="FCMLA_advsimd_vec">FCMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCADD_asimdsame2_C" arch_version="FEAT_FCMA" iformfile="fcadd_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">11x0</td>
|
|
<td class="iformname" iformid="FCADD_advsimd_vec">FCADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_31_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_35_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFDOT_asimdsame2_D" arch_version="FEAT_BF16" iformfile="bfdot_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="BFDOT_advsimd_vec">BFDOT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_38_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFMLAL_asimdsame2_F_" arch_version="FEAT_BF16" iformfile="bfmlal_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="BFMLAL_advsimd_vec">BFMLALB, BFMLALT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_21_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">011x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMMLA_asimdsame2_G" arch_version="FEAT_I8MM" iformfile="smmla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="SMMLA_advsimd_vec">SMMLA (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USMMLA_asimdsame2_G" arch_version="FEAT_I8MM" iformfile="usmmla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="USMMLA_advsimd_vec">USMMLA (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFMMLA_asimdsame2_E" arch_version="FEAT_BF16" iformfile="bfmmla_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="BFMMLA_advsimd">BFMMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMMLA_asimdsame2_G" arch_version="FEAT_I8MM" iformfile="ummla_advsimd_vec.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="UMMLA_advsimd_vec">UMMLA (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdsame2" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdmisc" title="Advanced SIMD two-register miscellaneous">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdmisc" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="46*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1000x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_53_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_37_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">011xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_61_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_88_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_58_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV64_asimdmisc_R" iformfile="rev64_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="REV64_advsimd">REV64</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV16_asimdmisc_R" iformfile="rev16_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="REV16_advsimd">REV16 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SADDLP_asimdmisc_P" iformfile="saddlp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="SADDLP_advsimd">SADDLP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUQADD_asimdmisc_R" iformfile="suqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="SUQADD_advsimd">SUQADD</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLS_asimdmisc_R" iformfile="cls_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="CLS_advsimd">CLS (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CNT_asimdmisc_R" iformfile="cnt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="CNT_advsimd">CNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SADALP_asimdmisc_P" iformfile="sadalp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="SADALP_advsimd">SADALP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQABS_asimdmisc_R" iformfile="sqabs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="SQABS_advsimd">SQABS</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGT_asimdmisc_Z" iformfile="cmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="CMGT_advsimd_zero">CMGT (zero)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMEQ_asimdmisc_Z" iformfile="cmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="CMEQ_advsimd_zero">CMEQ (zero)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMLT_asimdmisc_Z" iformfile="cmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname" iformid="CMLT_advsimd">CMLT (zero)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ABS_asimdmisc_R" iformfile="abs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="ABS_advsimd">ABS</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="XTN_asimdmisc_N" iformfile="xtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="XTN_advsimd">XTN, XTN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_49_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQXTN_asimdmisc_N" iformfile="sqxtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="SQXTN_advsimd">SQXTN, SQXTN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTN_asimdmisc_N" iformfile="fcvtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="FCVTN_advsimd">FCVTN, FCVTN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTL_asimdmisc_L" iformfile="fcvtl_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname" iformid="FCVTL_advsimd">FCVTL, FCVTL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTN_asimdmisc_R" iformfile="frintn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTN_advsimd">FRINTN (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTM_asimdmisc_R" iformfile="frintm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTM_advsimd">FRINTM (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_asimdmisc_R" iformfile="fcvtns_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNS_advsimd">FCVTNS (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_asimdmisc_R" iformfile="fcvtms_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMS_advsimd">FCVTMS (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_asimdmisc_R" iformfile="fcvtas_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAS_advsimd">FCVTAS (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asimdmisc_R" iformfile="scvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_int">SCVTF (vector, integer)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32Z_asimdmisc_R" arch_version="FEAT_FRINTTS" iformfile="frint32z_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FRINT32Z_advsimd">FRINT32Z (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64Z_asimdmisc_R" arch_version="FEAT_FRINTTS" iformfile="frint64z_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRINT64Z_advsimd">FRINT64Z (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asimdmisc_FZ" iformfile="fcmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_zero">FCMGT (zero)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asimdmisc_FZ" iformfile="fcmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_zero">FCMEQ (zero)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLT_asimdmisc_FZ" iformfile="fcmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="FCMLT_advsimd">FCMLT (zero)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABS_asimdmisc_R" iformfile="fabs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FABS_advsimd">FABS (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTP_asimdmisc_R" iformfile="frintp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTP_advsimd">FRINTP (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTZ_asimdmisc_R" iformfile="frintz_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTZ_advsimd">FRINTZ (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_asimdmisc_R" iformfile="fcvtps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPS_advsimd">FCVTPS (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asimdmisc_R" iformfile="fcvtzs_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_int">FCVTZS (vector, integer)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URECPE_asimdmisc_R" iformfile="urecpe_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="URECPE_advsimd">URECPE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPE_asimdmisc_R" iformfile="frecpe_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRECPE_advsimd">FRECPE</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_91_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFCVTN_asimdmisc_4S" arch_version="FEAT_BF16" iformfile="bfcvtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="BFCVTN_advsimd">BFCVTN, BFCVTN2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="REV32_asimdmisc_R" iformfile="rev32_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="REV32_advsimd">REV32 (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UADDLP_asimdmisc_P" iformfile="uaddlp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="UADDLP_advsimd">UADDLP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USQADD_asimdmisc_R" iformfile="usqadd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname" iformid="USQADD_advsimd">USQADD</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CLZ_asimdmisc_R" iformfile="clz_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="CLZ_advsimd">CLZ (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UADALP_asimdmisc_P" iformfile="uadalp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="UADALP_advsimd">UADALP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQNEG_asimdmisc_R" iformfile="sqneg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="SQNEG_advsimd">SQNEG</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMGE_asimdmisc_Z" iformfile="cmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="CMGE_advsimd_zero">CMGE (zero)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="CMLE_asimdmisc_Z" iformfile="cmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01001</td>
|
|
<td class="iformname" iformid="CMLE_advsimd">CMLE (zero)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="NEG_asimdmisc_R" iformfile="neg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">01011</td>
|
|
<td class="iformname" iformid="NEG_advsimd">NEG (vector)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQXTUN_asimdmisc_N" iformfile="sqxtun_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10010</td>
|
|
<td class="iformname" iformid="SQXTUN_advsimd">SQXTUN, SQXTUN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHLL_asimdmisc_S" iformfile="shll_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10011</td>
|
|
<td class="iformname" iformid="SHLL_advsimd">SHLL, SHLL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UQXTN_asimdmisc_N" iformfile="uqxtn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10100</td>
|
|
<td class="iformname" iformid="UQXTN_advsimd">UQXTN, UQXTN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTXN_asimdmisc_N" iformfile="fcvtxn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname" iformid="FCVTXN_advsimd">FCVTXN, FCVTXN2</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_60_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">10111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTA_asimdmisc_R" iformfile="frinta_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTA_advsimd">FRINTA (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTX_asimdmisc_R" iformfile="frintx_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTX_advsimd">FRINTX (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_asimdmisc_R" iformfile="fcvtnu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNU_advsimd">FCVTNU (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_asimdmisc_R" iformfile="fcvtmu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMU_advsimd">FCVTMU (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_asimdmisc_R" iformfile="fcvtau_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAU_advsimd">FCVTAU (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asimdmisc_R" iformfile="ucvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_int">UCVTF (vector, integer)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32X_asimdmisc_R" arch_version="FEAT_FRINTTS" iformfile="frint32x_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname" iformid="FRINT32X_advsimd">FRINT32X (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64X_asimdmisc_R" arch_version="FEAT_FRINTTS" iformfile="frint64x_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FRINT64X_advsimd">FRINT64X (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="NOT_asimdmisc_R" iformfile="not_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="NOT_advsimd">NOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RBIT_asimdmisc_R" iformfile="rbit_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="RBIT_advsimd">RBIT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_24_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asimdmisc_FZ" iformfile="fcmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_zero">FCMGE (zero)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLE_asimdmisc_FZ" iformfile="fcmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMLE_advsimd">FCMLE (zero)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_43_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNEG_asimdmisc_R" iformfile="fneg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FNEG_advsimd">FNEG (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_65_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTI_asimdmisc_R" iformfile="frinti_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTI_advsimd">FRINTI (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_asimdmisc_R" iformfile="fcvtpu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPU_advsimd">FCVTPU (vector)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asimdmisc_R" iformfile="fcvtzu_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_int">FCVTZU (vector, integer)</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="URSQRTE_asimdmisc_R" iformfile="ursqrte_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="URSQRTE_advsimd">URSQRTE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTE_asimdmisc_R" iformfile="frsqrte_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRSQRTE_advsimd">FRSQRTE</td>
|
|
<td class="enctags">Vector single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSQRT_asimdmisc_R" iformfile="fsqrt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FSQRT_advsimd">FSQRT (vector)</td>
|
|
<td class="enctags">Single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_57_asimdmisc" undef="1" oneofthismnem="15" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield">10110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdmiscfp16" title="Advanced SIMD two-register miscellaneous (FP16)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="a" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdmiscfp16" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">a</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">00xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">010xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_22_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_46_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">011xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_47_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTN_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frintn_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTN_advsimd">FRINTN (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTM_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frintm_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTM_advsimd">FRINTM (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtns_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNS_advsimd">FCVTNS (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtms_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMS_advsimd">FCVTMS (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtas_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAS_advsimd">FCVTAS (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="scvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="SCVTF_advsimd_int">SCVTF (vector, integer)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGT_asimdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmgt_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGT_advsimd_zero">FCMGT (zero)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMEQ_asimdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmeq_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMEQ_advsimd_zero">FCMEQ (zero)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLT_asimdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmlt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname" iformid="FCMLT_advsimd">FCMLT (zero)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fabs_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FABS_advsimd">FABS (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTP_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frintp_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTP_advsimd">FRINTP (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTZ_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frintz_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTZ_advsimd">FRINTZ (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtps_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPS_advsimd">FCVTPS (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtzs_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZS_advsimd_int">FCVTZS (vector, integer)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRECPE_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frecpe_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRECPE_advsimd">FRECPE</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTA_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frinta_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FRINTA_advsimd">FRINTA (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTX_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frintx_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTX_advsimd">FRINTX (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtnu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTNU_advsimd">FCVTNU (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtmu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTMU_advsimd">FCVTMU (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtau_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11100</td>
|
|
<td class="iformname" iformid="FCVTAU_advsimd">FCVTAU (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="ucvtf_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="UCVTF_advsimd_int">UCVTF (vector, integer)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMGE_asimdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmge_advsimd_zero.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01100</td>
|
|
<td class="iformname" iformid="FCMGE_advsimd_zero">FCMGE (zero)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLE_asimdmiscfp16_FZ" arch_version="FEAT_FP16" iformfile="fcmle_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01101</td>
|
|
<td class="iformname" iformid="FCMLE_advsimd">FCMLE (zero)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNEG_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fneg_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">01111</td>
|
|
<td class="iformname" iformid="FNEG_advsimd">FNEG (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdmiscfp16" undef="1" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTI_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frinti_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11001</td>
|
|
<td class="iformname" iformid="FRINTI_advsimd">FRINTI (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtpu_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11010</td>
|
|
<td class="iformname" iformid="FCVTPU_advsimd">FCVTPU (vector)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fcvtzu_advsimd_int.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11011</td>
|
|
<td class="iformname" iformid="FCVTZU_advsimd_int">FCVTZU (vector, integer)</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRSQRTE_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="frsqrte_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11101</td>
|
|
<td class="iformname" iformid="FRSQRTE_advsimd">FRSQRTE</td>
|
|
<td class="enctags">Vector half precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSQRT_asimdmiscfp16_R" arch_version="FEAT_FP16" iformfile="fsqrt_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="FSQRT_advsimd">FSQRT (vector)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="asimdelem" title="Advanced SIMD vector x indexed element">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="30" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="29" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="asimdelem" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="8*" />
|
|
<col colno="4" printwidth="32*" />
|
|
<col colno="5" printwidth="47*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_47_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMLAL_asimdelem_L" iformfile="smlal_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="SMLAL_advsimd_elt">SMLAL, SMLAL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLAL_asimdelem_L" iformfile="sqdmlal_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="SQDMLAL_advsimd_elt">SQDMLAL, SQDMLAL2 (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMLSL_asimdelem_L" iformfile="smlsl_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="SMLSL_advsimd_elt">SMLSL, SMLSL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMLSL_asimdelem_L" iformfile="sqdmlsl_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="SQDMLSL_advsimd_elt">SQDMLSL, SQDMLSL2 (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MUL_asimdelem_R" iformfile="mul_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="MUL_advsimd_elt">MUL (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SMULL_asimdelem_L" iformfile="smull_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="SMULL_advsimd_elt">SMULL, SMULL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULL_asimdelem_L" iformfile="sqdmull_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="SQDMULL_advsimd_elt">SQDMULL, SQDMULL2 (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQDMULH_asimdelem_R" iformfile="sqdmulh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="SQDMULH_advsimd_elt">SQDMULH (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMULH_asimdelem_R" iformfile="sqrdmulh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQRDMULH_advsimd_elt">SQRDMULH (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SDOT_asimdelem_D" arch_version="FEAT_DotProd" iformfile="sdot_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="SDOT_advsimd_elt">SDOT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_27_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asimdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmla_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_elt">FMLA (by element)</td>
|
|
<td class="enctags">Vector, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asimdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmls_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_elt">FMLS (by element)</td>
|
|
<td class="enctags">Vector, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asimdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmul_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_elt">FMUL (by element)</td>
|
|
<td class="enctags">Vector, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SUDOT_asimdelem_D" arch_version="FEAT_I8MM" iformfile="sudot_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="SUDOT_advsimd_elt">SUDOT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFDOT_asimdelem_E" arch_version="FEAT_BF16" iformfile="bfdot_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="BFDOT_advsimd_elt">BFDOT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLA_asimdelem_R_SD" iformfile="fmla_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FMLA_advsimd_elt">FMLA (by element)</td>
|
|
<td class="enctags">Vector, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLS_asimdelem_R_SD" iformfile="fmls_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMLS_advsimd_elt">FMLS (by element)</td>
|
|
<td class="enctags">Vector, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_asimdelem_R_SD" iformfile="fmul_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMUL_advsimd_elt">FMUL (by element)</td>
|
|
<td class="enctags">Vector, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLAL_asimdelem_LH" arch_version="FEAT_FHM" iformfile="fmlal_advsimd_elt.xml" label="FMLAL" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="FMLAL_advsimd_elt">FMLAL, FMLAL2 (by element)</td>
|
|
<td class="enctags">FMLAL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLSL_asimdelem_LH" arch_version="FEAT_FHM" iformfile="fmlsl_advsimd_elt.xml" label="FMLSL" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="FMLSL_advsimd_elt">FMLSL, FMLSL2 (by element)</td>
|
|
<td class="enctags">FMLSL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="USDOT_asimdelem_D" arch_version="FEAT_I8MM" iformfile="usdot_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="USDOT_advsimd_elt">USDOT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_29_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFMLAL_asimdelem_F" arch_version="FEAT_BF16" iformfile="bfmlal_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="BFMLAL_advsimd_elt">BFMLALB, BFMLALT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MLA_asimdelem_R" iformfile="mla_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="MLA_advsimd_elt">MLA (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMLAL_asimdelem_L" iformfile="umlal_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="UMLAL_advsimd_elt">UMLAL, UMLAL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="MLS_asimdelem_R" iformfile="mls_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="MLS_advsimd_elt">MLS (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMLSL_asimdelem_L" iformfile="umlsl_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="UMLSL_advsimd_elt">UMLSL, UMLSL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UMULL_asimdelem_L" iformfile="umull_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="UMULL_advsimd_elt">UMULL, UMULL2 (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_53_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLAH_asimdelem_R" arch_version="FEAT_RDM" iformfile="sqrdmlah_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="SQRDMLAH_advsimd_elt">SQRDMLAH (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UDOT_asimdelem_D" arch_version="FEAT_DotProd" iformfile="udot_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="UDOT_advsimd_elt">UDOT (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SQRDMLSH_asimdelem_R" arch_version="FEAT_RDM" iformfile="sqrdmlsh_advsimd_elt.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="SQRDMLSH_advsimd_elt">SQRDMLSH (by element)</td>
|
|
<td class="enctags">Vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_42_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_55_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_25_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_32_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asimdelem_RH_H" arch_version="FEAT_FP16" iformfile="fmulx_advsimd_elt.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_elt">FMULX (by element)</td>
|
|
<td class="enctags">Vector, half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLA_asimdelem_C_H" arch_version="FEAT_FCMA" iformfile="fcmla_advsimd_elt.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0xx1</td>
|
|
<td class="iformname" iformid="FCMLA_advsimd_elt">FCMLA (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMULX_asimdelem_R_SD" iformfile="fmulx_advsimd_elt.xml" label="single-precision and double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="FMULX_advsimd_elt">FMULX (by element)</td>
|
|
<td class="enctags">Vector, single-precision and double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMLA_asimdelem_C_S" arch_version="FEAT_FCMA" iformfile="fcmla_advsimd_elt.xml" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">0xx1</td>
|
|
<td class="iformname" iformid="FCMLA_advsimd_elt">FCMLA (by element)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLAL2_asimdelem_LH" arch_version="FEAT_FHM" iformfile="fmlal_advsimd_elt.xml" label="FMLAL2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="FMLAL_advsimd_elt">FMLAL, FMLAL2 (by element)</td>
|
|
<td class="enctags">FMLAL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMLSL2_asimdelem_LH" arch_version="FEAT_FHM" iformfile="fmlsl_advsimd_elt.xml" label="FMLSL2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="FMLSL_advsimd_elt">FMLSL, FMLSL2 (by element)</td>
|
|
<td class="enctags">FMLSL2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_21_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RESERVED_35_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_40_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_44_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_57_asimdelem" undef="1" oneofthismnem="20" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="float2fix" title="Conversion between floating-point and fixed-point">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="rmode" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="scale" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="float2fix" cols="8">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="7*" />
|
|
<col colno="5" printwidth="8*" />
|
|
<col colno="6" printwidth="8*" />
|
|
<col colno="7" printwidth="30*" />
|
|
<col colno="8" printwidth="28*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="6">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">rmode</th>
|
|
<th class="bitfields">opcode</th>
|
|
<th class="bitfields">scale</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_float2fix" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">0xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_S32_float2fix" iformfile="scvtf_float_fix.xml" label="32-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_S32_float2fix" iformfile="ucvtf_float_fix.xml" label="32-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32S_float2fix" iformfile="fcvtzs_float_fix.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32S_float2fix" iformfile="fcvtzu_float_fix.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_D32_float2fix" iformfile="scvtf_float_fix.xml" label="32-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_D32_float2fix" iformfile="ucvtf_float_fix.xml" label="32-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32D_float2fix" iformfile="fcvtzs_float_fix.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32D_float2fix" iformfile="fcvtzu_float_fix.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_H32_float2fix" arch_version="FEAT_FP16" iformfile="scvtf_float_fix.xml" label="32-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_H32_float2fix" arch_version="FEAT_FP16" iformfile="ucvtf_float_fix.xml" label="32-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32H_float2fix" arch_version="FEAT_FP16" iformfile="fcvtzs_float_fix.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32H_float2fix" arch_version="FEAT_FP16" iformfile="fcvtzu_float_fix.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_S64_float2fix" iformfile="scvtf_float_fix.xml" label="64-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_S64_float2fix" iformfile="ucvtf_float_fix.xml" label="64-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64S_float2fix" iformfile="fcvtzs_float_fix.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64S_float2fix" iformfile="fcvtzu_float_fix.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_D64_float2fix" iformfile="scvtf_float_fix.xml" label="64-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_D64_float2fix" iformfile="ucvtf_float_fix.xml" label="64-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64D_float2fix" iformfile="fcvtzs_float_fix.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64D_float2fix" iformfile="fcvtzu_float_fix.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_H64_float2fix" arch_version="FEAT_FP16" iformfile="scvtf_float_fix.xml" label="64-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="SCVTF_float_fix">SCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_H64_float2fix" arch_version="FEAT_FP16" iformfile="ucvtf_float_fix.xml" label="64-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="UCVTF_float_fix">UCVTF (scalar, fixed-point)</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64H_float2fix" arch_version="FEAT_FP16" iformfile="fcvtzs_float_fix.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZS_float_fix">FCVTZS (scalar, fixed-point)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64H_float2fix" arch_version="FEAT_FP16" iformfile="fcvtzu_float_fix.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname" iformid="FCVTZU_float_fix">FCVTZU (scalar, fixed-point)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="float2int" title="Conversion between floating-point and integer">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="rmode" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="float2int" cols="7">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="7*" />
|
|
<col colno="5" printwidth="8*" />
|
|
<col colno="6" printwidth="26*" />
|
|
<col colno="7" printwidth="31*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">rmode</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_76_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_77_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_40_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_32S_float2int" iformfile="fcvtns_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_32S_float2int" iformfile="fcvtnu_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_S32_float2int" iformfile="scvtf_float_int.xml" label="32-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_S32_float2int" iformfile="ucvtf_float_int.xml" label="32-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_32S_float2int" iformfile="fcvtas_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_32S_float2int" iformfile="fcvtau_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_32S_float2int" iformfile="fmov_float_gen.xml" label="single-precision to 32-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_S32_float2int" iformfile="fmov_float_gen.xml" label="32-bit to single-precision" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_32S_float2int" iformfile="fcvtps_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_32S_float2int" iformfile="fcvtpu_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_41_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_32S_float2int" iformfile="fcvtms_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_32S_float2int" iformfile="fcvtmu_float.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32S_float2int" iformfile="fcvtzs_float_int.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32S_float2int" iformfile="fcvtzu_float_int.xml" label="single-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_68_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_32D_float2int" iformfile="fcvtns_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_32D_float2int" iformfile="fcvtnu_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_D32_float2int" iformfile="scvtf_float_int.xml" label="32-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_D32_float2int" iformfile="ucvtf_float_int.xml" label="32-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_32D_float2int" iformfile="fcvtas_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_32D_float2int" iformfile="fcvtau_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_32D_float2int" iformfile="fcvtps_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_32D_float2int" iformfile="fcvtpu_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_32D_float2int" iformfile="fcvtms_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_32D_float2int" iformfile="fcvtmu_float.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_69_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32D_float2int" iformfile="fcvtzs_float_int.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32D_float2int" iformfile="fcvtzu_float_int.xml" label="double-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FJCVTZS_32D_float2int" arch_version="FEAT_JSCVT" iformfile="fjcvtzs.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FJCVTZS">FJCVTZS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_71_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_78_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtns_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtnu_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_H32_float2int" arch_version="FEAT_FP16" iformfile="scvtf_float_int.xml" label="32-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_H32_float2int" arch_version="FEAT_FP16" iformfile="ucvtf_float_int.xml" label="32-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtas_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtau_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_32H_float2int" arch_version="FEAT_FP16" iformfile="fmov_float_gen.xml" label="half-precision to 32-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_H32_float2int" arch_version="FEAT_FP16" iformfile="fmov_float_gen.xml" label="32-bit to half-precision" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtps_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtpu_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtms_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtmu_float.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtzs_float_int.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_32H_float2int" arch_version="FEAT_FP16" iformfile="fcvtzu_float_int.xml" label="half-precision to 32-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_39_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_64S_float2int" iformfile="fcvtns_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_64S_float2int" iformfile="fcvtnu_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_S64_float2int" iformfile="scvtf_float_int.xml" label="64-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_S64_float2int" iformfile="ucvtf_float_int.xml" label="64-bit to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_64S_float2int" iformfile="fcvtas_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_64S_float2int" iformfile="fcvtau_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_64S_float2int" iformfile="fcvtps_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_64S_float2int" iformfile="fcvtpu_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_64S_float2int" iformfile="fcvtms_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_64S_float2int" iformfile="fcvtmu_float.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64S_float2int" iformfile="fcvtzs_float_int.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64S_float2int" iformfile="fcvtzu_float_int.xml" label="single-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_72_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_64D_float2int" iformfile="fcvtns_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_64D_float2int" iformfile="fcvtnu_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_D64_float2int" iformfile="scvtf_float_int.xml" label="64-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_D64_float2int" iformfile="ucvtf_float_int.xml" label="64-bit to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_64D_float2int" iformfile="fcvtas_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_64D_float2int" iformfile="fcvtau_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_64D_float2int" iformfile="fmov_float_gen.xml" label="double-precision to 64-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_D64_float2int" iformfile="fmov_float_gen.xml" label="64-bit to double-precision" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_64D_float2int" iformfile="fcvtps_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_64D_float2int" iformfile="fcvtpu_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_73_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_64D_float2int" iformfile="fcvtms_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_64D_float2int" iformfile="fcvtmu_float.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64D_float2int" iformfile="fcvtzs_float_int.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64D_float2int" iformfile="fcvtzu_float_int.xml" label="double-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_79_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_64VX_float2int" iformfile="fmov_float_gen.xml" label="top half of 128-bit to 64-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">Top half of 128-bit to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_V64I_float2int" iformfile="fmov_float_gen.xml" label="64-bit to top half of 128-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">64-bit to top half of 128-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_80_float2int" undef="1" oneofthismnem="18" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNS_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtns_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTNS_float">FCVTNS (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTNU_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtnu_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTNU_float">FCVTNU (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SCVTF_H64_float2int" arch_version="FEAT_FP16" iformfile="scvtf_float_int.xml" label="64-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SCVTF_float_int">SCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UCVTF_H64_float2int" arch_version="FEAT_FP16" iformfile="ucvtf_float_int.xml" label="64-bit to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="UCVTF_float_int">UCVTF (scalar, integer)</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAS_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtas_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="FCVTAS_float">FCVTAS (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTAU_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtau_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="FCVTAU_float">FCVTAU (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_64H_float2int" arch_version="FEAT_FP16" iformfile="fmov_float_gen.xml" label="half-precision to 64-bit" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_H64_float2int" arch_version="FEAT_FP16" iformfile="fmov_float_gen.xml" label="64-bit to half-precision" oneofthismnem="10" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="FMOV_float_gen">FMOV (general)</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPS_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtps_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTPS_float">FCVTPS (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTPU_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtpu_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTPU_float">FCVTPU (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMS_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtms_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTMS_float">FCVTMS (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTMU_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtmu_float.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTMU_float">FCVTMU (scalar)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZS_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtzs_float_int.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="FCVTZS_float_int">FCVTZS (scalar, integer)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVTZU_64H_float2int" arch_version="FEAT_FP16" iformfile="fcvtzu_float_int.xml" label="half-precision to 64-bit" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="FCVTZU_float_int">FCVTZU (scalar, integer)</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="cryptoaes" title="Cryptographic AES">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="cryptoaes" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_cryptoaes" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">x1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_cryptoaes" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">000xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_cryptoaes" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_cryptoaes" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AESE_B_cryptoaes" arch_version="FEAT_AES" iformfile="aese_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00100</td>
|
|
<td class="iformname" iformid="AESE_advsimd">AESE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AESD_B_cryptoaes" arch_version="FEAT_AES" iformfile="aesd_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00101</td>
|
|
<td class="iformname" iformid="AESD_advsimd">AESD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AESMC_B_cryptoaes" arch_version="FEAT_AES" iformfile="aesmc_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00110</td>
|
|
<td class="iformname" iformid="AESMC_advsimd">AESMC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="AESIMC_B_cryptoaes" arch_version="FEAT_AES" iformfile="aesimc_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00111</td>
|
|
<td class="iformname" iformid="AESIMC_advsimd">AESIMC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_cryptoaes" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="crypto4" title="Cryptographic four-register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="Op0" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Ra" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="crypto4" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Op0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="EOR3_VVV16_crypto4" arch_version="FEAT_SHA3" iformfile="eor3_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="EOR3_advsimd">EOR3</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BCAX_VVV16_crypto4" arch_version="FEAT_SHA3" iformfile="bcax_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="BCAX_advsimd">BCAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3SS1_VVV4_crypto4" arch_version="FEAT_SM3" iformfile="sm3ss1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="SM3SS1_advsimd">SM3SS1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_crypto4" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="cryptosha3" title="Cryptographic three-register SHA">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="opcode" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="cryptosha3" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_20_cryptosha3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_cryptosha3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1C_QSV_cryptosha3" arch_version="FEAT_SHA1" iformfile="sha1c_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="SHA1C_advsimd">SHA1C</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1P_QSV_cryptosha3" arch_version="FEAT_SHA1" iformfile="sha1p_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="SHA1P_advsimd">SHA1P</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1M_QSV_cryptosha3" arch_version="FEAT_SHA1" iformfile="sha1m_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="SHA1M_advsimd">SHA1M</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1SU0_VVV_cryptosha3" arch_version="FEAT_SHA1" iformfile="sha1su0_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="SHA1SU0_advsimd">SHA1SU0</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA256H_QQV_cryptosha3" arch_version="FEAT_SHA256" iformfile="sha256h_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="SHA256H_advsimd">SHA256H</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA256H2_QQV_cryptosha3" arch_version="FEAT_SHA256" iformfile="sha256h2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="SHA256H2_advsimd">SHA256H2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA256SU1_VVV_cryptosha3" arch_version="FEAT_SHA256" iformfile="sha256su1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="SHA256SU1_advsimd">SHA256SU1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_cryptosha3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="cryptosha512_3" title="Cryptographic three-register SHA 512">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="O" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opcode" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="cryptosha512_3" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">O</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SHA512H_QQV_cryptosha512_3" arch_version="FEAT_SHA512" iformfile="sha512h_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="SHA512H_advsimd">SHA512H</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA512H2_QQV_cryptosha512_3" arch_version="FEAT_SHA512" iformfile="sha512h2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="SHA512H2_advsimd">SHA512H2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA512SU1_VVV2_cryptosha512_3" arch_version="FEAT_SHA512" iformfile="sha512su1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="SHA512SU1_advsimd">SHA512SU1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="RAX1_VVV2_cryptosha512_3" arch_version="FEAT_SHA3" iformfile="rax1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="RAX1_advsimd">RAX1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3PARTW1_VVV4_cryptosha512_3" arch_version="FEAT_SM3" iformfile="sm3partw1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="SM3PARTW1_advsimd">SM3PARTW1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3PARTW2_VVV4_cryptosha512_3" arch_version="FEAT_SM3" iformfile="sm3partw2_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="SM3PARTW2_advsimd">SM3PARTW2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM4EKEY_VVV4_cryptosha512_3" arch_version="FEAT_SM4" iformfile="sm4ekey_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="SM4EKEY_advsimd">SM4EKEY</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_cryptosha512_3" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="crypto3_imm2" title="Cryptographic three-register, imm2">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="imm2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opcode" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="crypto3_imm2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SM3TT1A_VVV4_crypto3_imm2" arch_version="FEAT_SM3" iformfile="sm3tt1a_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="SM3TT1A_advsimd">SM3TT1A</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3TT1B_VVV4_crypto3_imm2" arch_version="FEAT_SM3" iformfile="sm3tt1b_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="SM3TT1B_advsimd">SM3TT1B</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3TT2A_VVV4_crypto3_imm2" arch_version="FEAT_SM3" iformfile="sm3tt2a_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="SM3TT2A_advsimd">SM3TT2A</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM3TT2B_VVV_crypto3_imm2" arch_version="FEAT_SM3" iformfile="sm3tt2b_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="SM3TT2B_advsimd">SM3TT2B</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="crypto3_imm6" title="Cryptographic three-register, imm6">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="crypto3_imm6" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="XAR_VVV2_crypto3_imm6" arch_version="FEAT_SHA3" iformfile="xar_advsimd.xml" first="t" last="t">
|
|
<td class="iformname" iformid="XAR_advsimd">XAR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="cryptosha2" title="Cryptographic two-register SHA">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" width="5" name="opcode" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="cryptosha2" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xx1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_18_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">x1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1H_SS_cryptosha2" arch_version="FEAT_SHA1" iformfile="sha1h_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="SHA1H_advsimd">SHA1H</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA1SU1_VV_cryptosha2" arch_version="FEAT_SHA1" iformfile="sha1su1_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname" iformid="SHA1SU1_advsimd">SHA1SU1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SHA256SU0_VV_cryptosha2" arch_version="FEAT_SHA256" iformfile="sha256su0_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00010</td>
|
|
<td class="iformname" iformid="SHA256SU0_advsimd">SHA256SU0</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_cryptosha2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="cryptosha512_2" title="Cryptographic two-register SHA 512">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="20" settings="20">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opcode" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="cryptosha512_2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="SHA512SU0_VV2_cryptosha512_2" arch_version="FEAT_SHA512" iformfile="sha512su0_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="SHA512SU0_advsimd">SHA512SU0</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="SM4E_VV4_cryptosha512_2" arch_version="FEAT_SM4" iformfile="sm4e_advsimd.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="SM4E_advsimd">SM4E</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_cryptosha512_2" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatcmp" title="Floating-point compare">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" name="op" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="13" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="opcode2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatcmp" cols="7">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="9*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opcode2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xxxx1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xxx1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xx1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">x1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_S_floatcmp" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_SZ_floatcmp" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Single-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_S_floatcmp" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_SZ_floatcmp" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Single-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_D_floatcmp" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_DZ_floatcmp" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Double-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_D_floatcmp" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_DZ_floatcmp" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Double-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_H_floatcmp" arch_version="FEAT_FP16" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMP_HZ_floatcmp" arch_version="FEAT_FP16" iformfile="fcmp_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01000</td>
|
|
<td class="iformname" iformid="FCMP_float">FCMP</td>
|
|
<td class="enctags">Half-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_H_floatcmp" arch_version="FEAT_FP16" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">10000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCMPE_HZ_floatcmp" arch_version="FEAT_FP16" iformfile="fcmpe_float.xml" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">11000</td>
|
|
<td class="iformname" iformid="FCMPE_float">FCMPE</td>
|
|
<td class="enctags">Half-precision, zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatcmp" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatccmp" title="Floating-point conditional compare">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="nzcv" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatccmp" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatccmp" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatccmp" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMP_S_floatccmp" iformfile="fccmp_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FCCMP_float">FCCMP</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMPE_S_floatccmp" iformfile="fccmpe_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FCCMPE_float">FCCMPE</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMP_D_floatccmp" iformfile="fccmp_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FCCMP_float">FCCMP</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMPE_D_floatccmp" iformfile="fccmpe_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FCCMPE_float">FCCMPE</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMP_H_floatccmp" arch_version="FEAT_FP16" iformfile="fccmp_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FCCMP_float">FCCMP</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCCMPE_H_floatccmp" arch_version="FEAT_FP16" iformfile="fccmpe_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FCCMPE_float">FCCMPE</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatccmp" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatsel" title="Floating-point conditional select">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="cond" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatsel" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatsel" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatsel" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCSEL_S_floatsel" iformfile="fcsel_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="FCSEL_float">FCSEL</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCSEL_D_floatsel" iformfile="fcsel_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="FCSEL_float">FCSEL</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCSEL_H_floatsel" arch_version="FEAT_FP16" iformfile="fcsel_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="FCSEL_float">FCSEL</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatsel" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatdp1" title="Floating-point data-processing (1 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="6" name="opcode" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="14" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatdp1" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="19*" />
|
|
<col colno="6" printwidth="38*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield">1xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_S_floatdp1" iformfile="fmov_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname" iformid="FMOV_float">FMOV (register)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABS_S_floatdp1" iformfile="fabs_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td class="iformname" iformid="FABS_float">FABS (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNEG_S_floatdp1" iformfile="fneg_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td class="iformname" iformid="FNEG_float">FNEG (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSQRT_S_floatdp1" iformfile="fsqrt_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td class="iformname" iformid="FSQRT_float">FSQRT (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_DS_floatdp1" iformfile="fcvt_float.xml" label="single-precision to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Single-precision to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_19_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_HS_floatdp1" iformfile="fcvt_float.xml" label="single-precision to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">000111</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Single-precision to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTN_S_floatdp1" iformfile="frintn_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td class="iformname" iformid="FRINTN_float">FRINTN (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTP_S_floatdp1" iformfile="frintp_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td class="iformname" iformid="FRINTP_float">FRINTP (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTM_S_floatdp1" iformfile="frintm_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td class="iformname" iformid="FRINTM_float">FRINTM (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTZ_S_floatdp1" iformfile="frintz_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td class="iformname" iformid="FRINTZ_float">FRINTZ (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTA_S_floatdp1" iformfile="frinta_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td class="iformname" iformid="FRINTA_float">FRINTA (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_26_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTX_S_floatdp1" iformfile="frintx_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001110</td>
|
|
<td class="iformname" iformid="FRINTX_float">FRINTX (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTI_S_floatdp1" iformfile="frinti_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">001111</td>
|
|
<td class="iformname" iformid="FRINTI_float">FRINTI (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32Z_S_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint32z_float.xml" label="single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">010000</td>
|
|
<td class="iformname" iformid="FRINT32Z_float">FRINT32Z (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32X_S_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint32x_float.xml" label="single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">010001</td>
|
|
<td class="iformname" iformid="FRINT32X_float">FRINT32X (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64Z_S_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint64z_float.xml" label="single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">010010</td>
|
|
<td class="iformname" iformid="FRINT64Z_float">FRINT64Z (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64X_S_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint64x_float.xml" label="single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">010011</td>
|
|
<td class="iformname" iformid="FRINT64X_float">FRINT64X (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_33_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">0101xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_34_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="6" class="bitfield">011xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_D_floatdp1" iformfile="fmov_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname" iformid="FMOV_float">FMOV (register)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABS_D_floatdp1" iformfile="fabs_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td class="iformname" iformid="FABS_float">FABS (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNEG_D_floatdp1" iformfile="fneg_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td class="iformname" iformid="FNEG_float">FNEG (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSQRT_D_floatdp1" iformfile="fsqrt_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td class="iformname" iformid="FSQRT_float">FSQRT (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_SD_floatdp1" iformfile="fcvt_float.xml" label="double-precision to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Double-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_40_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="BFCVT_BS_floatdp1" arch_version="FEAT_BF16" iformfile="bfcvt_float.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000110</td>
|
|
<td class="iformname" iformid="BFCVT_float">BFCVT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_HD_floatdp1" iformfile="fcvt_float.xml" label="double-precision to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">000111</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Double-precision to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTN_D_floatdp1" iformfile="frintn_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td class="iformname" iformid="FRINTN_float">FRINTN (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTP_D_floatdp1" iformfile="frintp_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td class="iformname" iformid="FRINTP_float">FRINTP (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTM_D_floatdp1" iformfile="frintm_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td class="iformname" iformid="FRINTM_float">FRINTM (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTZ_D_floatdp1" iformfile="frintz_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td class="iformname" iformid="FRINTZ_float">FRINTZ (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTA_D_floatdp1" iformfile="frinta_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td class="iformname" iformid="FRINTA_float">FRINTA (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_48_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTX_D_floatdp1" iformfile="frintx_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001110</td>
|
|
<td class="iformname" iformid="FRINTX_float">FRINTX (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTI_D_floatdp1" iformfile="frinti_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">001111</td>
|
|
<td class="iformname" iformid="FRINTI_float">FRINTI (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32Z_D_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint32z_float.xml" label="double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">010000</td>
|
|
<td class="iformname" iformid="FRINT32Z_float">FRINT32Z (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT32X_D_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint32x_float.xml" label="double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">010001</td>
|
|
<td class="iformname" iformid="FRINT32X_float">FRINT32X (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64Z_D_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint64z_float.xml" label="double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">010010</td>
|
|
<td class="iformname" iformid="FRINT64Z_float">FRINT64Z (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINT64X_D_floatdp1" arch_version="FEAT_FRINTTS" iformfile="frint64x_float.xml" label="double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">010011</td>
|
|
<td class="iformname" iformid="FRINT64X_float">FRINT64X (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_55_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">0101xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_56_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="6" class="bitfield">011xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_57_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="6" class="bitfield">0xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_H_floatdp1" arch_version="FEAT_FP16" iformfile="fmov_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000000</td>
|
|
<td class="iformname" iformid="FMOV_float">FMOV (register)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FABS_H_floatdp1" arch_version="FEAT_FP16" iformfile="fabs_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000001</td>
|
|
<td class="iformname" iformid="FABS_float">FABS (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNEG_H_floatdp1" arch_version="FEAT_FP16" iformfile="fneg_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000010</td>
|
|
<td class="iformname" iformid="FNEG_float">FNEG (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSQRT_H_floatdp1" arch_version="FEAT_FP16" iformfile="fsqrt_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000011</td>
|
|
<td class="iformname" iformid="FSQRT_float">FSQRT (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_SH_floatdp1" iformfile="fcvt_float.xml" label="half-precision to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000100</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Half-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FCVT_DH_floatdp1" iformfile="fcvt_float.xml" label="half-precision to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">000101</td>
|
|
<td class="iformname" iformid="FCVT_float">FCVT</td>
|
|
<td class="enctags">Half-precision to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_64_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">00011x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTN_H_floatdp1" arch_version="FEAT_FP16" iformfile="frintn_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001000</td>
|
|
<td class="iformname" iformid="FRINTN_float">FRINTN (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTP_H_floatdp1" arch_version="FEAT_FP16" iformfile="frintp_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001001</td>
|
|
<td class="iformname" iformid="FRINTP_float">FRINTP (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTM_H_floatdp1" arch_version="FEAT_FP16" iformfile="frintm_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001010</td>
|
|
<td class="iformname" iformid="FRINTM_float">FRINTM (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTZ_H_floatdp1" arch_version="FEAT_FP16" iformfile="frintz_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001011</td>
|
|
<td class="iformname" iformid="FRINTZ_float">FRINTZ (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTA_H_floatdp1" arch_version="FEAT_FP16" iformfile="frinta_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001100</td>
|
|
<td class="iformname" iformid="FRINTA_float">FRINTA (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_70_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTX_H_floatdp1" arch_version="FEAT_FP16" iformfile="frintx_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001110</td>
|
|
<td class="iformname" iformid="FRINTX_float">FRINTX (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FRINTI_H_floatdp1" arch_version="FEAT_FP16" iformfile="frinti_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">001111</td>
|
|
<td class="iformname" iformid="FRINTI_float">FRINTI (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_73_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="6" class="bitfield">01xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatdp1" undef="1" oneofthismnem="16" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="6" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatdp2" title="Floating-point data-processing (2 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="opcode" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatdp2" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="8*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">opcode</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1xx1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1x1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">11xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_S_floatdp2" iformfile="fmul_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="FMUL_float">FMUL (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FDIV_S_floatdp2" iformfile="fdiv_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FDIV_float">FDIV (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADD_S_floatdp2" iformfile="fadd_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="FADD_float">FADD (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSUB_S_floatdp2" iformfile="fsub_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="FSUB_float">FSUB (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAX_S_floatdp2" iformfile="fmax_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="FMAX_float">FMAX (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMIN_S_floatdp2" iformfile="fmin_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMIN_float">FMIN (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNM_S_floatdp2" iformfile="fmaxnm_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="FMAXNM_float">FMAXNM (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNM_S_floatdp2" iformfile="fminnm_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="FMINNM_float">FMINNM (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMUL_S_floatdp2" iformfile="fnmul_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="FNMUL_float">FNMUL (scalar)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_D_floatdp2" iformfile="fmul_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="FMUL_float">FMUL (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FDIV_D_floatdp2" iformfile="fdiv_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FDIV_float">FDIV (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADD_D_floatdp2" iformfile="fadd_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="FADD_float">FADD (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSUB_D_floatdp2" iformfile="fsub_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="FSUB_float">FSUB (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAX_D_floatdp2" iformfile="fmax_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="FMAX_float">FMAX (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMIN_D_floatdp2" iformfile="fmin_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMIN_float">FMIN (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNM_D_floatdp2" iformfile="fmaxnm_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="FMAXNM_float">FMAXNM (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNM_D_floatdp2" iformfile="fminnm_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="FMINNM_float">FMINNM (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMUL_D_floatdp2" iformfile="fnmul_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="FNMUL_float">FNMUL (scalar)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMUL_H_floatdp2" arch_version="FEAT_FP16" iformfile="fmul_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="FMUL_float">FMUL (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FDIV_H_floatdp2" arch_version="FEAT_FP16" iformfile="fdiv_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="FDIV_float">FDIV (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FADD_H_floatdp2" arch_version="FEAT_FP16" iformfile="fadd_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="FADD_float">FADD (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FSUB_H_floatdp2" arch_version="FEAT_FP16" iformfile="fsub_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="FSUB_float">FSUB (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAX_H_floatdp2" arch_version="FEAT_FP16" iformfile="fmax_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="FMAX_float">FMAX (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMIN_H_floatdp2" arch_version="FEAT_FP16" iformfile="fmin_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="FMIN_float">FMIN (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMAXNM_H_floatdp2" arch_version="FEAT_FP16" iformfile="fmaxnm_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="FMAXNM_float">FMAXNM (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMINNM_H_floatdp2" arch_version="FEAT_FP16" iformfile="fminnm_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="FMINNM_float">FMINNM (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMUL_H_floatdp2" arch_version="FEAT_FP16" iformfile="fnmul_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="FNMUL_float">FNMUL (scalar)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatdp2" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatdp3" title="Floating-point data-processing (3 source)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="o0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="5" name="Ra" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatdp3" cols="7">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="4*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">o1</th>
|
|
<th class="bitfields">o0</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatdp3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatdp3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMADD_S_floatdp3" iformfile="fmadd_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FMADD_float">FMADD</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMSUB_S_floatdp3" iformfile="fmsub_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FMSUB_float">FMSUB</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMADD_S_floatdp3" iformfile="fnmadd_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FNMADD_float">FNMADD</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMSUB_S_floatdp3" iformfile="fnmsub_float.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FNMSUB_float">FNMSUB</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMADD_D_floatdp3" iformfile="fmadd_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FMADD_float">FMADD</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMSUB_D_floatdp3" iformfile="fmsub_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FMSUB_float">FMSUB</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMADD_D_floatdp3" iformfile="fnmadd_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FNMADD_float">FNMADD</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMSUB_D_floatdp3" iformfile="fnmsub_float.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FNMSUB_float">FNMSUB</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMADD_H_floatdp3" arch_version="FEAT_FP16" iformfile="fmadd_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FMADD_float">FMADD</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMSUB_H_floatdp3" arch_version="FEAT_FP16" iformfile="fmsub_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FMSUB_float">FMSUB</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMADD_H_floatdp3" arch_version="FEAT_FP16" iformfile="fnmadd_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="FNMADD_float">FNMADD</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FNMSUB_H_floatdp3" arch_version="FEAT_FP16" iformfile="fnmsub_float.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="FNMSUB_float">FNMSUB</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatdp3" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="floatimm" title="Floating-point immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="30" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="28" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="ptype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="floatimm" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="7*" />
|
|
<col colno="4" printwidth="7*" />
|
|
<col colno="5" printwidth="26*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">ptype</th>
|
|
<th class="bitfields">imm5</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_10_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xxxx1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_11_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xxx1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_12_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">xx1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_13_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">x1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_14_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_17_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_15_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_S_floatimm" iformfile="fmov_float_imm.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FMOV_float_imm">FMOV (scalar, immediate)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_D_floatimm" iformfile="fmov_float_imm.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FMOV_float_imm">FMOV (scalar, immediate)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="FMOV_H_floatimm" arch_version="FEAT_FP16" iformfile="fmov_float_imm.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="FMOV_float_imm">FMOV (scalar, immediate)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_16_floatimm" undef="1" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="perm_undef">UDF</funcgroupheader>
|
|
<iclass_sect id="perm_undef" title="Reserved">
|
|
<regdiagram form="32" psname="aarch64/instrs/udf">
|
|
<box hibit="31" width="16" settings="16">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" width="16" name="imm16" usename="1">
|
|
<c colspan="16"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="perm_undef" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UDF_only_perm_undef" iformfile="udf_perm_undef.xml" first="t" last="t">
|
|
<td class="iformname" iformid="UDF_perm_undef">UDF</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_pred_bin">SVE Integer Binary Arithmetic - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_pred_log" title="SVE bitwise logical operations (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_log" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="orr_z_p_zz_" iformfile="orr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="orr_z_p_zz">ORR (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eor_z_p_zz_" iformfile="eor_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="eor_z_p_zz">EOR (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="and_z_p_zz_" iformfile="and_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="and_z_p_zz">AND (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bic_z_p_zz_" iformfile="bic_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="bic_z_p_zz">BIC (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_310" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_arit_0" title="SVE integer add/subtract vectors (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_arit_0" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_z_p_zz_" iformfile="add_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="add_z_p_zz">ADD (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_z_p_zz_" iformfile="sub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="sub_z_p_zz">SUB (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_294" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="subr_z_p_zz_" iformfile="subr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="subr_z_p_zz">SUBR (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_297" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_div" title="SVE integer divide vectors (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_div" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdiv_z_p_zz_" iformfile="sdiv_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdiv_z_p_zz">SDIV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udiv_z_p_zz_" iformfile="udiv_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udiv_z_p_zz">UDIV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdivr_z_p_zz_" iformfile="sdivr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdivr_z_p_zz">SDIVR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udivr_z_p_zz_" iformfile="udivr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udivr_z_p_zz">UDIVR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_arit_1" title="SVE integer min/max/difference (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_arit_1" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smax_z_p_zz_" iformfile="smax_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_z_p_zz">SMAX (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_z_p_zz_" iformfile="umax_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umax_z_p_zz">UMAX (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_z_p_zz_" iformfile="smin_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_z_p_zz">SMIN (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_z_p_zz_" iformfile="umin_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umin_z_p_zz">UMIN (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sabd_z_p_zz_" iformfile="sabd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sabd_z_p_zz">SABD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uabd_z_p_zz_" iformfile="uabd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uabd_z_p_zz">UABD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_302" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_arit_2" title="SVE integer multiply vectors (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_arit_2" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">H</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mul_z_p_zz_" iformfile="mul_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mul_z_p_zz">MUL (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_304" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smulh_z_p_zz_" iformfile="smulh_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smulh_z_p_zz">SMULH (predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umulh_z_p_zz_" iformfile="umulh_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umulh_z_p_zz">UMULH (predicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_pred_red">SVE Integer Reduction</funcgroupheader>
|
|
<iclass_sect id="sve_int_reduce_2" title="SVE bitwise logical reduction (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="orv_r_p_z_" iformfile="orv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="orv_r_p_z">ORV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eorv_r_p_z_" iformfile="eorv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="eorv_r_p_z">EORV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="andv_r_p_z_" iformfile="andv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="andv_r_p_z">ANDV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_309" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_reduce_2q" title="SVE bitwise logical reduction (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_2q" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="orqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="orqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="orqv_z_p_z">ORQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eorqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="eorqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="eorqv_z_p_z">EORQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="andqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="andqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="andqv_z_p_z">ANDQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_312" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_movprfx_pred" title="SVE constructive prefix (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_movprfx_pred" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="movprfx_z_p_z_" iformfile="movprfx_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="movprfx_z_p_z">MOVPRFX (predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_305" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_307" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_reduce_0" title="SVE integer add reduction (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_0" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="saddv_r_p_z_" iformfile="saddv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="saddv_r_p_z">SADDV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaddv_r_p_z_" iformfile="uaddv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uaddv_r_p_z">UADDV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_295" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_reduce_0q" title="SVE integer add reduction (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_0q" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_298" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="addqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="addqv_z_p_z">ADDQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_300" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_reduce_1" title="SVE integer min/max reduction (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_1" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smaxv_r_p_z_" iformfile="smaxv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smaxv_r_p_z">SMAXV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umaxv_r_p_z_" iformfile="umaxv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umaxv_r_p_z">UMAXV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sminv_r_p_z_" iformfile="sminv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sminv_r_p_z">SMINV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uminv_r_p_z_" iformfile="uminv_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uminv_r_p_z">UMINV</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_reduce_1q" title="SVE integer min/max reduction (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_reduce_1q" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smaxqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="smaxqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smaxqv_z_p_z">SMAXQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umaxqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="umaxqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umaxqv_z_p_z">UMAXQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sminqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="sminqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sminqv_z_p_z">SMINQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uminqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="uminqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uminqv_z_p_z">UMINQV</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_pred_shift">SVE Bitwise Shift - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_pred_shift_0" title="SVE bitwise shift by immediate (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tszh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="17" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_shift_0" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="29*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="asr_z_p_zi_" iformfile="asr_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="asr_z_p_zi">ASR (immediate, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsr_z_p_zi_" iformfile="lsr_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsr_z_p_zi">LSR (immediate, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_296" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsl_z_p_zi_" iformfile="lsl_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsl_z_p_zi">LSL (immediate, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="asrd_z_p_zi_" iformfile="asrd_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="asrd_z_p_zi">ASRD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_299" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshl_z_p_zi_" iformfile="sqshl_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqshl_z_p_zi">SQSHL (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqshl_z_p_zi_" iformfile="uqshl_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqshl_z_p_zi">UQSHL (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_301" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshr_z_p_zi_" iformfile="srshr_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshr_z_p_zi">SRSHR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshr_z_p_zi_" iformfile="urshr_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshr_z_p_zi">URSHR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_303" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshlu_z_p_zi_" iformfile="sqshlu_z_p_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqshlu_z_p_zi">SQSHLU</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_shift_1" title="SVE bitwise shift by vector (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_shift_1" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_306" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="asr_z_p_zz_" iformfile="asr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="asr_z_p_zz">ASR (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsr_z_p_zz_" iformfile="lsr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsr_z_p_zz">LSR (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsl_z_p_zz_" iformfile="lsl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsl_z_p_zz">LSL (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="asrr_z_p_zz_" iformfile="asrr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="asrr_z_p_zz">ASRR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsrr_z_p_zz_" iformfile="lsrr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsrr_z_p_zz">LSRR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lslr_z_p_zz_" iformfile="lslr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lslr_z_p_zz">LSLR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_pred_shift_2" title="SVE bitwise shift by wide elements (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_pred_shift_2" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="33*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">L</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="asr_z_p_zw_" iformfile="asr_z_p_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="asr_z_p_zw">ASR (wide elements, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsr_z_p_zw_" iformfile="lsr_z_p_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsr_z_p_zw">LSR (wide elements, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_308" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsl_z_p_zw_" iformfile="lsl_z_p_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lsl_z_p_zw">LSL (wide elements, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_311" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_pred_un">SVE Integer Unary Arithmetic - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_un_pred_arit_1" title="SVE bitwise unary operations (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_un_pred_arit_1" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cls_z_p_z_" iformfile="cls_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="cls_z_p_z">CLS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="clz_z_p_z_" iformfile="clz_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="clz_z_p_z">CLZ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cnt_z_p_z_" iformfile="cnt_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="cnt_z_p_z">CNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cnot_z_p_z_" iformfile="cnot_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="cnot_z_p_z">CNOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fabs_z_p_z_" iformfile="fabs_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="fabs_z_p_z">FABS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fneg_z_p_z_" iformfile="fneg_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="fneg_z_p_z">FNEG</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="not_z_p_z_" iformfile="not_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="not_z_p_z">NOT (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_313" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_un_pred_arit_0" title="SVE integer unary operations (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_un_pred_arit_0" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sxtb_z_p_z_" iformfile="sxtb_z_p_z.xml" label="SXTB" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="sxtb_z_p_z">SXTB, SXTH, SXTW</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uxtb_z_p_z_" iformfile="uxtb_z_p_z.xml" label="UXTB" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="uxtb_z_p_z">UXTB, UXTH, UXTW</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sxth_z_p_z_" iformfile="sxtb_z_p_z.xml" label="SXTH" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="sxtb_z_p_z">SXTB, SXTH, SXTW</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uxth_z_p_z_" iformfile="uxtb_z_p_z.xml" label="UXTH" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="uxtb_z_p_z">UXTB, UXTH, UXTW</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sxtw_z_p_z_" iformfile="sxtb_z_p_z.xml" label="SXTW" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="sxtb_z_p_z">SXTB, SXTH, SXTW</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uxtw_z_p_z_" iformfile="uxtb_z_p_z.xml" label="UXTW" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="uxtb_z_p_z">UXTB, UXTH, UXTW</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="abs_z_p_z_" iformfile="abs_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="abs_z_p_z">ABS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="neg_z_p_z_" iformfile="neg_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="neg_z_p_z">NEG</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_muladd_pred">SVE Integer Multiply-Add - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_mlas_vvv_pred" title="SVE integer multiply-accumulate writing addend (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_mlas_vvv_pred" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mla_z_p_zzz_" iformfile="mla_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mla_z_p_zzz">MLA (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mls_z_p_zzz_" iformfile="mls_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mls_z_p_zzz">MLS (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_mladdsub_vvv_pred" title="SVE integer multiply-add writing multiplicand (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Za" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_mladdsub_vvv_pred" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mad_z_p_zzz_" iformfile="mad_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mad_z_p_zzz">MAD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="msb_z_p_zzz_" iformfile="msb_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="msb_z_p_zzz">MSB</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_unpred_arit">SVE Integer Arithmetic - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_cons_arit_0" title="SVE integer add/subtract vectors (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_arit_0" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="31*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_z_zz_" iformfile="add_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="add_z_zz">ADD (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_z_zz_" iformfile="sub_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="sub_z_zz">SUB (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_314" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqadd_z_zz_" iformfile="sqadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="sqadd_z_zz">SQADD (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqadd_z_zz_" iformfile="uqadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="uqadd_z_zz">UQADD (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqsub_z_zz_" iformfile="sqsub_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="sqsub_z_zz">SQSUB (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqsub_z_zz_" iformfile="uqsub_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="uqsub_z_zz">UQSUB (vectors, unpredicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_unpred_logical">SVE Bitwise Logical - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_cons_log" title="SVE bitwise logical operations (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_log" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="29*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="and_z_zz_" iformfile="and_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="and_z_zz">AND (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="orr_z_zz_" iformfile="orr_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="orr_z_zz">ORR (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eor_z_zz_" iformfile="eor_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="eor_z_zz">EOR (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bic_z_zz_" iformfile="bic_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="bic_z_zz">BIC (vectors, unpredicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_tern_log" title="SVE2 bitwise ternary operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zk" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_tern_log" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="eor3_z_zzz_" iformfile="eor3_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="eor3_z_zzz">EOR3</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bsl_z_zzz_" iformfile="bsl_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bsl_z_zzz">BSL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bcax_z_zzz_" iformfile="bcax_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bcax_z_zzz">BCAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bsl1n_z_zzz_" iformfile="bsl1n_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bsl1n_z_zzz">BSL1N</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_333" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bsl2n_z_zzz_" iformfile="bsl2n_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bsl2n_z_zzz">BSL2N</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nbsl_z_zzz_" iformfile="nbsl_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="nbsl_z_zzz">NBSL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_rotate_imm" title="sve_int_rotate_imm">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tszh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_rotate_imm" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="xar_z_zzi_" iformfile="xar_z_zzi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="xar_z_zzi">XAR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_index">SVE Index Generation</funcgroupheader>
|
|
<iclass_sect id="sve_int_index_ii" title="SVE index generation (immediate start, immediate increment)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5b" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_index_ii" cols="2">
|
|
<col colno="1" printwidth="20*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="index_z_ii_" iformfile="index_z_ii.xml" first="t" last="t">
|
|
<td class="iformname" iformid="index_z_ii">INDEX (immediates)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_index_ir" title="SVE index generation (immediate start, register increment)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_index_ir" cols="2">
|
|
<col colno="1" printwidth="27*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="index_z_ir_" iformfile="index_z_ir.xml" first="t" last="t">
|
|
<td class="iformname" iformid="index_z_ir">INDEX (immediate, scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_index_ri" title="SVE index generation (register start, immediate increment)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_index_ri" cols="2">
|
|
<col colno="1" printwidth="27*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="index_z_ri_" iformfile="index_z_ri.xml" first="t" last="t">
|
|
<td class="iformname" iformid="index_z_ri">INDEX (scalar, immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_index_rr" title="SVE index generation (register start, register increment)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_index_rr" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="index_z_rr_" iformfile="index_z_rr.xml" first="t" last="t">
|
|
<td class="iformname" iformid="index_z_rr">INDEX (scalars)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_alloca">SVE Stack Allocation</funcgroupheader>
|
|
<iclass_sect id="sve_int_arith_vl" title="SVE stack frame adjustment">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_arith_vl" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="addvl_r_ri_" iformfile="addvl_r_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="addvl_r_ri">ADDVL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addpl_r_ri_" iformfile="addpl_r_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="addpl_r_ri">ADDPL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_read_vl_a" title="SVE stack frame size">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_read_vl_a" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="7*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_334" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">0xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_338" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_340" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_342" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">1110x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_344" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rdvl_r_i_" iformfile="rdvl_r_i.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="rdvl_r_i">RDVL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_346" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_arith_svl" title="Streaming SVE stack frame adjustment">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_arith_svl" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="addsvl_r_ri_" arch_version="FEAT_SME" iformfile="addsvl_r_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="addsvl_r_ri">ADDSVL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addspl_r_ri_" arch_version="FEAT_SME" iformfile="addspl_r_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="addspl_r_ri">ADDSPL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_read_svl_a" title="Streaming SVE stack frame size">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_read_svl_a" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="7*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_335" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">0xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_339" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">10xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_341" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_343" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">1110x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_345" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rdsvl_r_i_" arch_version="FEAT_SME" iformfile="rdsvl_r_i.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="5" class="bitfield">11111</td>
|
|
<td class="iformname" iformid="rdsvl_r_i">RDSVL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_347" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_unpred_arit_b">SVE2 Integer Multiply - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_mul_b" title="SVE2 integer multiply vectors (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_mul_b" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mul_z_zz_" iformfile="mul_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="mul_z_zz">MUL (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smulh_z_zz_" iformfile="smulh_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="smulh_z_zz">SMULH (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umulh_z_zz_" iformfile="umulh_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="umulh_z_zz">UMULH (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmul_z_zz_" iformfile="pmul_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="pmul_z_zz">PMUL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_331" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_336" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_sqdmulh" title="SVE2 signed saturating doubling multiply high (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_sqdmulh" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="20*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_z_zz_" iformfile="sqdmulh_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmulh_z_zz">SQDMULH (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmulh_z_zz_" iformfile="sqrdmulh_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmulh_z_zz">SQRDMULH (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_unpred_shift">SVE Bitwise Shift - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_cons_shift_b" title="SVE bitwise shift by immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tszh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_shift_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="31*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="asr_z_zi_" iformfile="asr_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="asr_z_zi">ASR (immediate, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsr_z_zi_" iformfile="lsr_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="lsr_z_zi">LSR (immediate, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_316" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsl_z_zi_" iformfile="lsl_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="lsl_z_zi">LSL (immediate, unpredicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_cons_shift_a" title="SVE bitwise shift by wide elements (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_shift_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="35*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="asr_z_zw_" iformfile="asr_z_zw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="asr_z_zw">ASR (wide elements, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsr_z_zw_" iformfile="lsr_z_zw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="lsr_z_zw">LSR (wide elements, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_315" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lsl_z_zw_" iformfile="lsl_z_zw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="lsl_z_zw">LSL (wide elements, unpredicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_adr">SVE Address Generation</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_cons_misc_0_a" title="SVE address generation">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_misc_0_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="34*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="adr_z_az_d_s32_scaled" iformfile="adr_z_az.xml" label="Unpacked 32-bit signed offsets" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="adr_z_az">ADR</td>
|
|
<td class="enctags">Unpacked 32-bit signed offsets</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="adr_z_az_d_u32_scaled" iformfile="adr_z_az.xml" label="Unpacked 32-bit unsigned offsets" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="adr_z_az">ADR</td>
|
|
<td class="enctags">Unpacked 32-bit unsigned offsets</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="adr_z_az_sd_same_scaled" iformfile="adr_z_az.xml" label="Packed offsets" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname" iformid="adr_z_az">ADR</td>
|
|
<td class="enctags">Packed offsets</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_unpred_misc">SVE Integer Misc - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_bin_cons_misc_0_d" title="SVE constructive prefix (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc2" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_misc_0_d" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="7*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="movprfx_z_z_" iformfile="movprfx_z_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="movprfx_z_z">MOVPRFX (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_321" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_323" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">0001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_325" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">001xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_327" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">01xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_329" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_332" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_337" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="5" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_cons_misc_0_c" title="SVE floating-point exponential accelerator">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_misc_0_c" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fexpa_z_z_" iformfile="fexpa_z_z.xml" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">00000</td>
|
|
<td class="iformname" iformid="fexpa_z_z">FEXPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_320" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">00001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_322" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">0001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_324" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">001xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_326" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">01xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_328" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_bin_cons_misc_0_b" title="SVE floating-point trig select coefficient">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_bin_cons_misc_0_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ftssel_z_zz_" iformfile="ftssel_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ftssel_z_zz">FTSSEL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_317" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_countelt">SVE Element Count</funcgroupheader>
|
|
<iclass_sect id="sve_int_count" title="SVE element count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_count" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_319" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cntb_r_s_" iformfile="cntb_r_s.xml" label="CNTB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cntb_r_s">CNTB, CNTD, CNTH, CNTW</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cnth_r_s_" iformfile="cntb_r_s.xml" label="CNTH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cntb_r_s">CNTB, CNTD, CNTH, CNTW</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cntw_r_s_" iformfile="cntb_r_s.xml" label="CNTW" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cntb_r_s">CNTB, CNTD, CNTH, CNTW</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cntd_r_s_" iformfile="cntb_r_s.xml" label="CNTD" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cntb_r_s">CNTB, CNTD, CNTH, CNTW</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pred_pattern_a" title="SVE inc/dec register by element count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pred_pattern_a" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="33*" />
|
|
<col colno="4" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">D</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="incb_r_rs_" iformfile="incb_r_rs.xml" label="INCB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incb_r_rs">INCB, INCD, INCH, INCW (scalar)</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decb_r_rs_" iformfile="decb_r_rs.xml" label="DECB" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decb_r_rs">DECB, DECD, DECH, DECW (scalar)</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="inch_r_rs_" iformfile="incb_r_rs.xml" label="INCH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incb_r_rs">INCB, INCD, INCH, INCW (scalar)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="dech_r_rs_" iformfile="decb_r_rs.xml" label="DECH" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decb_r_rs">DECB, DECD, DECH, DECW (scalar)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incw_r_rs_" iformfile="incb_r_rs.xml" label="INCW" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incb_r_rs">INCB, INCD, INCH, INCW (scalar)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decw_r_rs_" iformfile="decb_r_rs.xml" label="DECW" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decb_r_rs">DECB, DECD, DECH, DECW (scalar)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incd_r_rs_" iformfile="incb_r_rs.xml" label="INCD" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incb_r_rs">INCB, INCD, INCH, INCW (scalar)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decd_r_rs_" iformfile="decb_r_rs.xml" label="DECD" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decb_r_rs">DECB, DECD, DECH, DECW (scalar)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_countvlv1" title="SVE inc/dec vector by element count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_countvlv1" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">D</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_330" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="inch_z_zs_" iformfile="incd_z_zs.xml" label="INCH" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incd_z_zs">INCD, INCH, INCW (vector)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="dech_z_zs_" iformfile="decd_z_zs.xml" label="DECH" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decd_z_zs">DECD, DECH, DECW (vector)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incw_z_zs_" iformfile="incd_z_zs.xml" label="INCW" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incd_z_zs">INCD, INCH, INCW (vector)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decw_z_zs_" iformfile="decd_z_zs.xml" label="DECW" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decd_z_zs">DECD, DECH, DECW (vector)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incd_z_zs_" iformfile="incd_z_zs.xml" label="INCD" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="incd_z_zs">INCD, INCH, INCW (vector)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decd_z_zs_" iformfile="decd_z_zs.xml" label="DECD" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="decd_z_zs">DECD, DECH, DECW (vector)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pred_pattern_b" title="SVE saturating inc/dec register by element count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pred_pattern_b" cols="6">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqincb_r_rs_sx" iformfile="sqincb_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincb_r_rs">SQINCB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincb_r_rs_uw" iformfile="uqincb_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincb_r_rs">UQINCB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecb_r_rs_sx" iformfile="sqdecb_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecb_r_rs">SQDECB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecb_r_rs_uw" iformfile="uqdecb_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecb_r_rs">UQDECB</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincb_r_rs_x" iformfile="sqincb_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincb_r_rs">SQINCB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincb_r_rs_x" iformfile="uqincb_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincb_r_rs">UQINCB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecb_r_rs_x" iformfile="sqdecb_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecb_r_rs">SQDECB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecb_r_rs_x" iformfile="uqdecb_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecb_r_rs">UQDECB</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqinch_r_rs_sx" iformfile="sqinch_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqinch_r_rs">SQINCH (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqinch_r_rs_uw" iformfile="uqinch_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqinch_r_rs">UQINCH (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdech_r_rs_sx" iformfile="sqdech_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdech_r_rs">SQDECH (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdech_r_rs_uw" iformfile="uqdech_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdech_r_rs">UQDECH (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqinch_r_rs_x" iformfile="sqinch_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqinch_r_rs">SQINCH (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqinch_r_rs_x" iformfile="uqinch_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqinch_r_rs">UQINCH (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdech_r_rs_x" iformfile="sqdech_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdech_r_rs">SQDECH (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdech_r_rs_x" iformfile="uqdech_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdech_r_rs">UQDECH (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincw_r_rs_sx" iformfile="sqincw_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincw_r_rs">SQINCW (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincw_r_rs_uw" iformfile="uqincw_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincw_r_rs">UQINCW (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecw_r_rs_sx" iformfile="sqdecw_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecw_r_rs">SQDECW (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecw_r_rs_uw" iformfile="uqdecw_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecw_r_rs">UQDECW (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincw_r_rs_x" iformfile="sqincw_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincw_r_rs">SQINCW (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincw_r_rs_x" iformfile="uqincw_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincw_r_rs">UQINCW (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecw_r_rs_x" iformfile="sqdecw_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecw_r_rs">SQDECW (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecw_r_rs_x" iformfile="uqdecw_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecw_r_rs">UQDECW (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincd_r_rs_sx" iformfile="sqincd_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincd_r_rs">SQINCD (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincd_r_rs_uw" iformfile="uqincd_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincd_r_rs">UQINCD (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecd_r_rs_sx" iformfile="sqdecd_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecd_r_rs">SQDECD (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecd_r_rs_uw" iformfile="uqdecd_r_rs.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecd_r_rs">UQDECD (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincd_r_rs_x" iformfile="sqincd_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincd_r_rs">SQINCD (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincd_r_rs_x" iformfile="uqincd_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincd_r_rs">UQINCD (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecd_r_rs_x" iformfile="sqdecd_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecd_r_rs">SQDECD (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecd_r_rs_x" iformfile="uqdecd_r_rs.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecd_r_rs">UQDECD (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_countvlv0" title="SVE saturating inc/dec vector by element count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_countvlv0" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_318" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqinch_z_zs_" iformfile="sqinch_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqinch_z_zs">SQINCH (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqinch_z_zs_" iformfile="uqinch_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqinch_z_zs">UQINCH (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdech_z_zs_" iformfile="sqdech_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdech_z_zs">SQDECH (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdech_z_zs_" iformfile="uqdech_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdech_z_zs">UQDECH (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincw_z_zs_" iformfile="sqincw_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincw_z_zs">SQINCW (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincw_z_zs_" iformfile="uqincw_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincw_z_zs">UQINCW (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecw_z_zs_" iformfile="sqdecw_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecw_z_zs">SQDECW (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecw_z_zs_" iformfile="uqdecw_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecw_z_zs">UQDECW (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincd_z_zs_" iformfile="sqincd_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincd_z_zs">SQINCD (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincd_z_zs_" iformfile="uqincd_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqincd_z_zs">UQINCD (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecd_z_zs_" iformfile="sqdecd_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecd_z_zs">SQDECD (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecd_z_zs_" iformfile="uqdecd_z_zs.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqdecd_z_zs">UQDECD (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_extract">SVE Permute Vector - Extract</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_extract_i" title="SVE extract vector (immediate offset, destructive)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm8h" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm8l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_extract_i" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ext_z_zi_des" iformfile="ext_z_zi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ext_z_zi">EXT</td>
|
|
<td class="enctags">Destructive</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_perm_extract_i" title="SVE2 extract vector (immediate offset, constructive)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm8h" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm8l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_perm_extract_i" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="14*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ext_z_zi_con" iformfile="ext_z_zi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ext_z_zi">EXT</td>
|
|
<td class="enctags">Constructive</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_inter_long">SVE Permute Vector - Segments</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_bin_long_perm_zz" title="SVE permute vector segments">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="10" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_bin_long_perm_zz" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<col colno="4" printwidth="25*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">H</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip1_z_zz_q" arch_version="FEAT_F64MM" iformfile="zip1_z_zz.xml" label="ZIP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip1_z_zz">ZIP1, ZIP2 (vectors)</td>
|
|
<td class="enctags">Low halves (quadwords)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zip2_z_zz_q" arch_version="FEAT_F64MM" iformfile="zip1_z_zz.xml" label="ZIP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="zip1_z_zz">ZIP1, ZIP2 (vectors)</td>
|
|
<td class="enctags">High halves (quadwords)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp1_z_zz_q" arch_version="FEAT_F64MM" iformfile="uzp1_z_zz.xml" label="UZP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uzp1_z_zz">UZP1, UZP2 (vectors)</td>
|
|
<td class="enctags">Even (quadwords)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp2_z_zz_q" arch_version="FEAT_F64MM" iformfile="uzp1_z_zz.xml" label="UZP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp1_z_zz">UZP1, UZP2 (vectors)</td>
|
|
<td class="enctags">Odd (quadwords)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_353" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn1_z_zz_q" arch_version="FEAT_F64MM" iformfile="trn1_z_zz.xml" label="TRN1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="trn1_z_zz">TRN1, TRN2 (vectors)</td>
|
|
<td class="enctags">Even (quadwords)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn2_z_zz_q" arch_version="FEAT_F64MM" iformfile="trn1_z_zz.xml" label="TRN2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="trn1_z_zz">TRN1, TRN2 (vectors)</td>
|
|
<td class="enctags">Odd (quadwords)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_maskimm">SVE Bitwise Immediate</funcgroupheader>
|
|
<iclass_sect id="sve_int_log_imm" title="SVE bitwise logical with immediate (unpredicated)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1" settings="2" constraint="!= 11">
|
|
<c colspan="2">!= 11</c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="13" name="imm13" usename="1">
|
|
<c colspan="13"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="11" />
|
|
<decode_constraint name="opc" op="!=" val="11" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_int_log_imm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="orr_z_zi_" iformfile="orr_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="orr_z_zi">ORR (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eor_z_zi_" iformfile="eor_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="eor_z_zi">EOR (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="and_z_zi_" iformfile="and_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="and_z_zi">AND (immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_dup_mask_imm" title="SVE broadcast bitmask immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="14" settings="14">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="13" name="imm13" usename="1">
|
|
<c colspan="13"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_dup_mask_imm" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="dupm_z_i_" iformfile="dupm_z_i.xml" first="t" last="t">
|
|
<td class="iformname" iformid="dupm_z_i">DUPM</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_wideimm_pred">SVE Integer Wide Immediate - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_dup_fpimm_pred" title="SVE copy floating-point immediate (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_dup_fpimm_pred" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcpy_z_p_i_" iformfile="fcpy_z_p_i.xml" first="t" last="t">
|
|
<td class="iformname" iformid="fcpy_z_p_i">FCPY</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_dup_imm_pred" title="SVE copy integer immediate (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="sh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_dup_imm_pred" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="26*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">M</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cpy_z_o_i_" iformfile="cpy_z_o_i.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cpy_z_o_i">CPY (immediate, zeroing)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cpy_z_p_i_" iformfile="cpy_z_p_i.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cpy_z_p_i">CPY (immediate, merging)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_unpred_a">SVE Permute Vector - Indexed DUP</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_dup_i" title="SVE broadcast indexed element">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="imm2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="tsz" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_dup_i" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="dup_z_zi_" iformfile="dup_z_zi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="dup_z_zi">DUP (indexed)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_quads_a">SVE Permute Vector - Quadwords</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_dupq_i" title="sve_int_perm_dupq_i">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" name="i1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="tsz" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_dupq_i" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="dupq_z_zi_" arch_version="FEAT_SVE2p1" iformfile="dupq_z_zi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="dupq_z_zi">DUPQ</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_extq" title="sve_int_perm_extq">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_extq" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="extq_z_zi_des" arch_version="FEAT_SVE2p1" iformfile="extq_z_zi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="extq_z_zi">EXTQ</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_unpred_b">SVE Permute Vector - Three Sources TBL</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_tbl_3src" title="SVE table lookup (three sources)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_tbl_3src" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="tbl_z_zz_2" iformfile="tbl_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="tbl_z_zz">TBL</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="tbx_z_zz_" iformfile="tbx_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="tbx_z_zz">TBX</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_unpred_c">SVE Permute Vector - Two Sources TBL</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_tbl" title="SVE table lookup">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_tbl" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="tbl_z_zz_1" iformfile="tbl_z_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="tbl_z_zz">TBL</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_quads_c">sve_perm_quads_c</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_tbxquads" title="sve_int_perm_tbxquads">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_tbxquads" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="tbxq_z_zz_" arch_version="FEAT_SVE2p1" iformfile="tbxq_z_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="tbxq_z_zz">TBXQ</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_unpred_d">SVE Permute Vector - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_dup_r" title="SVE broadcast general register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_dup_r" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="dup_z_r_" iformfile="dup_z_r.xml" first="t" last="t">
|
|
<td class="iformname" iformid="dup_z_r">DUP (scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_insrv" title="SVE insert SIMD&FP scalar register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Vm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_insrv" cols="2">
|
|
<col colno="1" printwidth="23*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="insr_z_v_" iformfile="insr_z_v.xml" first="t" last="t">
|
|
<td class="iformname" iformid="insr_z_v">INSR (SIMD&FP scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_insrs" title="SVE insert general register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_insrs" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="insr_z_r_" iformfile="insr_z_r.xml" first="t" last="t">
|
|
<td class="iformname" iformid="insr_z_r">INSR (scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_mov_v2p" title="SVE move predicate from vector">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_mov_v2p" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="21*" />
|
|
<col colno="4" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_350" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_p_zi_b" arch_version="FEAT_SVE2p1" iformfile="pmov_p_zi.xml" label="byte" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="pmov_p_zi">PMOV (to predicate)</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_p_zi_h" arch_version="FEAT_SVE2p1" iformfile="pmov_p_zi.xml" label="halfword" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname" iformid="pmov_p_zi">PMOV (to predicate)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_p_zi_s" arch_version="FEAT_SVE2p1" iformfile="pmov_p_zi.xml" label="word" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="pmov_p_zi">PMOV (to predicate)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_p_zi_d" arch_version="FEAT_SVE2p1" iformfile="pmov_p_zi.xml" label="doubleword" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="pmov_p_zi">PMOV (to predicate)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_mov_p2v" title="SVE move predicate into vector">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_mov_p2v" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="12*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_351" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_z_pi_b" arch_version="FEAT_SVE2p1" iformfile="pmov_z_pi.xml" label="byte" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="pmov_z_pi">PMOV (to vector)</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_z_pi_h" arch_version="FEAT_SVE2p1" iformfile="pmov_z_pi.xml" label="halfword" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname" iformid="pmov_z_pi">PMOV (to vector)</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_z_pi_s" arch_version="FEAT_SVE2p1" iformfile="pmov_z_pi.xml" label="word" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="pmov_z_pi">PMOV (to vector)</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmov_z_pi_d" arch_version="FEAT_SVE2p1" iformfile="pmov_z_pi.xml" label="doubleword" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="pmov_z_pi">PMOV (to vector)</td>
|
|
<td class="enctags">Doubleword</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_reverse_z" title="SVE reverse vector elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_reverse_z" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="rev_z_z_" iformfile="rev_z_z.xml" first="t" last="t">
|
|
<td class="iformname" iformid="rev_z_z">REV (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_unpk" title="SVE unpack vector elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_unpk" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="11*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">H</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sunpklo_z_z_" iformfile="sunpkhi_z_z.xml" label="SUNPKLO" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sunpkhi_z_z">SUNPKHI, SUNPKLO</td>
|
|
<td class="enctags">Low half</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sunpkhi_z_z_" iformfile="sunpkhi_z_z.xml" label="SUNPKHI" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sunpkhi_z_z">SUNPKHI, SUNPKLO</td>
|
|
<td class="enctags">High half</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uunpklo_z_z_" iformfile="uunpkhi_z_z.xml" label="UUNPKLO" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uunpkhi_z_z">UUNPKHI, UUNPKLO</td>
|
|
<td class="enctags">Low half</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uunpkhi_z_z_" iformfile="uunpkhi_z_z.xml" label="UUNPKHI" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uunpkhi_z_z">UUNPKHI, UUNPKLO</td>
|
|
<td class="enctags">High half</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_predicates">SVE Permute Predicate</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_bin_perm_pp" title="SVE permute predicate elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="10" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_bin_perm_pp" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="25*" />
|
|
<col colno="4" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">H</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip1_p_pp_" iformfile="zip1_p_pp.xml" label="ZIP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip1_p_pp">ZIP1, ZIP2 (predicates)</td>
|
|
<td class="enctags">Low halves</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zip2_p_pp_" iformfile="zip1_p_pp.xml" label="ZIP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="zip1_p_pp">ZIP1, ZIP2 (predicates)</td>
|
|
<td class="enctags">High halves</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp1_p_pp_" iformfile="uzp1_p_pp.xml" label="UZP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uzp1_p_pp">UZP1, UZP2 (predicates)</td>
|
|
<td class="enctags">Even</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp2_p_pp_" iformfile="uzp1_p_pp.xml" label="UZP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp1_p_pp">UZP1, UZP2 (predicates)</td>
|
|
<td class="enctags">Odd</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn1_p_pp_" iformfile="trn1_p_pp.xml" label="TRN1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="trn1_p_pp">TRN1, TRN2 (predicates)</td>
|
|
<td class="enctags">Even</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn2_p_pp_" iformfile="trn1_p_pp.xml" label="TRN2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="trn1_p_pp">TRN1, TRN2 (predicates)</td>
|
|
<td class="enctags">Odd</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_348" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_reverse_p" title="SVE reverse predicate elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_reverse_p" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="rev_p_p_" iformfile="rev_p_p.xml" first="t" last="t">
|
|
<td class="iformname" iformid="rev_p_p">REV (predicate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_punpk" title="SVE unpack predicate elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="15" settings="15">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="H" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_punpk" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="11*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">H</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="punpklo_p_p_" iformfile="punpkhi_p_p.xml" label="PUNPKLO" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="punpkhi_p_p">PUNPKHI, PUNPKLO</td>
|
|
<td class="enctags">Low half</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="punpkhi_p_p_" iformfile="punpkhi_p_p.xml" label="PUNPKHI" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="punpkhi_p_p">PUNPKHI, PUNPKLO</td>
|
|
<td class="enctags">High half</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_inter">SVE Permute Vector - Interleaving</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_bin_perm_zz" title="SVE permute vector elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_bin_perm_zz" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip1_z_zz_" iformfile="zip1_z_zz.xml" label="ZIP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="zip1_z_zz">ZIP1, ZIP2 (vectors)</td>
|
|
<td class="enctags">Low halves</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zip2_z_zz_" iformfile="zip1_z_zz.xml" label="ZIP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="zip1_z_zz">ZIP1, ZIP2 (vectors)</td>
|
|
<td class="enctags">High halves</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp1_z_zz_" iformfile="uzp1_z_zz.xml" label="UZP1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="uzp1_z_zz">UZP1, UZP2 (vectors)</td>
|
|
<td class="enctags">Even</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp2_z_zz_" iformfile="uzp1_z_zz.xml" label="UZP2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="uzp1_z_zz">UZP1, UZP2 (vectors)</td>
|
|
<td class="enctags">Odd</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn1_z_zz_" iformfile="trn1_z_zz.xml" label="TRN1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="trn1_z_zz">TRN1, TRN2 (vectors)</td>
|
|
<td class="enctags">Even</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="trn2_z_zz_" iformfile="trn1_z_zz.xml" label="TRN2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="trn1_z_zz">TRN1, TRN2 (vectors)</td>
|
|
<td class="enctags">Odd</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_349" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_pred">SVE Permute Vector - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_compact" title="SVE compress active elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_compact" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="compact_z_p_z_" iformfile="compact_z_p_z.xml" first="t" last="t">
|
|
<td class="iformname" iformid="compact_z_p_z">COMPACT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_clast_zz" title="SVE conditionally broadcast element to vector">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_clast_zz" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="clasta_z_p_zz_" iformfile="clasta_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="clasta_z_p_zz">CLASTA (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="clastb_z_p_zz_" iformfile="clastb_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="clastb_z_p_zz">CLASTB (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_clast_vz" title="SVE conditionally extract element to SIMD&FP scalar">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_clast_vz" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="25*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="clasta_v_p_z_" iformfile="clasta_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="clasta_v_p_z">CLASTA (SIMD&FP scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="clastb_v_p_z_" iformfile="clastb_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="clastb_v_p_z">CLASTB (SIMD&FP scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_clast_rz" title="SVE conditionally extract element to general register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_clast_rz" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="clasta_r_p_z_" iformfile="clasta_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="clasta_r_p_z">CLASTA (scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="clastb_r_p_z_" iformfile="clastb_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="clastb_r_p_z">CLASTB (scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_cpy_v" title="SVE copy SIMD&FP scalar register to vector (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Vn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_cpy_v" cols="2">
|
|
<col colno="1" printwidth="22*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cpy_z_p_v_" iformfile="cpy_z_p_v.xml" first="t" last="t">
|
|
<td class="iformname" iformid="cpy_z_p_v">CPY (SIMD&FP scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_cpy_r" title="SVE copy general register to vector (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_cpy_r" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cpy_z_p_r_" iformfile="cpy_z_p_r.xml" first="t" last="t">
|
|
<td class="iformname" iformid="cpy_z_p_r">CPY (scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_last_v" title="SVE extract element to SIMD&FP scalar register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_last_v" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="24*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="lasta_v_p_z_" iformfile="lasta_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="lasta_v_p_z">LASTA (SIMD&FP scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lastb_v_p_z_" iformfile="lastb_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lastb_v_p_z">LASTB (SIMD&FP scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_last_r" title="SVE extract element to general register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_last_r" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="lasta_r_p_z_" iformfile="lasta_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="lasta_r_p_z">LASTA (scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="lastb_r_p_z_" iformfile="lastb_r_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="lastb_r_p_z">LASTB (scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_revd" title="SVE reverse doublewords">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_revd" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="revd_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="revd_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="revd_z_p_z">REVD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_352" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_354" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_rev" title="SVE reverse within elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_rev" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="revb_z_z_" iformfile="revb_z_z.xml" label="REVB" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="revb_z_z">REVB, REVH, REVW</td>
|
|
<td class="enctags">Byte</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="revh_z_z_" iformfile="revb_z_z.xml" label="REVH" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="revb_z_z">REVB, REVH, REVW</td>
|
|
<td class="enctags">Halfword</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="revw_z_z_" iformfile="revb_z_z.xml" label="REVW" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="revb_z_z">REVB, REVH, REVW</td>
|
|
<td class="enctags">Word</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rbit_z_p_z_" iformfile="rbit_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="rbit_z_p_z">RBIT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_perm_splice" title="SVE vector splice (destructive)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pv" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_splice" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="splice_z_p_zz_des" iformfile="splice_z_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="splice_z_p_zz">SPLICE</td>
|
|
<td class="enctags">Destructive</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_perm_splice" title="SVE2 vector splice (constructive)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pv" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_perm_splice" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="14*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="splice_z_p_zz_con" iformfile="splice_z_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="splice_z_p_zz">SPLICE</td>
|
|
<td class="enctags">Constructive</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_int_select">SVE Vector Select</funcgroupheader>
|
|
<iclass_sect id="sve_int_sel_vvv" title="SVE select vector elements (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pv" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_sel_vvv" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sel_z_p_zz_" iformfile="sel_z_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sel_z_p_zz">SEL (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_cmpvec">SVE Integer Compare - Vectors</funcgroupheader>
|
|
<iclass_sect id="sve_int_cmp_0" title="SVE integer compare vectors">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_cmp_0" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="25*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cmphs_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPHS" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Higher or same</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmphi_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPHI" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Higher</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpeq_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPEQ" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpne_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPNE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpge_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPGE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpgt_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPGT" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpeq_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPEQ" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpne_p_p_zz_" iformfile="cmpeq_p_p_zz.xml" label="CMPNE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zz">CMP<cc> (vectors)</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_cmp_1" title="SVE integer compare with wide elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_cmp_1" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="25*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cmpge_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPGE" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpgt_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPGT" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmplt_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPLT" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Less than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmple_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPLE" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Less than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmphs_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPHS" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Higher or same</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmphi_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPHI" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Higher</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmplo_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPLO" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Lower</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpls_p_p_zw_" iformfile="cmpeq_p_p_zw.xml" label="CMPLS" oneofthismnem="8" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zw">CMP<cc> (wide elements)</td>
|
|
<td class="enctags">Lower or same</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_cmpuimm">SVE Integer Compare - Unsigned Immediate</funcgroupheader>
|
|
<iclass_sect id="sve_int_ucmp_vi" title="SVE integer compare with unsigned immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="7" name="imm7" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="13" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_ucmp_vi" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="21*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cmphs_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPHS" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Higher or same</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmphi_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPHI" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Higher</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmplo_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPLO" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Lower</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpls_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPLS" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Lower or same</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_gen_a">SVE Predicate Logical Operations</funcgroupheader>
|
|
<iclass_sect id="sve_int_pred_log" title="SVE predicate logical operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pred_log" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">o3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="and_p_p_pp_z" iformfile="and_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="and_p_p_pp">AND (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bic_p_p_pp_z" iformfile="bic_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bic_p_p_pp">BIC (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eor_p_p_pp_z" iformfile="eor_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="eor_p_p_pp">EOR (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sel_p_p_pp_" iformfile="sel_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sel_p_p_pp">SEL (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ands_p_p_pp_z" iformfile="ands_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ands_p_p_pp">ANDS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bics_p_p_pp_z" iformfile="bics_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bics_p_p_pp">BICS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eors_p_p_pp_z" iformfile="eors_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="eors_p_p_pp">EORS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_388" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="orr_p_p_pp_z" iformfile="orr_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="orr_p_p_pp">ORR (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="orn_p_p_pp_z" iformfile="orn_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="orn_p_p_pp">ORN (predicates)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nor_p_p_pp_z" iformfile="nor_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="nor_p_p_pp">NOR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nand_p_p_pp_z" iformfile="nand_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="nand_p_p_pp">NAND</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="orrs_p_p_pp_z" iformfile="orrs_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="orrs_p_p_pp">ORRS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="orns_p_p_pp_z" iformfile="orns_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="orns_p_p_pp">ORNS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nors_p_p_pp_z" iformfile="nors_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="nors_p_p_pp">NORS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nands_p_p_pp_z" iformfile="nands_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="nands_p_p_pp">NANDS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_gen_b">SVE Propagate Break</funcgroupheader>
|
|
<iclass_sect id="sve_int_brkp" title="SVE propagate break from previous partition">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_brkp" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">B</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="brkpa_p_p_pp_" iformfile="brkpa_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="brkpa_p_p_pp">BRKPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkpb_p_p_pp_" iformfile="brkpb_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="brkpb_p_p_pp">BRKPB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkpas_p_p_pp_" iformfile="brkpas_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="brkpas_p_p_pp">BRKPAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkpbs_p_p_pp_" iformfile="brkpbs_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="brkpbs_p_p_pp">BRKPBS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_398" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_gen_c">SVE Partition Break</funcgroupheader>
|
|
<iclass_sect id="sve_int_break" title="SVE partition break condition">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="B" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_break" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">B</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">M</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_389" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brka_p_p_p_" iformfile="brka_p_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="brka_p_p_p">BRKA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkas_p_p_p_z" iformfile="brkas_p_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="brkas_p_p_p">BRKAS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkb_p_p_p_" iformfile="brkb_p_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="brkb_p_p_p">BRKB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkbs_p_p_p_z" iformfile="brkbs_p_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="brkbs_p_p_p">BRKBS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_brkn" title="SVE propagate break to next partition">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pdm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_brkn" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="brkn_p_p_pp_" iformfile="brkn_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="brkn_p_p_pp">BRKN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="brkns_p_p_pp_" iformfile="brkns_p_p_pp.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="brkns_p_p_pp">BRKNS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_gen_d">SVE Predicate Misc</funcgroupheader>
|
|
<iclass_sect id="sve_int_pfirst" title="SVE predicate first active">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pfirst" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_357" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pfirst_p_p_p_" iformfile="pfirst_p_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="pfirst_p_p_p">PFIRST</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_400" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_ptrue" title="SVE predicate initialize">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="pattern" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_ptrue" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="19*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ptrue_p_s_" iformfile="ptrue_p_s.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ptrue_p_s">PTRUE (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ptrues_p_s_" iformfile="ptrues_p_s.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ptrues_p_s">PTRUES</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pnext" title="SVE predicate next active">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pv" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pnext" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="pnext_p_p_p_" iformfile="pnext_p_p_p.xml" first="t" last="t">
|
|
<td class="iformname" iformid="pnext_p_p_p">PNEXT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_rdffr" title="SVE predicate read from FFR (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_rdffr" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="20*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="rdffr_p_p_f_" iformfile="rdffr_p_p_f.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="rdffr_p_p_f">RDFFR (predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rdffrs_p_p_f_" iformfile="rdffrs_p_p_f.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="rdffrs_p_p_f">RDFFRS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_402" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_rdffr_2" title="SVE predicate read from FFR (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_rdffr_2" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="rdffr_p_f_" iformfile="rdffr_p_f.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="rdffr_p_f">RDFFR (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_395" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_403" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_ptest" title="SVE predicate test">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="opc2" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_ptest" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_356" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ptest_p_p_" iformfile="ptest_p_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ptest_p_p">PTEST</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_390" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_391" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_392" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_393" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_399" undef="1" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pfalse" title="SVE predicate zero">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pfalse" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="pfalse_p_" iformfile="pfalse_p.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="pfalse_p">PFALSE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_394" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_401" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_cmpsimm">SVE Integer Compare - Signed Immediate</funcgroupheader>
|
|
<iclass_sect id="sve_int_scmp_vi" title="SVE integer compare with signed immediate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_scmp_vi" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="21*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cmpge_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPGE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpgt_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPGT" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmplt_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPLT" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Less than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmple_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPLE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Less than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpeq_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPEQ" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmpne_p_p_zi_" iformfile="cmpeq_p_p_zi.xml" label="CMPNE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="cmpeq_p_p_zi">CMP<cc> (immediate)</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_355" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_count_a">SVE Predicate Count</funcgroupheader>
|
|
<iclass_sect id="sve_int_pcount_pred" title="SVE predicate count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pg" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pcount_pred" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cntp_r_p_p_" iformfile="cntp_r_p_p.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="cntp_r_p_p">CNTP (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_361" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_363" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_366" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pcount_pn" title="SVE predicate count (predicate-as-counter)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="vl" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="PNn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pcount_pn" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="29*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cntp_r_pn_" arch_version="FEAT_SVE2p1" iformfile="cntp_r_pn.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="cntp_r_pn">CNTP (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_362" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_364" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_367" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_count_b">SVE Inc/Dec by Predicate Count</funcgroupheader>
|
|
<iclass_sect id="sve_int_count_r" title="SVE inc/dec register by predicate count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_count_r" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_374" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_375" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incp_r_p_r_" iformfile="incp_r_p_r.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="incp_r_p_r">INCP (scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decp_r_p_r_" iformfile="decp_r_p_r.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="decp_r_p_r">DECP (scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_378" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_count_v" title="SVE inc/dec vector by predicate count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_count_v" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_372" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_373" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="incp_z_p_z_" iformfile="incp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="incp_z_p_z">INCP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="decp_z_p_z_" iformfile="decp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="decp_z_p_z">DECP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_377" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_count_r_sat" title="SVE saturating inc/dec register by predicate count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_count_r_sat" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">sf</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_370" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincp_r_p_r_sx" iformfile="sqincp_r_p_r.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincp_r_p_r">SQINCP (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincp_r_p_r_x" iformfile="sqincp_r_p_r.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqincp_r_p_r">SQINCP (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincp_r_p_r_uw" iformfile="uqincp_r_p_r.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqincp_r_p_r">UQINCP (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincp_r_p_r_x" iformfile="uqincp_r_p_r.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqincp_r_p_r">UQINCP (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecp_r_p_r_sx" iformfile="sqdecp_r_p_r.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecp_r_p_r">SQDECP (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecp_r_p_r_x" iformfile="sqdecp_r_p_r.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdecp_r_p_r">SQDECP (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecp_r_p_r_uw" iformfile="uqdecp_r_p_r.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqdecp_r_p_r">UQDECP (scalar)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecp_r_p_r_x" iformfile="uqdecp_r_p_r.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqdecp_r_p_r">UQDECP (scalar)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_count_v_sat" title="SVE saturating inc/dec vector by predicate count">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_count_v_sat" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">D</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_368" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_369" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqincp_z_p_z_" iformfile="sqincp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="sqincp_z_p_z">SQINCP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqincp_z_p_z_" iformfile="uqincp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="uqincp_z_p_z">UQINCP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdecp_z_p_z_" iformfile="sqdecp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="sqdecp_z_p_z">SQDECP (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqdecp_z_p_z_" iformfile="uqdecp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="uqdecp_z_p_z">UQDECP (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_wrffr">SVE Write FFR</funcgroupheader>
|
|
<iclass_sect id="sve_int_setffr" title="SVE FFR initialise">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_setffr" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="setffr_f_" iformfile="setffr_f.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="setffr_f">SETFFR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_397" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_405" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_wrffr" title="SVE FFR write from predicate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_wrffr" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="wrffr_f_p_" iformfile="wrffr_f_p.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="wrffr_f_p">WRFFR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_396" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_404" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_cmpgpr">SVE Integer Compare - Scalars</funcgroupheader>
|
|
<iclass_sect id="sve_int_cterm" title="SVE conditionally terminate scalars">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_cterm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="11*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_358" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ctermeq_rr_" iformfile="ctermeq_rr.xml" label="CTERMEQ" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ctermeq_rr">CTERMEQ, CTERMNE</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ctermne_rr_" iformfile="ctermeq_rr.xml" label="CTERMNE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ctermeq_rr">CTERMEQ, CTERMNE</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_while_rr" title="SVE integer compare scalar count and limit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" name="sf" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="eq" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_while_rr" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="21*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">eq</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="whilege_p_p_rr_" iformfile="whilege_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilege_p_p_rr">WHILEGE (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilegt_p_p_rr_" iformfile="whilegt_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilegt_p_p_rr">WHILEGT (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelt_p_p_rr_" iformfile="whilelt_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelt_p_p_rr">WHILELT (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilele_p_p_rr_" iformfile="whilele_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilele_p_p_rr">WHILELE (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehs_p_p_rr_" iformfile="whilehs_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilehs_p_p_rr">WHILEHS (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehi_p_p_rr_" iformfile="whilehi_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilehi_p_p_rr">WHILEHI (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelo_p_p_rr_" iformfile="whilelo_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelo_p_p_rr">WHILELO (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilels_p_p_rr_" iformfile="whilels_p_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilels_p_p_rr">WHILELS (predicate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_whilenc" title="SVE pointer conflict compare">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="rw" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_whilenc" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">rw</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="whilewr_p_rr_" iformfile="whilewr_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilewr_p_rr">WHILEWR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilerw_p_rr_" iformfile="whilerw_p_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilerw_p_rr">WHILERW</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_pred_dup">sve_pred_dup</funcgroupheader>
|
|
<iclass_sect id="sve_int_pred_dup" title="SVE broadcast predicate element">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="i1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="tszl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="4" name="Pn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="9" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="8" width="4" name="Pm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pred_dup" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="psel_p_ppi_" arch_version="FEAT_SVE2p1" iformfile="psel_p_ppi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="psel_p_ppi">PSEL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_359" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_while_pn">SVE Scalar Integer Compare - Predicate-as-counter</funcgroupheader>
|
|
<iclass_sect id="sve_int_ctr_to_mask" title="SVE extract mask predicate from predicate-as-counter">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="7" width="3" name="PNn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_ctr_to_mask" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="pext_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="pext_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="pext_pn_rr">PEXT (predicate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pext_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="pext_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname" iformid="pext_pp_rr">PEXT (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_360" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_while_rr_pair" title="SVE integer compare scalar count and limit (predicate pair)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="3" name="Pd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="0" name="eq" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_while_rr_pair" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">eq</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="whilege_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilege_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilege_pp_rr">WHILEGE (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilegt_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilegt_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilegt_pp_rr">WHILEGT (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelt_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilelt_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelt_pp_rr">WHILELT (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilele_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilele_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilele_pp_rr">WHILELE (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehs_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilehs_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilehs_pp_rr">WHILEHS (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehi_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilehi_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilehi_pp_rr">WHILEHI (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelo_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilelo_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelo_pp_rr">WHILELO (predicate pair)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilels_pp_rr_" arch_version="FEAT_SVE2p1" iformfile="whilels_pp_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilels_pp_rr">WHILELS (predicate pair)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_while_rr_pn" title="SVE integer compare scalar count and limit (predicate-as-counter)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="vl" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="eq" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="PNd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_while_rr_pn" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="32*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">eq</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="whilege_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilege_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilege_pn_rr">WHILEGE (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilegt_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilegt_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilegt_pn_rr">WHILEGT (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelt_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilelt_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelt_pn_rr">WHILELT (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilele_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilele_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilele_pn_rr">WHILELE (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehs_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilehs_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilehs_pn_rr">WHILEHS (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilehi_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilehi_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilehi_pn_rr">WHILEHI (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilelo_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilelo_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="whilelo_pn_rr">WHILELO (predicate as counter)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="whilels_pn_rr_" arch_version="FEAT_SVE2p1" iformfile="whilels_pn_rr.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="whilels_pn_rr">WHILELS (predicate as counter)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_pn_ptrue" title="sve_int_pn_ptrue">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="PNd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_pn_ptrue" cols="2">
|
|
<col colno="1" printwidth="30*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ptrue_pn_i_" arch_version="FEAT_SVE2p1" iformfile="ptrue_pn_i.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ptrue_pn_i">PTRUE (predicate as counter)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_wideimm_unpred">SVE Integer Wide Immediate - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_int_dup_fpimm" title="SVE broadcast floating-point immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_dup_fpimm" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdup_z_i_" iformfile="fdup_z_i.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fdup_z_i">FDUP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_383" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_385" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_387" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_dup_imm" title="SVE broadcast integer immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="sh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_dup_imm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="dup_z_i_" iformfile="dup_z_i.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="dup_z_i">DUP (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_384" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_386" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_arith_imm0" title="SVE integer add/subtract immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="sh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_arith_imm0" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="19*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_z_zi_" iformfile="add_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="add_z_zi">ADD (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_z_zi_" iformfile="sub_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="sub_z_zi">SUB (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_365" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="subr_z_zi_" iformfile="subr_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="subr_z_zi">SUBR (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqadd_z_zi_" iformfile="sqadd_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="sqadd_z_zi">SQADD (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqadd_z_zi_" iformfile="uqadd_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="uqadd_z_zi">UQADD (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqsub_z_zi_" iformfile="sqsub_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="sqsub_z_zi">SQSUB (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqsub_z_zi_" iformfile="uqsub_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="uqsub_z_zi">UQSUB (immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_arith_imm1" title="SVE integer min/max immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_arith_imm1" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_371" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smax_z_zi_" iformfile="smax_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_z_zi">SMAX (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_z_zi_" iformfile="umax_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umax_z_zi">UMAX (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_z_zi_" iformfile="smin_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_z_zi">SMIN (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_z_zi_" iformfile="umin_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umin_z_zi">UMIN (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_376" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_int_arith_imm2" title="SVE integer multiply immediate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_arith_imm2" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mul_z_zi_" iformfile="mul_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mul_z_zi">MUL (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_379" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_380" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_381" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_382" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_dot2">SVE Dot Product - Two-way</funcgroupheader>
|
|
<iclass_sect id="sve_intx_dot2" title="SVE two-way dot product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_dot2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_z32_zzz_" arch_version="FEAT_SVE2p1" iformfile="sdot_z32_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_z32_zzz">SDOT (2-way, vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_z32_zzz_" arch_version="FEAT_SVE2p1" iformfile="udot_z32_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_z32_zzz">UDOT (2-way, vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_dot2_by_indexed_elem">SVE Dot Product - Two-way Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_intx_dot2_by_indexed_elem" title="SVE two-way dot product (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_dot2_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_z32_zzzi_" arch_version="FEAT_SVE2p1" iformfile="sdot_z32_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_z32_zzzi">SDOT (2-way, indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_z32_zzzi_" arch_version="FEAT_SVE2p1" iformfile="udot_z32_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_z32_zzzi">UDOT (2-way, indexed)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_muladd_unpred">SVE Integer Multiply-Add - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_intx_dot" title="SVE integer dot product (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_dot" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_z_zzz_" iformfile="sdot_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_z_zzz">SDOT (4-way, vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_z_zzz_" iformfile="udot_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_z_zzz">UDOT (4-way, vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mixed_dot" title="SVE mixed sign dot product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mixed_dot" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_406" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usdot_z_zzz_s" arch_version="FEAT_I8MM" iformfile="usdot_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="usdot_z_zzz">USDOT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_422" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cdot" title="SVE2 complex integer dot product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cdot" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cdot_z_zzz_" iformfile="cdot_z_zzz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="cdot_z_zzz">CDOT (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cmla" title="SVE2 complex integer multiply-add">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cmla" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="21*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cmla_z_zzz_" iformfile="cmla_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cmla_z_zzz">CMLA (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdcmlah_z_zzz_" iformfile="sqrdcmlah_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdcmlah_z_zzz">SQRDCMLAH (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mlal_long" title="SVE2 integer multiply-add long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mlal_long" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlalb_z_zzz_" iformfile="smlalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlalb_z_zzz">SMLALB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlalt_z_zzz_" iformfile="smlalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlalt_z_zzz">SMLALT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalb_z_zzz_" iformfile="umlalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlalb_z_zzz">UMLALB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalt_z_zzz_" iformfile="umlalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlalt_z_zzz">UMLALT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslb_z_zzz_" iformfile="smlslb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlslb_z_zzz">SMLSLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslt_z_zzz_" iformfile="smlslt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlslt_z_zzz">SMLSLT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslb_z_zzz_" iformfile="umlslb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlslb_z_zzz">UMLSLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslt_z_zzz_" iformfile="umlslt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlslt_z_zzz">UMLSLT (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qrdmlah" title="SVE2 saturating multiply-add high">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qrdmlah" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="20*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqrdmlah_z_zzz_" iformfile="sqrdmlah_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrdmlah_z_zzz">SQRDMLAH (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlsh_z_zzz_" iformfile="sqrdmlsh_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmlsh_z_zzz">SQRDMLSH (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qdmlalbt" title="SVE2 saturating multiply-add interleaved long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qdmlalbt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmlalbt_z_zzz_" iformfile="sqdmlalbt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlalbt_z_zzz">SQDMLALBT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslbt_z_zzz_" iformfile="sqdmlslbt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlslbt_z_zzz">SQDMLSLBT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qdmlal_long" title="SVE2 saturating multiply-add long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qdmlal_long" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="20*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmlalb_z_zzz_" iformfile="sqdmlalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlalb_z_zzz">SQDMLALB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlalt_z_zzz_" iformfile="sqdmlalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlalt_z_zzz">SQDMLALT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslb_z_zzz_" iformfile="sqdmlslb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlslb_z_zzz">SQDMLSLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslt_z_zzz_" iformfile="sqdmlslt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlslt_z_zzz">SQDMLSLT (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_predicated">SVE2 Integer - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_intx_pred_arith_binary" title="SVE2 integer halving add/subtract (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_pred_arith_binary" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="shadd_z_p_zz_" iformfile="shadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="shadd_z_p_zz">SHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uhadd_z_p_zz_" iformfile="uhadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uhadd_z_p_zz">UHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="shsub_z_p_zz_" iformfile="shsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="shsub_z_p_zz">SHSUB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uhsub_z_p_zz_" iformfile="uhsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uhsub_z_p_zz">UHSUB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srhadd_z_p_zz_" iformfile="srhadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srhadd_z_p_zz">SRHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urhadd_z_p_zz_" iformfile="urhadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urhadd_z_p_zz">URHADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="shsubr_z_p_zz_" iformfile="shsubr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="shsubr_z_p_zz">SHSUBR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uhsubr_z_p_zz_" iformfile="uhsubr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uhsubr_z_p_zz">UHSUBR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_accumulate_long_pairs" title="SVE2 integer pairwise add and accumulate long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_accumulate_long_pairs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sadalp_z_p_z_" iformfile="sadalp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sadalp_z_p_z">SADALP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uadalp_z_p_z_" iformfile="uadalp_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uadalp_z_p_z">UADALP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_arith_binary_pairs" title="SVE2 integer pairwise arithmetic">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_arith_binary_pairs" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_411" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addp_z_p_zz_" iformfile="addp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="addp_z_p_zz">ADDP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_412" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smaxp_z_p_zz_" iformfile="smaxp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smaxp_z_p_zz">SMAXP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umaxp_z_p_zz_" iformfile="umaxp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umaxp_z_p_zz">UMAXP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sminp_z_p_zz_" iformfile="sminp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sminp_z_p_zz">SMINP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uminp_z_p_zz_" iformfile="uminp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uminp_z_p_zz">UMINP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_pred_arith_unary" title="SVE2 integer unary operations (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="18" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_pred_arith_unary" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Q</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_410" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urecpe_z_p_z_" iformfile="urecpe_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="urecpe_z_p_z">URECPE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ursqrte_z_p_z_" iformfile="ursqrte_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ursqrte_z_p_z">URSQRTE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqabs_z_p_z_" iformfile="sqabs_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="sqabs_z_p_z">SQABS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqneg_z_p_z_" iformfile="sqneg_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="sqneg_z_p_z">SQNEG</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_pred_arith_binary_sat" title="SVE2 saturating add/subtract">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_pred_arith_binary_sat" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="29*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqadd_z_p_zz_" iformfile="sqadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqadd_z_p_zz">SQADD (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqadd_z_p_zz_" iformfile="uqadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqadd_z_p_zz">UQADD (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqsub_z_p_zz_" iformfile="sqsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqsub_z_p_zz">SQSUB (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqsub_z_p_zz_" iformfile="uqsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqsub_z_p_zz">UQSUB (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="suqadd_z_p_zz_" iformfile="suqadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="suqadd_z_p_zz">SUQADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usqadd_z_p_zz_" iformfile="usqadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usqadd_z_p_zz">USQADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqsubr_z_p_zz_" iformfile="sqsubr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqsubr_z_p_zz">SQSUBR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqsubr_z_p_zz_" iformfile="uqsubr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqsubr_z_p_zz">UQSUBR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_bin_pred_shift_sat_round" title="SVE2 saturating/rounding bitwise shift left (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="18" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="17" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_bin_pred_shift_sat_round" cols="6">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">Q</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">N</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_407" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshl_z_p_zz_" iformfile="srshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshl_z_p_zz">SRSHL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshl_z_p_zz_" iformfile="urshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshl_z_p_zz">URSHL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshlr_z_p_zz_" iformfile="srshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshlr_z_p_zz">SRSHLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshlr_z_p_zz_" iformfile="urshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshlr_z_p_zz">URSHLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshl_z_p_zz_" iformfile="sqshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqshl_z_p_zz">SQSHL (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqshl_z_p_zz_" iformfile="uqshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqshl_z_p_zz">UQSHL (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshl_z_p_zz_" iformfile="sqrshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshl_z_p_zz">SQRSHL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshl_z_p_zz_" iformfile="uqrshl_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshl_z_p_zz">UQRSHL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshlr_z_p_zz_" iformfile="sqshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqshlr_z_p_zz">SQSHLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqshlr_z_p_zz_" iformfile="uqshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqshlr_z_p_zz">UQSHLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshlr_z_p_zz_" iformfile="sqrshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshlr_z_p_zz">SQRSHLR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshlr_z_p_zz_" iformfile="uqrshlr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshlr_z_p_zz">UQRSHLR</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_clamp">sve_intx_clamp</funcgroupheader>
|
|
<iclass_sect id="sve_intx_clamp" title="SVE integer clamp">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_clamp" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sclamp_z_zz_" arch_version="FEAT_SVE2p1" iformfile="sclamp_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sclamp_z_zz">SCLAMP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uclamp_z_zz_" arch_version="FEAT_SVE2p1" iformfile="uclamp_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uclamp_z_zz">UCLAMP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_perm_quads_b">sve_perm_quads_b</funcgroupheader>
|
|
<iclass_sect id="sve_int_perm_binquads" title="SVE permute vector elements (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_int_perm_binquads" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zipq1_z_zz_" arch_version="FEAT_SVE2p1" iformfile="zipq1_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="zipq1_z_zz">ZIPQ1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zipq2_z_zz_" arch_version="FEAT_SVE2p1" iformfile="zipq2_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="zipq2_z_zz">ZIPQ2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzpq1_z_zz_" arch_version="FEAT_SVE2p1" iformfile="uzpq1_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="uzpq1_z_zz">UZPQ1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzpq2_z_zz_" arch_version="FEAT_SVE2p1" iformfile="uzpq2_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="uzpq2_z_zz">UZPQ2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_408" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="tblq_z_zz_" arch_version="FEAT_SVE2p1" iformfile="tblq_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="tblq_z_zz">TBLQ</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_409" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_by_indexed_elem">SVE Multiply - Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_intx_dot_by_indexed_elem" title="SVE integer dot product (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_dot_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_413" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_z_zzzi_s" iformfile="sdot_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_z_zzzi">SDOT (4-way, indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_z_zzzi_s" iformfile="udot_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_z_zzzi">UDOT (4-way, indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_z_zzzi_d" iformfile="sdot_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_z_zzzi">SDOT (4-way, indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_z_zzzi_d" iformfile="udot_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_z_zzzi">UDOT (4-way, indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mixed_dot_by_indexed_elem" title="SVE mixed sign dot product (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mixed_dot_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_414" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usdot_z_zzzi_s" arch_version="FEAT_I8MM" iformfile="usdot_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usdot_z_zzzi">USDOT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sudot_z_zzzi_s" arch_version="FEAT_I8MM" iformfile="sudot_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sudot_z_zzzi">SUDOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_423" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cdot_by_indexed_elem" title="SVE2 complex integer dot product (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cdot_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_416" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cdot_z_zzzi_s" iformfile="cdot_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="cdot_z_zzzi">CDOT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cdot_z_zzzi_d" iformfile="cdot_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="cdot_z_zzzi">CDOT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cmla_by_indexed_elem" title="SVE2 complex integer multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cmla_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_417" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmla_z_zzzi_h" iformfile="cmla_z_zzzi.xml" label="16-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="cmla_z_zzzi">CMLA (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="cmla_z_zzzi_s" iformfile="cmla_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="cmla_z_zzzi">CMLA (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qrdcmla_by_indexed_elem" title="SVE2 complex saturating multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qrdcmla_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="21*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_418" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdcmlah_z_zzzi_h" iformfile="sqrdcmlah_z_zzzi.xml" label="16-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="sqrdcmlah_z_zzzi">SQRDCMLAH (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdcmlah_z_zzzi_s" iformfile="sqrdcmlah_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="sqrdcmlah_z_zzzi">SQRDCMLAH (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mul_by_indexed_elem" title="SVE2 integer multiply (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mul_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mul_z_zzi_h" iformfile="mul_z_zzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname" iformid="mul_z_zzi">MUL (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mul_z_zzi_s" iformfile="mul_z_zzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="mul_z_zzi">MUL (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mul_z_zzi_d" iformfile="mul_z_zzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="mul_z_zzi">MUL (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mul_long_by_indexed_elem" title="SVE2 integer multiply long (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="il" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mul_long_by_indexed_elem" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_420" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullb_z_zzi_s" iformfile="smullb_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smullb_z_zzi">SMULLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullt_z_zzi_s" iformfile="smullt_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smullt_z_zzi">SMULLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullb_z_zzi_s" iformfile="umullb_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umullb_z_zzi">UMULLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullt_z_zzi_s" iformfile="umullt_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umullt_z_zzi">UMULLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullb_z_zzi_d" iformfile="smullb_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smullb_z_zzi">SMULLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullt_z_zzi_d" iformfile="smullt_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smullt_z_zzi">SMULLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullb_z_zzi_d" iformfile="umullb_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umullb_z_zzi">UMULLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullt_z_zzi_d" iformfile="umullt_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umullt_z_zzi">UMULLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mla_by_indexed_elem" title="SVE2 integer multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mla_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mla_z_zzzi_h" iformfile="mla_z_zzzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mla_z_zzzi">MLA (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mls_z_zzzi_h" iformfile="mls_z_zzzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mls_z_zzzi">MLS (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mla_z_zzzi_s" iformfile="mla_z_zzzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mla_z_zzzi">MLA (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mls_z_zzzi_s" iformfile="mls_z_zzzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mls_z_zzzi">MLS (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mla_z_zzzi_d" iformfile="mla_z_zzzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mla_z_zzzi">MLA (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mls_z_zzzi_d" iformfile="mls_z_zzzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mls_z_zzzi">MLS (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_mla_long_by_indexed_elem" title="SVE2 integer multiply-add long (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="il" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mla_long_by_indexed_elem" cols="6">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_419" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlalb_z_zzzi_s" iformfile="smlalb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlalb_z_zzzi">SMLALB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlalt_z_zzzi_s" iformfile="smlalt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlalt_z_zzzi">SMLALT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalb_z_zzzi_s" iformfile="umlalb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlalb_z_zzzi">UMLALB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalt_z_zzzi_s" iformfile="umlalt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlalt_z_zzzi">UMLALT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslb_z_zzzi_s" iformfile="smlslb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlslb_z_zzzi">SMLSLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslt_z_zzzi_s" iformfile="smlslt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlslt_z_zzzi">SMLSLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslb_z_zzzi_s" iformfile="umlslb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlslb_z_zzzi">UMLSLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslt_z_zzzi_s" iformfile="umlslt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlslt_z_zzzi">UMLSLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlalb_z_zzzi_d" iformfile="smlalb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlalb_z_zzzi">SMLALB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlalt_z_zzzi_d" iformfile="smlalt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlalt_z_zzzi">SMLALT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalb_z_zzzi_d" iformfile="umlalb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlalb_z_zzzi">UMLALB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlalt_z_zzzi_d" iformfile="umlalt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlalt_z_zzzi">UMLALT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslb_z_zzzi_d" iformfile="smlslb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlslb_z_zzzi">SMLSLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlslt_z_zzzi_d" iformfile="smlslt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlslt_z_zzzi">SMLSLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslb_z_zzzi_d" iformfile="umlslb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlslb_z_zzzi">UMLSLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlslt_z_zzzi_d" iformfile="umlslt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlslt_z_zzzi">UMLSLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qdmul_long_by_indexed_elem" title="SVE2 saturating multiply (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="il" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qdmul_long_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="20*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_421" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmullb_z_zzi_s" iformfile="sqdmullb_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmullb_z_zzi">SQDMULLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmullt_z_zzi_s" iformfile="sqdmullt_z_zzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmullt_z_zzi">SQDMULLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmullb_z_zzi_d" iformfile="sqdmullb_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmullb_z_zzi">SQDMULLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmullt_z_zzi_d" iformfile="sqdmullt_z_zzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmullt_z_zzi">SQDMULLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qdmulh_by_indexed_elem" title="SVE2 saturating multiply high (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qdmulh_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="20*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">R</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_z_zzi_h" iformfile="sqdmulh_z_zzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmulh_z_zzi">SQDMULH (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmulh_z_zzi_h" iformfile="sqrdmulh_z_zzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmulh_z_zzi">SQRDMULH (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmulh_z_zzi_s" iformfile="sqdmulh_z_zzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmulh_z_zzi">SQDMULH (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmulh_z_zzi_s" iformfile="sqrdmulh_z_zzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmulh_z_zzi">SQRDMULH (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmulh_z_zzi_d" iformfile="sqdmulh_z_zzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmulh_z_zzi">SQDMULH (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmulh_z_zzi_d" iformfile="sqrdmulh_z_zzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmulh_z_zzi">SQRDMULH (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qdmla_long_by_indexed_elem" title="SVE2 saturating multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="il" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qdmla_long_by_indexed_elem" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="20*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_415" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlalb_z_zzzi_s" iformfile="sqdmlalb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlalb_z_zzzi">SQDMLALB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlalt_z_zzzi_s" iformfile="sqdmlalt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlalt_z_zzzi">SQDMLALT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslb_z_zzzi_s" iformfile="sqdmlslb_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlslb_z_zzzi">SQDMLSLB (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslt_z_zzzi_s" iformfile="sqdmlslt_z_zzzi.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlslt_z_zzzi">SQDMLSLT (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlalb_z_zzzi_d" iformfile="sqdmlalb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlalb_z_zzzi">SQDMLALB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlalt_z_zzzi_d" iformfile="sqdmlalt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlalt_z_zzzi">SQDMLALT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslb_z_zzzi_d" iformfile="sqdmlslb_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmlslb_z_zzzi">SQDMLSLB (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmlslt_z_zzzi_d" iformfile="sqdmlslt_z_zzzi.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmlslt_z_zzzi">SQDMLSLT (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_qrdmlah_by_indexed_elem" title="SVE2 saturating multiply-add high (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_qrdmlah_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="20*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqrdmlah_z_zzzi_h" iformfile="sqrdmlah_z_zzzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrdmlah_z_zzzi">SQRDMLAH (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlsh_z_zzzi_h" iformfile="sqrdmlsh_z_zzzi.xml" label="16-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmlsh_z_zzzi">SQRDMLSH (indexed)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlah_z_zzzi_s" iformfile="sqrdmlah_z_zzzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrdmlah_z_zzzi">SQRDMLAH (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlsh_z_zzzi_s" iformfile="sqrdmlsh_z_zzzi.xml" label="32-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmlsh_z_zzzi">SQRDMLSH (indexed)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlah_z_zzzi_d" iformfile="sqrdmlah_z_zzzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrdmlah_z_zzzi">SQRDMLAH (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrdmlsh_z_zzzi_d" iformfile="sqrdmlsh_z_zzzi.xml" label="64-bit" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrdmlsh_z_zzzi">SQRDMLSH (indexed)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_cons_widening">SVE2 Widening Integer Arithmetic</funcgroupheader>
|
|
<iclass_sect id="sve_intx_cons_arith_long" title="SVE2 integer add/subtract long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cons_arith_long" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="saddlb_z_zz_" iformfile="saddlb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="saddlb_z_zz">SADDLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="saddlt_z_zz_" iformfile="saddlt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="saddlt_z_zz">SADDLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaddlb_z_zz_" iformfile="uaddlb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uaddlb_z_zz">UADDLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaddlt_z_zz_" iformfile="uaddlt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uaddlt_z_zz">UADDLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssublb_z_zz_" iformfile="ssublb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ssublb_z_zz">SSUBLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssublt_z_zz_" iformfile="ssublt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ssublt_z_zz">SSUBLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usublb_z_zz_" iformfile="usublb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usublb_z_zz">USUBLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usublt_z_zz_" iformfile="usublt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usublt_z_zz">USUBLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_424" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sabdlb_z_zz_" iformfile="sabdlb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sabdlb_z_zz">SABDLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sabdlt_z_zz_" iformfile="sabdlt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sabdlt_z_zz">SABDLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uabdlb_z_zz_" iformfile="uabdlb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uabdlb_z_zz">UABDLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uabdlt_z_zz_" iformfile="uabdlt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uabdlt_z_zz">UABDLT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cons_arith_wide" title="SVE2 integer add/subtract wide">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cons_arith_wide" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="saddwb_z_zz_" iformfile="saddwb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="saddwb_z_zz">SADDWB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="saddwt_z_zz_" iformfile="saddwt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="saddwt_z_zz">SADDWT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaddwb_z_zz_" iformfile="uaddwb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uaddwb_z_zz">UADDWB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaddwt_z_zz_" iformfile="uaddwt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uaddwt_z_zz">UADDWT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssubwb_z_zz_" iformfile="ssubwb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ssubwb_z_zz">SSUBWB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssubwt_z_zz_" iformfile="ssubwt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ssubwt_z_zz">SSUBWT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usubwb_z_zz_" iformfile="usubwb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usubwb_z_zz">USUBWB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usubwt_z_zz_" iformfile="usubwt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usubwt_z_zz">USUBWT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cons_mul_long" title="SVE2 integer multiply long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cons_mul_long" cols="6">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="20*" />
|
|
<col colno="6" printwidth="27*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmullb_z_zz_" iformfile="sqdmullb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqdmullb_z_zz">SQDMULLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqdmullt_z_zz_" iformfile="sqdmullt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqdmullt_z_zz">SQDMULLT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullb_z_zz_" iformfile="smullb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smullb_z_zz">SMULLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smullt_z_zz_" iformfile="smullt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smullt_z_zz">SMULLT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullb_z_zz_" iformfile="umullb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umullb_z_zz">UMULLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umullt_z_zz_" iformfile="umullt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umullt_z_zz">UMULLT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmullb_z_zz_" iformfile="pmullb_z_zz.xml" label="16-bit or 64-bit elements" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="pmullb_z_zz">PMULLB</td>
|
|
<td class="enctags">16-bit or 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmullt_z_zz_" iformfile="pmullt_z_zz.xml" label="16-bit or 64-bit elements" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="pmullt_z_zz">PMULLT</td>
|
|
<td class="enctags">16-bit or 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmullb_z_zz_q" arch_version="FEAT_SVE_PMULL128" iformfile="pmullb_z_zz.xml" label="128-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="pmullb_z_zz">PMULLB</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="pmullt_z_zz_q" arch_version="FEAT_SVE_PMULL128" iformfile="pmullt_z_zz.xml" label="128-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="pmullt_z_zz">PMULLT</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_constructive">SVE Misc</funcgroupheader>
|
|
<iclass_sect id="sve_intx_mmla" title="SVE integer matrix multiply accumulate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="uns" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_mmla" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">uns</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smmla_z_zzz_" arch_version="FEAT_I8MM" iformfile="smmla_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="smmla_z_zzz">SMMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_432" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmmla_z_zzz_" arch_version="FEAT_I8MM" iformfile="usmmla_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="usmmla_z_zzz">USMMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ummla_z_zzz_" arch_version="FEAT_I8MM" iformfile="ummla_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ummla_z_zzz">UMMLA</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_eorx" title="SVE2 bitwise exclusive-or interleaved">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="tb" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_eorx" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">tb</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="eorbt_z_zz_" iformfile="eorbt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="eorbt_z_zz">EORBT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="eortb_z_zz_" iformfile="eortb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="eortb_z_zz">EORTB</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_perm_bit" title="SVE2 bitwise permute">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_perm_bit" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="bext_z_zz_" arch_version="FEAT_SVE_BitPerm" iformfile="bext_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bext_z_zz">BEXT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bdep_z_zz_" arch_version="FEAT_SVE_BitPerm" iformfile="bdep_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="bdep_z_zz">BDEP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bgrp_z_zz_" arch_version="FEAT_SVE_BitPerm" iformfile="bgrp_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="bgrp_z_zz">BGRP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_426" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_shift_long" title="SVE2 bitwise shift left long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_shift_long" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sshllb_z_zi_" iformfile="sshllb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sshllb_z_zi">SSHLLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sshllt_z_zi_" iformfile="sshllt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sshllt_z_zi">SSHLLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ushllb_z_zi_" iformfile="ushllb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ushllb_z_zi">USHLLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ushllt_z_zi_" iformfile="ushllt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ushllt_z_zi">USHLLT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_clong" title="SVE2 integer add/subtract interleaved long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="tb" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_clong" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">tb</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="saddlbt_z_zz_" iformfile="saddlbt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="saddlbt_z_zz">SADDLBT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_425" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssublbt_z_zz_" iformfile="ssublbt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ssublbt_z_zz">SSUBLBT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ssubltb_z_zz_" iformfile="ssubltb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ssubltb_z_zz">SSUBLTB</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_acc">SVE2 Accumulate</funcgroupheader>
|
|
<iclass_sect id="sve_intx_shift_insert" title="SVE2 bitwise shift and insert">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tszh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_shift_insert" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sri_z_zzi_" iformfile="sri_z_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sri_z_zzi">SRI</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sli_z_zzi_" iformfile="sli_z_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sli_z_zzi">SLI</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_sra" title="SVE2 bitwise shift right and accumulate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tszh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_sra" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ssra_z_zi_" iformfile="ssra_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ssra_z_zi">SSRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usra_z_zi_" iformfile="usra_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usra_z_zi">USRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srsra_z_zi_" iformfile="srsra_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srsra_z_zi">SRSRA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ursra_z_zi_" iformfile="ursra_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ursra_z_zi">URSRA</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_cadd" title="SVE2 complex integer add">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="rot" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_cadd" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="cadd_z_zz_" iformfile="cadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="cadd_z_zz">CADD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcadd_z_zz_" iformfile="sqcadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqcadd_z_zz">SQCADD</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_aba" title="SVE2 integer absolute difference and accumulate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_aba" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="saba_z_zzz_" iformfile="saba_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="saba_z_zzz">SABA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uaba_z_zzz_" iformfile="uaba_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uaba_z_zzz">UABA</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_aba_long" title="SVE2 integer absolute difference and accumulate long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_aba_long" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sabalb_z_zzz_" iformfile="sabalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sabalb_z_zzz">SABALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sabalt_z_zzz_" iformfile="sabalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sabalt_z_zzz">SABALT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uabalb_z_zzz_" iformfile="uabalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uabalb_z_zzz">UABALB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uabalt_z_zzz_" iformfile="uabalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uabalt_z_zzz">UABALT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_adc_long" title="SVE2 integer add/subtract long with carry">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_adc_long" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="adclb_z_zzz_" iformfile="adclb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="adclb_z_zzz">ADCLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="adclt_z_zzz_" iformfile="adclt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="adclt_z_zzz">ADCLT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sbclb_z_zzz_" iformfile="sbclb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sbclb_z_zzz">SBCLB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sbclt_z_zzz_" iformfile="sbclt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sbclt_z_zzz">SBCLT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_narrowing">SVE2 Narrowing</funcgroupheader>
|
|
<iclass_sect id="sve_intx_multi_extract_narrow" title="SME2 multi-vec extract narrow">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_multi_extract_narrow" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="5*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">tszh</th>
|
|
<th class="bitfields">tszl</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_428" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtn_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="sqcvtn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="sqcvtn_z_mz2">SQCVTN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqcvtn_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="uqcvtn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="uqcvtn_z_mz2">UQCVTN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtun_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="sqcvtun_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="sqcvtun_z_mz2">SQCVTUN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_430" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_431" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_435" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_multi_shift_narrow" title="SME2 multi-vec shift narrow">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" name="tszl" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_multi_shift_narrow" cols="7">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="3*" />
|
|
<col colno="6" printwidth="18*" />
|
|
<col colno="7" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="5">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">tszh</th>
|
|
<th class="bitfields">tszl</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">R</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_437" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_441" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrun_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="sqrshrun_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrshrun_z_mz2">SQRSHRUN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_442" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_443" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrn_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="sqrshrn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrshrn_z_mz2">SQRSHRN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshrn_z_mz2_" arch_version="FEAT_SVE2p1" iformfile="uqrshrn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshrn_z_mz2">UQRSHRN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_444" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_shift_narrow" title="SVE2 bitwise shift right narrow">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_shift_narrow" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="3*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<col colno="6" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqshrunb_z_zi_" iformfile="sqshrunb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqshrunb_z_zi">SQSHRUNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshrunt_z_zi_" iformfile="sqshrunt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqshrunt_z_zi">SQSHRUNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrunb_z_zi_" iformfile="sqrshrunb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshrunb_z_zi">SQRSHRUNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrunt_z_zi_" iformfile="sqrshrunt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrshrunt_z_zi">SQRSHRUNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="shrnb_z_zi_" iformfile="shrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="shrnb_z_zi">SHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="shrnt_z_zi_" iformfile="shrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="shrnt_z_zi">SHRNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rshrnb_z_zi_" iformfile="rshrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="rshrnb_z_zi">RSHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rshrnt_z_zi_" iformfile="rshrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="rshrnt_z_zi">RSHRNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshrnb_z_zi_" iformfile="sqshrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqshrnb_z_zi">SQSHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqshrnt_z_zi_" iformfile="sqshrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqshrnt_z_zi">SQSHRNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrnb_z_zi_" iformfile="sqrshrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshrnb_z_zi">SQRSHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrnt_z_zi_" iformfile="sqrshrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqrshrnt_z_zi">SQRSHRNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqshrnb_z_zi_" iformfile="uqshrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqshrnb_z_zi">UQSHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqshrnt_z_zi_" iformfile="uqshrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqshrnt_z_zi">UQSHRNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshrnb_z_zi_" iformfile="uqrshrnb_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqrshrnb_z_zi">UQRSHRNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshrnt_z_zi_" iformfile="uqrshrnt_z_zi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshrnt_z_zi">UQRSHRNT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_arith_narrow" title="SVE2 integer add/subtract narrow high part">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_arith_narrow" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">R</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="addhnb_z_zz_" iformfile="addhnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="addhnb_z_zz">ADDHNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addhnt_z_zz_" iformfile="addhnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="addhnt_z_zz">ADDHNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="raddhnb_z_zz_" iformfile="raddhnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="raddhnb_z_zz">RADDHNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="raddhnt_z_zz_" iformfile="raddhnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="raddhnt_z_zz">RADDHNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="subhnb_z_zz_" iformfile="subhnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="subhnb_z_zz">SUBHNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="subhnt_z_zz_" iformfile="subhnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="subhnt_z_zz">SUBHNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rsubhnb_z_zz_" iformfile="rsubhnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="rsubhnb_z_zz">RSUBHNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rsubhnt_z_zz_" iformfile="rsubhnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="rsubhnt_z_zz">RSUBHNT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_intx_extract_narrow" title="SVE2 saturating extract narrow">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="tszh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="tszl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_extract_narrow" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqxtnb_z_zz_" iformfile="sqxtnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqxtnb_z_zz">SQXTNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqxtnt_z_zz_" iformfile="sqxtnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqxtnt_z_zz">SQXTNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqxtnb_z_zz_" iformfile="uqxtnb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="uqxtnb_z_zz">UQXTNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqxtnt_z_zz_" iformfile="uqxtnt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqxtnt_z_zz">UQXTNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqxtunb_z_zz_" iformfile="sqxtunb_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqxtunb_z_zz">SQXTUNB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqxtunt_z_zz_" iformfile="sqxtunt_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sqxtunt_z_zz">SQXTUNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_427" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_string">SVE2 String Processing</funcgroupheader>
|
|
<iclass_sect id="sve_intx_match" title="SVE2 character match">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_match" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="match_p_p_zz_" iformfile="match_p_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="match_p_p_zz">MATCH</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="nmatch_p_p_zz_" iformfile="nmatch_p_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="nmatch_p_p_zz">NMATCH</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_histseg">SVE2 Histogram Computation - Segment</funcgroupheader>
|
|
<iclass_sect id="sve_intx_histseg" title="SVE2 histogram generation (segment)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_histseg" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="histseg_z_zz_" iformfile="histseg_z_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="histseg_z_zz">HISTSEG</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_histcnt">SVE2 Histogram Computation - Vector</funcgroupheader>
|
|
<iclass_sect id="sve_intx_histcnt" title="SVE2 histogram generation (vector)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_intx_histcnt" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="histcnt_z_p_zz_" iformfile="histcnt_z_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="histcnt_z_p_zz">HISTCNT</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_intx_crypto">SVE2 Crypto Extensions</funcgroupheader>
|
|
<iclass_sect id="sve_crypto_binary_const" title="SVE2 crypto constructive binary operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_crypto_binary_const" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sm4ekey_z_zz_" arch_version="FEAT_SVE_SM4" iformfile="sm4ekey_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sm4ekey_z_zz">SM4EKEY</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="rax1_z_zz_" arch_version="FEAT_SVE_SHA3" iformfile="rax1_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="rax1_z_zz">RAX1</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_434" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_439" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_crypto_binary_dest" title="SVE2 crypto destructive binary operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_crypto_binary_dest" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="aese_z_zz_" arch_version="FEAT_SVE_AES" iformfile="aese_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="aese_z_zz">AESE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="aesd_z_zz_" arch_version="FEAT_SVE_AES" iformfile="aesd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="aesd_z_zz">AESD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sm4e_z_zz_" arch_version="FEAT_SVE_SM4" iformfile="sm4e_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sm4e_z_zz">SM4E</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_429" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_436" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_440" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_crypto_unary" title="SVE2 crypto unary operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_crypto_unary" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="aesmc_z_z_" arch_version="FEAT_SVE_AES" iformfile="aesmc_z_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="aesmc_z_z">AESMC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="aesimc_z_z_" arch_version="FEAT_SVE_AES" iformfile="aesimc_z_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="aesimc_z_z">AESIMC</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_433" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_438" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fcadd">SVE Floating Point Complex Addition</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fcadd" title="SVE floating-point complex add (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="rot" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fcadd" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcadd_z_p_zz_" iformfile="fcadd_z_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="fcadd_z_p_zz">FCADD</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fcvt2">SVE Floating Point Convert Precision Odd Elements</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fcvt2" title="SVE floating-point convert precision odd elements">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fcvt2" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="38*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_446" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_445" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtxnt_z_p_z_d2s" iformfile="fcvtxnt_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fcvtxnt_z_p_z">FCVTXNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_454" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtnt_z_p_z_s2h" iformfile="fcvtnt_z_p_z.xml" label="single-precision to half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fcvtnt_z_p_z">FCVTNT</td>
|
|
<td class="enctags">Single-precision to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtlt_z_p_z_h2s" iformfile="fcvtlt_z_p_z.xml" label="half-precision to single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fcvtlt_z_p_z">FCVTLT</td>
|
|
<td class="enctags">Half-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfcvtnt_z_p_z_s2bf" arch_version="FEAT_BF16" iformfile="bfcvtnt_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="bfcvtnt_z_p_z">BFCVTNT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_459" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtnt_z_p_z_d2s" iformfile="fcvtnt_z_p_z.xml" label="double-precision to single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fcvtnt_z_p_z">FCVTNT</td>
|
|
<td class="enctags">Double-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtlt_z_p_z_s2d" iformfile="fcvtlt_z_p_z.xml" label="single-precision to double-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fcvtlt_z_p_z">FCVTLT</td>
|
|
<td class="enctags">Single-precision to double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_pairwise">SVE2 Floating Point Pairwise</funcgroupheader>
|
|
<iclass_sect id="sve_fp_pairwise" title="SVE2 floating-point pairwise operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_pairwise" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="faddp_z_p_zz_" iformfile="faddp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="faddp_z_p_zz">FADDP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_447" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_449" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnmp_z_p_zz_" iformfile="fmaxnmp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="fmaxnmp_z_p_zz">FMAXNMP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnmp_z_p_zz_" iformfile="fminnmp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="fminnmp_z_p_zz">FMINNMP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxp_z_p_zz_" iformfile="fmaxp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="fmaxp_z_p_zz">FMAXP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminp_z_p_zz_" iformfile="fminp_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="fminp_z_p_zz">FMINP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fastreduceq">sve_fp_fastreduceq</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fast_redq" title="SVE floating-point recursive reduction (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fast_redq" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="faddqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="faddqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="faddqv_z_p_z">FADDQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_448" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_450" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnmqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="fmaxnmqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="fmaxnmqv_z_p_z">FMAXNMQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnmqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="fminnmqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="fminnmqv_z_p_z">FMINNMQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="fmaxqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="fmaxqv_z_p_z">FMAXQV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminqv_z_p_z_" arch_version="FEAT_SVE2p1" iformfile="fminqv_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="fminqv_z_p_z">FMINQV</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fcmla">SVE Floating Point Complex Multiply-Add</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fcmla" title="SVE floating-point complex multiply-add (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fcmla" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcmla_z_p_zzz_" iformfile="fcmla_z_p_zzz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="fcmla_z_p_zzz">FCMLA (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fma_by_indexed_elem">SVE Floating Point Multiply-Add - Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fma_by_indexed_elem" title="SVE floating-point multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fma_by_indexed_elem" cols="5">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_z_zzzi_h" iformfile="fmla_z_zzzi.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_z_zzzi">FMLA (indexed)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_z_zzzi_h" iformfile="fmls_z_zzzi.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_z_zzzi">FMLS (indexed)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_z_zzzi_h" arch_version="FEAT_B16B16" iformfile="bfmla_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_z_zzzi">BFMLA (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_z_zzzi_h" arch_version="FEAT_B16B16" iformfile="bfmls_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_z_zzzi">BFMLS (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_457" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmla_z_zzzi_s" iformfile="fmla_z_zzzi.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_z_zzzi">FMLA (indexed)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_z_zzzi_s" iformfile="fmls_z_zzzi.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_z_zzzi">FMLS (indexed)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmla_z_zzzi_d" iformfile="fmla_z_zzzi.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_z_zzzi">FMLA (indexed)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_z_zzzi_d" iformfile="fmls_z_zzzi.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_z_zzzi">FMLS (indexed)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fcmla_by_indexed_elem">SVE Floating Point Complex Multiply-Add - Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fcmla_by_indexed_elem" title="SVE floating-point complex multiply-add (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="rot" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fcmla_by_indexed_elem" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_451" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmla_z_zzzi_h" iformfile="fcmla_z_zzzi.xml" label="half-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fcmla_z_zzzi">FCMLA (indexed)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmla_z_zzzi_s" iformfile="fcmla_z_zzzi.xml" label="single-precision" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fcmla_z_zzzi">FCMLA (indexed)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_clamp">sve_fp_clamp</funcgroupheader>
|
|
<iclass_sect id="sve_fp_clamp" title="SVE FP clamp">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_clamp" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fclamp_z_zz_" arch_version="FEAT_SVE2p1" iformfile="fclamp_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td class="iformname" iformid="fclamp_z_zz">FCLAMP</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfclamp_z_zz_" arch_version="FEAT_B16B16" iformfile="bfclamp_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bfclamp_z_zz">BFCLAMP</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fmul_by_indexed_elem">SVE Floating Point Multiply - Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fmul_by_indexed_elem" title="SVE floating-point multiply (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fmul_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmul_z_zzi_h" iformfile="fmul_z_zzi.xml" label="half-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmul_z_zzi">FMUL (indexed)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmul_z_zzi_h" arch_version="FEAT_B16B16" iformfile="bfmul_z_zzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmul_z_zzi">BFMUL (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_458" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmul_z_zzi_s" iformfile="fmul_z_zzi.xml" label="single-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmul_z_zzi">FMUL (indexed)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmul_z_zzi_d" iformfile="fmul_z_zzi.xml" label="double-precision" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmul_z_zzi">FMUL (indexed)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fma_w_by_indexed_elem">SVE Floating Point Widening Multiply-Add - Indexed</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fdot_by_indexed_elem" title="SVE BFloat16 floating-point dot product (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="i2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fdot_by_indexed_elem" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_z_zzzi_" arch_version="FEAT_SVE2p1" iformfile="fdot_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fdot_z_zzzi">FDOT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_z_zzzi_" arch_version="FEAT_BF16" iformfile="bfdot_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bfdot_z_zzzi">BFDOT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_455" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_fma_long_by_indexed_elem" title="SVE floating-point multiply-add long (indexed)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="18" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fma_long_by_indexed_elem" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="19*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlalb_z_zzzi_s" iformfile="fmlalb_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlalb_z_zzzi">FMLALB (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlalt_z_zzzi_s" iformfile="fmlalt_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlalt_z_zzzi">FMLALT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlslb_z_zzzi_s" iformfile="fmlslb_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlslb_z_zzzi">FMLSLB (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlslt_z_zzzi_s" iformfile="fmlslt_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlslt_z_zzzi">FMLSLT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlalb_z_zzzi_" arch_version="FEAT_BF16" iformfile="bfmlalb_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlalb_z_zzzi">BFMLALB (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlalt_z_zzzi_" arch_version="FEAT_BF16" iformfile="bfmlalt_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlalt_z_zzzi">BFMLALT (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlslb_z_zzzi_" arch_version="FEAT_SVE2p1" iformfile="bfmlslb_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlslb_z_zzzi">BFMLSLB (indexed)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlslt_z_zzzi_" arch_version="FEAT_SVE2p1" iformfile="bfmlslt_z_zzzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlslt_z_zzzi">BFMLSLT (indexed)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fma_w">SVE Floating Point Widening Multiply-Add</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fdot" title="SVE BFloat16 floating-point dot product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fdot" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">o3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_z_zzz_" arch_version="FEAT_SVE2p1" iformfile="fdot_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fdot_z_zzz">FDOT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_452" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_z_zzz_" arch_version="FEAT_BF16" iformfile="bfdot_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfdot_z_zzz">BFDOT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_456" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_fma_long" title="SVE floating-point multiply-add long">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="T" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fma_long" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="19*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">T</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlalb_z_zzz_" iformfile="fmlalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlalb_z_zzz">FMLALB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlalt_z_zzz_" iformfile="fmlalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlalt_z_zzz">FMLALT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlslb_z_zzz_" iformfile="fmlslb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlslb_z_zzz">FMLSLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlslt_z_zzz_" iformfile="fmlslt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlslt_z_zzz">FMLSLT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlalb_z_zzz_" arch_version="FEAT_BF16" iformfile="bfmlalb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlalb_z_zzz">BFMLALB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlalt_z_zzz_" arch_version="FEAT_BF16" iformfile="bfmlalt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlalt_z_zzz">BFMLALT (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlslb_z_zzz_" arch_version="FEAT_SVE2p1" iformfile="bfmlslb_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlslb_z_zzz">BFMLSLB (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlslt_z_zzz_" arch_version="FEAT_SVE2p1" iformfile="bfmlslt_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlslt_z_zzz">BFMLSLT (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fmmla">SVE Floating Point Matrix Multiply Accumulate</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fmmla" title="SVE floating point matrix multiply accumulate">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fmmla" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_453" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmmla_z_zzz_" arch_version="FEAT_BF16" iformfile="bfmmla_z_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="bfmmla_z_zzz">BFMMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmmla_z_zzz_s" arch_version="FEAT_F32MM" iformfile="fmmla_z_zzz.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fmmla_z_zzz">FMMLA</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmmla_z_zzz_d" arch_version="FEAT_F64MM" iformfile="fmmla_z_zzz.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fmmla_z_zzz">FMMLA</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fastreduce">SVE Floating Point Fast Reduction</funcgroupheader>
|
|
<iclass_sect id="sve_fp_fast_red" title="SVE floating-point recursive reduction">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_fast_red" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="faddv_v_p_z_" iformfile="faddv_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="faddv_v_p_z">FADDV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_462" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_463" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnmv_v_p_z_" iformfile="fmaxnmv_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="fmaxnmv_v_p_z">FMAXNMV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnmv_v_p_z_" iformfile="fminnmv_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="fminnmv_v_p_z">FMINNMV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxv_v_p_z_" iformfile="fmaxv_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="fmaxv_v_p_z">FMAXV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminv_v_p_z_" iformfile="fminv_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="fminv_v_p_z">FMINV</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_unary_unpred">SVE Floating Point Unary Operations - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_fp_2op_u_zd" title="SVE floating-point reciprocal estimate (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_u_zd" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_465" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_469" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frecpe_z_z_" iformfile="frecpe_z_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="frecpe_z_z">FRECPE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frsqrte_z_z_" iformfile="frsqrte_z_z.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="frsqrte_z_z">FRSQRTE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_cmpzero">SVE Floating Point Compare - with Zero</funcgroupheader>
|
|
<iclass_sect id="sve_fp_2op_p_pd" title="SVE floating-point compare with zero">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" name="eq" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="16" name="lt" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="ne" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_pd" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">eq</th>
|
|
<th class="bitfields">lt</th>
|
|
<th class="bitfields">ne</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcmge_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMGE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmgt_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMGT" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmlt_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMLT" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Less than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmle_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMLE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Less than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_472" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmeq_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMEQ" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmne_p_p_z0_" iformfile="fcmeq_p_p_z0.xml" label="FCMNE" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_z0">FCM<cc> (zero)</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_slowreduce">SVE Floating Point Accumulating Reduction</funcgroupheader>
|
|
<iclass_sect id="sve_fp_2op_p_vd" title="SVE floating-point serial reduction (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Vdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_vd" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadda_v_p_z_" iformfile="fadda_v_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fadda_v_p_z">FADDA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_473" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_475" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_unpred">SVE Floating Point Arithmetic - Unpredicated</funcgroupheader>
|
|
<iclass_sect id="sve_fp_3op_u_zd" title="SVE floating-point arithmetic (unpredicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_3op_u_zd" cols="4">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="31*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ftsmul_z_zz_" iformfile="ftsmul_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="ftsmul_z_zz">FTSMUL</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_460" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">10x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frecps_z_zz_" iformfile="frecps_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="frecps_z_zz">FRECPS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frsqrts_z_zz_" iformfile="frsqrts_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="frsqrts_z_zz">FRSQRTS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fadd_z_zz_" iformfile="fadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="fadd_z_zz">FADD (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_z_zz_" iformfile="fsub_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="fsub_z_zz">FSUB (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmul_z_zz_" iformfile="fmul_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="fmul_z_zz">FMUL (vectors, unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfadd_z_zz_" arch_version="FEAT_B16B16" iformfile="bfadd_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="bfadd_z_zz">BFADD (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfsub_z_zz_" arch_version="FEAT_B16B16" iformfile="bfsub_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="bfsub_z_zz">BFSUB (unpredicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmul_z_zz_" arch_version="FEAT_B16B16" iformfile="bfmul_z_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="bfmul_z_zz">BFMUL (vectors, unpredicated)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_pred">SVE Floating Point Arithmetic - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_fp_2op_p_zds" title="SVE floating-point arithmetic (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zds" cols="4">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fsubr_z_p_zz_" iformfile="fsubr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="fsubr_z_p_zz">FSUBR (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fabd_z_p_zz_" iformfile="fabd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="fabd_z_p_zz">FABD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fscale_z_p_zz_" iformfile="fscale_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="fscale_z_p_zz">FSCALE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmulx_z_p_zz_" iformfile="fmulx_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="fmulx_z_p_zz">FMULX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_467" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fdivr_z_p_zz_" iformfile="fdivr_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="fdivr_z_p_zz">FDIVR</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fdiv_z_p_zz_" iformfile="fdiv_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="fdiv_z_p_zz">FDIV</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fadd_z_p_zz_" iformfile="fadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="fadd_z_p_zz">FADD (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_z_p_zz_" iformfile="fsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="fsub_z_p_zz">FSUB (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmul_z_p_zz_" iformfile="fmul_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="fmul_z_p_zz">FMUL (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_z_p_zz_" iformfile="fmaxnm_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="fmaxnm_z_p_zz">FMAXNM (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_z_p_zz_" iformfile="fminnm_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="fminnm_z_p_zz">FMINNM (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmax_z_p_zz_" iformfile="fmax_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="fmax_z_p_zz">FMAX (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_z_p_zz_" iformfile="fmin_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="fmin_z_p_zz">FMIN (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfadd_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfadd_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="bfadd_z_p_zz">BFADD (predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfsub_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfsub_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="bfsub_z_p_zz">BFSUB (predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmul_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfmul_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="bfmul_z_p_zz">BFMUL (vectors, predicated)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmaxnm_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfmaxnm_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="bfmaxnm_z_p_zz">BFMAXNM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfminnm_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfminnm_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="bfminnm_z_p_zz">BFMINNM</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmax_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfmax_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="bfmax_z_p_zz">BFMAX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmin_z_p_zz_" arch_version="FEAT_B16B16" iformfile="bfmin_z_p_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="bfmin_z_p_zz">BFMIN</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_2op_i_p_zds" title="SVE floating-point arithmetic with immediate (predicated)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="i1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_i_p_zds" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="20*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadd_z_p_zs_" iformfile="fadd_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="fadd_z_p_zs">FADD (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_z_p_zs_" iformfile="fsub_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="fsub_z_p_zs">FSUB (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmul_z_p_zs_" iformfile="fmul_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="fmul_z_p_zs">FMUL (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsubr_z_p_zs_" iformfile="fsubr_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="fsubr_z_p_zs">FSUBR (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_z_p_zs_" iformfile="fmaxnm_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="fmaxnm_z_p_zs">FMAXNM (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_z_p_zs_" iformfile="fminnm_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="fminnm_z_p_zs">FMINNM (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmax_z_p_zs_" iformfile="fmax_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="fmax_z_p_zs">FMAX (immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_z_p_zs_" iformfile="fmin_z_p_zs.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="fmin_z_p_zs">FMIN (immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_ftmad" title="SVE floating-point trig multiply-add coefficient">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_ftmad" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ftmad_z_zzi_" iformfile="ftmad_z_zzi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ftmad_z_zzi">FTMAD</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_unary">SVE Floating Point Unary Operations - Predicated</funcgroupheader>
|
|
<iclass_sect id="sve_fp_2op_p_zd_b_0" title="SVE floating-point convert precision">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zd_b_0" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="38*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_468" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_466" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtx_z_p_z_d2s" iformfile="fcvtx_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fcvtx_z_p_z">FCVTX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_476" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_s2h" iformfile="fcvt_z_p_z.xml" label="single-precision to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Single-precision to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_h2s" iformfile="fcvt_z_p_z.xml" label="half-precision to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Half-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfcvt_z_p_z_s2bf" arch_version="FEAT_BF16" iformfile="bfcvt_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="bfcvt_z_p_z">BFCVT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_d2h" iformfile="fcvt_z_p_z.xml" label="double-precision to half-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Double-precision to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_h2d" iformfile="fcvt_z_p_z.xml" label="half-precision to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Half-precision to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_d2s" iformfile="fcvt_z_p_z.xml" label="double-precision to single-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Double-precision to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvt_z_p_z_s2d" iformfile="fcvt_z_p_z.xml" label="single-precision to double-precision" oneofthismnem="6" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fcvt_z_p_z">FCVT</td>
|
|
<td class="enctags">Single-precision to double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_2op_p_zd_d" title="SVE floating-point convert to integer">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zd_d" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="flogb_z_p_z_" iformfile="flogb_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="flogb_z_p_z">FLOGB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_474" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_478" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_fp162h" iformfile="fcvtzs_z_p_z.xml" label="half-precision to 16-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Half-precision to 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_fp162h" iformfile="fcvtzu_z_p_z.xml" label="half-precision to 16-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Half-precision to 16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_fp162w" iformfile="fcvtzs_z_p_z.xml" label="half-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_fp162w" iformfile="fcvtzu_z_p_z.xml" label="half-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Half-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_fp162x" iformfile="fcvtzs_z_p_z.xml" label="half-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_fp162x" iformfile="fcvtzu_z_p_z.xml" label="half-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Half-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_481" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_s2w" iformfile="fcvtzs_z_p_z.xml" label="single-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_s2w" iformfile="fcvtzu_z_p_z.xml" label="single-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Single-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_482" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_d2w" iformfile="fcvtzs_z_p_z.xml" label="double-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_d2w" iformfile="fcvtzu_z_p_z.xml" label="double-precision to 32-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Double-precision to 32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_484" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_s2x" iformfile="fcvtzs_z_p_z.xml" label="single-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_s2x" iformfile="fcvtzu_z_p_z.xml" label="single-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Single-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzs_z_p_z_d2x" iformfile="fcvtzs_z_p_z.xml" label="double-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_z_p_z">FCVTZS</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_z_p_z_d2x" iformfile="fcvtzu_z_p_z.xml" label="double-precision to 64-bit" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_z_p_z">FCVTZU</td>
|
|
<td class="enctags">Double-precision to 64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_2op_p_zd_a" title="SVE floating-point round to integral value">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zd_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="33*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="frintn_z_p_z_" iformfile="frinta_z_p_z.xml" label="nearest with ties to even" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Nearest with ties to even</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintp_z_p_z_" iformfile="frinta_z_p_z.xml" label="toward plus infinity" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Toward plus infinity</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintm_z_p_z_" iformfile="frinta_z_p_z.xml" label="toward minus infinity" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Toward minus infinity</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintz_z_p_z_" iformfile="frinta_z_p_z.xml" label="toward zero" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Toward zero</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frinta_z_p_z_" iformfile="frinta_z_p_z.xml" label="nearest with ties to away" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Nearest with ties to away</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_464" undef="1" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintx_z_p_z_" iformfile="frinta_z_p_z.xml" label="current mode signalling inexact" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Current mode signalling inexact</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frinti_z_p_z_" iformfile="frinta_z_p_z.xml" label="current mode" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="frinta_z_p_z">FRINT<r></td>
|
|
<td class="enctags">Current mode</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_2op_p_zd_b_1" title="SVE floating-point unary operations">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zd_b_1" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="frecpx_z_p_z_" iformfile="frecpx_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="frecpx_z_p_z">FRECPX</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsqrt_z_p_z_" iformfile="fsqrt_z_p_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fsqrt_z_p_z">FSQRT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_470" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_2op_p_zd_c" title="SVE integer convert to floating-point">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="16" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_2op_p_zd_c" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_471" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_477" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_h2fp16" iformfile="scvtf_z_p_z.xml" label="16-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">16-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_h2fp16" iformfile="ucvtf_z_p_z.xml" label="16-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">16-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_w2fp16" iformfile="scvtf_z_p_z.xml" label="32-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_w2fp16" iformfile="ucvtf_z_p_z.xml" label="32-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">32-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_x2fp16" iformfile="scvtf_z_p_z.xml" label="64-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_x2fp16" iformfile="ucvtf_z_p_z.xml" label="64-bit to half-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">64-bit to half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_479" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_w2s" iformfile="scvtf_z_p_z.xml" label="32-bit to single-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_w2s" iformfile="ucvtf_z_p_z.xml" label="32-bit to single-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">32-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_480" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_w2d" iformfile="scvtf_z_p_z.xml" label="32-bit to double-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_w2d" iformfile="ucvtf_z_p_z.xml" label="32-bit to double-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">32-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_483" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_x2s" iformfile="scvtf_z_p_z.xml" label="64-bit to single-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_x2s" iformfile="ucvtf_z_p_z.xml" label="64-bit to single-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">64-bit to single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="scvtf_z_p_z_x2d" iformfile="scvtf_z_p_z.xml" label="64-bit to double-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_z_p_z">SCVTF</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_z_p_z_x2d" iformfile="ucvtf_z_p_z.xml" label="64-bit to double-precision" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_z_p_z">UCVTF</td>
|
|
<td class="enctags">64-bit to double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_cmpvev">SVE Floating Point Compare - Vectors</funcgroupheader>
|
|
<iclass_sect id="sve_fp_3op_p_pd" title="SVE floating-point compare vectors">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="o3" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_3op_p_pd" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="19*" />
|
|
<col colno="5" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
<th class="bitfields">o3</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcmge_p_p_zz_" iformfile="fcmeq_p_p_zz.xml" label="FCMGE" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_zz">FCM<cc> (vectors)</td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmgt_p_p_zz_" iformfile="fcmeq_p_p_zz.xml" label="FCMGT" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_zz">FCM<cc> (vectors)</td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmeq_p_p_zz_" iformfile="fcmeq_p_p_zz.xml" label="FCMEQ" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_zz">FCM<cc> (vectors)</td>
|
|
<td class="enctags">Equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmne_p_p_zz_" iformfile="fcmeq_p_p_zz.xml" label="FCMNE" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_zz">FCM<cc> (vectors)</td>
|
|
<td class="enctags">Not equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcmuo_p_p_zz_" iformfile="fcmeq_p_p_zz.xml" label="FCMUO" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcmeq_p_p_zz">FCM<cc> (vectors)</td>
|
|
<td class="enctags">Unordered</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="facge_p_p_zz_" iformfile="facge_p_p_zz.xml" label="FACGE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="facge_p_p_zz">FAC<cc></td>
|
|
<td class="enctags">Greater than or equal</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_461" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="facgt_p_p_zz_" iformfile="facge_p_p_zz.xml" label="FACGT" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="facge_p_p_zz">FAC<cc></td>
|
|
<td class="enctags">Greater than</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_fp_fma">SVE Floating Point Multiply-Add</funcgroupheader>
|
|
<iclass_sect id="sve_fp_3op_p_zds_a" title="SVE floating-point multiply-accumulate writing addend">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zda" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_3op_p_zds_a" cols="4">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fnmla_z_p_zzz_" iformfile="fnmla_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fnmla_z_p_zzz">FNMLA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fnmls_z_p_zzz_" iformfile="fnmls_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fnmls_z_p_zzz">FNMLS</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmla_z_p_zzz_" iformfile="fmla_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fmla_z_p_zzz">FMLA (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_z_p_zzz_" iformfile="fmls_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fmls_z_p_zzz">FMLS (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_z_p_zzz_" arch_version="FEAT_B16B16" iformfile="bfmla_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bfmla_z_p_zzz">BFMLA (vectors)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_z_p_zzz_" arch_version="FEAT_B16B16" iformfile="bfmls_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="bfmls_z_p_zzz">BFMLS (vectors)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_fp_3op_p_zds_b" title="SVE floating-point multiply-accumulate writing multiplicand">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Za" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zdn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_fp_3op_p_zds_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmad_z_p_zzz_" iformfile="fmad_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fmad_z_p_zzz">FMAD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmsb_z_p_zzz_" iformfile="fmsb_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="fmsb_z_p_zzz">FMSB</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fnmad_z_p_zzz_" iformfile="fnmad_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fnmad_z_p_zzz">FNMAD</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fnmsb_z_p_zzz_" iformfile="fnmsb_z_p_zzz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="fnmsb_z_p_zzz">FNMSB</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_mem32">SVE Memory - 32-bit Gather and Unsized Contiguous</funcgroupheader>
|
|
<iclass_sect id="sve_mem_32b_gld_vs" title="SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="opc" usename="1" settings="2" constraint="!= 11">
|
|
<c colspan="2">!= 11</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="11" />
|
|
<decode_constraint name="opc" op="!=" val="11" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_32b_gld_vs" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bz_s_x32_unscaled" iformfile="ld1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bz">LD1SB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_bz_s_x32_unscaled" iformfile="ldff1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_bz">LDFF1SB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bz_s_x32_unscaled" iformfile="ld1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bz">LD1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_bz_s_x32_unscaled" iformfile="ldff1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_bz">LDFF1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_s_x32_unscaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_s_x32_unscaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_s_x32_unscaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_s_x32_unscaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_485" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_s_x32_unscaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_s_x32_unscaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_gld_vi" title="SVE 32-bit gather load (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_gld_vi" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="33*" />
|
|
<col colno="5" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_ai_s" iformfile="ld1sb_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_ai">LD1SB (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_ai_s" iformfile="ldff1sb_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_ai">LDFF1SB (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_ai_s" iformfile="ld1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_z_p_ai">LD1B (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_ai_s" iformfile="ldff1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_ai">LDFF1B (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_ai_s" iformfile="ld1sh_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_ai">LD1SH (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_ai_s" iformfile="ldff1sh_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_ai">LDFF1SH (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_ai_s" iformfile="ld1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_ai">LD1H (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_ai_s" iformfile="ldff1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_ai">LDFF1H (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_488" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_ai_s" iformfile="ld1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_ai">LD1W (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_ai_s" iformfile="ldff1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_ai">LDFF1W (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_490" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_gld_sv_a" title="SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_gld_sv_a" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="30*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_s_x32_scaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_s_x32_scaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_s_x32_scaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_s_x32_scaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_gld_sv_b" title="SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_gld_sv_b" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_487" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_s_x32_scaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_s_x32_scaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_prfm_sv" title="SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_prfm_sv" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_bz_s_x32_scaled" iformfile="prfb_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_bz">PRFB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_bz_s_x32_scaled" iformfile="prfh_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_bz">PRFH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_bz_s_x32_scaled" iformfile="prfw_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_bz">PRFW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_bz_s_x32_scaled" iformfile="prfd_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_bz">PRFD (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_prfm_vi" title="SVE 32-bit gather prefetch (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_prfm_vi" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_ai_s" iformfile="prfb_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_ai">PRFB (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_ai_s" iformfile="prfh_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_ai">PRFH (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_ai_s" iformfile="prfw_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_ai">PRFW (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_ai_s" iformfile="prfd_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_ai">PRFD (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_prfm_si" title="SVE contiguous prefetch (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_prfm_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_bi_s" iformfile="prfb_i_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_bi">PRFB (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_bi_s" iformfile="prfh_i_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_bi">PRFH (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_bi_s" iformfile="prfw_i_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_bi">PRFW (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_bi_s" iformfile="prfd_i_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_bi">PRFD (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_prfm_ss" title="SVE contiguous prefetch (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_prfm_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_br_s" iformfile="prfb_i_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_br">PRFB (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_br_s" iformfile="prfh_i_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_br">PRFH (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_br_s" iformfile="prfw_i_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_br">PRFW (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_br_s" iformfile="prfd_i_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_br">PRFD (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_ld_dup" title="SVE load and broadcast element">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="dtypeh" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm6" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="dtypel" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_ld_dup" cols="4">
|
|
<col colno="1" printwidth="8*" />
|
|
<col colno="2" printwidth="8*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtypeh</th>
|
|
<th class="bitfields">dtypel</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1rb_z_p_bi_u8" iformfile="ld1rb_z_p_bi.xml" label="8-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rb_z_p_bi">LD1RB</td>
|
|
<td class="enctags">8-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rb_z_p_bi_u16" iformfile="ld1rb_z_p_bi.xml" label="16-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rb_z_p_bi">LD1RB</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rb_z_p_bi_u32" iformfile="ld1rb_z_p_bi.xml" label="32-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1rb_z_p_bi">LD1RB</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rb_z_p_bi_u64" iformfile="ld1rb_z_p_bi.xml" label="64-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1rb_z_p_bi">LD1RB</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsw_z_p_bi_s64" iformfile="ld1rsw_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rsw_z_p_bi">LD1RSW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rh_z_p_bi_u16" iformfile="ld1rh_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rh_z_p_bi">LD1RH</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rh_z_p_bi_u32" iformfile="ld1rh_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1rh_z_p_bi">LD1RH</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rh_z_p_bi_u64" iformfile="ld1rh_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1rh_z_p_bi">LD1RH</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsh_z_p_bi_s64" iformfile="ld1rsh_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rsh_z_p_bi">LD1RSH</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsh_z_p_bi_s32" iformfile="ld1rsh_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rsh_z_p_bi">LD1RSH</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rw_z_p_bi_u32" iformfile="ld1rw_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1rw_z_p_bi">LD1RW</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rw_z_p_bi_u64" iformfile="ld1rw_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1rw_z_p_bi">LD1RW</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsb_z_p_bi_s64" iformfile="ld1rsb_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rsb_z_p_bi">LD1RSB</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsb_z_p_bi_s32" iformfile="ld1rsb_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rsb_z_p_bi">LD1RSB</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rsb_z_p_bi_s16" iformfile="ld1rsb_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1rsb_z_p_bi">LD1RSB</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rd_z_p_bi_u64" iformfile="ld1rd_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1rd_z_p_bi">LD1RD</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_pfill" title="SVE load predicate register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm9h" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm9l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_pfill" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldr_p_bi_" iformfile="ldr_p_bi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ldr_p_bi">LDR (predicate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_fill" title="SVE load vector register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm9h" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm9l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_fill" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldr_z_bi_" iformfile="ldr_z_bi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ldr_z_bi">LDR (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_32b_gldnt_vs" title="SVE2 32-bit gather non-temporal load (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_32b_gldnt_vs" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldnt1sb_z_p_ar_s_x32_unscaled" iformfile="ldnt1sb_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldnt1sb_z_p_ar">LDNT1SB</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_z_p_ar_s_x32_unscaled" iformfile="ldnt1b_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_z_p_ar">LDNT1B (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1sh_z_p_ar_s_x32_unscaled" iformfile="ldnt1sh_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldnt1sh_z_p_ar">LDNT1SH</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_z_p_ar_s_x32_unscaled" iformfile="ldnt1h_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_z_p_ar">LDNT1H (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_486" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_z_p_ar_s_x32_unscaled" iformfile="ldnt1w_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_z_p_ar">LDNT1W (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_489" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memcld">SVE Memory - Contiguous Load</funcgroupheader>
|
|
<iclass_sect id="sve_mem_cldff_ss" title="SVE contiguous first-fault load (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="dtype" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cldff_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_br_u8" iformfile="ldff1b_z_p_br.xml" label="8-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_br">LDFF1B (scalar plus scalar)</td>
|
|
<td class="enctags">8-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_br_u16" iformfile="ldff1b_z_p_br.xml" label="16-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_br">LDFF1B (scalar plus scalar)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_br_u32" iformfile="ldff1b_z_p_br.xml" label="32-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_br">LDFF1B (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_br_u64" iformfile="ldff1b_z_p_br.xml" label="64-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_br">LDFF1B (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_br_s64" iformfile="ldff1sw_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_br">LDFF1SW (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_br_u16" iformfile="ldff1h_z_p_br.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_br">LDFF1H (scalar plus scalar)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_br_u32" iformfile="ldff1h_z_p_br.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_br">LDFF1H (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_br_u64" iformfile="ldff1h_z_p_br.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_br">LDFF1H (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_br_s64" iformfile="ldff1sh_z_p_br.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_br">LDFF1SH (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_br_s32" iformfile="ldff1sh_z_p_br.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_br">LDFF1SH (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_br_u32" iformfile="ldff1w_z_p_br.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_br">LDFF1W (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_br_u64" iformfile="ldff1w_z_p_br.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_br">LDFF1W (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_br_s64" iformfile="ldff1sb_z_p_br.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_br">LDFF1SB (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_br_s32" iformfile="ldff1sb_z_p_br.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_br">LDFF1SB (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_br_s16" iformfile="ldff1sb_z_p_br.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_br">LDFF1SB (scalar plus scalar)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_br_u64" iformfile="ldff1d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_br">LDFF1D (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cld_si_q" title="SVE contiguous load (quadwords, scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="dtype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cld_si_q" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="47*" />
|
|
<col colno="3" printwidth="17*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_492" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bi_u128" arch_version="FEAT_SVE2p1" iformfile="ld1w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bi">LD1W (scalar plus immediate, single register)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bi_u128" arch_version="FEAT_SVE2p1" iformfile="ld1d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bi">LD1D (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cld_ss_q" title="SVE contiguous load (quadwords, scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="dtype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cld_ss_q" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="44*" />
|
|
<col colno="3" printwidth="17*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_491" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_br_u128" arch_version="FEAT_SVE2p1" iformfile="ld1w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1w_z_p_br">LD1W (scalar plus scalar, single register)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_br_u128" arch_version="FEAT_SVE2p1" iformfile="ld1d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1d_z_p_br">LD1D (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cld_si" title="SVE contiguous load (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="dtype" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cld_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="47*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bi_u8" iformfile="ld1b_z_p_bi.xml" label="8-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bi">LD1B (scalar plus immediate, single register)</td>
|
|
<td class="enctags">8-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bi_u16" iformfile="ld1b_z_p_bi.xml" label="16-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bi">LD1B (scalar plus immediate, single register)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bi_u32" iformfile="ld1b_z_p_bi.xml" label="32-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bi">LD1B (scalar plus immediate, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bi_u64" iformfile="ld1b_z_p_bi.xml" label="64-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bi">LD1B (scalar plus immediate, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_bi_s64" iformfile="ld1sw_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_bi">LD1SW (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bi_u16" iformfile="ld1h_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bi">LD1H (scalar plus immediate, single register)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bi_u32" iformfile="ld1h_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bi">LD1H (scalar plus immediate, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bi_u64" iformfile="ld1h_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bi">LD1H (scalar plus immediate, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bi_s64" iformfile="ld1sh_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bi">LD1SH (scalar plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bi_s32" iformfile="ld1sh_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bi">LD1SH (scalar plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bi_u32" iformfile="ld1w_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bi">LD1W (scalar plus immediate, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bi_u64" iformfile="ld1w_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bi">LD1W (scalar plus immediate, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bi_s64" iformfile="ld1sb_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bi">LD1SB (scalar plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bi_s32" iformfile="ld1sb_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bi">LD1SB (scalar plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bi_s16" iformfile="ld1sb_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bi">LD1SB (scalar plus immediate)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bi_u64" iformfile="ld1d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bi">LD1D (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cld_ss" title="SVE contiguous load (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="dtype" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cld_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="44*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_z_p_br_u8" iformfile="ld1b_z_p_br.xml" label="8-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ld1b_z_p_br">LD1B (scalar plus scalar, single register)</td>
|
|
<td class="enctags">8-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_br_u16" iformfile="ld1b_z_p_br.xml" label="16-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="ld1b_z_p_br">LD1B (scalar plus scalar, single register)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_br_u32" iformfile="ld1b_z_p_br.xml" label="32-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ld1b_z_p_br">LD1B (scalar plus scalar, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_br_u64" iformfile="ld1b_z_p_br.xml" label="64-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="ld1b_z_p_br">LD1B (scalar plus scalar, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_br_s64" iformfile="ld1sw_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_br">LD1SW (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_br_u16" iformfile="ld1h_z_p_br.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="ld1h_z_p_br">LD1H (scalar plus scalar, single register)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_br_u32" iformfile="ld1h_z_p_br.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ld1h_z_p_br">LD1H (scalar plus scalar, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_br_u64" iformfile="ld1h_z_p_br.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ld1h_z_p_br">LD1H (scalar plus scalar, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_br_s64" iformfile="ld1sh_z_p_br.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_br">LD1SH (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_br_s32" iformfile="ld1sh_z_p_br.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_br">LD1SH (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_br_u32" iformfile="ld1w_z_p_br.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ld1w_z_p_br">LD1W (scalar plus scalar, single register)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_br_u64" iformfile="ld1w_z_p_br.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="ld1w_z_p_br">LD1W (scalar plus scalar, single register)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_br_s64" iformfile="ld1sb_z_p_br.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_br">LD1SB (scalar plus scalar)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_br_s32" iformfile="ld1sb_z_p_br.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_br">LD1SB (scalar plus scalar)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_br_s16" iformfile="ld1sb_z_p_br.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_br">LD1SB (scalar plus scalar)</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_br_u64" iformfile="ld1d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="ld1d_z_p_br">LD1D (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cldnf_si" title="SVE contiguous non-fault load (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="4" name="dtype" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cldnf_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">dtype</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldnf1b_z_p_bi_u8" iformfile="ldnf1b_z_p_bi.xml" label="8-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname" iformid="ldnf1b_z_p_bi">LDNF1B</td>
|
|
<td class="enctags">8-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1b_z_p_bi_u16" iformfile="ldnf1b_z_p_bi.xml" label="16-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="ldnf1b_z_p_bi">LDNF1B</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1b_z_p_bi_u32" iformfile="ldnf1b_z_p_bi.xml" label="32-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0010</td>
|
|
<td class="iformname" iformid="ldnf1b_z_p_bi">LDNF1B</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1b_z_p_bi_u64" iformfile="ldnf1b_z_p_bi.xml" label="64-bit element" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0011</td>
|
|
<td class="iformname" iformid="ldnf1b_z_p_bi">LDNF1B</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sw_z_p_bi_s64" iformfile="ldnf1sw_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0100</td>
|
|
<td class="iformname" iformid="ldnf1sw_z_p_bi">LDNF1SW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1h_z_p_bi_u16" iformfile="ldnf1h_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0101</td>
|
|
<td class="iformname" iformid="ldnf1h_z_p_bi">LDNF1H</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1h_z_p_bi_u32" iformfile="ldnf1h_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0110</td>
|
|
<td class="iformname" iformid="ldnf1h_z_p_bi">LDNF1H</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1h_z_p_bi_u64" iformfile="ldnf1h_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0111</td>
|
|
<td class="iformname" iformid="ldnf1h_z_p_bi">LDNF1H</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sh_z_p_bi_s64" iformfile="ldnf1sh_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1000</td>
|
|
<td class="iformname" iformid="ldnf1sh_z_p_bi">LDNF1SH</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sh_z_p_bi_s32" iformfile="ldnf1sh_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1001</td>
|
|
<td class="iformname" iformid="ldnf1sh_z_p_bi">LDNF1SH</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1w_z_p_bi_u32" iformfile="ldnf1w_z_p_bi.xml" label="32-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1010</td>
|
|
<td class="iformname" iformid="ldnf1w_z_p_bi">LDNF1W</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1w_z_p_bi_u64" iformfile="ldnf1w_z_p_bi.xml" label="64-bit element" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1011</td>
|
|
<td class="iformname" iformid="ldnf1w_z_p_bi">LDNF1W</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sb_z_p_bi_s64" iformfile="ldnf1sb_z_p_bi.xml" label="64-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1100</td>
|
|
<td class="iformname" iformid="ldnf1sb_z_p_bi">LDNF1SB</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sb_z_p_bi_s32" iformfile="ldnf1sb_z_p_bi.xml" label="32-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1101</td>
|
|
<td class="iformname" iformid="ldnf1sb_z_p_bi">LDNF1SB</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1sb_z_p_bi_s16" iformfile="ldnf1sb_z_p_bi.xml" label="16-bit element" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1110</td>
|
|
<td class="iformname" iformid="ldnf1sb_z_p_bi">LDNF1SB</td>
|
|
<td class="enctags">16-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnf1d_z_p_bi_u64" iformfile="ldnf1d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1111</td>
|
|
<td class="iformname" iformid="ldnf1d_z_p_bi">LDNF1D</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cldnt_si" title="SVE contiguous non-temporal load (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cldnt_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="49*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldnt1b_z_p_bi_contiguous" iformfile="ldnt1b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ldnt1b_z_p_bi">LDNT1B (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_z_p_bi_contiguous" iformfile="ldnt1h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ldnt1h_z_p_bi">LDNT1H (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_z_p_bi_contiguous" iformfile="ldnt1w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ldnt1w_z_p_bi">LDNT1W (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_z_p_bi_contiguous" iformfile="ldnt1d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ldnt1d_z_p_bi">LDNT1D (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cldnt_ss" title="SVE contiguous non-temporal load (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cldnt_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="46*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldnt1b_z_p_br_contiguous" iformfile="ldnt1b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ldnt1b_z_p_br">LDNT1B (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_z_p_br_contiguous" iformfile="ldnt1h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ldnt1h_z_p_br">LDNT1H (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_z_p_br_contiguous" iformfile="ldnt1w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ldnt1w_z_p_br">LDNT1W (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_z_p_br_contiguous" iformfile="ldnt1d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ldnt1d_z_p_br">LDNT1D (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_ldqr_si" title="SVE load and broadcast quadword (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="ssz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_ldqr_si" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="32*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">ssz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_496" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqb_z_p_bi_u8" iformfile="ld1rqb_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqb_z_p_bi">LD1RQB (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rob_z_p_bi_u8" arch_version="FEAT_F64MM" iformfile="ld1rob_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rob_z_p_bi">LD1ROB (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqh_z_p_bi_u16" iformfile="ld1rqh_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqh_z_p_bi">LD1RQH (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1roh_z_p_bi_u16" arch_version="FEAT_F64MM" iformfile="ld1roh_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1roh_z_p_bi">LD1ROH (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqw_z_p_bi_u32" iformfile="ld1rqw_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqw_z_p_bi">LD1RQW (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1row_z_p_bi_u32" arch_version="FEAT_F64MM" iformfile="ld1row_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1row_z_p_bi">LD1ROW (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqd_z_p_bi_u64" iformfile="ld1rqd_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqd_z_p_bi">LD1RQD (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rod_z_p_bi_u64" arch_version="FEAT_F64MM" iformfile="ld1rod_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rod_z_p_bi">LD1ROD (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_ldqr_ss" title="SVE load and broadcast quadword (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="ssz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_ldqr_ss" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">ssz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_495" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqb_z_p_br_contiguous" iformfile="ld1rqb_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqb_z_p_br">LD1RQB (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rob_z_p_br_contiguous" arch_version="FEAT_F64MM" iformfile="ld1rob_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rob_z_p_br">LD1ROB (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqh_z_p_br_contiguous" iformfile="ld1rqh_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqh_z_p_br">LD1RQH (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1roh_z_p_br_contiguous" arch_version="FEAT_F64MM" iformfile="ld1roh_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1roh_z_p_br">LD1ROH (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqw_z_p_br_contiguous" iformfile="ld1rqw_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqw_z_p_br">LD1RQW (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1row_z_p_br_contiguous" arch_version="FEAT_F64MM" iformfile="ld1row_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1row_z_p_br">LD1ROW (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rqd_z_p_br_contiguous" iformfile="ld1rqd_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1rqd_z_p_br">LD1RQD (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1rod_z_p_br_contiguous" arch_version="FEAT_F64MM" iformfile="ld1rod_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1rod_z_p_br">LD1ROD (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_eldq_si" title="SVE load multiple structures (quadwords, scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="num" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_eldq_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">num</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_493" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld2q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2q_z_p_bi">LD2Q (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld3q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3q_z_p_bi">LD3Q (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld4q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4q_z_p_bi">LD4Q (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_eldq_ss" title="SVE load multiple structures (quadwords, scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="num" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_eldq_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">num</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_494" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld2q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2q_z_p_br">LD2Q (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld3q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3q_z_p_br">LD3Q (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="ld4q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4q_z_p_br">LD4Q (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_eld_si" title="SVE load multiple structures (scalar plus immediate)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_eld_si" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="30*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld2b_z_p_bi_contiguous" iformfile="ld2b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2b_z_p_bi">LD2B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3b_z_p_bi_contiguous" iformfile="ld3b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3b_z_p_bi">LD3B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4b_z_p_bi_contiguous" iformfile="ld4b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4b_z_p_bi">LD4B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2h_z_p_bi_contiguous" iformfile="ld2h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2h_z_p_bi">LD2H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3h_z_p_bi_contiguous" iformfile="ld3h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3h_z_p_bi">LD3H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4h_z_p_bi_contiguous" iformfile="ld4h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4h_z_p_bi">LD4H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2w_z_p_bi_contiguous" iformfile="ld2w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2w_z_p_bi">LD2W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3w_z_p_bi_contiguous" iformfile="ld3w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3w_z_p_bi">LD3W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4w_z_p_bi_contiguous" iformfile="ld4w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4w_z_p_bi">LD4W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2d_z_p_bi_contiguous" iformfile="ld2d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2d_z_p_bi">LD2D (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3d_z_p_bi_contiguous" iformfile="ld3d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3d_z_p_bi">LD3D (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4d_z_p_bi_contiguous" iformfile="ld4d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4d_z_p_bi">LD4D (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_eld_ss" title="SVE load multiple structures (scalar plus scalar)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_eld_ss" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld2b_z_p_br_contiguous" iformfile="ld2b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2b_z_p_br">LD2B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3b_z_p_br_contiguous" iformfile="ld3b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3b_z_p_br">LD3B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4b_z_p_br_contiguous" iformfile="ld4b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4b_z_p_br">LD4B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2h_z_p_br_contiguous" iformfile="ld2h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2h_z_p_br">LD2H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3h_z_p_br_contiguous" iformfile="ld3h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3h_z_p_br">LD3H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4h_z_p_br_contiguous" iformfile="ld4h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4h_z_p_br">LD4H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2w_z_p_br_contiguous" iformfile="ld2w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2w_z_p_br">LD2W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3w_z_p_br_contiguous" iformfile="ld3w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3w_z_p_br">LD3W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4w_z_p_br_contiguous" iformfile="ld4w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4w_z_p_br">LD4W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld2d_z_p_br_contiguous" iformfile="ld2d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld2d_z_p_br">LD2D (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld3d_z_p_br_contiguous" iformfile="ld3d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld3d_z_p_br">LD3D (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld4d_z_p_br_contiguous" iformfile="ld4d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld4d_z_p_br">LD4D (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_mem64">SVE Memory - 64-bit Gather</funcgroupheader>
|
|
<iclass_sect id="sve_mem_64b_gld_sv" title="SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_64b_gld_sv" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="31*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_d_x32_scaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_d_x32_scaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_d_x32_scaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_d_x32_scaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_bz_d_x32_scaled" iformfile="ld1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_bz">LD1SW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_bz_d_x32_scaled" iformfile="ldff1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_bz">LDFF1SW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_d_x32_scaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_d_x32_scaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_610" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bz_d_x32_scaled" iformfile="ld1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bz">LD1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_bz_d_x32_scaled" iformfile="ldff1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_bz">LDFF1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gld_sv2" title="SVE 64-bit gather load (scalar plus 64-bit scaled offsets)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_64b_gld_sv2" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_d_64_scaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_d_64_scaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_d_64_scaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_d_64_scaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_bz_d_64_scaled" iformfile="ld1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_bz">LD1SW (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_bz_d_64_scaled" iformfile="ldff1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_bz">LDFF1SW (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_d_64_scaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_d_64_scaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_613" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bz_d_64_scaled" iformfile="ld1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bz">LD1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_bz_d_64_scaled" iformfile="ldff1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_bz">LDFF1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gld_vs2" title="SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_gld_vs2" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bz_d_64_unscaled" iformfile="ld1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bz">LD1SB (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_bz_d_64_unscaled" iformfile="ldff1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_bz">LDFF1SB (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bz_d_64_unscaled" iformfile="ld1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bz">LD1B (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_bz_d_64_unscaled" iformfile="ldff1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_bz">LDFF1B (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_d_64_unscaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_d_64_unscaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_d_64_unscaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_d_64_unscaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_bz_d_64_unscaled" iformfile="ld1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_bz">LD1SW (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_bz_d_64_unscaled" iformfile="ldff1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_bz">LDFF1SW (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_d_64_unscaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_d_64_unscaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_612" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bz_d_64_unscaled" iformfile="ld1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bz">LD1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_bz_d_64_unscaled" iformfile="ldff1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_bz">LDFF1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gld_vs" title="SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_gld_vs" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="30*" />
|
|
<col colno="5" printwidth="33*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_bz_d_x32_unscaled" iformfile="ld1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_bz">LD1SB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_bz_d_x32_unscaled" iformfile="ldff1sb_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_bz">LDFF1SB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_bz_d_x32_unscaled" iformfile="ld1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_z_p_bz">LD1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_bz_d_x32_unscaled" iformfile="ldff1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_bz">LDFF1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_bz_d_x32_unscaled" iformfile="ld1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_bz">LD1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_bz_d_x32_unscaled" iformfile="ldff1sh_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_bz">LDFF1SH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_bz_d_x32_unscaled" iformfile="ld1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_bz">LD1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_bz_d_x32_unscaled" iformfile="ldff1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_bz">LDFF1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_bz_d_x32_unscaled" iformfile="ld1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_bz">LD1SW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_bz_d_x32_unscaled" iformfile="ldff1sw_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_bz">LDFF1SW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_bz_d_x32_unscaled" iformfile="ld1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_bz">LD1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_bz_d_x32_unscaled" iformfile="ldff1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_bz">LDFF1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_608" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_bz_d_x32_unscaled" iformfile="ld1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_z_p_bz">LD1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_bz_d_x32_unscaled" iformfile="ldff1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_bz">LDFF1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gld_vi" title="SVE 64-bit gather load (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" name="ff" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_gld_vi" cols="5">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="33*" />
|
|
<col colno="5" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">ff</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1sb_z_p_ai_d" iformfile="ld1sb_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sb_z_p_ai">LD1SB (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sb_z_p_ai_d" iformfile="ldff1sb_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sb_z_p_ai">LDFF1SB (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1b_z_p_ai_d" iformfile="ld1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_z_p_ai">LD1B (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1b_z_p_ai_d" iformfile="ldff1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1b_z_p_ai">LDFF1B (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sh_z_p_ai_d" iformfile="ld1sh_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sh_z_p_ai">LD1SH (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sh_z_p_ai_d" iformfile="ldff1sh_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sh_z_p_ai">LDFF1SH (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_z_p_ai_d" iformfile="ld1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_z_p_ai">LD1H (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1h_z_p_ai_d" iformfile="ldff1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1h_z_p_ai">LDFF1H (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1sw_z_p_ai_d" iformfile="ld1sw_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1sw_z_p_ai">LD1SW (vector plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1sw_z_p_ai_d" iformfile="ldff1sw_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1sw_z_p_ai">LDFF1SW (vector plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_z_p_ai_d" iformfile="ld1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_z_p_ai">LD1W (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1w_z_p_ai_d" iformfile="ldff1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1w_z_p_ai">LDFF1W (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_611" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_z_p_ai_d" iformfile="ld1d_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_z_p_ai">LD1D (vector plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldff1d_z_p_ai_d" iformfile="ldff1d_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldff1d_z_p_ai">LDFF1D (vector plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_prfm_sv2" title="SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_prfm_sv2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_bz_d_64_scaled" iformfile="prfb_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_bz">PRFB (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_bz_d_64_scaled" iformfile="prfh_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_bz">PRFH (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_bz_d_64_scaled" iformfile="prfw_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_bz">PRFW (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_bz_d_64_scaled" iformfile="prfd_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_bz">PRFD (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_prfm_sv" title="SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_prfm_sv" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="31*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_bz_d_x32_scaled" iformfile="prfb_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_bz">PRFB (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_bz_d_x32_scaled" iformfile="prfh_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_bz">PRFH (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_bz_d_x32_scaled" iformfile="prfw_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_bz">PRFW (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_bz_d_x32_scaled" iformfile="prfd_i_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_bz">PRFD (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_prfm_vi" title="SVE 64-bit gather prefetch (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="prfop" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_prfm_vi" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="prfb_i_p_ai_d" iformfile="prfb_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="prfb_i_p_ai">PRFB (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfh_i_p_ai_d" iformfile="prfh_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="prfh_i_p_ai">PRFH (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfw_i_p_ai_d" iformfile="prfw_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="prfw_i_p_ai">PRFW (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="prfd_i_p_ai_d" iformfile="prfd_i_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="prfd_i_p_ai">PRFD (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gldq_vs" title="SVE2 128-bit gather load (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_gldq_vs" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1q_z_p_ar_d_64_unscaled" arch_version="FEAT_SVE2p1" iformfile="ld1q_z_p_ar.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ld1q_z_p_ar">LD1Q</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_64b_gldnt_vs" title="SVE2 64-bit gather non-temporal load (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_64b_gldnt_vs" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="29*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldnt1sb_z_p_ar_d_64_unscaled" iformfile="ldnt1sb_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldnt1sb_z_p_ar">LDNT1SB</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_z_p_ar_d_64_unscaled" iformfile="ldnt1b_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_z_p_ar">LDNT1B (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1sh_z_p_ar_d_64_unscaled" iformfile="ldnt1sh_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldnt1sh_z_p_ar">LDNT1SH</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_z_p_ar_d_64_unscaled" iformfile="ldnt1h_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_z_p_ar">LDNT1H (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1sw_z_p_ar_d_64_unscaled" iformfile="ldnt1sw_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldnt1sw_z_p_ar">LDNT1SW</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_z_p_ar_d_64_unscaled" iformfile="ldnt1w_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_z_p_ar">LDNT1W (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_609" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_z_p_ar_d_64_unscaled" iformfile="ldnt1d_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_z_p_ar">LDNT1D (vector plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memsst_nt">SVE Memory - Non-temporal and Quadword Scatter Store</funcgroupheader>
|
|
<iclass_sect id="sve_mem_sstq_64b_vs" title="SVE2 128-bit scatter store (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sstq_64b_vs" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1q_z_p_ar_d_64_unscaled" arch_version="FEAT_SVE2p1" iformfile="st1q_z_p_ar.xml" first="t" last="t">
|
|
<td class="iformname" iformid="st1q_z_p_ar">ST1Q</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sstnt_32b_vs" title="SVE2 32-bit scatter non-temporal store (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sstnt_32b_vs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="29*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="stnt1b_z_p_ar_s_x32_unscaled" iformfile="stnt1b_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="stnt1b_z_p_ar">STNT1B (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_z_p_ar_s_x32_unscaled" iformfile="stnt1h_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="stnt1h_z_p_ar">STNT1H (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_z_p_ar_s_x32_unscaled" iformfile="stnt1w_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="stnt1w_z_p_ar">STNT1W (vector plus scalar)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_628" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sstnt_64b_vs" title="SVE2 64-bit scatter non-temporal store (vector plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sstnt_64b_vs" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="29*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="stnt1b_z_p_ar_d_64_unscaled" iformfile="stnt1b_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="stnt1b_z_p_ar">STNT1B (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_z_p_ar_d_64_unscaled" iformfile="stnt1h_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="stnt1h_z_p_ar">STNT1H (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_z_p_ar_d_64_unscaled" iformfile="stnt1w_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="stnt1w_z_p_ar">STNT1W (vector plus scalar)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_z_p_ar_d_64_unscaled" iformfile="stnt1d_z_p_ar.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="stnt1d_z_p_ar">STNT1D (vector plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memcst_nt">SVE Memory - Non-temporal and Multi-register Contiguous Store</funcgroupheader>
|
|
<iclass_sect id="sve_mem_cstnt_ss" title="SVE contiguous non-temporal store (scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cstnt_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="46*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="stnt1b_z_p_br_contiguous" iformfile="stnt1b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="stnt1b_z_p_br">STNT1B (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_z_p_br_contiguous" iformfile="stnt1h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="stnt1h_z_p_br">STNT1H (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_z_p_br_contiguous" iformfile="stnt1w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="stnt1w_z_p_br">STNT1W (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_z_p_br_contiguous" iformfile="stnt1d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="stnt1d_z_p_br">STNT1D (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_est_ss" title="SVE store multiple structures (scalar plus scalar)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_est_ss" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st2b_z_p_br_contiguous" iformfile="st2b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2b_z_p_br">ST2B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3b_z_p_br_contiguous" iformfile="st3b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3b_z_p_br">ST3B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4b_z_p_br_contiguous" iformfile="st4b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4b_z_p_br">ST4B (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2h_z_p_br_contiguous" iformfile="st2h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2h_z_p_br">ST2H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3h_z_p_br_contiguous" iformfile="st3h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3h_z_p_br">ST3H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4h_z_p_br_contiguous" iformfile="st4h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4h_z_p_br">ST4H (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2w_z_p_br_contiguous" iformfile="st2w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2w_z_p_br">ST2W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3w_z_p_br_contiguous" iformfile="st3w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3w_z_p_br">ST3W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4w_z_p_br_contiguous" iformfile="st4w_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4w_z_p_br">ST4W (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2d_z_p_br_contiguous" iformfile="st2d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2d_z_p_br">ST2D (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3d_z_p_br_contiguous" iformfile="st3d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3d_z_p_br">ST3D (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4d_z_p_br_contiguous" iformfile="st4d_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4d_z_p_br">ST4D (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memst_cs">SVE Memory - Contiguous Store and Unsized Contiguous</funcgroupheader>
|
|
<iclass_sect id="sve_mem_cst_ss" title="SVE contiguous store (scalar plus scalar)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="3" name="opc" usename="1" settings="3" constraint="!= 110">
|
|
<c colspan="3">!= 110</c>
|
|
</box>
|
|
<box hibit="21" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="110" />
|
|
<decode_constraint name="opc" op="!=" val="110" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_cst_ss" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="44*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_br_" iformfile="st1b_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="st1b_z_p_br">ST1B (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_br_" iformfile="st1h_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="st1h_z_p_br">ST1H (scalar plus scalar, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_br_u128" arch_version="FEAT_SVE2p1" iformfile="st1w_z_p_br.xml" label="SVE2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_z_p_br">ST1W (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_br_" iformfile="st1w_z_p_br.xml" label="SVE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname" iformid="st1w_z_p_br">ST1W (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_br_u128" arch_version="FEAT_SVE2p1" iformfile="st1d_z_p_br.xml" label="SVE2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_z_p_br">ST1D (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_br_" iformfile="st1d_z_p_br.xml" label="SVE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="st1d_z_p_br">ST1D (scalar plus scalar, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_estq_si" title="SVE store multiple structures (quadwords, scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="num" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_estq_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">num</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_621" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="st2q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2q_z_p_bi">ST2Q (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="st3q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3q_z_p_bi">ST3Q (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4q_z_p_bi_contiguous" arch_version="FEAT_SVE2p1" iformfile="st4q_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4q_z_p_bi">ST4Q (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_estq_ss" title="SVE store multiple structures (quadwords, scalar plus scalar)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="num" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_estq_ss" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">num</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_622" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="st2q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2q_z_p_br">ST2Q (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="st3q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3q_z_p_br">ST3Q (scalar plus scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4q_z_p_br_contiguous" arch_version="FEAT_SVE2p1" iformfile="st4q_z_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4q_z_p_br">ST4Q (scalar plus scalar)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_pspill" title="SVE store predicate register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm9h" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm9l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Pt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_pspill" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="str_p_bi_" iformfile="str_p_bi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="str_p_bi">STR (predicate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_spill" title="SVE store vector register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="imm9h" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="imm9l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_spill" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="str_z_bi_" iformfile="str_z_bi.xml" first="t" last="t">
|
|
<td class="iformname" iformid="str_z_bi">STR (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memst_ss2">SVE Memory - Scatter</funcgroupheader>
|
|
<iclass_sect id="sve_mem_sst_vi_b" title="SVE 32-bit scatter store (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_vi_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_ai_s" iformfile="st1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_z_p_ai">ST1B (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_ai_s" iformfile="st1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_ai">ST1H (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_ai_s" iformfile="st1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_ai">ST1W (vector plus immediate)</td>
|
|
<td class="enctags">32-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_631" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_sv2" title="SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_sv2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_624" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_d_64_scaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_d_64_scaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bz_d_64_scaled" iformfile="st1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_bz">ST1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_vs2" title="SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_vs2" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_bz_d_64_unscaled" iformfile="st1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_z_p_bz">ST1B (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_d_64_unscaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_d_64_unscaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bz_d_64_unscaled" iformfile="st1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_bz">ST1D (scalar plus vector)</td>
|
|
<td class="enctags">64-bit unscaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_vi_a" title="SVE 64-bit scatter store (vector plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_vi_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="30*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_ai_d" iformfile="st1b_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_z_p_ai">ST1B (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_ai_d" iformfile="st1h_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_ai">ST1H (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_ai_d" iformfile="st1w_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_ai">ST1W (vector plus immediate)</td>
|
|
<td class="enctags">64-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_ai_d" iformfile="st1d_z_p_ai.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_ai">ST1D (vector plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memst_si">SVE Memory - Contiguous Store with Immediate Offset</funcgroupheader>
|
|
<iclass_sect id="sve_mem_cstnt_si" title="SVE contiguous non-temporal store (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cstnt_si" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="49*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="stnt1b_z_p_bi_contiguous" iformfile="stnt1b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="stnt1b_z_p_bi">STNT1B (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_z_p_bi_contiguous" iformfile="stnt1h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="stnt1h_z_p_bi">STNT1H (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_z_p_bi_contiguous" iformfile="stnt1w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="stnt1w_z_p_bi">STNT1W (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_z_p_bi_contiguous" iformfile="stnt1d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="stnt1d_z_p_bi">STNT1D (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_cst_si" title="SVE contiguous store (scalar plus immediate)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_cst_si" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="47*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_bi_" iformfile="st1b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="st1b_z_p_bi">ST1B (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bi_" iformfile="st1h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname" iformid="st1h_z_p_bi">ST1H (scalar plus immediate, single register)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bi_u128" arch_version="FEAT_SVE2p1" iformfile="st1w_z_p_bi.xml" label="SVE2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1w_z_p_bi">ST1W (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_626" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bi_" iformfile="st1w_z_p_bi.xml" label="SVE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname" iformid="st1w_z_p_bi">ST1W (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_627" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bi_u128" arch_version="FEAT_SVE2p1" iformfile="st1d_z_p_bi.xml" label="SVE2" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1d_z_p_bi">ST1D (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE2</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bi_" iformfile="st1d_z_p_bi.xml" label="SVE" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_bi">ST1D (scalar plus immediate, single register)</td>
|
|
<td class="enctags">SVE</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_est_si" title="SVE store multiple structures (scalar plus immediate)">
|
|
<regdiagram form="32" psname="" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" name="opc" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<decode_constraints>
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
<decode_constraint name="opc" op="!=" val="00" />
|
|
</decode_constraints>
|
|
<instructiontable iclass="sve_mem_est_si" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="30*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st2b_z_p_bi_contiguous" iformfile="st2b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2b_z_p_bi">ST2B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3b_z_p_bi_contiguous" iformfile="st3b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3b_z_p_bi">ST3B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4b_z_p_bi_contiguous" iformfile="st4b_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4b_z_p_bi">ST4B (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2h_z_p_bi_contiguous" iformfile="st2h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2h_z_p_bi">ST2H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3h_z_p_bi_contiguous" iformfile="st3h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3h_z_p_bi">ST3H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4h_z_p_bi_contiguous" iformfile="st4h_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4h_z_p_bi">ST4H (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2w_z_p_bi_contiguous" iformfile="st2w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2w_z_p_bi">ST2W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3w_z_p_bi_contiguous" iformfile="st3w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3w_z_p_bi">ST3W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4w_z_p_bi_contiguous" iformfile="st4w_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4w_z_p_bi">ST4W (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st2d_z_p_bi_contiguous" iformfile="st2d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st2d_z_p_bi">ST2D (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st3d_z_p_bi_contiguous" iformfile="st3d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st3d_z_p_bi">ST3D (scalar plus immediate)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st4d_z_p_bi_contiguous" iformfile="st4d_z_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st4d_z_p_bi">ST4D (scalar plus immediate)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="sve_memst_ss">SVE Memory - Scatter with Optional Sign Extend</funcgroupheader>
|
|
<iclass_sect id="sve_mem_sst_sv_b" title="SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_sv_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_625" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_s_x32_scaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_s_x32_scaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_630" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_vs_b" title="SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_vs_b" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_bz_s_x32_unscaled" iformfile="st1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_z_p_bz">ST1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_s_x32_unscaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_s_x32_unscaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_629" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_sv_a" title="SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_sv_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="31*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_623" undef="1" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_d_x32_scaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_d_x32_scaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bz_d_x32_scaled" iformfile="st1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_bz">ST1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked scaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="sve_mem_sst_vs_a" title="SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="22" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" name="xs" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="sve_mem_sst_vs_a" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="27*" />
|
|
<col colno="3" printwidth="33*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_z_p_bz_d_x32_unscaled" iformfile="st1b_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_z_p_bz">ST1B (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_z_p_bz_d_x32_unscaled" iformfile="st1h_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_z_p_bz">ST1H (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_z_p_bz_d_x32_unscaled" iformfile="st1w_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_z_p_bz">ST1W (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_z_p_bz_d_x32_unscaled" iformfile="st1d_z_p_bz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_z_p_bz">ST1D (scalar plus vector)</td>
|
|
<td class="enctags">32-bit unpacked unscaled offset</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_32bit_bin_prod">SME2 Binary Outer Product - 32 bit</funcgroupheader>
|
|
<iclass_sect id="mortlach_bini32_prod" title="SME2 32-bit binary outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_bini32_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="bmopa_za_pp_zz_32" arch_version="FEAT_SME2" iformfile="bmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bmopa_za_pp_zz">BMOPA</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bmops_za_pp_zz_32" arch_version="FEAT_SME2" iformfile="bmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bmops_za_pp_zz">BMOPS</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_16bit_fp_prod">SME FP Outer Product - 16 bit</funcgroupheader>
|
|
<iclass_sect id="mortlach_f16f16_prod" title="SME FP16 non-widening outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="ZAda" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_f16f16_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmopa_za_pp_zz_16" arch_version="FEAT_SME_F16F16" iformfile="fmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmopa_za_pp_zz">FMOPA (non-widening)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmops_za_pp_zz_16" arch_version="FEAT_SME_F16F16" iformfile="fmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmops_za_pp_zz">FMOPS (non-widening)</td>
|
|
<td class="enctags">Half-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_b16b16_prod" title="SME non-widening BF16 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="ZAda" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_b16b16_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="bfmopa_za_pp_zz_16" arch_version="FEAT_B16B16" iformfile="bfmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmopa_za_pp_zz">BFMOPA (non-widening)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmops_za_pp_zz_16" arch_version="FEAT_B16B16" iformfile="bfmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmops_za_pp_zz">BFMOPS (non-widening)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_32bit_fp_prod">SME FP Outer Product - 32 bit</funcgroupheader>
|
|
<iclass_sect id="mortlach_f16f32_prod" title="SME FP16 widening outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_f16f32_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmopa_za32_pp_zz_16" arch_version="FEAT_SME" iformfile="fmopa_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmopa_za32_pp_zz">FMOPA (widening)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmops_za32_pp_zz_16" arch_version="FEAT_SME" iformfile="fmops_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmops_za32_pp_zz">FMOPS (widening)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_f32f32_prod" title="SME FP32 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_f32f32_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmopa_za_pp_zz_32" arch_version="FEAT_SME" iformfile="fmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmopa_za_pp_zz">FMOPA (non-widening)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmops_za_pp_zz_32" arch_version="FEAT_SME" iformfile="fmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmops_za_pp_zz">FMOPS (non-widening)</td>
|
|
<td class="enctags">Single-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_b16f32_prod" title="SME widening BF16 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_b16f32_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="19*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="bfmopa_za32_pp_zz_" arch_version="FEAT_SME" iformfile="bfmopa_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmopa_za32_pp_zz">BFMOPA (widening)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmops_za32_pp_zz_" arch_version="FEAT_SME" iformfile="bfmops_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmops_za32_pp_zz">BFMOPS (widening)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_mem_ctg">SME2 Multi-vector - Memory (Contiguous)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_cld_cldnt_si_ctg" title="SME2 multi-vec contiguous load (scalar plus immediate, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zt" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cld_cldnt_si_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="55*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ld1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mz_p_bi">LD1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mz_p_bi">LDNT1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ld1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mz_p_bi">LD1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mz_p_bi">LDNT1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ld1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mz_p_bi">LD1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mz_p_bi">LDNT1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ld1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mz_p_bi">LD1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mz_p_bi">LDNT1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cld_cldnt_si_ctg" title="SME2 multi-vec contiguous load (scalar plus immediate, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cld_cldnt_si_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="55*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ld1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mz_p_bi">LD1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mz_p_bi">LDNT1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ld1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mz_p_bi">LD1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mz_p_bi">LDNT1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ld1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mz_p_bi">LD1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mz_p_bi">LDNT1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ld1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mz_p_bi">LD1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mz_p_bi">LDNT1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cld_cldnt_ss_ctg" title="SME2 multi-vec contiguous load (scalar plus scalar, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zt" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cld_cldnt_ss_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="52*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ld1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mz_p_br">LD1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mz_p_br">LDNT1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ld1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mz_p_br">LD1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mz_p_br">LDNT1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ld1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mz_p_br">LD1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mz_p_br">LDNT1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ld1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mz_p_br">LD1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="ldnt1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mz_p_br">LDNT1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cld_cldnt_ss_ctg" title="SME2 multi-vec contiguous load (scalar plus scalar, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cld_cldnt_ss_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="52*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ld1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mz_p_br">LD1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mz_p_br">LDNT1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ld1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mz_p_br">LD1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mz_p_br">LDNT1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ld1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mz_p_br">LD1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mz_p_br">LDNT1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ld1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mz_p_br">LD1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="ldnt1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mz_p_br">LDNT1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cst_cstnt_si_ctg" title="SME2 multi-vec contiguous store (scalar plus immediate, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zt" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cst_cstnt_si_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="55*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="st1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mz_p_bi">ST1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="stnt1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mz_p_bi">STNT1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="st1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mz_p_bi">ST1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="stnt1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mz_p_bi">STNT1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="st1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mz_p_bi">ST1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="stnt1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mz_p_bi">STNT1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="st1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mz_p_bi">ST1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mz_p_bi_4" arch_version="FEAT_SVE2p1" iformfile="stnt1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mz_p_bi">STNT1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cst_cstnt_si_ctg" title="SME2 multi-vec contiguous store (scalar plus immediate, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cst_cstnt_si_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="55*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="st1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mz_p_bi">ST1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="stnt1b_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mz_p_bi">STNT1B (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="st1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mz_p_bi">ST1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="stnt1h_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mz_p_bi">STNT1H (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="st1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mz_p_bi">ST1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="stnt1w_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mz_p_bi">STNT1W (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="st1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mz_p_bi">ST1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mz_p_bi_2" arch_version="FEAT_SVE2p1" iformfile="stnt1d_mz_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mz_p_bi">STNT1D (scalar plus immediate, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cst_cstnt_ss_ctg" title="SME2 multi-vec contiguous store (scalar plus scalar, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zt" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cst_cstnt_ss_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="52*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="st1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mz_p_br">ST1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="stnt1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mz_p_br">STNT1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="st1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mz_p_br">ST1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="stnt1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mz_p_br">STNT1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="st1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mz_p_br">ST1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="stnt1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mz_p_br">STNT1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="st1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mz_p_br">ST1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mz_p_br_4" arch_version="FEAT_SVE2p1" iformfile="stnt1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mz_p_br">STNT1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cst_cstnt_ss_ctg" title="SME2 multi-vec contiguous store (scalar plus scalar, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cst_cstnt_ss_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="52*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="st1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mz_p_br">ST1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="stnt1b_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mz_p_br">STNT1B (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="st1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mz_p_br">ST1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="stnt1h_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mz_p_br">STNT1H (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="st1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mz_p_br">ST1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="stnt1w_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mz_p_br">STNT1W (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="st1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mz_p_br">ST1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mz_p_br_2" arch_version="FEAT_SVE2p1" iformfile="stnt1d_mz_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mz_p_br">STNT1D (scalar plus scalar, consecutive registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_mem_nctg">SME2 Multi-vector - Memory (Strided)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_cld_cldnt_si_nctg" title="SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="Ztl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cld_cldnt_si_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="51*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ld1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mzx_p_bi">LD1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ldnt1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mzx_p_bi">LDNT1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ld1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mzx_p_bi">LD1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ldnt1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mzx_p_bi">LDNT1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ld1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mzx_p_bi">LD1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ldnt1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mzx_p_bi">LDNT1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ld1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mzx_p_bi">LD1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="ldnt1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mzx_p_bi">LDNT1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cld_cldnt_si_nctg" title="SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="Ztl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cld_cldnt_si_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="51*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ld1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mzx_p_bi">LD1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ldnt1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mzx_p_bi">LDNT1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ld1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mzx_p_bi">LD1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ldnt1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mzx_p_bi">LDNT1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ld1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mzx_p_bi">LD1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ldnt1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mzx_p_bi">LDNT1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ld1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mzx_p_bi">LD1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="ldnt1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mzx_p_bi">LDNT1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cld_cldnt_ss_nctg" title="SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="Ztl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cld_cldnt_ss_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="48*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ld1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mzx_p_br">LD1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ldnt1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mzx_p_br">LDNT1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ld1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mzx_p_br">LD1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ldnt1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mzx_p_br">LDNT1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ld1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mzx_p_br">LD1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ldnt1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mzx_p_br">LDNT1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ld1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mzx_p_br">LD1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="ldnt1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mzx_p_br">LDNT1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cld_cldnt_ss_nctg" title="SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="Ztl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cld_cldnt_ss_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="48*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ld1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1b_mzx_p_br">LD1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1b_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ldnt1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1b_mzx_p_br">LDNT1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ld1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1h_mzx_p_br">LD1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1h_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ldnt1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1h_mzx_p_br">LDNT1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ld1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1w_mzx_p_br">LD1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1w_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ldnt1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1w_mzx_p_br">LDNT1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ld1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ld1d_mzx_p_br">LD1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldnt1d_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="ldnt1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ldnt1d_mzx_p_br">LDNT1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cst_cstnt_si_nctg" title="SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="Ztl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cst_cstnt_si_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="51*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="st1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mzx_p_bi">ST1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="stnt1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mzx_p_bi">STNT1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="st1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mzx_p_bi">ST1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="stnt1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mzx_p_bi">STNT1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="st1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mzx_p_bi">ST1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="stnt1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mzx_p_bi">STNT1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="st1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mzx_p_bi">ST1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mzx_p_bi_4x4" arch_version="FEAT_SME2" iformfile="stnt1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mzx_p_bi">STNT1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cst_cstnt_si_nctg" title="SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="Ztl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cst_cstnt_si_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="51*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="st1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mzx_p_bi">ST1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="stnt1b_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mzx_p_bi">STNT1B (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="st1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mzx_p_bi">ST1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="stnt1h_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mzx_p_bi">STNT1H (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="st1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mzx_p_bi">ST1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="stnt1w_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mzx_p_bi">STNT1W (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="st1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mzx_p_bi">ST1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mzx_p_bi_2x8" arch_version="FEAT_SME2" iformfile="stnt1d_mzx_p_bi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mzx_p_bi">STNT1D (scalar plus immediate, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_cst_cstnt_ss_nctg" title="SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="Ztl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_cst_cstnt_ss_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="48*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="st1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mzx_p_br">ST1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="stnt1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mzx_p_br">STNT1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="st1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mzx_p_br">ST1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="stnt1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mzx_p_br">STNT1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="st1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mzx_p_br">ST1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="stnt1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mzx_p_br">STNT1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="st1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mzx_p_br">ST1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mzx_p_br_4x4" arch_version="FEAT_SME2" iformfile="stnt1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mzx_p_br">STNT1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_cst_cstnt_ss_nctg" title="SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zth" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="Ztl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_cst_cstnt_ss_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="48*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="st1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1b_mzx_p_br">ST1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1b_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="stnt1b_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1b_mzx_p_br">STNT1B (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="st1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1h_mzx_p_br">ST1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1h_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="stnt1h_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1h_mzx_p_br">STNT1H (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="st1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1w_mzx_p_br">ST1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1w_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="stnt1w_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1w_mzx_p_br">STNT1W (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="st1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="st1d_mzx_p_br">ST1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="stnt1d_mzx_p_br_2x8" arch_version="FEAT_SME2" iformfile="stnt1d_mzx_p_br.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="stnt1d_mzx_p_br">STNT1D (scalar plus scalar, strided registers)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_32bit_int_prod">SME Integer Outer Product - 32 bit</funcgroupheader>
|
|
<iclass_sect id="mortlach_i8i32_prod" title="SME Int8 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="u0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" name="u1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_i8i32_prod" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">u0</th>
|
|
<th class="bitfields">u1</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smopa_za_pp_zz_32" arch_version="FEAT_SME" iformfile="smopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smopa_za_pp_zz">SMOPA (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smops_za_pp_zz_32" arch_version="FEAT_SME" iformfile="smops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smops_za_pp_zz">SMOPS (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumopa_za_pp_zz_32" arch_version="FEAT_SME" iformfile="sumopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sumopa_za_pp_zz">SUMOPA</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumops_za_pp_zz_32" arch_version="FEAT_SME" iformfile="sumops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sumops_za_pp_zz">SUMOPS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmopa_za_pp_zz_32" arch_version="FEAT_SME" iformfile="usmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usmopa_za_pp_zz">USMOPA</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmops_za_pp_zz_32" arch_version="FEAT_SME" iformfile="usmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmops_za_pp_zz">USMOPS</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umopa_za_pp_zz_32" arch_version="FEAT_SME" iformfile="umopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umopa_za_pp_zz">UMOPA (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umops_za_pp_zz_32" arch_version="FEAT_SME" iformfile="umops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umops_za_pp_zz">UMOPS (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_i16i32_prod" title="SME2 Int16 two-way outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="u0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="ZAda" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_i16i32_prod" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">u0</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smopa_za32_pp_zz_16" arch_version="FEAT_SME2" iformfile="smopa_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smopa_za32_pp_zz">SMOPA (2-way)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smops_za32_pp_zz_16" arch_version="FEAT_SME2" iformfile="smops_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smops_za32_pp_zz">SMOPS (2-way)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umopa_za32_pp_zz_16" arch_version="FEAT_SME2" iformfile="umopa_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umopa_za32_pp_zz">UMOPA (2-way)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umops_za32_pp_zz_16" arch_version="FEAT_SME2" iformfile="umops_za32_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umops_za32_pp_zz">UMOPS (2-way)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_64bit_prod">SME Outer Product - 64 bit</funcgroupheader>
|
|
<iclass_sect id="mortlach_f64f64_prod" title="SME FP64 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="ZAda" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_f64f64_prod" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmopa_za_pp_zz_64" arch_version="FEAT_SME_F64F64" iformfile="fmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmopa_za_pp_zz">FMOPA (non-widening)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmops_za_pp_zz_64" arch_version="FEAT_SME_F64F64" iformfile="fmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmops_za_pp_zz">FMOPS (non-widening)</td>
|
|
<td class="enctags">Double-precision</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_i16i64_prod" title="SME Int16 outer product">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="29" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="u0" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="21" name="u1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="ZAda" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_i16i64_prod" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">u0</th>
|
|
<th class="bitfields">u1</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smopa_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="smopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smopa_za_pp_zz">SMOPA (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smops_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="smops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smops_za_pp_zz">SMOPS (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumopa_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="sumopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sumopa_za_pp_zz">SUMOPA</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumops_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="sumops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sumops_za_pp_zz">SUMOPS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmopa_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="usmopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usmopa_za_pp_zz">USMOPA</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmops_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="usmops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmops_za_pp_zz">USMOPS</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umopa_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="umopa_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umopa_za_pp_zz">UMOPA (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umops_za_pp_zz_64" arch_version="FEAT_SME_I16I64" iformfile="umops_za_pp_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umops_za_pp_zz">UMOPS (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_zero">SME Zero</funcgroupheader>
|
|
<iclass_sect id="mortlach_zero" title="SME zero array">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_zero" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zero_za_i_" arch_version="FEAT_SME" iformfile="zero_za_i.xml" first="t" last="t">
|
|
<td class="iformname" iformid="zero_za_i">ZERO (tile)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multizero">SME2 Multiple Zero</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi_zero" title="SME multiple vectors zero array">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="12" settings="12">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="17" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="opc2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi_zero" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="22*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_503" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">x1x</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za1_ri_2" arch_version="FEAT_SME2p1" iformfile="zero_za1_ri.xml" label="two ZA single-vectors" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="zero_za1_ri">ZERO (single-vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za2_ri_1" arch_version="FEAT_SME2p1" iformfile="zero_za2_ri.xml" label="one ZA double-vector" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="zero_za2_ri">ZERO (double-vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za2_ri_2" arch_version="FEAT_SME2p1" iformfile="zero_za2_ri.xml" label="two ZA double-vectors" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="zero_za2_ri">ZERO (double-vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za2_ri_4" arch_version="FEAT_SME2p1" iformfile="zero_za2_ri.xml" label="four ZA double-vectors" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="zero_za2_ri">ZERO (double-vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za1_ri_4" arch_version="FEAT_SME2p1" iformfile="zero_za1_ri.xml" label="four ZA single-vectors" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="zero_za1_ri">ZERO (single-vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za4_ri_1" arch_version="FEAT_SME2p1" iformfile="zero_za4_ri.xml" label="one ZA quad-vector" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="zero_za4_ri">ZERO (quad-vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_504" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_505" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za4_ri_2" arch_version="FEAT_SME2p1" iformfile="zero_za4_ri.xml" label="two ZA quad-vectors" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td class="iformname" iformid="zero_za4_ri">ZERO (quad-vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_za4_ri_4" arch_version="FEAT_SME2p1" iformfile="zero_za4_ri.xml" label="four ZA quad-vectors" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td class="iformname" iformid="zero_za4_ri">ZERO (quad-vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_zero_zt">SME2 Zero Lookup Table</funcgroupheader>
|
|
<iclass_sect id="mortlach_zero_zt" title="SME2 zero lookup table">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_zero_zt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_506" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0000</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="zero_zt_i_" arch_version="FEAT_SME2" iformfile="zero_zt_i.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">0001</td>
|
|
<td class="iformname" iformid="zero_zt_i">ZERO (ZT0)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_507" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">001x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_508" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_509" undef="1" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_mov_zt">SME2 Move Lookup Table</funcgroupheader>
|
|
<iclass_sect id="mortlach_extract_zt" title="SME2 move from lookup table">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="7" name="opc" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_extract_zt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_510" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">000xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_511" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0010xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_512" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">00110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_513" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">001110x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_514" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0011110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movt_r_zt_" arch_version="FEAT_SME2" iformfile="movt_r_zt.xml" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0011111</td>
|
|
<td class="iformname" iformid="movt_r_zt">MOVT (ZT0 to scalar)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_515" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">01xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_516" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">1xxxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_insert_zt" title="SME2 move into lookup table">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="11" width="7" name="opc" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Rt" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_insert_zt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_517" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">000xxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_518" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0010xxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_519" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">00110xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_520" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">001110x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_521" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0011110</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movt_zt_r_" arch_version="FEAT_SME2" iformfile="movt_zt_r.xml" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">0011111</td>
|
|
<td class="iformname" iformid="movt_zt_r">MOVT (scalar to ZT0)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_522" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">01xxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_523" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="7" class="bitfield">1xxxxxx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_zt_expand_nctg">SME2 Expand Lookup Table (Non-contiguous)</funcgroupheader>
|
|
<iclass_sect id="mortlach_expand_4dst_nctg" title="SME2 lookup table expand four non-contiguous registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zdh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="Zdl" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_expand_4dst_nctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_542" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti4_mz4_ztz_4" arch_version="FEAT_SME2p1" iformfile="luti4_mz4_ztz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti4_mz4_ztz">LUTI4 (four registers)</td>
|
|
<td class="enctags">Strided</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_545" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_546" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti2_mz4_ztz_4" arch_version="FEAT_SME2p1" iformfile="luti2_mz4_ztz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti2_mz4_ztz">LUTI2 (four registers)</td>
|
|
<td class="enctags">Strided</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_549" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_550" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_expand_2dst_nctg" title="SME2 lookup table expand two non-contiguous registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="11" settings="11">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="Zdh" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="Zdl" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_expand_2dst_nctg" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_541" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">00xx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti4_mz2_ztz_8" arch_version="FEAT_SME2p1" iformfile="luti4_mz2_ztz.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti4_mz2_ztz">LUTI4 (two registers)</td>
|
|
<td class="enctags">Strided</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_543" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_544" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti2_mz2_ztz_8" arch_version="FEAT_SME2p1" iformfile="luti2_mz2_ztz.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti2_mz2_ztz">LUTI2 (two registers)</td>
|
|
<td class="enctags">Strided</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_547" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_548" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_zt_expand_ctg">SME2 Expand Lookup Table (Contiguous)</funcgroupheader>
|
|
<iclass_sect id="mortlach_expand_4dst_ctg" title="SME2 lookup table expand four contiguous registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="13" settings="13">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_expand_4dst_ctg" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_531" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">00x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti4_mz4_ztz_1" arch_version="FEAT_SME2" iformfile="luti4_mz4_ztz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti4_mz4_ztz">LUTI4 (four registers)</td>
|
|
<td class="enctags">Consecutive</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_534" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_535" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti2_mz4_ztz_1" arch_version="FEAT_SME2" iformfile="luti2_mz4_ztz.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti2_mz4_ztz">LUTI2 (four registers)</td>
|
|
<td class="enctags">Consecutive</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_538" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_539" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_expand_1dst" title="SME2 lookup table expand one register">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="13" settings="13">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="5" name="opc" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="13" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_expand_1dst" cols="4">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_551" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">00xxx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti4_z_ztz_" arch_version="FEAT_SME2" iformfile="luti4_z_ztz.xml" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">01xxx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti4_z_ztz">LUTI4 (single)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_552" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">01xxx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_553" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">01xxx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti2_z_ztz_" arch_version="FEAT_SME2" iformfile="luti2_z_ztz.xml" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti2_z_ztz">LUTI2 (single)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_554" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_555" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="5" class="bitfield">1xxxx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_expand_2dst_ctg" title="SME2 lookup table expand two contiguous registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="13" settings="13">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="14" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="13" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_expand_2dst_ctg" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<col colno="4" printwidth="13*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_530" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">00xx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti4_mz2_ztz_1" arch_version="FEAT_SME2" iformfile="luti4_mz2_ztz.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti4_mz2_ztz">LUTI4 (two registers)</td>
|
|
<td class="enctags">Consecutive</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_532" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_533" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">01xx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="luti2_mz2_ztz_1" arch_version="FEAT_SME2" iformfile="luti2_mz2_ztz.xml" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="luti2_mz2_ztz">LUTI2 (two registers)</td>
|
|
<td class="enctags">Consecutive</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_536" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_537" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="4" class="bitfield">1xxx</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_ins">SME Move into Array</funcgroupheader>
|
|
<iclass_sect id="mortlach_insert_pred" title="SME move vector to array">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_insert_pred" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="31*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">Q</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_497" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za_p_rz_b" arch_version="FEAT_SME" iformfile="mova_za_p_rz.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_za_p_rz">MOVA (vector to tile, single)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za_p_rz_h" arch_version="FEAT_SME" iformfile="mova_za_p_rz.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_za_p_rz">MOVA (vector to tile, single)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za_p_rz_w" arch_version="FEAT_SME" iformfile="mova_za_p_rz.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_za_p_rz">MOVA (vector to tile, single)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_524" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za_p_rz_d" arch_version="FEAT_SME" iformfile="mova_za_p_rz.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_za_p_rz">MOVA (vector to tile, single)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za_p_rz_q" arch_version="FEAT_SME" iformfile="mova_za_p_rz.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mova_za_p_rz">MOVA (vector to tile, single)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_za_insert_ctg" title="SME2 move vector to array, four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="15" settings="15">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_za_insert_ctg" cols="2">
|
|
<col colno="1" printwidth="40*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_za_mz4_1" arch_version="FEAT_SME2" iformfile="mova_za_mz4.xml" first="t" last="t">
|
|
<td class="iformname" iformid="mova_za_mz4">MOVA (vector to array, four registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_za_insert_ctg" title="SME2 move vector to array, two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="15" settings="15">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_za_insert_ctg" cols="2">
|
|
<col colno="1" printwidth="39*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_za_mz2_1" arch_version="FEAT_SME2" iformfile="mova_za_mz2.xml" first="t" last="t">
|
|
<td class="iformname" iformid="mova_za_mz2">MOVA (vector to array, two registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_insert_ctg" title="SME2 move vector to tile, four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_insert_ctg" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="39*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_500" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za4_z_b1" arch_version="FEAT_SME2" iformfile="mova_za4_z.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_za4_z">MOVA (vector to tile, four registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za4_z_h1" arch_version="FEAT_SME2" iformfile="mova_za4_z.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_za4_z">MOVA (vector to tile, four registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za4_z_w1" arch_version="FEAT_SME2" iformfile="mova_za4_z.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_za4_z">MOVA (vector to tile, four registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_527" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za4_z_d1" arch_version="FEAT_SME2" iformfile="mova_za4_z.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="mova_za4_z">MOVA (vector to tile, four registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_insert_ctg" title="SME2 move vector to tile, two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_insert_ctg" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="38*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_za2_z_b1" arch_version="FEAT_SME2" iformfile="mova_za2_z.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="mova_za2_z">MOVA (vector to tile, two registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za2_z_h1" arch_version="FEAT_SME2" iformfile="mova_za2_z.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="mova_za2_z">MOVA (vector to tile, two registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za2_z_w1" arch_version="FEAT_SME2" iformfile="mova_za2_z.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="mova_za2_z">MOVA (vector to tile, two registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_za2_z_d1" arch_version="FEAT_SME2" iformfile="mova_za2_z.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="mova_za2_z">MOVA (vector to tile, two registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_ext">SME Move from Array</funcgroupheader>
|
|
<iclass_sect id="mortlach_extract_pred" title="SME move array to vector">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_extract_pred" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="31*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">Q</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_498" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_z_p_rza_b" arch_version="FEAT_SME" iformfile="mova_z_p_rza.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_z_p_rza">MOVA (tile to vector, single)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_z_p_rza_h" arch_version="FEAT_SME" iformfile="mova_z_p_rza.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_z_p_rza">MOVA (tile to vector, single)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_z_p_rza_w" arch_version="FEAT_SME" iformfile="mova_z_p_rza.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_z_p_rza">MOVA (tile to vector, single)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_525" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_z_p_rza_d" arch_version="FEAT_SME" iformfile="mova_z_p_rza.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="mova_z_p_rza">MOVA (tile to vector, single)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_z_p_rza_q" arch_version="FEAT_SME" iformfile="mova_z_p_rza.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="mova_z_p_rza">MOVA (tile to vector, single)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_extract_zero" title="SME zeroing move array to vector">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="16" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="8" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_extract_zero" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="32*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">Q</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_499" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_z_rza_b" arch_version="FEAT_SME2p1" iformfile="movaz_z_rza.xml" label="8-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="movaz_z_rza">MOVAZ (tile to vector, single)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_z_rza_h" arch_version="FEAT_SME2p1" iformfile="movaz_z_rza.xml" label="16-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="movaz_z_rza">MOVAZ (tile to vector, single)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_z_rza_w" arch_version="FEAT_SME2p1" iformfile="movaz_z_rza.xml" label="32-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="movaz_z_rza">MOVAZ (tile to vector, single)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_526" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_z_rza_d" arch_version="FEAT_SME2p1" iformfile="movaz_z_rza.xml" label="64-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="movaz_z_rza">MOVAZ (tile to vector, single)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_z_rza_q" arch_version="FEAT_SME2p1" iformfile="movaz_z_rza.xml" label="128-bit" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="movaz_z_rza">MOVAZ (tile to vector, single)</td>
|
|
<td class="enctags">128-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_za_extract_ctg" title="SME2 move array to vector, four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_za_extract_ctg" cols="2">
|
|
<col colno="1" printwidth="40*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_mz_za4_1" arch_version="FEAT_SME2" iformfile="mova_mz_za4.xml" first="t" last="t">
|
|
<td class="iformname" iformid="mova_mz_za4">MOVA (array to vector, four registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_za_extract_ctg" title="SME2 move array to vector, two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_za_extract_ctg" cols="2">
|
|
<col colno="1" printwidth="39*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_mz_za2_1" arch_version="FEAT_SME2" iformfile="mova_mz_za2.xml" first="t" last="t">
|
|
<td class="iformname" iformid="mova_mz_za2">MOVA (array to vector, two registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_extract_ctg" title="SME2 move tile to vector, four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_extract_ctg" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="39*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_501" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz4_za_b1" arch_version="FEAT_SME2" iformfile="mova_mz4_za.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_mz4_za">MOVA (tile to vector, four registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz4_za_h1" arch_version="FEAT_SME2" iformfile="mova_mz4_za.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_mz4_za">MOVA (tile to vector, four registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz4_za_w1" arch_version="FEAT_SME2" iformfile="mova_mz4_za.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="mova_mz4_za">MOVA (tile to vector, four registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_528" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz4_za_d1" arch_version="FEAT_SME2" iformfile="mova_mz4_za.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="mova_mz4_za">MOVA (tile to vector, four registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_extract_ctg" title="SME2 move tile to vector, two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_extract_ctg" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="38*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="mova_mz2_za_b1" arch_version="FEAT_SME2" iformfile="mova_mz2_za.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="mova_mz2_za">MOVA (tile to vector, two registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz2_za_h1" arch_version="FEAT_SME2" iformfile="mova_mz2_za.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="mova_mz2_za">MOVA (tile to vector, two registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz2_za_w1" arch_version="FEAT_SME2" iformfile="mova_mz2_za.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="mova_mz2_za">MOVA (tile to vector, two registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="mova_mz2_za_d1" arch_version="FEAT_SME2" iformfile="mova_mz2_za.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="mova_mz2_za">MOVA (tile to vector, two registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_extract_zero" title="SME2 zeroing move tile to vector, four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_extract_zero" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="40*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_502" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz4_za_b1" arch_version="FEAT_SME2p1" iformfile="movaz_mz4_za.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="movaz_mz4_za">MOVAZ (tile to vector, four registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz4_za_h1" arch_version="FEAT_SME2p1" iformfile="movaz_mz4_za.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="movaz_mz4_za">MOVAZ (tile to vector, four registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz4_za_w1" arch_version="FEAT_SME2p1" iformfile="movaz_mz4_za.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="movaz_mz4_za">MOVAZ (tile to vector, four registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_529" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz4_za_d1" arch_version="FEAT_SME2p1" iformfile="movaz_mz4_za.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="movaz_mz4_za">MOVAZ (tile to vector, four registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_extract_zero" title="SME2 zeroing move tile to vector, two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_extract_zero" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="39*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="movaz_mz2_za_b1" arch_version="FEAT_SME2p1" iformfile="movaz_mz2_za.xml" label="8-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="movaz_mz2_za">MOVAZ (tile to vector, two registers)</td>
|
|
<td class="enctags">8-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz2_za_h1" arch_version="FEAT_SME2p1" iformfile="movaz_mz2_za.xml" label="16-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="movaz_mz2_za">MOVAZ (tile to vector, two registers)</td>
|
|
<td class="enctags">16-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz2_za_w1" arch_version="FEAT_SME2p1" iformfile="movaz_mz2_za.xml" label="32-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="movaz_mz2_za">MOVAZ (tile to vector, two registers)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="movaz_mz2_za_d1" arch_version="FEAT_SME2p1" iformfile="movaz_mz2_za.xml" label="64-bit" oneofthismnem="4" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="movaz_mz2_za">MOVAZ (tile to vector, two registers)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_za_extract_zero" title="mortlach_multi2_za_extract_zero">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_za_extract_zero" cols="2">
|
|
<col colno="1" printwidth="40*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="movaz_mz_za2_1" arch_version="FEAT_SME2p1" iformfile="movaz_mz_za2.xml" first="t" last="t">
|
|
<td class="iformname" iformid="movaz_mz_za2">MOVAZ (array to vector, two registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_za_extract_zero" title="mortlach_multi4_za_extract_zero">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="17" settings="17">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_za_extract_zero" cols="2">
|
|
<col colno="1" printwidth="41*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="movaz_mz_za4_1" arch_version="FEAT_SME2p1" iformfile="movaz_mz_za4.xml" first="t" last="t">
|
|
<td class="iformname" iformid="movaz_mz_za4">MOVAZ (array to vector, four registers)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_hvadd">SME Add Vector to Array</funcgroupheader>
|
|
<iclass_sect id="mortlach_addhv" title="SME add vector to array">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="16" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="15" width="3" name="Pm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="opc2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_addhv" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="6*" />
|
|
<col colno="4" printwidth="18*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">V</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_540" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addha_za_pp_z_32" arch_version="FEAT_SME" iformfile="addha_za_pp_z.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="addha_za_pp_z">ADDHA</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addva_za_pp_z_32" arch_version="FEAT_SME" iformfile="addva_za_pp_z.xml" label="32-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">0xx</td>
|
|
<td class="iformname" iformid="addva_za_pp_z">ADDVA</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addha_za_pp_z_64" arch_version="FEAT_SME_I16I64" iformfile="addha_za_pp_z.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="addha_za_pp_z">ADDHA</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="addva_za_pp_z_64" arch_version="FEAT_SME_I16I64" iformfile="addva_za_pp_z.xml" label="64-bit" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname" iformid="addva_za_pp_z">ADDVA</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_array_1">SME2 Multi-vector - Multiple and Single Array Vectors</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi1_zz_za_fma_long_sm" title="SME2 multiple and single vector long FMA one source">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_zz_za_fma_long_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzv_1" arch_version="FEAT_SME2" iformfile="fmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzv">FMLAL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzv_1" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzv">FMLSL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzv_1" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzv">BFMLAL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzv_1" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzv">BFMLSL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi1_zz_za_mla_long_sm" title="SME2 multiple and single vector long MLA one source">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_zz_za_mla_long_sm" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzv_1" arch_version="FEAT_SME2" iformfile="smlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzv">SMLAL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzv_1" arch_version="FEAT_SME2" iformfile="smlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzv">SMLSL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzv_1" arch_version="FEAT_SME2" iformfile="umlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzv">UMLAL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzv_1" arch_version="FEAT_SME2" iformfile="umlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzv">UMLSL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi1_zz_za_mla_long_long_sm" title="SME2 multiple and single vector long long FMA one source">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_zz_za_mla_long_long_sm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="38*" />
|
|
<col colno="6" printwidth="20*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzv_1" arch_version="FEAT_SME2" iformfile="smlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzv">SMLALL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzv_1" arch_version="FEAT_SME2" iformfile="smlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzv">SMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzv_1" arch_version="FEAT_SME2" iformfile="umlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzv">UMLALL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzv_1" arch_version="FEAT_SME2" iformfile="umlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzv">UMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzv_s" arch_version="FEAT_SME2" iformfile="usmlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzv">USMLALL (multiple and single vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_560" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_561" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_580" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_fpdot_sm" title="SME2 single-multi FP dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_fpdot_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="fdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fdot_za_zzv">FDOT (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="bfdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="bfdot_za_zzv">BFDOT (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_585" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_586" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_fpdot_sm" title="SME2 single-multi FP dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_fpdot_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="fdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fdot_za_zzv">FDOT (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="bfdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="bfdot_za_zzv">BFDOT (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_581" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_582" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_4way_dot_sm" title="SME2 single-multi four-way dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_4way_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="42*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="sdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za_zzv">SDOT (4-way, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="udot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za_zzv">UDOT (4-way, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_4way_dot_sm" title="SME2 single-multi four-way dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_4way_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="42*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="sdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za_zzv">SDOT (4-way, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="udot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za_zzv">UDOT (4-way, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_fma_long_sm" title="SME2 single-multi long FMA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_fma_long_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzv">FMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzv">FMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzv">BFMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzv">BFMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_fma_long_sm" title="SME2 single-multi long FMA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_fma_long_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzv">FMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzv">FMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzv">BFMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzv">BFMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_mla_long_sm" title="SME2 single-multi long MLA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_mla_long_sm" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="smlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzv">SMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="smlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzv">SMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="umlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzv">UMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="umlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzv">UMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_mla_long_sm" title="SME2 single-multi long MLA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_mla_long_sm" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="smlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzv">SMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="smlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzv">SMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="umlal_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzv">UMLAL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="umlsl_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzv">UMLSL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_mla_long_long_sm" title="SME2 single-multi long long MLA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_mla_long_long_sm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="38*" />
|
|
<col colno="6" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="smlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzv">SMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="smlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzv">SMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="umlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzv">UMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="umlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzv">UMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_576" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzv_s4x1" arch_version="FEAT_SME2" iformfile="usmlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzv">USMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumlall_za_zzv_s4x1" arch_version="FEAT_SME2" iformfile="sumlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sumlall_za_zzv">SUMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_584" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_mla_long_long_sm" title="SME2 single-multi long long MLA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_mla_long_long_sm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="38*" />
|
|
<col colno="6" printwidth="21*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="smlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzv">SMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="smlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzv">SMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="umlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzv">UMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="umlsll_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzv">UMLSLL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_559" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzv_s2x1" arch_version="FEAT_SME2" iformfile="usmlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzv">USMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumlall_za_zzv_s2x1" arch_version="FEAT_SME2" iformfile="sumlall_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sumlall_za_zzv">SUMLALL (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_579" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_mixed_dot_sm" title="SME2 single-multi mixed dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_mixed_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="36*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="usdot_za_zzv_s4x1" arch_version="FEAT_SME2" iformfile="usdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usdot_za_zzv">USDOT (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sudot_za_zzv_s4x1" arch_version="FEAT_SME2" iformfile="sudot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sudot_za_zzv">SUDOT (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_mixed_dot_sm" title="SME2 single-multi mixed dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_mixed_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="36*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="usdot_za_zzv_s2x1" arch_version="FEAT_SME2" iformfile="usdot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usdot_za_zzv">USDOT (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sudot_za_zzv_s2x1" arch_version="FEAT_SME2" iformfile="sudot_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sudot_za_zzv">SUDOT (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_float_sm" title="SME2 single-multi ternary FP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_float_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="35*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzv">FMLA (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzv">FMLS (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_float_sm" title="SME2 single-multi ternary FP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_float_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="35*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzv">FMLA (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzv">FMLS (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_f16_sm" title="SME2 single-multi ternary FP16 four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_f16_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="51*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzv_4x1_16" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzv">FMLA (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzv_4x1_16" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzv">FMLS (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzv_4x1_16" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzv">BFMLA (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzv_4x1_16" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzv">BFMLS (multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_f16_sm" title="SME2 single-multi ternary FP16 two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_f16_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="50*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzv_2x1_16" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzv">FMLA (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzv_2x1_16" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzv">FMLS (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzv_2x1_16" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzv">BFMLA (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzv_2x1_16" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzv">BFMLS (multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_int_sm" title="SME2 single-multi ternary int four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_int_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="49*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="add_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zzv">ADD (array results, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zzv_4x1" arch_version="FEAT_SME2" iformfile="sub_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zzv">SUB (array results, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_int_sm" title="SME2 single-multi ternary int two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_int_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="49*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="add_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zzv">ADD (array results, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zzv_2x1" arch_version="FEAT_SME2" iformfile="sub_za_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zzv">SUB (array results, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_2way_dot_sm" title="SME2 single-multi two-way dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_2way_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="42*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za32_zzv_4x1" arch_version="FEAT_SME2" iformfile="sdot_za32_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za32_zzv">SDOT (2-way, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzv_4x1" arch_version="FEAT_SME2" iformfile="udot_za32_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za32_zzv">UDOT (2-way, multiple and single vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_2way_dot_sm" title="SME2 single-multi two-way dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="10" settings="10">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_2way_dot_sm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="42*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za32_zzv_2x1" arch_version="FEAT_SME2" iformfile="sdot_za32_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za32_zzv">SDOT (2-way, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzv_2x1" arch_version="FEAT_SME2" iformfile="udot_za32_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za32_zzv">UDOT (2-way, multiple and single vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_array_2a">SME2 Multi-vector - Multiple Array Vectors (Two registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi2_z_za_fpdot_mm" title="SME2 multiple vectors FP dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_fpdot_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="fdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fdot_za_zzw">FDOT (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="bfdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="bfdot_za_zzw">BFDOT (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_600" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_601" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_float_mm" title="SME2 multiple vectors binary FP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_float_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadd_za_zw_2x2" arch_version="FEAT_SME2" iformfile="fadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fadd_za_zw">FADD</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_za_zw_2x2" arch_version="FEAT_SME2" iformfile="fsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fsub_za_zw">FSUB</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_f16_mm" title="SME2 multiple vectors binary FP16 two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_f16_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="50*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadd_za_zw_2x2_16" arch_version="FEAT_SME_F16F16" iformfile="fadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fadd_za_zw">FADD</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_za_zw_2x2_16" arch_version="FEAT_SME_F16F16" iformfile="fsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fsub_za_zw">FSUB</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfadd_za_zw_2x2_16" arch_version="FEAT_B16B16" iformfile="bfadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfadd_za_zw">BFADD</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfsub_za_zw_2x2_16" arch_version="FEAT_B16B16" iformfile="bfsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfsub_za_zw">BFSUB</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_int_mm" title="SME2 multiple vectors binary int two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_int_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="26*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zw_2x2" arch_version="FEAT_SME2" iformfile="add_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zw">ADD (array accumulators)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zw_2x2" arch_version="FEAT_SME2" iformfile="sub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zw">SUB (array accumulators)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_4way_dot_mm" title="SME2 multiple vectors four-way dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_4way_dot_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="32*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="sdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za_zzw">SDOT (4-way, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="udot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za_zzw">UDOT (4-way, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_fma_long_mm" title="SME2 multiple vectors long FMA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_fma_long_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzw">FMLAL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzw">FMLSL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzw">BFMLAL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzw">BFMLSL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_mla_long_mm" title="SME2 multiple vectors long MLA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_mla_long_mm" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="smlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzw">SMLAL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="smlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzw">SMLSL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="umlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzw">UMLAL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="umlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzw">UMLSL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_mla_long_long_mm" title="SME2 multiple vectors long long MLA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_mla_long_long_mm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<col colno="6" printwidth="21*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="smlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzw">SMLALL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="smlsll_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzw">SMLSLL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="umlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzw">UMLALL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="umlsll_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzw">UMLSLL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzw_s2x2" arch_version="FEAT_SME2" iformfile="usmlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzw">USMLALL (multiple vectors)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_588" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_589" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_599" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_mixed_dot_mm" title="SME2 multiple vectors mixed dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_mixed_dot_mm" cols="2">
|
|
<col colno="1" printwidth="26*" />
|
|
<col colno="2" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="usdot_za_zzw_s2x2" arch_version="FEAT_SME2" iformfile="usdot_za_zzw.xml" first="t" last="t">
|
|
<td class="iformname" iformid="usdot_za_zzw">USDOT (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_float_mm" title="SME2 multiple vectors ternary FP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_float_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="25*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzw">FMLA (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzw">FMLS (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_f16_mm" title="SME2 multiple vectors ternary FP16 two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_f16_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="50*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzw_2x2_16" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzw">FMLA (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzw_2x2_16" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzw">FMLS (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzw_2x2_16" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzw">BFMLA (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzw_2x2_16" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzw">BFMLS (multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zz_za_int_mm" title="SME2 multiple vectors ternary int two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zz_za_int_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="39*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="add_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zzw">ADD (array results, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zzw_2x2" arch_version="FEAT_SME2" iformfile="sub_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zzw">SUB (array results, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_za_2way_dot_mm" title="SME2 multiple vectors two-way dot product two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_za_2way_dot_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="32*" />
|
|
<col colno="3" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za32_zzw_2x2" arch_version="FEAT_SME2" iformfile="sdot_za32_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za32_zzw">SDOT (2-way, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzw_2x2" arch_version="FEAT_SME2" iformfile="udot_za32_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za32_zzw">UDOT (2-way, multiple vectors)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_array_2b">SME2 Multi-vector - Multiple Array Vectors (Four registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_z_za_fpdot_mm" title="SME2 multiple vectors FP dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_fpdot_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fdot_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="fdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fdot_za_zzw">FDOT (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="bfdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="bfdot_za_zzw">BFDOT (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_603" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_604" undef="1" oneofthismnem="2" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_float_mm" title="SME2 multiple vectors binary FP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_float_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadd_za_zw_4x4" arch_version="FEAT_SME2" iformfile="fadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fadd_za_zw">FADD</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_za_zw_4x4" arch_version="FEAT_SME2" iformfile="fsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fsub_za_zw">FSUB</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_f16_mm" title="SME2 multiple vectors binary FP16 four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_f16_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="51*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fadd_za_zw_4x4_16" arch_version="FEAT_SME_F16F16" iformfile="fadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fadd_za_zw">FADD</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fsub_za_zw_4x4_16" arch_version="FEAT_SME_F16F16" iformfile="fsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fsub_za_zw">FSUB</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfadd_za_zw_4x4_16" arch_version="FEAT_B16B16" iformfile="bfadd_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfadd_za_zw">BFADD</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfsub_za_zw_4x4_16" arch_version="FEAT_B16B16" iformfile="bfsub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfsub_za_zw">BFSUB</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_int_mm" title="SME2 multiple vectors binary int four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_int_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="26*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zw_4x4" arch_version="FEAT_SME2" iformfile="add_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zw">ADD (array accumulators)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zw_4x4" arch_version="FEAT_SME2" iformfile="sub_za_zw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zw">SUB (array accumulators)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_4way_dot_mm" title="SME2 multiple vectors four-way dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_4way_dot_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="32*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="sdot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za_zzw">SDOT (4-way, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="udot_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za_zzw">UDOT (4-way, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_fma_long_mm" title="SME2 multiple vectors long FMA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_fma_long_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="27*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzw">FMLAL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzw">FMLSL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzw">BFMLAL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzw">BFMLSL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_mla_long_mm" title="SME2 multiple vectors long MLA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_mla_long_mm" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="smlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzw">SMLAL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="smlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzw">SMLSL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="umlal_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzw">UMLAL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="umlsl_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzw">UMLSL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_mla_long_long_mm" title="SME2 multiple vectors long long MLA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_mla_long_long_mm" cols="6">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="4*" />
|
|
<col colno="5" printwidth="28*" />
|
|
<col colno="6" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="4">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="smlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzw">SMLALL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="smlsll_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzw">SMLSLL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="umlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzw">UMLALL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="umlsll_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzw">UMLSLL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzw_s4x4" arch_version="FEAT_SME2" iformfile="usmlall_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzw">USMLALL (multiple vectors)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_590" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_591" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_602" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_mixed_dot_mm" title="SME2 multiple vectors mixed dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_mixed_dot_mm" cols="2">
|
|
<col colno="1" printwidth="26*" />
|
|
<col colno="2" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="usdot_za_zzw_s4x4" arch_version="FEAT_SME2" iformfile="usdot_za_zzw.xml" first="t" last="t">
|
|
<td class="iformname" iformid="usdot_za_zzw">USDOT (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_float_mm" title="SME2 multiple vectors ternary FP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_float_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="25*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzw">FMLA (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzw">FMLS (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_f16_mm" title="SME2 multiple vectors ternary FP16 four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_f16_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="51*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">sz</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzw_4x4_16" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzw">FMLA (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzw_4x4_16" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzw">FMLS (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzw_4x4_16" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzw">BFMLA (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzw_4x4_16" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzw">BFMLS (multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zz_za_int_mm" title="SME2 multiple vectors ternary int four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zz_za_int_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="39*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="add_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="add_za_zzw">ADD (array results, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sub_za_zzw_4x4" arch_version="FEAT_SME2" iformfile="sub_za_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sub_za_zzw">SUB (array results, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_za_2way_dot_mm" title="SME2 multiple vectors two-way dot product four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="9" settings="9">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_za_2way_dot_mm" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="32*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sdot_za32_zzw_4x4" arch_version="FEAT_SME2" iformfile="sdot_za32_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sdot_za32_zzw">SDOT (2-way, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzw_4x4" arch_version="FEAT_SME2" iformfile="udot_za32_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="udot_za32_zzw">UDOT (2-way, multiple vectors)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_indexed_1">SME2 Multi-vector - Indexed (One register)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi1_fma_long_idx" title="SME2 multi-vec indexed long FMA one source">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" name="i3h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_fma_long_idx" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzi_1" arch_version="FEAT_SME2" iformfile="fmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzi">FMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzi_1" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzi">FMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzi_1" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzi">BFMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzi_1" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzi">BFMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi1_mla_long_idx" title="SME2 multi-vec indexed long MLA one source">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" name="i3h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_mla_long_idx" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="22*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzi_1" arch_version="FEAT_SME2" iformfile="smlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzi">SMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzi_1" arch_version="FEAT_SME2" iformfile="smlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzi">SMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzi_1" arch_version="FEAT_SME2" iformfile="umlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzi">UMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzi_1" arch_version="FEAT_SME2" iformfile="umlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzi">UMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA double-vector</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi1_mla_long_long_idx_s" title="SME2 multi-vec indexed long long MLA one source 32-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" name="i4h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="i4l" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_mla_long_long_idx_s" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="39*" />
|
|
<col colno="5" printwidth="39*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_556" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_s" arch_version="FEAT_SME2" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzi_s" arch_version="FEAT_SME2" iformfile="usmlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="usmlall_za_zzi">USMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_s" arch_version="FEAT_SME2" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_s" arch_version="FEAT_SME2" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumlall_za_zzi_s" arch_version="FEAT_SME2" iformfile="sumlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="sumlall_za_zzi">SUMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_s" arch_version="FEAT_SME2" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 32-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi1_mla_long_long_idx_d" title="SME2 multi-vec indexed long long MLA one source 64-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" name="i3h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi1_mla_long_long_idx_d" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="39*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_d" arch_version="FEAT_SME_I16I64" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_d" arch_version="FEAT_SME_I16I64" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_d" arch_version="FEAT_SME_I16I64" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_d" arch_version="FEAT_SME_I16I64" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">One ZA quad-vector of 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_indexed_2">SME2 Multi-vector - Indexed (Two registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi2_fma_long_idx" title="SME2 multi-vec indexed long FMA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_fma_long_idx" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="fmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzi">FMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzi">FMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzi">BFMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzi">BFMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_mla_long_idx" title="SME2 multi-vec indexed long MLA two sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_mla_long_idx" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="23*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="smlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzi">SMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="smlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzi">SMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="umlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzi">UMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="umlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzi">UMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_mla_long_long_idx_s" title="SME2 multi-vec indexed long long MLA two sources 32-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i4h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="2" name="i4l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_mla_long_long_idx_s" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="39*" />
|
|
<col colno="5" printwidth="40*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_557" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="usmlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usmlall_za_zzi">USMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumlall_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="sumlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sumlall_za_zzi">SUMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_mla_long_long_idx_d" title="SME2 multi-vec indexed long long MLA two sources 64-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="i3h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="2" name="i3l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_mla_long_long_idx_d" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="40*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zza_idx_h" title="SME2 multi-vec ternary indexed two registers 16-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zza_idx_h" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="50*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_h2xi" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_h2xi" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzi_h2xi" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzi">BFMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzi_h2xi" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzi">BFMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zza_idx_s" title="SME2 multi-vec ternary indexed two registers 32-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" width="3" name="opc2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zza_idx_s" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="43*" />
|
|
<col colno="4" printwidth="52*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of single precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fvdot_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="fvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="fvdot_za_zzi">FVDOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of single precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfvdot_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="bfvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="bfvdot_za_zzi">BFVDOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="svdot_za32_zzi_2xi" arch_version="FEAT_SME2" iformfile="svdot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="svdot_za32_zzi">SVDOT (2-way)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_578" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uvdot_za32_zzi_2xi" arch_version="FEAT_SME2" iformfile="uvdot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="uvdot_za32_zzi">UVDOT (2-way)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za32_zzi_2xi" arch_version="FEAT_SME2" iformfile="sdot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="sdot_za32_zzi">SDOT (2-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fdot_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="fdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="fdot_za_zzi">FDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzi_2xi" arch_version="FEAT_SME2" iformfile="udot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="udot_za32_zzi">UDOT (2-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzi_2xi" arch_version="FEAT_SME2" iformfile="bfdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="bfdot_za_zzi">BFDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="sdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="sdot_za_zzi">SDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usdot_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="usdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="usdot_za_zzi">USDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="udot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="udot_za_zzi">UDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sudot_za_zzi_s2xi" arch_version="FEAT_SME2" iformfile="sudot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="sudot_za_zzi">SUDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_zza_idx_d" title="SME2 multi-vec ternary indexed two registers 64-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="i1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="2" name="opc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_zza_idx_d" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="43*" />
|
|
<col colno="3" printwidth="52*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_d2xi" arch_version="FEAT_SME_F64F64" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of double precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="sdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="sdot_za_zzi">SDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_d2xi" arch_version="FEAT_SME_F64F64" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of double precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzi_d2xi" arch_version="FEAT_SME_I16I64" iformfile="udot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="udot_za_zzi">UDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Two ZA single-vectors of 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_indexed_3">SME2 Multi-vector - Indexed (Four registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_fma_long_idx" title="SME2 multi-vec indexed long FMA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_fma_long_idx" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmlal_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="fmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmlal_za_zzi">FMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmlsl_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="fmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmlsl_za_zzi">FMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlal_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="bfmlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmlal_za_zzi">BFMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmlsl_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="bfmlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmlsl_za_zzi">BFMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_mla_long_idx" title="SME2 multi-vec indexed long MLA four sources">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="1" width="2" name="off2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_mla_long_idx" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="24*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlal_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="smlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlal_za_zzi">SMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsl_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="smlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsl_za_zzi">SMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlal_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="umlal_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlal_za_zzi">UMLAL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsl_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="umlsl_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsl_za_zzi">UMLSL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA double-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_mla_long_long_idx_s" title="SME2 multi-vec indexed long long MLA four sources 32-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i4h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="2" name="i4l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_mla_long_long_idx_s" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="39*" />
|
|
<col colno="5" printwidth="41*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_558" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usmlall_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="usmlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="usmlall_za_zzi">USMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sumlall_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="sumlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sumlall_za_zzi">SUMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_mla_long_long_idx_d" title="SME2 multi-vec indexed long long MLA four sources 64-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="10" name="i3h" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="2" name="i3l" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="0" name="o1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_mla_long_long_idx_d" cols="4">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="38*" />
|
|
<col colno="4" printwidth="41*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smlall_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="smlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smlall_za_zzi">SMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smlsll_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="smlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="smlsll_za_zzi">SMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlall_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="umlall_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="umlall_za_zzi">UMLALL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umlsll_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="umlsll_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umlsll_za_zzi">UMLSLL (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA quad-vectors of 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zza_idx_h" title="SME2 multi-vec ternary indexed four registers 16-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i3h" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="3" name="i3l" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zza_idx_h" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="37*" />
|
|
<col colno="4" printwidth="51*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">S</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_h4xi" arch_version="FEAT_SME_F16F16" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_h4xi" arch_version="FEAT_SME_F16F16" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of half precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmla_za_zzi_h4xi" arch_version="FEAT_B16B16" iformfile="bfmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmla_za_zzi">BFMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmls_za_zzi_h4xi" arch_version="FEAT_B16B16" iformfile="bfmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmls_za_zzi">BFMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zza_idx_s" title="SME2 multi-vec ternary indexed four registers 32-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="i2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" width="3" name="opc2" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zza_idx_s" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="43*" />
|
|
<col colno="4" printwidth="53*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of single precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of single precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="svdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="svdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="svdot_za_zzi">SVDOT (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usvdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="usvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="usvdot_za_zzi">USVDOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uvdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="uvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="uvdot_za_zzi">UVDOT (4-way)</td>
|
|
<td class="enctags">32-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="suvdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="suvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="suvdot_za_zzi">SUVDOT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za32_zzi_4xi" arch_version="FEAT_SME2" iformfile="sdot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="sdot_za32_zzi">SDOT (2-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fdot_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="fdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="fdot_za_zzi">FDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za32_zzi_4xi" arch_version="FEAT_SME2" iformfile="udot_za32_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="udot_za32_zzi">UDOT (2-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfdot_za_zzi_4xi" arch_version="FEAT_SME2" iformfile="bfdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname" iformid="bfdot_za_zzi">BFDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="sdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="sdot_za_zzi">SDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="usdot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="usdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname" iformid="usdot_za_zzi">USDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="udot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">110</td>
|
|
<td class="iformname" iformid="udot_za_zzi">UDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of 32-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sudot_za_zzi_s4xi" arch_version="FEAT_SME2" iformfile="sudot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="3" class="bitfield">111</td>
|
|
<td class="iformname" iformid="sudot_za_zzi">SUDOT (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_zza_idx_d" title="SME2 multi-vec ternary indexed four registers 64-bit">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="10" name="i1" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="2" width="3" name="off3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_zza_idx_d" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="43*" />
|
|
<col colno="4" printwidth="53*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmla_za_zzi_d4xi" arch_version="FEAT_SME_F64F64" iformfile="fmla_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="fmla_za_zzi">FMLA (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of double precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sdot_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="sdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="sdot_za_zzi">SDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmls_za_zzi_d4xi" arch_version="FEAT_SME_F64F64" iformfile="fmls_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="fmls_za_zzi">FMLS (multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of double precision elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="udot_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="udot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="udot_za_zzi">UDOT (4-way, multiple and indexed vector)</td>
|
|
<td class="enctags">Four ZA single-vectors of 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_598" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">x0</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="svdot_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="svdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="svdot_za_zzi">SVDOT (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uvdot_za_zzi_d4xi" arch_version="FEAT_SME_I16I64" iformfile="uvdot_za_zzi.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="uvdot_za_zzi">UVDOT (4-way)</td>
|
|
<td class="enctags">64-bit</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_2a">SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi2_z_z_fminmax_sm" title="SME2 single-multi FP min/max two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_fminmax_sm" cols="5">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="38*" />
|
|
<col colno="5" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmax_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmax_mz_zzv">FMAX (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmin_mz_zzv">FMIN (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="fmaxnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmaxnm_mz_zzv">FMAXNM (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="fminnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fminnm_mz_zzv">FMINNM (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmax_mz_zzv_2x1" arch_version="FEAT_B16B16" iformfile="bfmax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmax_mz_zzv">BFMAX (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmin_mz_zzv_2x1" arch_version="FEAT_B16B16" iformfile="bfmin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmin_mz_zzv">BFMIN (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmaxnm_mz_zzv_2x1" arch_version="FEAT_B16B16" iformfile="bfmaxnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmaxnm_mz_zzv">BFMAXNM (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfminnm_mz_zzv_2x1" arch_version="FEAT_B16B16" iformfile="bfminnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfminnm_mz_zzv">BFMINNM (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_add_sm" title="SME2 single-multi add two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_add_sm" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="add_mz_zzv.xml" first="t" last="t">
|
|
<td class="iformname" iformid="add_mz_zzv">ADD (to vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_minmax_sm" title="SME2 single-multi int min/max two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_minmax_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="35*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smax_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="smax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_mz_zzv">SMAX (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="umax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umax_mz_zzv">UMAX (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="smin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_mz_zzv">SMIN (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="umin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umin_mz_zzv">UMIN (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_shift_sm" title="SME2 single-multi shift two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_shift_sm" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_562" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshl_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="srshl_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshl_mz_zzv">SRSHL (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshl_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="urshl_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshl_mz_zzv">URSHL (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_563" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_564" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_sqdmulh_sm" title="SME2 single-multi signed saturating doubling multiply high two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_sqdmulh_sm" cols="2">
|
|
<col colno="1" printwidth="38*" />
|
|
<col colno="2" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_mz_zzv_2x1" arch_version="FEAT_SME2" iformfile="sqdmulh_mz_zzv.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sqdmulh_mz_zzv">SQDMULH (multiple and single vector)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_2b">SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_z_z_fminmax_sm" title="SME2 single-multi FP min/max four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_fminmax_sm" cols="5">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="38*" />
|
|
<col colno="5" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmax_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmax_mz_zzv">FMAX (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmin_mz_zzv">FMIN (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="fmaxnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmaxnm_mz_zzv">FMAXNM (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="fminnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fminnm_mz_zzv">FMINNM (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmax_mz_zzv_4x1" arch_version="FEAT_B16B16" iformfile="bfmax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmax_mz_zzv">BFMAX (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmin_mz_zzv_4x1" arch_version="FEAT_B16B16" iformfile="bfmin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmin_mz_zzv">BFMIN (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmaxnm_mz_zzv_4x1" arch_version="FEAT_B16B16" iformfile="bfmaxnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmaxnm_mz_zzv">BFMAXNM (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfminnm_mz_zzv_4x1" arch_version="FEAT_B16B16" iformfile="bfminnm_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfminnm_mz_zzv">BFMINNM (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_add_sm" title="SME2 single-multi add four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_add_sm" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="add_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="add_mz_zzv.xml" first="t" last="t">
|
|
<td class="iformname" iformid="add_mz_zzv">ADD (to vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_minmax_sm" title="SME2 single-multi int min/max four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_minmax_sm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="35*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smax_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="smax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_mz_zzv">SMAX (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="umax_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umax_mz_zzv">UMAX (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="smin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_mz_zzv">SMIN (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="umin_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umin_mz_zzv">UMIN (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_shift_sm" title="SME2 single-multi shift four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_shift_sm" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="36*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_565" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshl_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="srshl_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshl_mz_zzv">SRSHL (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshl_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="urshl_mz_zzv.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshl_mz_zzv">URSHL (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_566" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_567" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_sqdmulh_sm" title="SME2 single-multi signed saturating doubling multiply high four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_sqdmulh_sm" cols="2">
|
|
<col colno="1" printwidth="38*" />
|
|
<col colno="2" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_mz_zzv_4x1" arch_version="FEAT_SME2" iformfile="sqdmulh_mz_zzv.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sqdmulh_mz_zzv">SQDMULH (multiple and single vector)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_2c">SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi2_z_z_sqdmulh_mm" title="SME2 multi-vector signed saturating doubling multiply high two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_sqdmulh_mm" cols="2">
|
|
<col colno="1" printwidth="28*" />
|
|
<col colno="2" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="sqdmulh_mz_zzw.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sqdmulh_mz_zzw">SQDMULH (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_fminmax_mm" title="SME2 multiple vectors FP min/max two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_fminmax_mm" cols="5">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="28*" />
|
|
<col colno="5" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmax_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmax_mz_zzw">FMAX (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmin_mz_zzw">FMIN (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="fmaxnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmaxnm_mz_zzw">FMAXNM (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="fminnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fminnm_mz_zzw">FMINNM (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmax_mz_zzw_2x2" arch_version="FEAT_B16B16" iformfile="bfmax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmax_mz_zzw">BFMAX (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmin_mz_zzw_2x2" arch_version="FEAT_B16B16" iformfile="bfmin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmin_mz_zzw">BFMIN (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmaxnm_mz_zzw_2x2" arch_version="FEAT_B16B16" iformfile="bfmaxnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmaxnm_mz_zzw">BFMAXNM (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfminnm_mz_zzw_2x2" arch_version="FEAT_B16B16" iformfile="bfminnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfminnm_mz_zzw">BFMINNM (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_minmax_mm" title="SME2 multiple vectors int min/max two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_minmax_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="25*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smax_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="smax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_mz_zzw">SMAX (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="umax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umax_mz_zzw">UMAX (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="smin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_mz_zzw">SMIN (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="umin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umin_mz_zzw">UMIN (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_shift_mm" title="SME2 multiple vectors shift two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="7" settings="7">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zdn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_shift_mm" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_568" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshl_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="srshl_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshl_mz_zzw">SRSHL (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshl_mz_zzw_2x2" arch_version="FEAT_SME2" iformfile="urshl_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshl_mz_zzw">URSHL (multiple vectors)</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_569" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_570" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_2d">SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_z_z_sqdmulh_mm" title="SME2 multi-vector signed saturating doubling multiply high four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_sqdmulh_mm" cols="2">
|
|
<col colno="1" printwidth="28*" />
|
|
<col colno="2" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqdmulh_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="sqdmulh_mz_zzw.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sqdmulh_mz_zzw">SQDMULH (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_fminmax_mm" title="SME2 multiple vectors FP min/max four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="o2" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_fminmax_mm" cols="5">
|
|
<col colno="1" printwidth="7*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="4*" />
|
|
<col colno="4" printwidth="28*" />
|
|
<col colno="5" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">o2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fmax_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmax_mz_zzw">FMAX (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmin_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fmin_mz_zzw">FMIN (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fmaxnm_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="fmaxnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fmaxnm_mz_zzw">FMAXNM (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fminnm_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="fminnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fminnm_mz_zzw">FMINNM (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmax_mz_zzw_4x4" arch_version="FEAT_B16B16" iformfile="bfmax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmax_mz_zzw">BFMAX (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmin_mz_zzw_4x4" arch_version="FEAT_B16B16" iformfile="bfmin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfmin_mz_zzw">BFMIN (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfmaxnm_mz_zzw_4x4" arch_version="FEAT_B16B16" iformfile="bfmaxnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfmaxnm_mz_zzw">BFMAXNM (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfminnm_mz_zzw_4x4" arch_version="FEAT_B16B16" iformfile="bfminnm_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfminnm_mz_zzw">BFMINNM (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_minmax_mm" title="SME2 multiple vectors int min/max four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_minmax_mm" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="25*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="smax_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="smax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smax_mz_zzw">SMAX (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umax_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="umax_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umax_mz_zzw">UMAX (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="smin_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="smin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="smin_mz_zzw">SMIN (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="umin_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="umin_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="umin_mz_zzw">UMIN (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_shift_mm" title="SME2 multiple vectors shift four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="8" settings="8">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zdn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_shift_mm" cols="4">
|
|
<col colno="1" printwidth="5*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_571" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="srshl_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="srshl_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="srshl_mz_zzw">SRSHL (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="urshl_mz_zzw_4x4" arch_version="FEAT_SME2" iformfile="urshl_mz_zzw.xml" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="urshl_mz_zzw">URSHL (multiple vectors)</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_572" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">01x</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_573" undef="1" oneofthismnem="3" first="t" last="t">
|
|
<td bitwidth="3" class="bitfield">1xx</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_1">SME2 Multi-vector - SVE Select</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_select_int" title="SME2 multi-vec select four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="3" name="Zm" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="17" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_select_int" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sel_mz_p_zz_4" arch_version="FEAT_SME2" iformfile="sel_mz_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sel_mz_p_zz">SEL</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_select_int" title="SME2 multi-vec select two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="4" name="Zm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="16" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="12" width="3" name="PNg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_select_int" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sel_mz_p_zz_2" arch_version="FEAT_SME2" iformfile="sel_mz_p_zz.xml" first="t" last="t">
|
|
<td class="iformname" iformid="sel_mz_p_zz">SEL</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_3">SME2 Multi-vector - SVE Constructive Binary</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi4_clamp_int" title="SME2 multi-vec CLAMP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_clamp_int" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sclamp_mz_zz_4" arch_version="FEAT_SME2" iformfile="sclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sclamp_mz_zz">SCLAMP</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uclamp_mz_zz_4" arch_version="FEAT_SME2" iformfile="uclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uclamp_mz_zz">UCLAMP</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_clamp_int" title="SME2 multi-vec CLAMP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_clamp_int" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sclamp_mz_zz_2" arch_version="FEAT_SME2" iformfile="sclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sclamp_mz_zz">SCLAMP</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uclamp_mz_zz_2" arch_version="FEAT_SME2" iformfile="uclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uclamp_mz_zz">UCLAMP</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_fclamp" title="SME2 multi-vec FCLAMP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_fclamp" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fclamp_mz_zz_4" arch_version="FEAT_SME2" iformfile="fclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td class="iformname" iformid="fclamp_mz_zz">FCLAMP</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfclamp_mz_zz_4" arch_version="FEAT_B16B16" iformfile="bfclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bfclamp_mz_zz">BFCLAMP</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_fclamp" title="SME2 multi-vec FCLAMP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_fclamp" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fclamp_mz_zz_2" arch_version="FEAT_SME2" iformfile="fclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">!= 00</td>
|
|
<td class="iformname" iformid="fclamp_mz_zz">FCLAMP</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfclamp_mz_zz_2" arch_version="FEAT_B16B16" iformfile="bfclamp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="bfclamp_mz_zz">BFCLAMP</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_zip" title="SME2 multi-vec ZIP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_zip" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="21*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip_mz_zz_2" arch_version="FEAT_SME2" iformfile="zip_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip_mz_zz">ZIP (two registers)</td>
|
|
<td class="enctags">8-bit to 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp_mz_zz_2" arch_version="FEAT_SME2" iformfile="uzp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp_mz_zz">UZP (two registers)</td>
|
|
<td class="enctags">8-bit to 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_z_z_long_zip" title="SME2 multi-vec quadwords ZIP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Zm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_z_z_long_zip" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="21*" />
|
|
<col colno="3" printwidth="17*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip_mz_zz_2q" arch_version="FEAT_SME2" iformfile="zip_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip_mz_zz">ZIP (two registers)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp_mz_zz_2q" arch_version="FEAT_SME2" iformfile="uzp_mz_zz.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp_mz_zz">UZP (two registers)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_qrshr" title="SME2 multi-vec saturating shift right narrow four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="tsize" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="imm5" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_qrshr" cols="5">
|
|
<col colno="1" printwidth="3*" />
|
|
<col colno="2" printwidth="4*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="26*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">N</th>
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_574" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshr_z_mz4_" arch_version="FEAT_SME2" iformfile="sqrshr_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshr_z_mz4">SQRSHR (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshr_z_mz4_" arch_version="FEAT_SME2" iformfile="uqrshr_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshr_z_mz4">UQRSHR (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshru_z_mz4_" arch_version="FEAT_SME2" iformfile="sqrshru_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshru_z_mz4">SQRSHRU (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrn_z_mz4_" arch_version="FEAT_SME2" iformfile="sqrshrn_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshrn_z_mz4">SQRSHRN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshrn_z_mz4_" arch_version="FEAT_SME2" iformfile="uqrshrn_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshrn_z_mz4">UQRSHRN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshrun_z_mz4_" arch_version="FEAT_SME2" iformfile="sqrshrun_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshrun_z_mz4">SQRSHRUN</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_qrshr" title="SME2 multi-vec saturating shift right narrow two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_qrshr" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="25*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqrshr_z_mz2_" arch_version="FEAT_SME2" iformfile="sqrshr_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshr_z_mz2">SQRSHR (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqrshr_z_mz2_" arch_version="FEAT_SME2" iformfile="uqrshr_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqrshr_z_mz2">UQRSHR (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqrshru_z_mz2_" arch_version="FEAT_SME2" iformfile="sqrshru_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqrshru_z_mz2">SQRSHRU (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_606" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_multi_sve_4">SME2 Multi-vector - SVE Constructive Unary</funcgroupheader>
|
|
<iclass_sect id="mortlach_multi2_narrow_fp_cvrt" title="SME2 multi-vec FP down convert two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_narrow_fp_cvrt" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcvt_z_mz2_" arch_version="FEAT_SME2" iformfile="fcvt_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvt_z_mz2">FCVT (narrowing)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtn_z_mz2_" arch_version="FEAT_SME2" iformfile="fcvtn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtn_z_mz2">FCVTN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfcvt_z_mz2_" arch_version="FEAT_SME2" iformfile="bfcvt_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="bfcvt_z_mz2">BFCVT</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="bfcvtn_z_mz2_" arch_version="FEAT_SME2" iformfile="bfcvtn_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="bfcvtn_z_mz2">BFCVTN</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_fpint_cvrt" title="SME2 multi-vec FP to int convert four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_fpint_cvrt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcvtzs_mz_z_4" arch_version="FEAT_SME2" iformfile="fcvtzs_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_mz_z">FCVTZS</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_mz_z_4" arch_version="FEAT_SME2" iformfile="fcvtzu_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_mz_z">FCVTZU</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_fpint_cvrt" title="SME2 multi-vec FP to int convert two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_fpint_cvrt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcvtzs_mz_z_2" arch_version="FEAT_SME2" iformfile="fcvtzs_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvtzs_mz_z">FCVTZS</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtzu_mz_z_2" arch_version="FEAT_SME2" iformfile="fcvtzu_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtzu_mz_z">FCVTZU</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_frint" title="SME2 multi-vec FRINT four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_frint" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_577" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintn_mz_z_4" arch_version="FEAT_SME2" iformfile="frintn_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="frintn_mz_z">FRINTN</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintp_mz_z_4" arch_version="FEAT_SME2" iformfile="frintp_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="frintp_mz_z">FRINTP</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintm_mz_z_4" arch_version="FEAT_SME2" iformfile="frintm_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="frintm_mz_z">FRINTM</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_595" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frinta_mz_z_4" arch_version="FEAT_SME2" iformfile="frinta_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="frinta_mz_z">FRINTA</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_596" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_597" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_607" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_frint" title="SME2 multi-vec FRINT two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="opc" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_frint" cols="4">
|
|
<col colno="1" printwidth="6*" />
|
|
<col colno="2" printwidth="5*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">size</th>
|
|
<th class="bitfields">opc</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_575" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">0x</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintn_mz_z_2" arch_version="FEAT_SME2" iformfile="frintn_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">000</td>
|
|
<td class="iformname" iformid="frintn_mz_z">FRINTN</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintp_mz_z_2" arch_version="FEAT_SME2" iformfile="frintp_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">001</td>
|
|
<td class="iformname" iformid="frintp_mz_z">FRINTP</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frintm_mz_z_2" arch_version="FEAT_SME2" iformfile="frintm_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">010</td>
|
|
<td class="iformname" iformid="frintm_mz_z">FRINTM</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_592" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">011</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="frinta_mz_z_2" arch_version="FEAT_SME2" iformfile="frinta_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">100</td>
|
|
<td class="iformname" iformid="frinta_mz_z">FRINTA</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_593" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">101</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_594" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td bitwidth="3" class="bitfield">11x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_605" undef="1" oneofthismnem="5" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td bitwidth="3" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_zip" title="SME2 multi-vec ZIP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_zip" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="26*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip_mz_z_4" arch_version="FEAT_SME2" iformfile="zip_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip_mz_z">ZIP (four registers)</td>
|
|
<td class="enctags">8-bit to 64-bit elements</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp_mz_z_4" arch_version="FEAT_SME2" iformfile="uzp_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp_mz_z">UZP (four registers)</td>
|
|
<td class="enctags">8-bit to 64-bit elements</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_wide_fp_cvrt" title="SME2 multi-vec convert two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="L" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_wide_fp_cvrt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">L</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="fcvt_mz2_z_" arch_version="FEAT_SME_F16F16" iformfile="fcvt_mz2_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="fcvt_mz2_z">FCVT (widening)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="fcvtl_mz2_z_" arch_version="FEAT_SME_F16F16" iformfile="fcvtl_mz2_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="fcvtl_mz2_z">FCVTL</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_narrow_int_cvrt" title="SME2 multi-vec int down convert four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" name="sz" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_narrow_int_cvrt" cols="5">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="3*" />
|
|
<col colno="4" printwidth="25*" />
|
|
<col colno="5" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="3">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">N</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqcvt_z_mz4_" arch_version="FEAT_SME2" iformfile="sqcvt_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvt_z_mz4">SQCVT (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqcvt_z_mz4_" arch_version="FEAT_SME2" iformfile="uqcvt_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqcvt_z_mz4">UQCVT (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtn_z_mz4_" arch_version="FEAT_SME2" iformfile="sqcvtn_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvtn_z_mz4">SQCVTN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqcvtn_z_mz4_" arch_version="FEAT_SME2" iformfile="uqcvtn_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqcvtn_z_mz4">UQCVTN</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_587" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield"></td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtu_z_mz4_" arch_version="FEAT_SME2" iformfile="sqcvtu_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvtu_z_mz4">SQCVTU (four registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtun_z_mz4_" arch_version="FEAT_SME2" iformfile="sqcvtun_z_mz4.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvtun_z_mz4">SQCVTUN</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_narrow_int_cvrt" title="SME2 multi-vec int down convert two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="5" name="Zd" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_narrow_int_cvrt" cols="4">
|
|
<col colno="1" printwidth="4*" />
|
|
<col colno="2" printwidth="3*" />
|
|
<col colno="3" printwidth="24*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sqcvt_z_mz2_" arch_version="FEAT_SME2" iformfile="sqcvt_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvt_z_mz2">SQCVT (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uqcvt_z_mz2_" arch_version="FEAT_SME2" iformfile="uqcvt_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uqcvt_z_mz2">UQCVT (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="sqcvtu_z_mz2_" arch_version="FEAT_SME2" iformfile="sqcvtu_z_mz2.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sqcvtu_z_mz2">SQCVTU (two registers)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_583" undef="1" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_intfp_cvrt" title="SME2 multi-vec int to FP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_intfp_cvrt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="scvtf_mz_z_4" arch_version="FEAT_SME2" iformfile="scvtf_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_mz_z">SCVTF</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_mz_z_4" arch_version="FEAT_SME2" iformfile="ucvtf_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_mz_z">UCVTF</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_intfp_cvrt" title="SME2 multi-vec int to FP two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_intfp_cvrt" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="scvtf_mz_z_2" arch_version="FEAT_SME2" iformfile="scvtf_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="scvtf_mz_z">SCVTF</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ucvtf_mz_z_2" arch_version="FEAT_SME2" iformfile="ucvtf_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="ucvtf_mz_z">UCVTF</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_z_z_long_zip" title="SME2 multi-vec quadwords ZIP four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="22" settings="22">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="3" name="Zn" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="6" width="2" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_z_z_long_zip" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="22*" />
|
|
<col colno="3" printwidth="17*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="zip_mz_z_4q" arch_version="FEAT_SME2" iformfile="zip_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="zip_mz_z">ZIP (four registers)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uzp_mz_z_4q" arch_version="FEAT_SME2" iformfile="uzp_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uzp_mz_z">UZP (four registers)</td>
|
|
<td class="enctags">128-bit element</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi4_wide_int" title="SME2 multi-vec unpack four registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="4" name="Zn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" width="3" name="Zd" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi4_wide_int" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="16*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sunpk_mz_z_4" arch_version="FEAT_SME2" iformfile="sunpk_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sunpk_mz_z">SUNPK</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uunpk_mz_z_4" arch_version="FEAT_SME2" iformfile="uunpk_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uunpk_mz_z">UUNPK</td>
|
|
<td class="enctags">Four registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_multi2_wide_int" title="SME2 multi-vec unpack two registers">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" width="12" settings="12">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Zn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" width="4" name="Zd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="0" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_multi2_wide_int" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="15*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">U</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="sunpk_mz_z_2" arch_version="FEAT_SME2" iformfile="sunpk_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="sunpk_mz_z">SUNPK</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="uunpk_mz_z_2" arch_version="FEAT_SME2" iformfile="uunpk_mz_z.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="uunpk_mz_z">UUNPK</td>
|
|
<td class="enctags">Two registers</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<funcgroupheader id="mortlach_mem">SME Memory</funcgroupheader>
|
|
<iclass_sect id="mortlach_contig_load" title="SME load array vector (elements)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_contig_load" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="39*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1b_za_p_rrr_" arch_version="FEAT_SME" iformfile="ld1b_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ld1b_za_p_rrr">LD1B (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1h_za_p_rrr_" arch_version="FEAT_SME" iformfile="ld1h_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="ld1h_za_p_rrr">LD1H (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1w_za_p_rrr_" arch_version="FEAT_SME" iformfile="ld1w_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="ld1w_za_p_rrr">LD1W (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ld1d_za_p_rrr_" arch_version="FEAT_SME" iformfile="ld1d_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="ld1d_za_p_rrr">LD1D (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_contig_qload" title="SME load array vector (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="ZAt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_contig_qload" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ld1q_za_p_rrr_" arch_version="FEAT_SME" iformfile="ld1q_za_p_rrr.xml" first="t" last="t">
|
|
<td class="iformname" iformid="ld1q_za_p_rrr">LD1Q</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_ctxt_ldst" title="SME save and restore array">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="10" settings="10">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" name="op" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" width="6" settings="6">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rv" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_ctxt_ldst" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="18*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">op</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="ldr_za_ri_" arch_version="FEAT_SME" iformfile="ldr_za_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">0</td>
|
|
<td class="iformname" iformid="ldr_za_ri">LDR (vector)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="str_za_ri_" arch_version="FEAT_SME" iformfile="str_za_ri.xml" first="t" last="t">
|
|
<td bitwidth="1" class="bitfield">1</td>
|
|
<td class="iformname" iformid="str_za_ri">STR (vector)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_contig_store" title="SME store array vector (elements)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="2" name="msz" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="opc" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_contig_store" cols="3">
|
|
<col colno="1" printwidth="15*" />
|
|
<col colno="2" printwidth="39*" />
|
|
<col colno="3" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">msz</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1b_za_p_rrr_" arch_version="FEAT_SME" iformfile="st1b_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="st1b_za_p_rrr">ST1B (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1h_za_p_rrr_" arch_version="FEAT_SME" iformfile="st1h_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname" iformid="st1h_za_p_rrr">ST1H (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1w_za_p_rrr_" arch_version="FEAT_SME" iformfile="st1w_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">10</td>
|
|
<td class="iformname" iformid="st1w_za_p_rrr">ST1W (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="st1d_za_p_rrr_" arch_version="FEAT_SME" iformfile="st1d_za_p_rrr.xml" first="t" last="t">
|
|
<td bitwidth="2" class="bitfield">11</td>
|
|
<td class="iformname" iformid="st1d_za_p_rrr">ST1D (scalar plus scalar, tile slice)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_contig_qstore" title="SME store array vector (quadwords)">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" width="5" name="Rm" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="15" name="V" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="14" width="2" name="Rs" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="12" width="3" name="Pg" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="ZAt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_contig_qstore" cols="2">
|
|
<col colno="1" printwidth="18*" />
|
|
<col colno="2" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th rowspan="1" class="iformname">Instruction page</th>
|
|
<th rowspan="1" class="enctags">Encoding</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="st1q_za_p_rrr_" arch_version="FEAT_SME" iformfile="st1q_za_p_rrr.xml" first="t" last="t">
|
|
<td class="iformname" iformid="st1q_za_p_rrr">ST1Q</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
<iclass_sect id="mortlach_zt_ldst" title="SME2 lookup table load/store">
|
|
<regdiagram form="32" psname="">
|
|
<box hibit="31" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="29" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="6" name="opc" usename="1">
|
|
<c colspan="6"></c>
|
|
</box>
|
|
<box hibit="15" width="6" settings="6">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="5" name="Rn" usename="1">
|
|
<c colspan="5"></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="1" width="2" name="opc2" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<instructiontable iclass="mortlach_zt_ldst" cols="4">
|
|
<col colno="1" printwidth="8*" />
|
|
<col colno="2" printwidth="6*" />
|
|
<col colno="3" printwidth="18*" />
|
|
<col colno="4" printwidth="10*" />
|
|
<thead class="instructiontable">
|
|
<tr id="heading1">
|
|
<th colno="1" class="bitfields-heading" colspan="2">Decode fields</th>
|
|
<th rowspan="2" class="iformname">Instruction page</th>
|
|
<th rowspan="2" class="enctags">Encoding</th>
|
|
</tr>
|
|
<tr id="heading2">
|
|
<th class="bitfields">opc</th>
|
|
<th class="bitfields">opc2</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="instructiontable" encname="UNALLOCATED_614" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x0xxxx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_615" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x10xxx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_616" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x110xx</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_617" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x1110x</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_618" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x11110</td>
|
|
<td bitwidth="2" class="bitfield"></td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_619" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x11111</td>
|
|
<td bitwidth="2" class="bitfield">01</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="UNALLOCATED_620" undef="1" oneofthismnem="7" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">x11111</td>
|
|
<td bitwidth="2" class="bitfield">1x</td>
|
|
<td class="iformname">UNALLOCATED</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="ldr_zt_br_" arch_version="FEAT_SME2" iformfile="ldr_zt_br.xml" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">011111</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="ldr_zt_br">LDR (ZT0)</td>
|
|
</tr>
|
|
<tr class="instructiontable" encname="str_zt_br_" arch_version="FEAT_SME2" iformfile="str_zt_br.xml" first="t" last="t">
|
|
<td bitwidth="6" class="bitfield">111111</td>
|
|
<td bitwidth="2" class="bitfield">00</td>
|
|
<td class="iformname" iformid="str_zt_br">STR (ZT0)</td>
|
|
</tr>
|
|
</tbody>
|
|
</instructiontable>
|
|
</iclass_sect>
|
|
</encodingindex>
|