mirror of
https://github.com/pound-emu/ballistic.git
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235 lines
12 KiB
XML
235 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="FADD_float" title="FADD (scalar) -- A64" type="instruction">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FADD" />
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</docvars>
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<heading>FADD (scalar)</heading>
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<desc>
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<brief>
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<para>Floating-point Add (scalar)</para>
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</brief>
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<authored>
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<para>Floating-point Add (scalar). This instruction adds the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.</para>
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<para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch64.fpcr">FPCR</xref>, the exception results in either a flag being set in <xref linkend="AArch64.fpsr">FPSR</xref>, or a synchronous exception being generated. For more information, see <xref linkend="BEIJDDAG">Floating-point exception traps</xref>.</para>
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<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="Floating-point" oneof="1" id="iclass_float" no_encodings="3" isa="A64">
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<docvars>
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FADD" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch64/instrs/float/arithmetic/add-sub" tworows="1">
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<box hibit="31" name="M" settings="1">
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<c>0</c>
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</box>
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<box hibit="30" settings="1">
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<c>0</c>
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</box>
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<box hibit="29" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="28" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="2" name="ftype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="21" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" width="5" name="Rm" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="15" width="3" name="opcode[3:1]" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="12" name="op" usename="1" settings="1" psbits="x">
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<c>0</c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="5" name="Rn" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="4" width="5" name="Rd" usename="1">
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<c colspan="5"></c>
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</box>
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</regdiagram>
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<encoding name="FADD_H_floatdp2" oneofinclass="3" oneof="3" label="Half-precision" bitdiffs="ftype == 11">
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<docvars>
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<docvar key="datatype" value="half" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FADD" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="23" width="2" name="ftype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FADD </text><a link="sa_hd" hover="16-bit SIMD&FP destination register (field "Rd")"><Hd></a><text>, </text><a link="sa_hn" hover="First 16-bit SIMD&FP source register (field "Rn")"><Hn></a><text>, </text><a link="sa_hm" hover="Second 16-bit SIMD&FP source register (field "Rm")"><Hm></a></asmtemplate>
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</encoding>
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<encoding name="FADD_S_floatdp2" oneofinclass="3" oneof="3" label="Single-precision" bitdiffs="ftype == 00">
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<docvars>
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<docvar key="datatype" value="single" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FADD" />
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</docvars>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate><text>FADD </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Rd")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Rn")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Rm")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="FADD_D_floatdp2" oneofinclass="3" oneof="3" label="Double-precision" bitdiffs="ftype == 01">
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<docvars>
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<docvar key="datatype" value="double" />
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<docvar key="instr-class" value="float" />
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<docvar key="isa" value="A64" />
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<docvar key="mnemonic" value="FADD" />
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</docvars>
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<box hibit="23" width="2" name="ftype">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>FADD </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "Rd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "Rn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "Rm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/arithmetic/add-sub" mylink="aarch64.instrs.float.arithmetic.add-sub" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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integer esize;
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case ftype of
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when '00' esize = 32;
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when '01' esize = 64;
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when '10' UNDEFINED;
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when '11'
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if <a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
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esize = 16;
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else
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UNDEFINED;
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boolean sub_op = (op == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="FADD_D_floatdp2" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_D_floatdp2" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_D_floatdp2" symboldefcount="1">
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<symbol link="sa_dm"><Dm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_H_floatdp2" symboldefcount="1">
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<symbol link="sa_hd"><Hd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_H_floatdp2" symboldefcount="1">
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<symbol link="sa_hn"><Hn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_H_floatdp2" symboldefcount="1">
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<symbol link="sa_hm"><Hm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_S_floatdp2" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_S_floatdp2" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="FADD_S_floatdp2" symboldefcount="1">
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<symbol link="sa_sm"><Sm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch64/instrs/float/arithmetic/add-sub" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
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bits(esize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
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bits(esize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, esize];
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<a link="FPCRType" file="shared_pseudocode.xml" hover="type FPCRType">FPCRType</a> fpcr = FPCR[];
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boolean merge = <a link="impl-shared.IsMerging.1" file="shared_pseudocode.xml" hover="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
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bits(128) result = if merge then <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
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if sub_op then
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPSub.3" file="shared_pseudocode.xml" hover="function: bits(N) FPSub(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPSub</a>(operand1, operand2, fpcr);
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else
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(operand1, operand2, fpcr);
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<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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