mirror of
https://github.com/ptitSeb/box64.git
synced 2026-11-08 10:10:25 -10:00
[LA64_DYNAREC] Add more 32/64 lock opcodes. (#3126)
* 87 LOCK XCHG Ed, Gd * F0 09 LOCK OR Ed, Gd * F0 21 LOCK AND Ed, Gd * F0 31 LOCK XOR Ed, Gd * F0 81/83 /1 LOCK OR Ed, Id/Ib * F0 81/83 /4 LOCK AND Ed, Id/Ib * F0 81/83 /6 LOCK XOR Ed, Id/Ib * F0 87 LOCK XCHG Ed, Gd * F0 F7 /2 LOCK NOT Ed * F0 F7 /3 fix LOCK NEG, not reading CF. * Guard amo op's B_MARK3_nocond with ALIGNED_ATOMICxw
This commit is contained in:
phorcys authored and GitHub committed
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commit
14e3d05b87
2 files changed
+326
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@@ -1133,19 +1133,40 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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} else {
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GETGD;
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addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
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ANDI(x3, ed, (1 << (2 + rex.w)) - 1);
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BNEZ_MARK(x3);
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MARKLOCK;
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LLxw(x1, ed, 0);
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MVxw(x3, gd);
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SCxw(x3, ed, 0);
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BEQZ_MARKLOCK(x3);
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B_MARK2_nocond;
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MARK;
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LDxw(x1, ed, 0);
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SDxw(gd, ed, 0);
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MARK2;
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MVxw(gd, x1);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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/* LoongArch Reference Manual Vol1 2.2.7.1
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If the AM* atomic memory access instruction has the same register number as rd and rk,
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the execution result is uncertain. Please software to avoid this situation.
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*/
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AMSWAP_DB_D(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMSWAP_DB_W(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(ADDI_W(x4, gd, 0), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(ADDI_D(x4, gd, 0), x1, wback, x4, x5, x6);
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MARK3;
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}
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MV(gd, x1);
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}
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break;
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case 0x88:
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@@ -68,7 +68,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, gd, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -106,11 +106,35 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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emit_or32(dyn, ninst, rex, ed, gd, x3, x4);
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} else {
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addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
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MARKLOCK;
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LLxw(x1, wback, 0);
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OR(x4, x1, gd);
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SCxw(x4, wback, 0);
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BEQZ_MARKLOCK(x4);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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AMOR_DB_D(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMOR_DB_W(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(OR(x4, x1, gd), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(OR(x4, x1, gd), x1, wback, x4, x5, x6);
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MARK3;
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}
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IFXORNAT (X_ALL | X_PEND)
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emit_or32(dyn, ninst, rex, x1, gd, x3, x4);
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}
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@@ -420,7 +444,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, gd, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -615,7 +639,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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}
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ADD_D(x7, gd, x7);
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -670,7 +694,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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SUB_D(x7, xZR, gd);
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SUB_D(x7, x7, x6);
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -714,7 +738,35 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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emit_and32(dyn, ninst, rex, ed, gd, x3, x4);
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} else {
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addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
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AMAND_DBxw(x1, gd, wback);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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AMAND_DB_D(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMAND_DB_W(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(AND(x4, x1, gd), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(AND(x4, x1, gd), x1, wback, x4, x5, x6);
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MARK3;
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}
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IFXORNAT (X_ALL | X_PEND)
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emit_and32(dyn, ninst, rex, x1, gd, x3, x4);
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}
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@@ -736,7 +788,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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}
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NEG_D(x7, gd);
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -764,6 +816,49 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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emit_sub32(dyn, ninst, rex, x1, gd, x3, x4, x5);
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}
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break;
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case 0x31:
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INST_NAME("LOCK XOR Ed, Gd");
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SETFLAGS(X_ALL, SF_SET_PENDING, NAT_FLAGS_FUSION);
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nextop = F8;
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GETGD;
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if (MODREG) {
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ed = TO_NAT((nextop & 7) + (rex.b << 3));
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emit_xor32(dyn, ninst, rex, ed, gd, x3, x4);
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} else {
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addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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AMXOR_DB_D(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMXOR_DB_W(x1, gd, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(XOR(x4, x1, gd), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(XOR(x4, x1, gd), x1, wback, x4, x5, x6);
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MARK3;
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}
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IFXORNAT (X_ALL | X_PEND)
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emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);
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}
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break;
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case 0x66:
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return dynarec64_66F0(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
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@@ -831,7 +926,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -880,19 +975,36 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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} else {
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i64 = F8S;
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}
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if (i64 <= -2048 || i64 > 2048) {
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MOV64xw(x3, i64);
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}
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MARKLOCK;
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LLxw(x1, wback, 0);
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if (i64 >= -2048 && i64 < 2048) {
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ORI(x4, x1, i64);
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MOV64xw(x7, i64);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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AMOR_DB_D(x1, x7, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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OR(x4, x1, x3);
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMOR_DB_W(x1, x7, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(OR(x4, x1, x7), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(OR(x4, x1, x7), x1, wback, x4, x5, x6);
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MARK3;
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}
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if (!rex.w) ZEROUP(x4);
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SCxw(x4, wback, 0);
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BEQZ_MARKLOCK(x4);
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IFXORNAT (X_ALL | X_PEND)
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emit_or32c(dyn, ninst, rex, x1, i64, x3, x4);
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}
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@@ -931,7 +1043,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -994,7 +1106,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -1045,9 +1157,33 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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i64 = F8S;
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MOV64xw(x7, i64);
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if (rex.w) {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b111);
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BNEZ_MARK2(x3);
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}
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AMAND_DB_D(x1, x7, wback);
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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BNEZ_MARK(x3);
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}
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// aligned 4byte
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AMAND_DB_W(x1, x7, wback);
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if (!ALIGNED_ATOMICxw) {
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B_MARK3_nocond;
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MARK;
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ANDI(x3, wback, 0b111);
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SLTI(x4, x3, 4);
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BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
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LOCK_32_IN_8BYTE(AND(x4, x1, x7), x1, wback, x3, x4, x5, x6, x7);
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B_MARK3_nocond;
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}
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}
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if (!ALIGNED_ATOMICxw) {
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MARK2;
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LOCK_3264_CROSS_8BYTE(AND(x4, x1, x7), x1, wback, x4, x5, x6);
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MARK3;
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}
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IFXORNAT (X_ALL | X_PEND)
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emit_and32c(dyn, ninst, rex, x1, i64, x3, x4);
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@@ -1080,7 +1216,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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BNEZ_MARK2(x3);
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}
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AMADD_DB_D(x1, x7, wback);
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B_MARK3_nocond;
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if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
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} else {
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if (!ALIGNED_ATOMICxw) {
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ANDI(x3, wback, 0b11);
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@@ -1107,6 +1243,60 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
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emit_sub32c(dyn, ninst, rex, x1, i64, x3, x4, x5, x6);
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}
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break;
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case 6:
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if (opcode == 0x81) {
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INST_NAME("LOCK XOR Ed, Id");
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} else {
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INST_NAME("LOCK XOR Ed, Ib");
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}
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SETFLAGS(X_ALL, SF_SET_PENDING, NAT_FLAGS_FUSION);
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if (MODREG) {
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if (opcode == 0x81)
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i64 = F32S;
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else
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i64 = F8S;
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ed = TO_NAT((nextop & 7) + (rex.b << 3));
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emit_xor32c(dyn, ninst, rex, ed, i64, x3, x4);
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} else {
|
||||
addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, (opcode == 0x81) ? 4 : 1);
|
||||
if (opcode == 0x81)
|
||||
i64 = F32S;
|
||||
else
|
||||
i64 = F8S;
|
||||
MOV64xw(x7, i64);
|
||||
if (rex.w) {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b111);
|
||||
BNEZ_MARK2(x3);
|
||||
}
|
||||
AMXOR_DB_D(x1, x7, wback);
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; };
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
BNEZ_MARK(x3);
|
||||
}
|
||||
// aligned 4byte
|
||||
AMXOR_DB_W(x1, x7, wback);
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
B_MARK3_nocond;
|
||||
MARK;
|
||||
ANDI(x3, wback, 0b111);
|
||||
SLTI(x4, x3, 4);
|
||||
BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
|
||||
LOCK_32_IN_8BYTE(XOR(x4, x1, x7), x1, wback, x3, x4, x5, x6, x7);
|
||||
B_MARK3_nocond;
|
||||
}
|
||||
}
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
MARK2;
|
||||
LOCK_3264_CROSS_8BYTE(XOR(x4, x1, x7), x1, wback, x4, x5, x6);
|
||||
MARK3;
|
||||
}
|
||||
IFXORNAT (X_ALL | X_PEND)
|
||||
emit_xor32c(dyn, ninst, rex, x1, i64, x3, x4);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DEFAULT;
|
||||
}
|
||||
@@ -1123,20 +1313,86 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
|
||||
} else {
|
||||
GETGD;
|
||||
addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
|
||||
MARKLOCK;
|
||||
LLxw(x1, wback, 0);
|
||||
MV(x4, gd);
|
||||
SCxw(x4, wback, 0);
|
||||
BEQZ_MARKLOCK(x4);
|
||||
MVxw(gd, x1);
|
||||
if (rex.w) {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b111);
|
||||
BNEZ_MARK2(x3);
|
||||
}
|
||||
/* LoongArch Reference Manual Vol1 2.2.7.1
|
||||
If the AM* atomic memory access instruction has the same register number as rd and rk,
|
||||
the execution result is uncertain. Please software to avoid this situation.
|
||||
*/
|
||||
AMSWAP_DB_D(x1, gd, wback);
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
BNEZ_MARK(x3);
|
||||
}
|
||||
// aligned 4byte
|
||||
AMSWAP_DB_W(x1, gd, wback);
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
B_MARK3_nocond;
|
||||
MARK;
|
||||
ANDI(x3, wback, 0b111);
|
||||
SLTI(x4, x3, 4);
|
||||
BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
|
||||
LOCK_32_IN_8BYTE(ADDI_W(x4, gd, 0), x1, wback, x3, x4, x5, x6, x7);
|
||||
B_MARK3_nocond;
|
||||
}
|
||||
}
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
MARK2;
|
||||
LOCK_3264_CROSS_8BYTE(ADDI_D(x4, gd, 0), x1, wback, x4, x5, x6);
|
||||
MARK3;
|
||||
}
|
||||
MV(gd, x1);
|
||||
}
|
||||
break;
|
||||
case 0xF7:
|
||||
nextop = F8;
|
||||
switch ((nextop >> 3) & 7) {
|
||||
case 2:
|
||||
INST_NAME("LOCK NOT Ed");
|
||||
if (MODREG) {
|
||||
ed = TO_NAT((nextop & 7) + (rex.b << 3));
|
||||
NOR(ed, ed, xZR);
|
||||
} else {
|
||||
addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, LOCK_LOCK, 0, 0);
|
||||
MOV64xw(x7, -1);
|
||||
if (rex.w) {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b111);
|
||||
BNEZ_MARK2(x3);
|
||||
}
|
||||
AMXOR_DB_D(x1, x7, wback);
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
BNEZ_MARK(x3);
|
||||
}
|
||||
// aligned 4byte
|
||||
AMXOR_DB_W(x1, x7, wback);
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
B_MARK3_nocond;
|
||||
MARK;
|
||||
ANDI(x3, wback, 0b111);
|
||||
SLTI(x4, x3, 4);
|
||||
BEQZ_MARK2(x4); // addr %8 >4 , cross 8bytes or cross cacheline
|
||||
LOCK_32_IN_8BYTE(XOR(x4, x1, x7), x1, wback, x3, x4, x5, x6, x7);
|
||||
B_MARK3_nocond;
|
||||
}
|
||||
}
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
MARK2;
|
||||
LOCK_3264_CROSS_8BYTE(XOR(x4, x1, x7), x1, wback, x4, x5, x6);
|
||||
MARK3;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
INST_NAME("LOCK NEG Ed");
|
||||
READFLAGS(X_CF);
|
||||
SETFLAGS(X_ALL, SF_SET_PENDING, NAT_FLAGS_FUSION);
|
||||
if (MODREG) {
|
||||
ed = TO_NAT((nextop & 7) + (rex.b << 3));
|
||||
@@ -1160,7 +1416,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
|
||||
SC_D(x4, wback, 0);
|
||||
BEQZ(x4, -4 * 3);
|
||||
}
|
||||
B_MARK3_nocond;
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
@@ -1222,7 +1478,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
|
||||
}
|
||||
MOV32w(x7, 1);
|
||||
AMADD_DB_D(x1, x7, wback);
|
||||
B_MARK3_nocond;
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
@@ -1265,7 +1521,7 @@ uintptr_t dynarec64_F0(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
|
||||
}
|
||||
MOV64xw(x7, -1);
|
||||
AMADD_DB_D(x1, x7, wback);
|
||||
B_MARK3_nocond;
|
||||
if (!ALIGNED_ATOMICxw) { B_MARK3_nocond; }
|
||||
} else {
|
||||
if (!ALIGNED_ATOMICxw) {
|
||||
ANDI(x3, wback, 0b11);
|
||||
|
||||
Reference in new issue
Block a user