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v0.0.2

v0.0.4

v0.0.6

v0.0.8

v0.1.0

v0.1.2

v0.1.4

v0.1.6

v0.1.8

v0.2.0

v0.2.2

v0.2.4

v0.2.6

v0.2.8

v0.3.0

v0.3.2

v0.3.4

v0.3.6

v0.3.8

v0.4.0

v0.4.1-1

v0.4.1-2

v0.4.1-3

v0.4.2

v0.4.3-1

v0.4.3-2

v0.4.3-3

v0.4.3-4

v0.4.4

v0.4.5-1

Mono Color

• 37f5e4b7b0 Expand special names in DT_NEEDED names too (for #4682) main ptitSeb 2026-11-07 11:26:50 +01:00
• 70cdfdb2c2 Fixed proc/self/maps formating (for #4681) ptitSeb 2026-11-07 10:44:59 +01:00
• 50855a1e2b [ARM64_DYNAREC] Fix native flags record in signal arch info (#4678) Alex BeverageandClaude Opus 5.5 2026-11-06 09:36:04 -10:00
• 0b5002e8df [SIGNAL] Restore FPU state and drop deferred flags when a handler changes the context (#4679) Alex BeverageandClaude Opus 5.5 2026-11-06 09:35:49 -10:00
• 4049ceacf0 Windows builds needs ULL to be 64bits ptitSeb 2026-11-06 12:02:52 +01:00
• 5c60cf8f42 [ARM64_DYNAREC] Small optimsation for test emitters ptitSeb 2026-11-05 11:39:06 +01:00
• 59b3eb1555 [RV64_DYNAREC] Reuse sew to remove vsetvli for avx_load_reg_vector (#4668) Zhijin Zeng 2026-11-05 12:07:06 +08:00
• 83935bc134 [BOX64EC] Compile Dynarec emitters, add Box64EC register mapping (#4666) airidosas252 2026-11-05 06:04:41 +02:00
• 27a2d1f81d [WRAPPER] Wrapped CRYPTO_set_mem_functions for libcrypto.so.3 (#4665) Yang Liu 2026-11-04 01:01:15 +08:00
• b71b00322e [RV64_DYNAREC] Added autocrc support (#4664) Yang Liu 2026-11-03 22:08:09 +08:00
• b640a570b3 [RV64_DYNAREC] Use fence.tso for RET and strongmem barriers (#4663) Yang Liu 2026-11-03 19:18:50 +08:00
• 9c5e8a541a [RV64_DYNAREC] Include up32 and rsp in arch state detection (#4662) Yang Liu 2026-11-03 18:55:35 +08:00
• 6bee368bd2 [RV64_DYNAREC] Fence stores at RET by default (#4655) Yang Liu 2026-11-03 16:02:07 +08:00
• 3d48b55edb [RV64_DYNAREC] Extend nativeflags to 1+N pattern (#4661) Yang Liu 2026-11-03 16:01:21 +08:00
• 03d689bf56 [RV64_DYNAREC] Materialize direct call return address from xRIP (#4660) Yang Liu 2026-11-03 16:00:28 +08:00
• b8171c2402 [RV64_DYNAREC] Track zero-extension of LEA and SRLIW results (#4659) Yang Liu 2026-11-03 15:58:32 +08:00
• d338d4660e [RV64] Reset RVV extensions when vector is disabled (#4658) Yang Liu 2026-11-03 15:57:33 +08:00
• 20807c208c [RV64_DYNAREC] Reuse zero-extended operands in fused 32-bit compares (#4657) Yang Liu 2026-11-03 15:56:35 +08:00
• 23597f62fd [RV64_DYNAREC] Keep SEW when flushing YMM upper halves to reduce vsetvli (#4652) Zhijin Zeng 2026-11-02 16:03:40 +08:00
• 27fd407318 [DYNAREC] Preserved flags when a block is truncated on a fill fault (#4653) Yang Liu 2026-11-02 15:50:52 +08:00
• 22f67f2b20 [DYNAREC] Clear pending df on all DIV/IDIV paths (#4651) Yang Liu 2026-11-02 01:47:28 +08:00
• 74d9149095 [DYNAREC] Rollbacked a wrong optimization in PR #4648 (#4650) Yang Liu 2026-11-01 23:12:20 +08:00
• 37d91ce5ee [RV64_DYNAREC] Fixed cache transform on a back-edge to the block start Yang Liu 2026-11-01 20:57:39 +08:00
• 59955e15bb [RV64_DYNAREC] Restore YMM upper halves after a native call Yang Liu 2026-11-01 20:57:39 +08:00
• 5cc72d9d7a [RV64_DYNAREC] Reset vtype tracking after native calls Yang Liu 2026-11-01 20:57:39 +08:00
• 9f0814e08f [RV64_DYNAREC] Zero-extend SHLD/SHRD destination in 32-bit mode Yang Liu 2026-11-01 20:57:39 +08:00
• 89566077a7 [RV64_DYNAREC] Do locked bit ops on the aligned 32-bit word Yang Liu 2026-11-01 20:57:39 +08:00
• 0b046f594c [DYNAREC] Fixed deferred 16-bit SHLD/SHRD flags with count>16 (#4648) Yang Liu 2026-11-01 18:27:06 +08:00
• 93c68acd37 [LA64_DYNAREC] Restore pending scalar XMM values on signal exit (#4647) Yang Liu 2026-11-01 03:06:44 +08:00
• 5177ca4732 [LA64_DYNAREC] Fixed AES source being clobbered by AVX cache sync in SCRATCH (#4646) Yang Liu 2026-11-01 03:03:18 +08:00
• e86a766cbe [ARM64] Added a dection of write error on segfault using extra signal information (for #4644) ptitSeb 2026-10-31 14:30:55 +01:00
• f60dea9b4b [ARM64_DYNAREC] Keep the guest base register when adding a segment base in geted() (#4645) NickletsandClaude Opus 5.5 2026-10-31 09:37:40 -03:00
• d7124fdd64 [DYNAREC] Reused getDB result is InternalDBGetBlock (linked with #4642) ptitSeb 2026-10-31 11:58:24 +01:00
• d74ec762c6 [DYNAREC] Don't run a block that intersects a hot page (#4642) Yang Liu 2026-10-31 15:06:27 +08:00
• a7f9094034 [INTERP] Fixed more unaligned LOCK BT* opcodes (#4641) Yang Liu 2026-10-31 14:56:55 +08:00
• 6dfbebd2d4 [ARM64_DYNAREC] Fixed YMM upper half lost with VPCLMULQDQ fallback (#4632) Yang Liu 2026-10-31 03:13:21 +08:00
• 6367180c2c [ARM64_DYNAREC] Fixed 16-bit BT/BTS/BTR/BTC displacement scale (#4639) Yang Liu 2026-10-31 03:11:44 +08:00
• 81e0246b2a [DYNAREC] Small fixes to in_used tracking (#4638) Yang Liu 2026-10-31 03:10:33 +08:00
• 8a7a148bdd [RV64_DYNAREC] Translate round mode for some int to float convert opcodes (#4636) Zhijin Zeng 2026-10-31 00:45:33 +08:00
• 6c88bbda42 [RV64_DYNAREC] Keep live XMMs when reflecting cache (#4624) Zhijin Zeng 2026-10-31 00:44:05 +08:00
• 75cff5c584 [INTERP] Fixed unaligned LOCK BTS (#4635) Yang Liu 2026-10-30 16:26:41 +08:00
• fb0b267f53 [ARM64_DYNAREC] Don't skip dirty preloaded regs on loopback (#4626) Yang Liu 2026-10-30 16:15:05 +08:00
• d318afe1b9 [INTERP] Added 16-bit LOCK BTR/BTC/BTS opcodes (#4634) Yang Liu 2026-10-30 16:12:12 +08:00
• 5250c6e7a5 [ARM64_DYNAREC] Fixed BOUND leaking a cleared deferred flags state (#4633) Yang Liu 2026-10-30 15:15:12 +08:00
• 7e06f2bd28 [INTERP] Fix some small errors (#4631) Zhijin Zeng 2026-10-30 15:08:22 +08:00
• 25418aa192 [ARM64_DYNAREC] Fixed another xmm value lost in a loop (#4630) Yang Liu 2026-10-30 15:05:12 +08:00
• 07e9e5c344 Fix typos in documentation (#4629) Ari (Hamid) Zare 2026-10-29 10:37:25 -05:00
• 5055f947eb [ARM64_DYNAREC] Fixed wrong x87 NaN sign with memory operands (#4628) Yang Liu 2026-10-29 23:26:10 +08:00
• 4df6988c9f [ARM64_DYNAREC] Fixed xmm value lost in a loop (#4627) Yang Liu 2026-10-29 21:19:55 +08:00
• 4e8f73c277 [DEBIAN] Fix changelog formatting (#4625) Mark Zhuang 2026-10-29 16:09:48 +08:00
• 30d5c77188 [RV64_DYNAREC] Keep live YMMs cached across merge points, skip dead write-backs (#4610) Yang Liu 2026-10-28 19:16:15 +08:00
• ea513ac125 [RV64_DYNAREC] Cleared pending zero on materialized upper halves (#4623) Yang Liu 2026-10-28 18:37:59 +08:00
• 3795fe40fb [RV64_DYNAREC] Fix POPCNT/TZCNT/LZCNT with 66h and rex.w prefix (#4622) Zhijin Zeng 2026-10-28 18:37:24 +08:00
• 2da641175c [RV64_DYNAREC] Fixed vtype restore skipped by epilog branches (#4621) Yang Liu 2026-10-28 17:40:33 +08:00
• ec2f98e95a [RV64_DYNAREC] Fixed up32 handling in some opcodes (#4620) Yang Liu 2026-10-28 17:39:14 +08:00
• 4c6be6cb23 [RV64_DYNAREC] Kept pending YMM zero mask on local purges (#4619) Yang Liu 2026-10-28 17:28:16 +08:00
• 78217d33fe [RV64_DYNAREC] Reset vtype tracking at block start and reset (#4618) Yang Liu 2026-10-28 17:13:02 +08:00
• c4eb274b9a [RV64_DYNAREC] Fixed extcache initialization for preloaded registers (#4617) Yang Liu 2026-10-28 17:12:03 +08:00
• 61bbb76bdc [RV64_DYNAREC] Fixed displacement range for some opcodes (#4616) Yang Liu 2026-10-28 17:10:29 +08:00
• 13f5aea7d2 [RV64_DYNAREC] Fixed vtype tracking across cache transforms (#4615) Yang Liu 2026-10-28 17:06:48 +08:00
• 9cb238fd92 [RV64_DYNAREC] Fixed missing read tracking in AVX register loads (#4614) Yang Liu 2026-10-28 17:05:46 +08:00
• 11a20e37c8 [RV64_DYNAREC] Emit scalar AVX FMA with vl=1 (#4613) Yang Liu 2026-10-27 15:26:44 +08:00
• 63ed07ac83 [RV64_DYNAREC] Store VMOVSS directly from the vector register (#4612) Yang Liu 2026-10-27 15:10:18 +08:00
• 4b7d2eaabe [RV64_DYNAREC] Remove redundant vsetvli from scalar AVX prolog (#4611) Yang Liu 2026-10-27 15:09:29 +08:00
• 74ee4280db [DYNAREC] Added callret=3 and move in_used tracking to it (#4609) Yang Liu 2026-10-26 23:12:23 +08:00
• 11effee660 Arm64 lrcpc (#4608) ptitSeb 2026-10-26 16:00:27 +01:00
• 21c14f1c04 [RV64_DYNAREC] Keep origin vtype for VPMOVSX and VPMOVZX opcodes (#4607) Zhijin Zeng 2026-10-26 22:04:23 +08:00
• 61add52ed5 [RV64_DYNAREC] Use generic vector stores for XMM spills (#4605) Yang Liu 2026-10-26 15:56:56 +08:00
• e9f705df0c [RV64_DYNAREC] Avoid duplicate pending-zero upper stores (#4604) Yang Liu 2026-10-26 15:56:18 +08:00
• 319a1a8ad6 [RV64_DYNAREC] Avoid duplicate YMM upper zeroing on SSE cache purge (#4603) Yang Liu 2026-10-26 15:55:04 +08:00
• be6e39cdeb [RV64_DYNAREC] Added more AVX opcodes (#4602) Yang Liu 2026-10-26 15:54:21 +08:00
• 49341072c8 [RV64_DYNAREC] Optimized a few AVX opcodes (#4601) Yang Liu 2026-10-26 15:52:56 +08:00
• a62e03fc7f [RV64_DYNAREC] Fix width error for VMOVSS (#4600) Zhijin Zeng 2026-10-26 15:51:35 +08:00
• 3c563ba603 [RV64_DYNAREC] Added fast path to extcacheUnwind (#4599) Yang Liu 2026-10-26 15:50:37 +08:00
• e8a2f7f9c9 [RV64_DYNAREC] Skipped cache type sync when no vector reg is used (#4598) Yang Liu 2026-10-26 15:49:25 +08:00
• 1a49e47075 [RV64_DYNAREC] Fixed stale YMM upper in scalar AVX upper access (#4594) Yang Liu 2026-10-26 15:17:09 +08:00
• 1d2083fe59 [RV64][CMAKE] Disabled auto-vectorization (#4596) Yang Liu 2026-10-26 15:06:40 +08:00
• d04c270fa9 [RV64_DYNAREC] Fixed dynarec dump buffer overflow (#4595) Yang Liu 2026-10-26 15:05:14 +08:00
• 7fffe8dfb5 [RV64_DYNAREC] Fixed CMPXCHG up32 handling (#4593) Yang Liu 2026-10-26 15:04:30 +08:00
• a46ad9dfe9 [RV64_DYNAREC] Reworked move immediate (#4591) Yang Liu 2026-10-26 03:57:34 +08:00
• 420eda69ff [RV64_DYNAREC] Fix VPERM2I128 vector mask multiple (#4589) Zhijin Zeng 2026-10-23 21:56:40 +08:00
• 5735c8b7c8 [RV64_DYNAREC] Optimize some opcodes by removing redundant some vsetvli (#4588) Zhijin Zeng 2026-10-23 21:56:21 +08:00
• 827f0ee54e [RV64_DYNAREC] Optimitize VSHUFPS and VPERMILPS 128-bit case Zhijin Zeng 2026-10-21 18:29:53 +08:00
• 0b0a31c53c [RV64_DYNAREC] Avoid redundant vsetvli when loading vector masks (#4583) Zhijin Zeng 2026-10-23 14:15:23 +08:00
• 39aae76ddf [RV64_DYNAREC] Optimized some AVX opcodes (#4586) Yang Liu 2026-10-22 20:05:52 +08:00
• f267770d75 [RV64_DYNAREC] Optimize contiguous-1-bit cases Zhijin Zeng 2026-10-21 19:22:58 +08:00
• 082ecb92b1 [RV64_DYNAREC] Use bseti for single-bit 64-bit constants Zhijin Zeng 2026-10-21 18:47:03 +08:00
• fbba162d7c [RCFILE] Optimise steam profile ptitSeb 2026-10-22 10:55:32 +02:00
• 8851be9278 [WOWBOX64] Fixed GetEnvironnementVariableA (for #4585) ptitSeb 2026-10-22 10:33:55 +02:00
• a111fcafee [RV64_DYNAREC] Fix vector register aliasing Zhijin Zeng 2026-10-21 17:25:44 +08:00
• d96343fbb1 [RV64_DYNAREC] Added and optimized some SSE/AVX opcodes (#4581) Yang Liu 2026-10-21 16:29:55 +08:00
• ae3412c1bf [RV64_DYNAREC] Deferred upper-zero and matched AVX load SEW Yang Liu 2026-10-20 02:50:45 +08:00
• db0615cbb0 [RV64_DYNAREC] Used LMUL1 scratch for byte shuffles Yang Liu 2026-10-20 02:50:45 +08:00
• 3835fe369e [RV64_DYNAREC] Used vl=1 RVV for scalar SSE/AVX opcodes Yang Liu 2026-10-20 02:47:37 +08:00
• d07e3def9c [RV64_DYNAREC] Fixed AVX source/destination aliasing Yang Liu 2026-10-20 02:47:37 +08:00
• d0c7da583d [RV64_DYNAREC] Added combined VY/EY/GY vector load macros Yang Liu 2026-10-20 02:47:17 +08:00
• 259ba9f554 [RV64_DYNAREC] Used encoded registers for AVX vector operands Yang Liu 2026-10-20 02:47:04 +08:00
• 2c3ac5ff08 [RV64_DYNAREC] Forced vsetvli in SSE cache purge Yang Liu 2026-10-20 02:46:43 +08:00
• d11def2d5b [RV64_DYNAREC] Kept vtype across linear instructions Yang Liu 2026-10-20 02:46:43 +08:00
• d166be5dcc [RV64_DYNAREC] Restricted AES vector path to 128-bit operands Yang Liu 2026-10-20 02:46:43 +08:00