diff --git a/qiling/arch/register.py b/qiling/arch/register.py
index 53810cf8..66eb74b3 100644
--- a/qiling/arch/register.py
+++ b/qiling/arch/register.py
@@ -109,6 +109,9 @@ class QlRegisterManager:
         """Get register size in bits.
         """
 
+        if type(reg) is str:
+            reg = self.register_mapping[reg]
+
         return self.ql.arch.get_reg_bit(reg)
 
 
@@ -146,9 +149,5 @@ class QlRegisterManager:
         return self.ql.uc.reg_write(self.uc_sp, value)
 
 
-    def get_uc_reg(self, reg_name: str) -> int:
-        return self.register_mapping[reg_name]
-
-
     def create_reverse_mapping(self):
         self.reverse_mapping = {v:k for k, v in self.register_mapping.items()}
diff --git a/qiling/arch/x86.py b/qiling/arch/x86.py
index 5b37932d..dedeff13 100644
--- a/qiling/arch/x86.py
+++ b/qiling/arch/x86.py
@@ -4,7 +4,6 @@
 #
 
 from struct import pack
-from typing import Union
 
 from unicorn import Uc, UC_ARCH_X86, UC_MODE_16, UC_MODE_32, UC_MODE_64
 from capstone import Cs, CS_ARCH_X86, CS_MODE_16, CS_MODE_32, CS_MODE_64
@@ -18,10 +17,7 @@ from qiling.exception import QlGDTError
 class QlArchIntel(QlArch):
 
     # TODO: generalize this
-    def get_reg_bit(self, register: Union[str, int]) -> int:
-        if type(register) is str:
-            register = self.ql.reg.get_uc_reg(register)
-
+    def get_reg_bit(self, register: int) -> int:
         # all regs in reg_map_misc are 16 bits except of eflags
         if register == UC_X86_REG_EFLAGS:
             return self.ql.archbit