2018-08-16 10:23:51 -07:00
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# Copyright 2018 syzkaller project authors. All rights reserved.
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# Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file.
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# See https://fuchsia.googlesource.com/zircon/+/master/docs/fidl/wire-format/index.md
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include <zircon/fidl.h>
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2018-08-27 17:48:08 -07:00
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type fidl_call_args[REQ_MESSAGE, REQ_HANDLES, RESP_MESSAGE, RESP_HANDLES] {
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2018-08-16 10:23:51 -07:00
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wr_bytes ptr[in, REQ_MESSAGE]
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wr_handles ptr[in, REQ_HANDLES]
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2018-08-27 17:48:08 -07:00
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rd_bytes ptr[out, RESP_MESSAGE]
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2018-08-16 10:23:51 -07:00
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rd_handles ptr[out, RESP_HANDLES]
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wr_num_bytes bytesize[wr_bytes, int32]
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wr_num_handles bytesize4[wr_handles, int32]
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rd_num_bytes bytesize[rd_bytes, int32]
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rd_num_handles bytesize4[rd_handles, int32]
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}
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2018-09-06 15:49:23 -07:00
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type fidl_union_member[TAG, TYPE] {
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tag const[TAG, int32]
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data TYPE
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}
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2018-08-16 10:23:51 -07:00
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type fidl_message_header[METHOD_ORDINAL] {
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txid const[0, int32]
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reserved const[0, int32]
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flags const[0, int32]
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ordinal const[METHOD_ORDINAL, int32]
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}
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fidl_string {
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size int64
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data flags[fidl_alloc_presence, int64]
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}
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fidl_vector {
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size int64
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data flags[fidl_alloc_presence, int64]
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}
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type fidl_aligned[T] {
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var T
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} [align_8]
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type parallel_array[A, B] {
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a array[A]
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b array[B]
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} [packed]
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fidl_alloc_presence = FIDL_ALLOC_ABSENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT, FIDL_ALLOC_PRESENT
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fidl_handle_presence = FIDL_HANDLE_ABSENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT, FIDL_HANDLE_PRESENT
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