From 9d9e0606a4a45909de731094b749c8fac3982050 Mon Sep 17 00:00:00 2001
From: Marcus Meissner <marcus@jet.franken.de>
Date: Fri, 12 Mar 1999 16:55:46 +0000
Subject: [PATCH] Emulate (well, ignore) mov cr0,eax and mov eax,cr0.

---
 miscemu/instr.c | 58 ++++++++++++++++++++++++++++++++++---------------
 1 file changed, 40 insertions(+), 18 deletions(-)

diff --git a/miscemu/instr.c b/miscemu/instr.c
index 01f817c465..c970ea272d 100644
--- a/miscemu/instr.c
+++ b/miscemu/instr.c
@@ -411,24 +411,46 @@ BOOL INSTR_EmulateInstruction( SIGCONTEXT *context )
         case 0x0f: /* extended instruction */
             switch(instr[1])
             {
-	    case 0x20: /* mov cr4, eax */
-	    	if (instr[2]!=0xe0) 
-			break;
-		/* CR4 register . See linux/arch/i386/mm/init.c, X86_CR4_ defs
-		 * bit 0: VME	Virtual Mode Exception ?
-		 * bit 1: PVI	Protected mode Virtual Interrupt
-		 * bit 2: TSD	Timestamp disable
-		 * bit 3: DE	Debugging extensions
-		 * bit 4: PSE	Page size extensions
-		 * bit 5: PAE   Physical address extension
-		 * bit 6: MCE	Machine check enable
-		 * bit 7: PGE   Enable global pages
-		 * bit 8: PCE	Enable performance counters at IPL3
-		 */
-		fprintf(stderr,"mov cr4,eax at 0x%08lx\n",EIP_sig(context));
-		EAX_sig(context) = 0;
-		EIP_sig(context) += prefixlen+3;
-		return TRUE;
+	    case 0x22: /* mov eax, crX */
+	    	switch (instr[2]) {
+		case 0xc0:
+			fprintf(stderr,"mov eax,cr0 at 0x%08lx, EAX=0x%08lx\n",
+				EIP_sig(context),EAX_sig(context)
+			);
+			EIP_sig(context) += prefixlen+3;
+			return TRUE;
+		default:
+			break; /*fallthrough to bad instruction handling */
+		}
+		break; /*fallthrough to bad instruction handling */
+	    case 0x20: /* mov crX, eax */
+	        switch (instr[2]) {
+		case 0xe0: /* mov cr4, eax */
+		    /* CR4 register . See linux/arch/i386/mm/init.c, X86_CR4_ defs
+		     * bit 0: VME	Virtual Mode Exception ?
+		     * bit 1: PVI	Protected mode Virtual Interrupt
+		     * bit 2: TSD	Timestamp disable
+		     * bit 3: DE	Debugging extensions
+		     * bit 4: PSE	Page size extensions
+		     * bit 5: PAE   Physical address extension
+		     * bit 6: MCE	Machine check enable
+		     * bit 7: PGE   Enable global pages
+		     * bit 8: PCE	Enable performance counters at IPL3
+		     */
+		    fprintf(stderr,"mov cr4,eax at 0x%08lx\n",EIP_sig(context));
+		    EAX_sig(context) = 0;
+		    EIP_sig(context) += prefixlen+3;
+		    return TRUE;
+		case 0xc0: /* mov cr0, eax */
+		    fprintf(stderr,"mov cr0,eax at 0x%08lx\n",EIP_sig(context));
+		    EAX_sig(context) = 0x10; /* FIXME: set more bits ? */
+		    EIP_sig(context) += prefixlen+3;
+		    return TRUE;
+		default: /* fallthrough to illegal instruction */
+		    break;
+		}
+		/* fallthrough to illegal instruction */
+		break;
 #ifdef FS_sig
             case 0xa1: /* pop fs */
                 {