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winedbg: Implement be_x86_64_init_registers.
This commit is contained in:
Ge van Geldorp
Alexandre Julliard
parent
6a65bf6a2b
commit
a2e94444ad
@ -420,6 +420,114 @@ enum CV_HREG_e
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CV_M32R_ACHI = 32,
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CV_M32R_ACLO = 33,
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CV_M32R_PC = 34,
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/* AMD/Intel x86_64 CPU */
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CV_AMD64_NONE = CV_REG_NONE,
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CV_AMD64_AL = CV_REG_AL,
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CV_AMD64_CL = CV_REG_CL,
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CV_AMD64_DL = CV_REG_DL,
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CV_AMD64_BL = CV_REG_BL,
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CV_AMD64_AH = CV_REG_AH,
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CV_AMD64_CH = CV_REG_CH,
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CV_AMD64_DH = CV_REG_DH,
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CV_AMD64_BH = CV_REG_BH,
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CV_AMD64_AX = CV_REG_AX,
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CV_AMD64_CX = CV_REG_CX,
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CV_AMD64_DX = CV_REG_DX,
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CV_AMD64_BX = CV_REG_BX,
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CV_AMD64_SP = CV_REG_SP,
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CV_AMD64_BP = CV_REG_BP,
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CV_AMD64_SI = CV_REG_SI,
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CV_AMD64_DI = CV_REG_DI,
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CV_AMD64_EAX = CV_REG_EAX,
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CV_AMD64_ECX = CV_REG_ECX,
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CV_AMD64_EDX = CV_REG_EDX,
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CV_AMD64_EBX = CV_REG_EBX,
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CV_AMD64_ESP = CV_REG_ESP,
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CV_AMD64_EBP = CV_REG_EBP,
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CV_AMD64_ESI = CV_REG_ESI,
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CV_AMD64_EDI = CV_REG_EDI,
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CV_AMD64_ES = CV_REG_ES,
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CV_AMD64_CS = CV_REG_CS,
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CV_AMD64_SS = CV_REG_SS,
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CV_AMD64_DS = CV_REG_DS,
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CV_AMD64_FS = CV_REG_FS,
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CV_AMD64_GS = CV_REG_GS,
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CV_AMD64_FLAGS = CV_REG_FLAGS,
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CV_AMD64_RIP = CV_REG_EIP,
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CV_AMD64_EFLAGS = CV_REG_EFLAGS,
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/* <pcode> */
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CV_AMD64_TEMP = CV_REG_TEMP,
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CV_AMD64_TEMPH = CV_REG_TEMPH,
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CV_AMD64_QUOTE = CV_REG_QUOTE,
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CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
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CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */
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CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */
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/* </pcode> */
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CV_AMD64_GDTR = CV_REG_GDTR,
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CV_AMD64_GDTL = CV_REG_GDTL,
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CV_AMD64_IDTR = CV_REG_IDTR,
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CV_AMD64_IDTL = CV_REG_IDTL,
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CV_AMD64_LDTR = CV_REG_LDTR,
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CV_AMD64_TR = CV_REG_TR,
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CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseuso09 */
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CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */
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CV_AMD64_CTRL = CV_REG_CTRL,
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CV_AMD64_STAT = CV_REG_STAT,
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CV_AMD64_TAG = CV_REG_TAG,
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CV_AMD64_FPIP = CV_REG_FPIP,
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CV_AMD64_FPCS = CV_REG_FPCS,
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CV_AMD64_FPDO = CV_REG_FPDO,
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CV_AMD64_FPDS = CV_REG_FPDS,
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CV_AMD64_ISEM = CV_REG_ISEM,
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CV_AMD64_FPEIP = CV_REG_FPEIP,
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CV_AMD64_FPEDO = CV_REG_FPEDO,
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CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */
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CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */
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CV_AMD64_XMM00 = CV_REG_XMM00,
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CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */
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CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */
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CV_AMD64_MXCSR = CV_REG_MXCSR,
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CV_AMD64_EDXEAX = CV_REG_EDXEAX,
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CV_AMD64_EMM0L = CV_REG_EMM0L,
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CV_AMD64_EMM0H = CV_REG_EMM0H,
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CV_AMD64_MM00 = CV_REG_MM00,
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CV_AMD64_MM01 = CV_REG_MM01,
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CV_AMD64_MM10 = CV_REG_MM10,
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CV_AMD64_MM11 = CV_REG_MM11,
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CV_AMD64_MM20 = CV_REG_MM20,
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CV_AMD64_MM21 = CV_REG_MM21,
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CV_AMD64_MM30 = CV_REG_MM30,
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CV_AMD64_MM31 = CV_REG_MM31,
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CV_AMD64_MM40 = CV_REG_MM40,
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CV_AMD64_MM41 = CV_REG_MM41,
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CV_AMD64_MM50 = CV_REG_MM50,
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CV_AMD64_MM51 = CV_REG_MM51,
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CV_AMD64_MM60 = CV_REG_MM60,
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CV_AMD64_MM61 = CV_REG_MM61,
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CV_AMD64_MM70 = CV_REG_MM70,
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CV_AMD64_MM71 = CV_REG_MM71,
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CV_AMD64_RAX = 328,
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CV_AMD64_RBX = 329,
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CV_AMD64_RCX = 330,
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CV_AMD64_RDX = 331,
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CV_AMD64_RSI = 332,
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CV_AMD64_RDI = 333,
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CV_AMD64_RBP = 334,
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CV_AMD64_RSP = 335,
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CV_AMD64_R8 = 336,
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CV_AMD64_R9 = 337,
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CV_AMD64_R10 = 338,
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CV_AMD64_R11 = 339,
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CV_AMD64_R12 = 340,
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CV_AMD64_R13 = 341,
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CV_AMD64_R14 = 342,
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CV_AMD64_R15 = 343,
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} CV_HREG_e;
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typedef enum
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@ -45,12 +45,64 @@ static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
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static struct dbg_internal_var be_x86_64_ctx[] =
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{
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{CV_AMD64_AL, "AL", (DWORD*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
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{CV_AMD64_BL, "BL", (DWORD*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
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{CV_AMD64_CL, "CL", (DWORD*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
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{CV_AMD64_DL, "DL", (DWORD*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
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{CV_AMD64_AH, "AH", (DWORD*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
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{CV_AMD64_BH, "BH", (DWORD*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
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{CV_AMD64_CH, "CH", (DWORD*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
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{CV_AMD64_DH, "DH", (DWORD*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
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{CV_AMD64_AX, "AX", (DWORD*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
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{CV_AMD64_BX, "BX", (DWORD*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
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{CV_AMD64_CX, "CX", (DWORD*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
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{CV_AMD64_DX, "DX", (DWORD*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
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{CV_AMD64_SP, "SP", (DWORD*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
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{CV_AMD64_BP, "BP", (DWORD*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
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{CV_AMD64_SI, "SI", (DWORD*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
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{CV_AMD64_DI, "DI", (DWORD*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
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{CV_AMD64_EAX, "EAX", (DWORD*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
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{CV_AMD64_EBX, "EBX", (DWORD*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
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{CV_AMD64_ECX, "ECX", (DWORD*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
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{CV_AMD64_EDX, "EDX", (DWORD*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
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{CV_AMD64_ESP, "ESP", (DWORD*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
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{CV_AMD64_EBP, "EBP", (DWORD*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
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{CV_AMD64_ESI, "ESI", (DWORD*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
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{CV_AMD64_EDI, "EDI", (DWORD*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
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{CV_AMD64_ES, "ES", (DWORD*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
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{CV_AMD64_CS, "CS", (DWORD*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
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{CV_AMD64_SS, "SS", (DWORD*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
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{CV_AMD64_DS, "DS", (DWORD*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
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{CV_AMD64_FS, "FS", (DWORD*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
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{CV_AMD64_GS, "GS", (DWORD*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
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{CV_AMD64_FLAGS, "FLAGS", (DWORD*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
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{CV_AMD64_EFLAGS, "EFLAGS", (DWORD*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
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{CV_AMD64_RIP, "RIP", (DWORD*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_int},
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{CV_AMD64_RAX, "RAX", (DWORD*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
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{CV_AMD64_RBX, "RBX", (DWORD*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
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{CV_AMD64_RCX, "RCX", (DWORD*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
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{CV_AMD64_RDX, "RDX", (DWORD*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
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{CV_AMD64_RSP, "RSP", (DWORD*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
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{CV_AMD64_RBP, "RBP", (DWORD*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
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{CV_AMD64_RSI, "RSI", (DWORD*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
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{CV_AMD64_RDI, "RDI", (DWORD*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
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{CV_AMD64_R8, "R8", (DWORD*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
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{CV_AMD64_R9, "R9", (DWORD*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
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{CV_AMD64_R10, "R10", (DWORD*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
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{CV_AMD64_R11, "R11", (DWORD*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
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{CV_AMD64_R12, "R12", (DWORD*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
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{CV_AMD64_R13, "R13", (DWORD*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
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{CV_AMD64_R14, "R14", (DWORD*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
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{CV_AMD64_R15, "R15", (DWORD*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
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{0, NULL, 0, dbg_itype_none}
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};
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static const struct dbg_internal_var* be_x86_64_init_registers(CONTEXT* ctx)
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{
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dbg_printf("not done\n");
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struct dbg_internal_var* div;
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for (div = be_x86_64_ctx; div->name; div++)
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div->pval = (DWORD*)((char*)ctx + (DWORD_PTR)div->pval);
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return be_x86_64_ctx;
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}
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