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435 lines
13 KiB
C
435 lines
13 KiB
C
/*
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* Emulation of privileged instructions
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*
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* Copyright 1995 Alexandre Julliard
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* Copyright 2005 Ivan Leo Puoti
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* Copyright 2005 Laurent Pinchart
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "config.h"
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#include "wine/port.h"
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#ifdef __i386__
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#include <stdarg.h>
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#include "windef.h"
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#include "winbase.h"
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#include "winternl.h"
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#include "excpt.h"
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#include "wine/debug.h"
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#include "wine/exception.h"
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WINE_DEFAULT_DEBUG_CHANNEL(int);
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#include "pshpack1.h"
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struct idtr
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{
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WORD limit;
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BYTE *base;
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};
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#include "poppack.h"
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static LDT_ENTRY idt[256];
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static inline struct idtr get_idtr(void)
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{
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struct idtr ret;
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#ifdef __GNUC__
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__asm__( "sidtl %0" : "=m" (ret) );
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#else
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ret.base = (BYTE *)idt;
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ret.limit = sizeof(idt) - 1;
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#endif
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return ret;
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}
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/* store an operand into a register */
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static void store_reg( CONTEXT *context, BYTE regmodrm, const BYTE *addr, int long_op )
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{
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switch((regmodrm >> 3) & 7)
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{
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case 0:
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if (long_op) context->Eax = *(const DWORD *)addr;
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else context->Eax = (context->Eax & 0xffff0000) | *(const WORD *)addr;
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break;
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case 1:
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if (long_op) context->Ecx = *(const DWORD *)addr;
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else context->Ecx = (context->Ecx & 0xffff0000) | *(const WORD *)addr;
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break;
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case 2:
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if (long_op) context->Edx = *(const DWORD *)addr;
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else context->Edx = (context->Edx & 0xffff0000) | *(const WORD *)addr;
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break;
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case 3:
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if (long_op) context->Ebx = *(const DWORD *)addr;
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else context->Ebx = (context->Ebx & 0xffff0000) | *(const WORD *)addr;
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break;
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case 4:
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if (long_op) context->Esp = *(const DWORD *)addr;
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else context->Esp = (context->Esp & 0xffff0000) | *(const WORD *)addr;
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break;
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case 5:
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if (long_op) context->Ebp = *(const DWORD *)addr;
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else context->Ebp = (context->Ebp & 0xffff0000) | *(const WORD *)addr;
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break;
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case 6:
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if (long_op) context->Esi = *(const DWORD *)addr;
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else context->Esi = (context->Esi & 0xffff0000) | *(const WORD *)addr;
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break;
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case 7:
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if (long_op) context->Edi = *(const DWORD *)addr;
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else context->Edi = (context->Edi & 0xffff0000) | *(const WORD *)addr;
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break;
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}
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}
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/***********************************************************************
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* INSTR_GetOperandAddr
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*
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* Return the address of an instruction operand (from the mod/rm byte).
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*/
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static BYTE *INSTR_GetOperandAddr( CONTEXT *context, BYTE *instr,
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int long_addr, int segprefix, int *len )
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{
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int mod, rm, base = 0, index = 0, ss = 0, off;
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#define GET_VAL(val,type) \
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{ *val = *(type *)instr; instr += sizeof(type); *len += sizeof(type); }
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*len = 0;
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GET_VAL( &mod, BYTE );
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rm = mod & 7;
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mod >>= 6;
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if (mod == 3)
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{
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switch(rm)
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{
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case 0: return (BYTE *)&context->Eax;
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case 1: return (BYTE *)&context->Ecx;
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case 2: return (BYTE *)&context->Edx;
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case 3: return (BYTE *)&context->Ebx;
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case 4: return (BYTE *)&context->Esp;
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case 5: return (BYTE *)&context->Ebp;
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case 6: return (BYTE *)&context->Esi;
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case 7: return (BYTE *)&context->Edi;
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}
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}
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if (long_addr)
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{
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if (rm == 4)
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{
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BYTE sib;
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GET_VAL( &sib, BYTE );
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rm = sib & 7;
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ss = sib >> 6;
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switch(sib >> 3)
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{
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case 0: index = context->Eax; break;
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case 1: index = context->Ecx; break;
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case 2: index = context->Edx; break;
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case 3: index = context->Ebx; break;
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case 4: index = 0; break;
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case 5: index = context->Ebp; break;
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case 6: index = context->Esi; break;
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case 7: index = context->Edi; break;
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}
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}
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switch(rm)
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{
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case 0: base = context->Eax; break;
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case 1: base = context->Ecx; break;
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case 2: base = context->Edx; break;
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case 3: base = context->Ebx; break;
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case 4: base = context->Esp; break;
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case 5: base = context->Ebp; break;
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case 6: base = context->Esi; break;
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case 7: base = context->Edi; break;
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}
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switch (mod)
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{
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case 0:
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if (rm == 5) /* special case: ds:(disp32) */
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{
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GET_VAL( &base, DWORD );
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 32-bit disp */
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GET_VAL( &off, DWORD );
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base += (signed long)off;
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break;
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}
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}
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else /* short address */
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{
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switch(rm)
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{
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case 0: /* ds:(bx,si) */
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base = LOWORD(context->Ebx) + LOWORD(context->Esi);
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break;
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case 1: /* ds:(bx,di) */
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base = LOWORD(context->Ebx) + LOWORD(context->Edi);
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break;
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case 2: /* ss:(bp,si) */
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base = LOWORD(context->Ebp) + LOWORD(context->Esi);
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break;
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case 3: /* ss:(bp,di) */
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base = LOWORD(context->Ebp) + LOWORD(context->Edi);
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break;
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case 4: /* ds:(si) */
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base = LOWORD(context->Esi);
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break;
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case 5: /* ds:(di) */
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base = LOWORD(context->Edi);
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break;
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case 6: /* ss:(bp) */
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base = LOWORD(context->Ebp);
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break;
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case 7: /* ds:(bx) */
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base = LOWORD(context->Ebx);
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break;
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}
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switch(mod)
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{
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case 0:
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if (rm == 6) /* special case: ds:(disp16) */
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{
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GET_VAL( &base, WORD );
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 16-bit disp */
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GET_VAL( &off, WORD );
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base += (signed short)off;
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break;
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}
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base &= 0xffff;
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}
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/* FIXME: we assume that all segments have a base of 0 */
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return (BYTE *)(base + (index << ss));
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#undef GET_VAL
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}
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/***********************************************************************
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* emulate_instruction
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*
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* Emulate a privileged instruction.
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* Returns exception continuation status.
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*/
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static DWORD emulate_instruction( EXCEPTION_RECORD *rec, CONTEXT *context )
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{
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int prefix, segprefix, prefixlen, len, long_op, long_addr;
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BYTE *instr;
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long_op = long_addr = 1;
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instr = (BYTE *)context->Eip;
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if (!instr) return ExceptionContinueSearch;
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/* First handle any possible prefix */
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segprefix = -1; /* no prefix */
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prefix = 1;
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prefixlen = 0;
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while(prefix)
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{
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switch(*instr)
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{
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case 0x2e:
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segprefix = context->SegCs;
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break;
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case 0x36:
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segprefix = context->SegSs;
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break;
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case 0x3e:
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segprefix = context->SegDs;
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break;
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case 0x26:
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segprefix = context->SegEs;
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break;
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case 0x64:
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segprefix = context->SegFs;
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break;
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case 0x65:
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segprefix = context->SegGs;
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break;
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case 0x66:
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long_op = !long_op; /* opcode size prefix */
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break;
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case 0x67:
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long_addr = !long_addr; /* addr size prefix */
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break;
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case 0xf0: /* lock */
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break;
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case 0xf2: /* repne */
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break;
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case 0xf3: /* repe */
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break;
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default:
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prefix = 0; /* no more prefixes */
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break;
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}
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if (prefix)
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{
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instr++;
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prefixlen++;
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}
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}
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/* Now look at the actual instruction */
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switch(*instr)
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{
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case 0x0f: /* extended instruction */
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switch(instr[1])
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{
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case 0x22: /* mov eax, crX */
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switch (instr[2])
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{
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case 0xc0:
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TRACE("mov eax,cr0 at 0x%08x, EAX=0x%08x\n", context->Eip,context->Eax );
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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default:
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break; /*fallthrough to bad instruction handling */
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}
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break; /*fallthrough to bad instruction handling */
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case 0x20: /* mov crX, eax */
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switch (instr[2])
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{
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case 0xe0: /* mov cr4, eax */
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/* CR4 register . See linux/arch/i386/mm/init.c, X86_CR4_ defs
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* bit 0: VME Virtual Mode Exception ?
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* bit 1: PVI Protected mode Virtual Interrupt
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* bit 2: TSD Timestamp disable
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* bit 3: DE Debugging extensions
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* bit 4: PSE Page size extensions
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* bit 5: PAE Physical address extension
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* bit 6: MCE Machine check enable
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* bit 7: PGE Enable global pages
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* bit 8: PCE Enable performance counters at IPL3
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*/
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TRACE("mov cr4,eax at 0x%08x\n",context->Eip);
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context->Eax = 0;
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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case 0xc0: /* mov cr0, eax */
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TRACE("mov cr0,eax at 0x%08x\n",context->Eip);
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context->Eax = 0x10; /* FIXME: set more bits ? */
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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default: /* fallthrough to illegal instruction */
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break;
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}
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/* fallthrough to illegal instruction */
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break;
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case 0x21: /* mov drX, eax */
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switch (instr[2])
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{
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case 0xc8: /* mov dr1, eax */
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TRACE("mov dr1,eax at 0x%08x\n",context->Eip);
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context->Eax = context->Dr1;
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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case 0xf8: /* mov dr7, eax */
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TRACE("mov dr7,eax at 0x%08x\n",context->Eip);
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context->Eax = 0x400;
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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}
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ERR("Unsupported DR register, eip+2 is %02x\n", instr[2]);
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/* fallthrough to illegal instruction */
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break;
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case 0x23: /* mov eax drX */
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switch (instr[2])
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{
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case 0xc8: /* mov eax, dr1 */
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context->Dr1 = context->Eax;
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context->Eip += prefixlen+3;
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return ExceptionContinueExecution;
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}
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ERR("Unsupported DR register, eip+2 is %02x\n", instr[2]);
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/* fallthrough to illegal instruction */
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break;
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}
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break; /* Unable to emulate it */
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case 0x8b: /* mov Ev, Gv */
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{
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BYTE *addr = INSTR_GetOperandAddr(context, instr + 1, long_addr,
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segprefix, &len);
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struct idtr idtr = get_idtr();
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unsigned int offset = addr - idtr.base;
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if (offset <= idtr.limit + 1 - (long_op ? 4 : 2))
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{
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idt[1].LimitLow = 0x100; /* FIXME */
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idt[2].LimitLow = 0x11E; /* FIXME */
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idt[3].LimitLow = 0x500; /* FIXME */
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store_reg( context, instr[1], (BYTE *)idt + offset, long_op );
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context->Eip += prefixlen + len + 1;
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return ExceptionContinueExecution;
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}
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break; /* Unable to emulate it */
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}
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case 0xfa: /* cli */
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case 0xfb: /* sti */
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context->Eip += prefixlen + 1;
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return ExceptionContinueExecution;
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}
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return ExceptionContinueSearch; /* Unable to emulate it */
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}
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/***********************************************************************
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* vectored_handler
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*
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* Vectored exception handler used to emulate protected instructions
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* from 32-bit code.
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*/
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LONG CALLBACK vectored_handler( EXCEPTION_POINTERS *ptrs )
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{
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EXCEPTION_RECORD *record = ptrs->ExceptionRecord;
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CONTEXT *context = ptrs->ContextRecord;
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if ((record->ExceptionCode == EXCEPTION_ACCESS_VIOLATION ||
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record->ExceptionCode == EXCEPTION_PRIV_INSTRUCTION))
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{
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if (emulate_instruction( record, context ) == ExceptionContinueExecution)
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return EXCEPTION_CONTINUE_EXECUTION;
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}
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return EXCEPTION_CONTINUE_SEARCH;
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}
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#endif /* __i386__ */
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