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385 lines
12 KiB
C
385 lines
12 KiB
C
/*
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* DMA Emulation
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*
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* Copyright 2002 Christian Costa
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "config.h"
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#include <stdarg.h>
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#include "windef.h"
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#include "winbase.h"
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#include "dosexe.h"
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#include "wine/debug.h"
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WINE_DEFAULT_DEBUG_CHANNEL(dma);
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/* Internal registers of the 2 DMA chips which control 8 DMA channels */
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static DWORD DMA_BaseAddress[8];
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static WORD DMA_ByteCount[8];
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static DWORD DMA_CurrentBaseAddress[8];
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static WORD DMA_CurrentByteCount[8];
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static BYTE DMA_Command[8];
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static BYTE DMA_Mask[2]={0x0F,0x0F};
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static BYTE DMA_Status[2]={0x00,0x00};
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static BOOL DMA_Toggle[2]={FALSE,FALSE};
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/*
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* DMA_Transfer : Try to perform a transfer of reqlen elements (8 or 16 bits)
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* on the specified channel and return the elements transferred
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*/
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int DMA_Transfer(int channel,int reqlen,void* buffer)
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{
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int i,size,ret=0;
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int opmode,increment,autoinit,trmode,dmachip;
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int regmode = DMA_Command[channel];
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char *p,*dmabuf;
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dmabuf = buffer;
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dmachip = (channel<4) ? 0 : 1;
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TRACE("DMA_Command = %x reqlen=%d\n",regmode,reqlen);
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/* Exit if channel is masked */
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if (DMA_Mask[dmachip]&(1<<(channel&3)))
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return 0;
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opmode = (regmode & 0xC0) >> 6;
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increment = !(regmode & 0x20);
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autoinit = regmode & 0x10;
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trmode = (regmode & 0x0C) >> 2;
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/* Transfer size : 8 bits for channels 0..3, 16 bits for channels 4..7 */
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size = (channel<4) ? 1 : 2;
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/* Process operating mode */
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switch(opmode)
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{
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case 0:
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/* Request mode */
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FIXME("Request Mode - Not Implemented\n");
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return 0;
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case 1:
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/* Single Mode */
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break;
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case 2:
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/* Request mode */
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FIXME("Block Mode - Not Implemented\n");
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return 0;
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case 3:
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/* Cascade Mode */
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ERR("Cascade Mode should not be used by regular apps\n");
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return 0;
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}
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/* Perform one the 4 transfer modes */
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if (trmode == 4) {
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/* Illegal */
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ERR("DMA Transfer Type Illegal\n");
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return 0;
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}
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ret = min(DMA_CurrentByteCount[channel],reqlen);
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/* Update DMA registers */
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DMA_CurrentByteCount[channel]-=ret;
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if (increment)
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DMA_CurrentBaseAddress[channel] += ret * size;
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else
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DMA_CurrentBaseAddress[channel] -= ret * size;
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switch(trmode)
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{
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case 0:
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/* Verification (no real transfer)*/
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TRACE("Verification DMA operation\n");
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break;
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case 1:
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/* Write */
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TRACE("Perform Write transfer of %d bytes at %x with count %x\n",ret,
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DMA_CurrentBaseAddress[channel],DMA_CurrentByteCount[channel]);
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if (increment)
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memcpy((void*)DMA_CurrentBaseAddress[channel],dmabuf,ret*size);
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else
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for(i=0,p=(char*)DMA_CurrentBaseAddress[channel];i<ret*size;i++)
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/* FIXME: possible endianness issue for 16 bits DMA */
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*(p-i) = dmabuf[i];
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break;
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case 2:
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/* Read */
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TRACE("Perform Read transfer of %d bytes at %x with count %x\n",ret,
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DMA_CurrentBaseAddress[channel],DMA_CurrentByteCount[channel]);
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if (increment)
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memcpy(dmabuf,(void*)DMA_CurrentBaseAddress[channel],ret*size);
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else
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for(i=0,p=(char*)DMA_CurrentBaseAddress[channel];i<ret*size;i++)
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/* FIXME: possible endianness issue for 16 bits DMA */
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dmabuf[i] = *(p-i);
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break;
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}
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/* Check for end of transfer */
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if (DMA_CurrentByteCount[channel]==0) {
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TRACE("DMA buffer empty\n");
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/* Update status register of the DMA chip corresponding to the channel */
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DMA_Status[dmachip] |= 1 << (channel & 0x3); /* Mark transfer as finished */
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DMA_Status[dmachip] &= ~(1 << ((channel & 0x3) + 4)); /* Reset soft request if any */
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if (autoinit) {
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/* Reload Current* register to their initial values */
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DMA_CurrentBaseAddress[channel] = DMA_BaseAddress[channel];
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DMA_CurrentByteCount[channel] = DMA_ByteCount[channel];
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}
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}
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return ret;
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}
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void DMA_ioport_out( WORD port, BYTE val )
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{
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int channel,dmachip;
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switch(port)
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{
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case 0x00:
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case 0x02:
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case 0x04:
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case 0x06:
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case 0xC0:
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case 0xC4:
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case 0xC8:
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case 0xCC:
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/* Base Address*/
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channel = (port&0xC0)?((port-0xC0)>>2):(port>>1);
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dmachip = (channel<4) ? 0 : 1;
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if (!DMA_Toggle[dmachip])
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DMA_BaseAddress[channel]=(DMA_BaseAddress[channel] & ~0xFF)|(val & 0xFF);
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else {
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DMA_BaseAddress[channel]=(DMA_BaseAddress[channel] & (~(0xFF << 8)))|((val & 0xFF) << 8);
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DMA_CurrentBaseAddress[channel] = DMA_BaseAddress[channel];
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TRACE("Write Base Address = %x\n",DMA_BaseAddress[channel]);
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}
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DMA_Toggle[dmachip] = !DMA_Toggle[dmachip];
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break;
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case 0x01:
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case 0x03:
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case 0x05:
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case 0x07:
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case 0xC2:
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case 0xC6:
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case 0xCA:
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case 0xCE:
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/* Count*/
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channel = ((port-1)&0xC0)?(((port-1)-0xC0)>>2):(port>>1);
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dmachip = (channel<4) ? 0 : 1;
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if (!DMA_Toggle[dmachip])
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DMA_ByteCount[channel]=(DMA_ByteCount[channel] & ~0xFF)|((val+1) & 0xFF);
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else {
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DMA_ByteCount[channel]=(DMA_ByteCount[channel] & (~(0xFF << 8)))|(((val+1) & 0xFF) << 8);
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DMA_CurrentByteCount[channel] = DMA_ByteCount[channel];
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TRACE("Write Count = %x.\n",DMA_ByteCount[channel]);
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}
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DMA_Toggle[dmachip] = !DMA_Toggle[dmachip];
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break;
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/* Low Page Base Address */
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case 0x87: DMA_BaseAddress[0]=(DMA_BaseAddress[0] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x83: DMA_BaseAddress[1]=(DMA_BaseAddress[1] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x81: DMA_BaseAddress[2]=(DMA_BaseAddress[2] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x82: DMA_BaseAddress[3]=(DMA_BaseAddress[3] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x8B: DMA_BaseAddress[5]=(DMA_BaseAddress[5] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x89: DMA_BaseAddress[6]=(DMA_BaseAddress[6] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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case 0x8A: DMA_BaseAddress[7]=(DMA_BaseAddress[7] & (~0xFF << 16))|((val & 0xFF) << 16); break;
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/* Low Page Base Address (only 4 lower bits are significant) */
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case 0x487: DMA_BaseAddress[0]=(DMA_BaseAddress[0] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x483: DMA_BaseAddress[1]=(DMA_BaseAddress[1] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x481: DMA_BaseAddress[2]=(DMA_BaseAddress[2] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x482: DMA_BaseAddress[3]=(DMA_BaseAddress[3] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x48B: DMA_BaseAddress[5]=(DMA_BaseAddress[5] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x489: DMA_BaseAddress[6]=(DMA_BaseAddress[6] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x48A: DMA_BaseAddress[7]=(DMA_BaseAddress[7] & (~0xFF << 24))|((val & 0x0F) << 24); break;
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case 0x08:
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case 0xD0:
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/* Command */
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FIXME("Write Command (%x) - Not Implemented\n",val);
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break;
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case 0x0B:
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case 0xD6:
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/* Mode */
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TRACE("Write Mode (%x)\n",val);
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DMA_Command[((port==0xD6)?4:0)+(val&0x3)]=val;
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switch(val>>6)
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{
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case 0:
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/* Request mode */
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FIXME("Request Mode - Not Implemented\n");
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break;
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case 1:
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/* Single Mode */
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break;
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case 2:
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/* Block mode */
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FIXME("Block Mode - Not Implemented\n");
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break;
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case 3:
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/* Cascade Mode */
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ERR("Cascade Mode should not be used by regular apps\n");
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break;
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}
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break;
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case 0x0A:
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case 0xD4:
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/* Write Single Mask Bit */
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TRACE("Write Single Mask Bit (%x)\n",val);
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dmachip = (port==0x0A) ? 0 : 1;
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if (val&4)
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DMA_Mask[dmachip] |= 1<<(val&3);
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else
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DMA_Mask[dmachip] &= ~(1<<(val&3));
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break;
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case 0x0F:
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case 0xDE:
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/* Write All Mask Bits (only 4 lower bits are significant */
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FIXME("Write All Mask Bits (%x)\n",val);
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dmachip = (port==0x0F) ? 0 : 1;
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DMA_Mask[dmachip] = val & 0x0F;
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break;
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case 0x09:
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case 0xD2:
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/* Software DRQx Request */
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FIXME("Software DRQx Request (%x) - Not Implemented\n",val);
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break;
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case 0x0C:
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case 0xD8:
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/* Reset DMA Pointer Flip-Flop */
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TRACE("Reset Flip-Flop\n");
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DMA_Toggle[port==0xD8]=FALSE;
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break;
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case 0x0D:
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case 0xDA:
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/* Master Reset */
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TRACE("Master Reset\n");
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dmachip = (port==0x0D) ? 0 : 1;
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/* Reset DMA Pointer Flip-Flop */
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DMA_Toggle[dmachip]=FALSE;
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/* Mask all channels */
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DMA_Mask[dmachip] = 0x0F;
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break;
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case 0x0E:
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case 0xDC:
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/* Reset Mask Register */
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FIXME("Reset Mask Register\n");
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dmachip = (port==0x0E) ? 0 : 1;
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/* Unmask all channels */
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DMA_Mask[dmachip] = 0x00;
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break;
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}
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}
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BYTE DMA_ioport_in( WORD port )
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{
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int channel,dmachip;
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BYTE res = 0;
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switch(port)
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{
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case 0x00:
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case 0x02:
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case 0x04:
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case 0x06:
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case 0xC0:
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case 0xC4:
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case 0xC8:
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case 0xCC:
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/* Base Address*/
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channel = (port&0xC0)?((port-0xC0)>>2):(port>>1);
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dmachip = (channel<4) ? 0 : 1;
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if (!DMA_Toggle[dmachip])
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res = DMA_CurrentBaseAddress[channel] & 0xFF;
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else {
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res = (DMA_CurrentBaseAddress[channel] & (0xFF << 8))>>8;
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TRACE("Read Current Base Address = %x\n",DMA_CurrentBaseAddress[channel]);
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}
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DMA_Toggle[dmachip] = !DMA_Toggle[dmachip];
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break;
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case 0x01:
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case 0x03:
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case 0x05:
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case 0x07:
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case 0xC2:
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case 0xC6:
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case 0xCA:
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case 0xCE:
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/* Count*/
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channel = ((port-1)&0xC0)?(((port-1)-0xC0)>>2):(port>>1);
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dmachip = (channel<4) ? 0 : 1;
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if (!DMA_Toggle[dmachip])
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res = DMA_CurrentByteCount[channel] & 0xFF;
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else {
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res = (DMA_CurrentByteCount[channel] & (0xFF << 8))>>8;
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TRACE("Read Current Count = %x.\n",DMA_CurrentByteCount[channel]);
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}
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DMA_Toggle[dmachip] = !DMA_Toggle[dmachip];
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break;
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/* Low Page Base Address */
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case 0x87: res = (DMA_BaseAddress[0]&(0xFF<<16))>>16; break;
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case 0x83: res = (DMA_BaseAddress[1]&(0xFF<<16))>>16; break;
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case 0x81: res = (DMA_BaseAddress[2]&(0xFF<<16))>>16; break;
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case 0x82: res = (DMA_BaseAddress[3]&(0xFF<<16))>>16; break;
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case 0x8B: res = (DMA_BaseAddress[5]&(0xFF<<16))>>16; break;
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case 0x89: res = (DMA_BaseAddress[6]&(0xFF<<16))>>16; break;
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case 0x8A: res = (DMA_BaseAddress[7]&(0xFF<<16))>>16; break;
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/* High Page Base Address */
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case 0x487: res = (DMA_BaseAddress[0]&(0xFF<<24))>>24; break;
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case 0x483: res = (DMA_BaseAddress[1]&(0xFF<<24))>>24; break;
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case 0x481: res = (DMA_BaseAddress[2]&(0xFF<<24))>>24; break;
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case 0x482: res = (DMA_BaseAddress[3]&(0xFF<<24))>>24; break;
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case 0x48B: res = (DMA_BaseAddress[5]&(0xFF<<24))>>24; break;
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case 0x489: res = (DMA_BaseAddress[6]&(0xFF<<24))>>24; break;
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case 0x48A: res = (DMA_BaseAddress[7]&(0xFF<<24))>>24; break;
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case 0x08:
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case 0xD0:
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/* Status */
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TRACE("Status Register Read\n");
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res = DMA_Status[(port==0x08)?0:1];
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case 0x0D:
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case 0xDA:
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/* Temporary */
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FIXME("Temporary Register Read- Not Implemented\n");
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break;
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}
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return res;
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}
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