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1716 lines
74 KiB
Plaintext
1716 lines
74 KiB
Plaintext
/*
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* Direct3D shader assembler
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*
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* Copyright 2008 Stefan Dösinger
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* Copyright 2009 Matteo Bruni
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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%{
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#include "config.h"
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#include "wine/port.h"
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#include "wine/debug.h"
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#include "d3dcompiler_private.h"
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WINE_DEFAULT_DEBUG_CHANNEL(asmshader);
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struct asm_parser asm_ctx;
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void asmparser_message(struct asm_parser *ctx, const char *fmt, ...)
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{
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va_list args;
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va_start(args, fmt);
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compilation_message(&ctx->messages, fmt, args);
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va_end(args);
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}
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static void asmshader_error(char const *s) {
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asmparser_message(&asm_ctx, "Line %u: Error \"%s\" from bison\n", asm_ctx.line_no, s);
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set_parse_status(&asm_ctx.status, PARSE_ERR);
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}
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static void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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/* We can have an additional offset without true relative addressing
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* ex. c2[ 4 ] */
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reg->regnum += rel->additional_offset;
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if(!rel->has_rel_reg) {
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reg->rel_reg = NULL;
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} else {
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reg->rel_reg = d3dcompiler_alloc(sizeof(*reg->rel_reg));
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if(!reg->rel_reg) {
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return;
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}
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reg->rel_reg->type = rel->type;
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reg->rel_reg->u.swizzle = rel->swizzle;
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reg->rel_reg->regnum = rel->rel_regnum;
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}
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}
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/* Needed lexer functions declarations */
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int asmshader_lex(void);
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%}
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%union {
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struct {
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float val;
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BOOL integer;
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} immval;
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BOOL immbool;
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unsigned int regnum;
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struct shader_reg reg;
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DWORD srcmod;
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DWORD writemask;
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struct {
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DWORD writemask;
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DWORD idx;
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DWORD last;
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} wm_components;
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DWORD swizzle;
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struct {
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DWORD swizzle;
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DWORD idx;
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} sw_components;
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DWORD component;
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struct {
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DWORD mod;
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DWORD shift;
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} modshift;
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enum bwriter_comparison_type comptype;
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struct {
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DWORD dclusage;
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unsigned int regnum;
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} declaration;
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BWRITERSAMPLER_TEXTURE_TYPE samplertype;
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struct rel_reg rel_reg;
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struct src_regs sregs;
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}
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/* Common instructions between vertex and pixel shaders */
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%token INSTR_ADD
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%token INSTR_NOP
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%token INSTR_MOV
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%token INSTR_SUB
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%token INSTR_MAD
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%token INSTR_MUL
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%token INSTR_RCP
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%token INSTR_RSQ
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%token INSTR_DP3
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%token INSTR_DP4
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%token INSTR_MIN
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%token INSTR_MAX
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%token INSTR_SLT
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%token INSTR_SGE
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%token INSTR_ABS
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%token INSTR_EXP
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%token INSTR_LOG
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%token INSTR_EXPP
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%token INSTR_LOGP
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%token INSTR_DST
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%token INSTR_LRP
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%token INSTR_FRC
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%token INSTR_POW
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%token INSTR_CRS
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%token INSTR_SGN
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%token INSTR_NRM
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%token INSTR_SINCOS
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%token INSTR_M4x4
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%token INSTR_M4x3
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%token INSTR_M3x4
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%token INSTR_M3x3
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%token INSTR_M3x2
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%token INSTR_DCL
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%token INSTR_DEF
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%token INSTR_DEFB
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%token INSTR_DEFI
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%token INSTR_REP
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%token INSTR_ENDREP
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%token INSTR_IF
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%token INSTR_ELSE
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%token INSTR_ENDIF
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%token INSTR_BREAK
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%token INSTR_BREAKP
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%token INSTR_CALL
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%token INSTR_CALLNZ
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%token INSTR_LOOP
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%token INSTR_RET
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%token INSTR_ENDLOOP
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%token INSTR_LABEL
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%token INSTR_SETP
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%token INSTR_TEXLDL
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/* Vertex shader only instructions */
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%token INSTR_LIT
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%token INSTR_MOVA
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/* Pixel shader only instructions */
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%token INSTR_CND
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%token INSTR_CMP
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%token INSTR_DP2ADD
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%token INSTR_TEXCOORD
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%token INSTR_TEXCRD
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%token INSTR_TEXKILL
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%token INSTR_TEX
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%token INSTR_TEXLD
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%token INSTR_TEXBEM
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%token INSTR_TEXBEML
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%token INSTR_TEXREG2AR
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%token INSTR_TEXREG2GB
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%token INSTR_TEXREG2RGB
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%token INSTR_TEXM3x2PAD
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%token INSTR_TEXM3x2TEX
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%token INSTR_TEXM3x3PAD
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%token INSTR_TEXM3x3SPEC
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%token INSTR_TEXM3x3VSPEC
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%token INSTR_TEXM3x3TEX
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%token INSTR_TEXDP3TEX
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%token INSTR_TEXM3x2DEPTH
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%token INSTR_TEXDP3
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%token INSTR_TEXM3x3
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%token INSTR_TEXDEPTH
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%token INSTR_BEM
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%token INSTR_DSX
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%token INSTR_DSY
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%token INSTR_TEXLDP
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%token INSTR_TEXLDB
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%token INSTR_TEXLDD
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%token INSTR_PHASE
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/* Registers */
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%token <regnum> REG_TEMP
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%token <regnum> REG_OUTPUT
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%token <regnum> REG_INPUT
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%token <regnum> REG_CONSTFLOAT
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%token <regnum> REG_CONSTINT
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%token <regnum> REG_CONSTBOOL
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%token <regnum> REG_TEXTURE
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%token <regnum> REG_SAMPLER
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%token <regnum> REG_TEXCRDOUT
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%token REG_OPOS
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%token REG_OFOG
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%token REG_OPTS
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%token <regnum> REG_VERTEXCOLOR
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%token <regnum> REG_FRAGCOLOR
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%token REG_FRAGDEPTH
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%token REG_VPOS
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%token REG_VFACE
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%token REG_ADDRESS
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%token REG_LOOP
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%token REG_PREDICATE
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%token <regnum> REG_LABEL
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/* Version tokens */
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%token VER_VS10
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%token VER_VS11
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%token VER_VS20
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%token VER_VS2X
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%token VER_VS30
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%token VER_PS10
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%token VER_PS11
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%token VER_PS12
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%token VER_PS13
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%token VER_PS14
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%token VER_PS20
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%token VER_PS2X
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%token VER_PS30
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/* Output modifiers */
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%token SHIFT_X2
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%token SHIFT_X4
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%token SHIFT_X8
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%token SHIFT_D2
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%token SHIFT_D4
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%token SHIFT_D8
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%token MOD_SAT
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%token MOD_PP
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%token MOD_CENTROID
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/* Compare tokens */
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%token COMP_GT
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%token COMP_LT
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%token COMP_GE
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%token COMP_LE
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%token COMP_EQ
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%token COMP_NE
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/* Source register modifiers */
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%token SMOD_BIAS
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%token SMOD_SCALEBIAS
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%token SMOD_DZ
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%token SMOD_DW
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%token SMOD_ABS
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%token SMOD_NOT
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/* Sampler types */
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%token SAMPTYPE_1D
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%token SAMPTYPE_2D
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%token SAMPTYPE_CUBE
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%token SAMPTYPE_VOLUME
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/* Usage declaration tokens */
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%token <regnum> USAGE_POSITION
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%token <regnum> USAGE_BLENDWEIGHT
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%token <regnum> USAGE_BLENDINDICES
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%token <regnum> USAGE_NORMAL
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%token <regnum> USAGE_PSIZE
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%token <regnum> USAGE_TEXCOORD
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%token <regnum> USAGE_TANGENT
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%token <regnum> USAGE_BINORMAL
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%token <regnum> USAGE_TESSFACTOR
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%token <regnum> USAGE_POSITIONT
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%token <regnum> USAGE_COLOR
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%token <regnum> USAGE_FOG
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%token <regnum> USAGE_DEPTH
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%token <regnum> USAGE_SAMPLE
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/* Misc stuff */
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%token <component> COMPONENT
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%token <immval> IMMVAL
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%token <immbool> IMMBOOL
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%type <reg> dreg_name
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%type <reg> dreg
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%type <reg> sreg_name
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%type <reg> relreg_name
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%type <reg> sreg
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%type <srcmod> smod
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%type <writemask> writemask
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%type <wm_components> wm_components
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%type <swizzle> swizzle
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%type <sw_components> sw_components
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%type <modshift> omods
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%type <modshift> omodifier
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%type <comptype> comp
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%type <declaration> dclusage
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%type <reg> dcl_inputreg
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%type <samplertype> sampdcl
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%type <rel_reg> rel_reg
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%type <reg> predicate
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%type <immval> immsum
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%type <sregs> sregs
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%%
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shader: version_marker instructions
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{
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asm_ctx.funcs->end(&asm_ctx);
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}
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version_marker: VER_VS10
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{
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TRACE("Vertex shader 1.0\n");
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create_vs10_parser(&asm_ctx);
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}
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| VER_VS11
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{
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TRACE("Vertex shader 1.1\n");
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create_vs11_parser(&asm_ctx);
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}
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| VER_VS20
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{
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TRACE("Vertex shader 2.0\n");
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create_vs20_parser(&asm_ctx);
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}
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| VER_VS2X
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{
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TRACE("Vertex shader 2.x\n");
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create_vs2x_parser(&asm_ctx);
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}
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| VER_VS30
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{
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TRACE("Vertex shader 3.0\n");
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create_vs30_parser(&asm_ctx);
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}
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| VER_PS10
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{
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TRACE("Pixel shader 1.0\n");
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create_ps10_parser(&asm_ctx);
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}
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| VER_PS11
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{
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TRACE("Pixel shader 1.1\n");
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create_ps11_parser(&asm_ctx);
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}
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| VER_PS12
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{
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TRACE("Pixel shader 1.2\n");
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create_ps12_parser(&asm_ctx);
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}
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| VER_PS13
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{
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TRACE("Pixel shader 1.3\n");
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create_ps13_parser(&asm_ctx);
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}
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| VER_PS14
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{
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TRACE("Pixel shader 1.4\n");
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create_ps14_parser(&asm_ctx);
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}
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| VER_PS20
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{
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TRACE("Pixel shader 2.0\n");
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create_ps20_parser(&asm_ctx);
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}
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| VER_PS2X
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{
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TRACE("Pixel shader 2.x\n");
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create_ps2x_parser(&asm_ctx);
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}
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| VER_PS30
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{
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TRACE("Pixel shader 3.0\n");
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create_ps30_parser(&asm_ctx);
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}
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instructions: /* empty */
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| instructions complexinstr
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{
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/* Nothing to do */
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}
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complexinstr: instruction
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{
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}
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| predicate instruction
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{
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TRACE("predicate\n");
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asm_ctx.funcs->predicate(&asm_ctx, &$1);
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}
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| '+' instruction
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{
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TRACE("coissue\n");
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asm_ctx.funcs->coissue(&asm_ctx);
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}
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instruction: INSTR_ADD omods dreg ',' sregs
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{
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TRACE("ADD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ADD, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_NOP
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{
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TRACE("NOP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NOP, 0, 0, 0, 0, 0, 0);
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}
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| INSTR_MOV omods dreg ',' sregs
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{
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TRACE("MOV\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOV, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_SUB omods dreg ',' sregs
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{
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TRACE("SUB\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SUB, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_MAD omods dreg ',' sregs
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{
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TRACE("MAD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAD, $2.mod, $2.shift, 0, &$3, &$5, 3);
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}
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| INSTR_MUL omods dreg ',' sregs
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{
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TRACE("MUL\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MUL, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_RCP omods dreg ',' sregs
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{
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TRACE("RCP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RCP, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_RSQ omods dreg ',' sregs
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{
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TRACE("RSQ\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RSQ, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_DP3 omods dreg ',' sregs
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{
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TRACE("DP3\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP3, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_DP4 omods dreg ',' sregs
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{
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TRACE("DP4\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP4, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_MIN omods dreg ',' sregs
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{
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TRACE("MIN\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MIN, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_MAX omods dreg ',' sregs
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{
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TRACE("MAX\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAX, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_SLT omods dreg ',' sregs
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{
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TRACE("SLT\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SLT, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_SGE omods dreg ',' sregs
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{
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TRACE("SGE\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGE, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_ABS omods dreg ',' sregs
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{
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TRACE("ABS\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ABS, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_EXP omods dreg ',' sregs
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{
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TRACE("EXP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXP, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_LOG omods dreg ',' sregs
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{
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TRACE("LOG\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOG, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_LOGP omods dreg ',' sregs
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{
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TRACE("LOGP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOGP, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_EXPP omods dreg ',' sregs
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{
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TRACE("EXPP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXPP, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_DST omods dreg ',' sregs
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{
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TRACE("DST\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DST, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_LRP omods dreg ',' sregs
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{
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TRACE("LRP\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LRP, $2.mod, $2.shift, 0, &$3, &$5, 3);
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}
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| INSTR_FRC omods dreg ',' sregs
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{
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TRACE("FRC\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_FRC, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_POW omods dreg ',' sregs
|
|
{
|
|
TRACE("POW\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_POW, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_CRS omods dreg ',' sregs
|
|
{
|
|
TRACE("CRS\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CRS, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_SGN omods dreg ',' sregs
|
|
{
|
|
TRACE("SGN\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGN, $2.mod, $2.shift, 0, &$3, &$5, 3);
|
|
}
|
|
| INSTR_NRM omods dreg ',' sregs
|
|
{
|
|
TRACE("NRM\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NRM, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_SINCOS omods dreg ',' sregs
|
|
{
|
|
TRACE("SINCOS\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SINCOS, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_M4x4 omods dreg ',' sregs
|
|
{
|
|
TRACE("M4x4\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_M4x3 omods dreg ',' sregs
|
|
{
|
|
TRACE("M4x3\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_M3x4 omods dreg ',' sregs
|
|
{
|
|
TRACE("M3x4\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_M3x3 omods dreg ',' sregs
|
|
{
|
|
TRACE("M3x3\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_M3x2 omods dreg ',' sregs
|
|
{
|
|
TRACE("M3x2\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x2, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_DCL dclusage REG_OUTPUT
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Output reg declaration\n");
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = BWRITERSPR_OUTPUT;
|
|
reg.regnum = $3;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
|
|
asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, ®);
|
|
}
|
|
| INSTR_DCL dclusage REG_OUTPUT writemask
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Output reg declaration\n");
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = BWRITERSPR_OUTPUT;
|
|
reg.regnum = $3;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = $4;
|
|
asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, ®);
|
|
}
|
|
| INSTR_DCL dclusage omods dcl_inputreg
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Input reg declaration\n");
|
|
if($3.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
|
|
asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
|
|
asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = $4.type;
|
|
reg.regnum = $4.regnum;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
|
|
asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, ®);
|
|
}
|
|
| INSTR_DCL dclusage omods dcl_inputreg writemask
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Input reg declaration\n");
|
|
if($3.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
|
|
asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
|
|
asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = $4.type;
|
|
reg.regnum = $4.regnum;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = $5;
|
|
asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, ®);
|
|
}
|
|
| INSTR_DCL omods dcl_inputreg
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Input reg declaration\n");
|
|
if($2.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
if(asm_ctx.shader->type != ST_PIXEL) {
|
|
asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = $3.type;
|
|
reg.regnum = $3.regnum;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
|
|
asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, ®);
|
|
}
|
|
| INSTR_DCL omods dcl_inputreg writemask
|
|
{
|
|
struct shader_reg reg;
|
|
TRACE("Input reg declaration\n");
|
|
if($2.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
if(asm_ctx.shader->type != ST_PIXEL) {
|
|
asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
ZeroMemory(®, sizeof(reg));
|
|
reg.type = $3.type;
|
|
reg.regnum = $3.regnum;
|
|
reg.rel_reg = NULL;
|
|
reg.srcmod = 0;
|
|
reg.u.writemask = $4;
|
|
asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, ®);
|
|
}
|
|
| INSTR_DCL sampdcl omods REG_SAMPLER
|
|
{
|
|
TRACE("Sampler declared\n");
|
|
if($3.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
asm_ctx.funcs->dcl_sampler(&asm_ctx, $2, $3.mod, $4, asm_ctx.line_no);
|
|
}
|
|
| INSTR_DCL omods REG_SAMPLER
|
|
{
|
|
TRACE("Sampler declared\n");
|
|
if($2.shift != 0) {
|
|
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
if(asm_ctx.shader->type != ST_PIXEL) {
|
|
asmparser_message(&asm_ctx, "Line %u: Declaration needs a sampler type\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
asm_ctx.funcs->dcl_sampler(&asm_ctx, BWRITERSTT_UNKNOWN, $2.mod, $3, asm_ctx.line_no);
|
|
}
|
|
| INSTR_DCL sampdcl omods dcl_inputreg
|
|
{
|
|
TRACE("Error rule: sampler decl of input reg\n");
|
|
asmparser_message(&asm_ctx, "Line %u: Sampler declarations of input regs is not valid\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| INSTR_DCL sampdcl omods REG_OUTPUT
|
|
{
|
|
TRACE("Error rule: sampler decl of output reg\n");
|
|
asmparser_message(&asm_ctx, "Line %u: Sampler declarations of output regs is not valid\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| INSTR_DEF REG_CONSTFLOAT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
|
|
{
|
|
asm_ctx.funcs->constF(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
|
|
}
|
|
| INSTR_DEFI REG_CONSTINT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
|
|
{
|
|
asm_ctx.funcs->constI(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
|
|
}
|
|
| INSTR_DEFB REG_CONSTBOOL ',' IMMBOOL
|
|
{
|
|
asm_ctx.funcs->constB(&asm_ctx, $2, $4);
|
|
}
|
|
| INSTR_REP sregs
|
|
{
|
|
TRACE("REP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_REP, 0, 0, 0, 0, &$2, 1);
|
|
}
|
|
| INSTR_ENDREP
|
|
{
|
|
TRACE("ENDREP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDREP, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_IF sregs
|
|
{
|
|
TRACE("IF\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IF, 0, 0, 0, 0, &$2, 1);
|
|
}
|
|
| INSTR_IF comp sregs
|
|
{
|
|
TRACE("IFC\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IFC, 0, 0, $2, 0, &$3, 2);
|
|
}
|
|
| INSTR_ELSE
|
|
{
|
|
TRACE("ELSE\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ELSE, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_ENDIF
|
|
{
|
|
TRACE("ENDIF\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDIF, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_BREAK
|
|
{
|
|
TRACE("BREAK\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAK, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_BREAK comp sregs
|
|
{
|
|
TRACE("BREAKC\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKC, 0, 0, $2, 0, &$3, 2);
|
|
}
|
|
| INSTR_BREAKP sregs
|
|
{
|
|
TRACE("BREAKP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKP, 0, 0, 0, 0, &$2, 1);
|
|
}
|
|
| INSTR_CALL sregs
|
|
{
|
|
TRACE("CALL\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALL, 0, 0, 0, 0, &$2, 1);
|
|
}
|
|
| INSTR_CALLNZ sregs
|
|
{
|
|
TRACE("CALLNZ\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALLNZ, 0, 0, 0, 0, &$2, 2);
|
|
}
|
|
| INSTR_LOOP sregs
|
|
{
|
|
TRACE("LOOP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOOP, 0, 0, 0, 0, &$2, 2);
|
|
}
|
|
| INSTR_RET
|
|
{
|
|
TRACE("RET\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RET, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_ENDLOOP
|
|
{
|
|
TRACE("ENDLOOP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDLOOP, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
| INSTR_LABEL sregs
|
|
{
|
|
TRACE("LABEL\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LABEL, 0, 0, 0, 0, &$2, 1);
|
|
}
|
|
| INSTR_SETP comp dreg ',' sregs
|
|
{
|
|
TRACE("SETP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SETP, 0, 0, $2, &$3, &$5, 2);
|
|
}
|
|
| INSTR_TEXLDL omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXLDL\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDL, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_LIT omods dreg ',' sregs
|
|
{
|
|
TRACE("LIT\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LIT, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_MOVA omods dreg ',' sregs
|
|
{
|
|
TRACE("MOVA\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOVA, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_CND omods dreg ',' sregs
|
|
{
|
|
TRACE("CND\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CND, $2.mod, $2.shift, 0, &$3, &$5, 3);
|
|
}
|
|
| INSTR_CMP omods dreg ',' sregs
|
|
{
|
|
TRACE("CMP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CMP, $2.mod, $2.shift, 0, &$3, &$5, 3);
|
|
}
|
|
| INSTR_DP2ADD omods dreg ',' sregs
|
|
{
|
|
TRACE("DP2ADD\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP2ADD, $2.mod, $2.shift, 0, &$3, &$5, 3);
|
|
}
|
|
| INSTR_TEXCOORD omods dreg
|
|
{
|
|
TRACE("TEXCOORD\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, 0, 0);
|
|
}
|
|
| INSTR_TEXCRD omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXCRD\n");
|
|
/* texcoord and texcrd share the same opcode */
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXKILL dreg
|
|
{
|
|
TRACE("TEXKILL\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXKILL, 0, 0, 0, &$2, 0, 0);
|
|
}
|
|
| INSTR_TEX omods dreg
|
|
{
|
|
TRACE("TEX\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, 0, 0);
|
|
}
|
|
| INSTR_TEXDEPTH omods dreg
|
|
{
|
|
TRACE("TEXDEPTH\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDEPTH, $2.mod, $2.shift, 0, &$3, 0, 0);
|
|
}
|
|
| INSTR_TEXLD omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXLD\n");
|
|
/* There is more than one acceptable syntax for texld:
|
|
with 1 sreg (PS 1.4) or
|
|
with 2 sregs (PS 2.0+)
|
|
Moreover, texld shares the same opcode as the tex instruction,
|
|
so there are a total of 3 valid syntaxes
|
|
These variations are handled in asmparser.c */
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_TEXLDP omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXLDP\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDP, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_TEXLDB omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXLDB\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDB, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_TEXBEM omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXBEM\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEM, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXBEML omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXBEML\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEML, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXREG2AR omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXREG2AR\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2AR, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXREG2GB omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXREG2GB\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2GB, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXREG2RGB omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXREG2RGB\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2RGB, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x2PAD omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x2PAD\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x3PAD omods dreg ',' sregs
|
|
{
|
|
TRACE("INSTR_TEXM3x3PAD\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x3SPEC omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x3SPEC\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3SPEC, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_TEXM3x3VSPEC omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x3VSPEC\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3VSPEC, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x3TEX omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x3TEX\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXDP3TEX omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXDP3TEX\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x2DEPTH omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x2DEPTH\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2DEPTH, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x2TEX omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x2TEX\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXDP3 omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXDP3\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXM3x3 omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXM3x3\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_BEM omods dreg ',' sregs
|
|
{
|
|
TRACE("BEM\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BEM, $2.mod, $2.shift, 0, &$3, &$5, 2);
|
|
}
|
|
| INSTR_DSX omods dreg ',' sregs
|
|
{
|
|
TRACE("DSX\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSX, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_DSY omods dreg ',' sregs
|
|
{
|
|
TRACE("DSY\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSY, $2.mod, $2.shift, 0, &$3, &$5, 1);
|
|
}
|
|
| INSTR_TEXLDD omods dreg ',' sregs
|
|
{
|
|
TRACE("TEXLDD\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDD, $2.mod, $2.shift, 0, &$3, &$5, 4);
|
|
}
|
|
| INSTR_PHASE
|
|
{
|
|
TRACE("PHASE\n");
|
|
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_PHASE, 0, 0, 0, 0, 0, 0);
|
|
}
|
|
|
|
|
|
dreg: dreg_name rel_reg
|
|
{
|
|
$$.regnum = $1.regnum;
|
|
$$.type = $1.type;
|
|
$$.u.writemask = BWRITERSP_WRITEMASK_ALL;
|
|
$$.srcmod = BWRITERSPSM_NONE;
|
|
set_rel_reg(&$$, &$2);
|
|
}
|
|
| dreg_name writemask
|
|
{
|
|
$$.regnum = $1.regnum;
|
|
$$.type = $1.type;
|
|
$$.u.writemask = $2;
|
|
$$.srcmod = BWRITERSPSM_NONE;
|
|
$$.rel_reg = NULL;
|
|
}
|
|
|
|
dreg_name: REG_TEMP
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEMP;
|
|
}
|
|
| REG_OUTPUT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_OUTPUT;
|
|
}
|
|
| REG_INPUT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
|
|
}
|
|
| REG_CONSTFLOAT
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register c%u is not a valid destination register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_CONSTINT
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register i%u is not a valid destination register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_CONSTBOOL
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register b%u is not a valid destination register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_TEXTURE
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
|
|
}
|
|
| REG_TEXCRDOUT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEXCRDOUT;
|
|
}
|
|
| REG_SAMPLER
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register s%u is not a valid destination register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_OPOS
|
|
{
|
|
$$.regnum = BWRITERSRO_POSITION; $$.type = BWRITERSPR_RASTOUT;
|
|
}
|
|
| REG_OPTS
|
|
{
|
|
$$.regnum = BWRITERSRO_POINT_SIZE; $$.type = BWRITERSPR_RASTOUT;
|
|
}
|
|
| REG_OFOG
|
|
{
|
|
$$.regnum = BWRITERSRO_FOG; $$.type = BWRITERSPR_RASTOUT;
|
|
}
|
|
| REG_VERTEXCOLOR
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_ATTROUT;
|
|
}
|
|
| REG_FRAGCOLOR
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_COLOROUT;
|
|
}
|
|
| REG_FRAGDEPTH
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_DEPTHOUT;
|
|
}
|
|
| REG_PREDICATE
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
|
|
}
|
|
| REG_VPOS
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register vPos is not a valid destination register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_VFACE
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register vFace is not a valid destination register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_ADDRESS
|
|
{
|
|
/* index 0 is hardcoded for the addr register */
|
|
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
|
|
}
|
|
| REG_LOOP
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register aL is not a valid destination register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
|
|
writemask: '.' wm_components
|
|
{
|
|
if($2.writemask == SWIZZLE_ERR) {
|
|
asmparser_message(&asm_ctx, "Line %u: Invalid writemask specified\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
/* Provide a correct writemask to prevent following complaints */
|
|
$$ = BWRITERSP_WRITEMASK_ALL;
|
|
}
|
|
else {
|
|
$$ = $2.writemask;
|
|
TRACE("Writemask: %x\n", $$);
|
|
}
|
|
}
|
|
|
|
wm_components: COMPONENT
|
|
{
|
|
$$.writemask = 1 << $1;
|
|
$$.last = $1;
|
|
$$.idx = 1;
|
|
}
|
|
| wm_components COMPONENT
|
|
{
|
|
if($1.writemask == SWIZZLE_ERR || $1.idx == 4)
|
|
/* Wrong writemask */
|
|
$$.writemask = SWIZZLE_ERR;
|
|
else {
|
|
if($2 <= $1.last)
|
|
$$.writemask = SWIZZLE_ERR;
|
|
else {
|
|
$$.writemask = $1.writemask | (1 << $2);
|
|
$$.idx = $1.idx + 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
swizzle: /* empty */
|
|
{
|
|
$$ = BWRITERVS_NOSWIZZLE;
|
|
TRACE("Default swizzle: %08x\n", $$);
|
|
}
|
|
| '.' sw_components
|
|
{
|
|
if($2.swizzle == SWIZZLE_ERR) {
|
|
asmparser_message(&asm_ctx, "Line %u: Invalid swizzle\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
/* Provide a correct swizzle to prevent following complaints */
|
|
$$ = BWRITERVS_NOSWIZZLE;
|
|
}
|
|
else {
|
|
DWORD last, i;
|
|
|
|
$$ = $2.swizzle << BWRITERVS_SWIZZLE_SHIFT;
|
|
/* Fill the swizzle by extending the last component */
|
|
last = ($2.swizzle >> 2 * ($2.idx - 1)) & 0x03;
|
|
for(i = $2.idx; i < 4; i++){
|
|
$$ |= last << (BWRITERVS_SWIZZLE_SHIFT + 2 * i);
|
|
}
|
|
TRACE("Got a swizzle: %08x\n", $$);
|
|
}
|
|
}
|
|
|
|
sw_components: COMPONENT
|
|
{
|
|
$$.swizzle = $1;
|
|
$$.idx = 1;
|
|
}
|
|
| sw_components COMPONENT
|
|
{
|
|
if($1.idx == 4) {
|
|
/* Too many sw_components */
|
|
$$.swizzle = SWIZZLE_ERR;
|
|
$$.idx = 4;
|
|
}
|
|
else {
|
|
$$.swizzle = $1.swizzle | ($2 << 2 * $1.idx);
|
|
$$.idx = $1.idx + 1;
|
|
}
|
|
}
|
|
|
|
omods: /* Empty */
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 0;
|
|
}
|
|
| omods omodifier
|
|
{
|
|
$$.mod = $1.mod | $2.mod;
|
|
if($1.shift && $2.shift) {
|
|
asmparser_message(&asm_ctx, "Line %u: More than one shift flag\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
$$.shift = $1.shift;
|
|
} else {
|
|
$$.shift = $1.shift | $2.shift;
|
|
}
|
|
}
|
|
|
|
omodifier: SHIFT_X2
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 1;
|
|
}
|
|
| SHIFT_X4
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 2;
|
|
}
|
|
| SHIFT_X8
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 3;
|
|
}
|
|
| SHIFT_D2
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 15;
|
|
}
|
|
| SHIFT_D4
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 14;
|
|
}
|
|
| SHIFT_D8
|
|
{
|
|
$$.mod = 0;
|
|
$$.shift = 13;
|
|
}
|
|
| MOD_SAT
|
|
{
|
|
$$.mod = BWRITERSPDM_SATURATE;
|
|
$$.shift = 0;
|
|
}
|
|
| MOD_PP
|
|
{
|
|
$$.mod = BWRITERSPDM_PARTIALPRECISION;
|
|
$$.shift = 0;
|
|
}
|
|
| MOD_CENTROID
|
|
{
|
|
$$.mod = BWRITERSPDM_MSAMPCENTROID;
|
|
$$.shift = 0;
|
|
}
|
|
|
|
sregs: sreg
|
|
{
|
|
$$.reg[0] = $1;
|
|
$$.count = 1;
|
|
}
|
|
| sregs ',' sreg
|
|
{
|
|
if($$.count == MAX_SRC_REGS){
|
|
asmparser_message(&asm_ctx, "Line %u: Too many source registers in this instruction\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
else
|
|
$$.reg[$$.count++] = $3;
|
|
}
|
|
|
|
sreg: sreg_name rel_reg swizzle
|
|
{
|
|
$$.type = $1.type;
|
|
$$.regnum = $1.regnum;
|
|
$$.u.swizzle = $3;
|
|
$$.srcmod = BWRITERSPSM_NONE;
|
|
set_rel_reg(&$$, &$2);
|
|
}
|
|
| sreg_name rel_reg smod swizzle
|
|
{
|
|
$$.type = $1.type;
|
|
$$.regnum = $1.regnum;
|
|
set_rel_reg(&$$, &$2);
|
|
$$.srcmod = $3;
|
|
$$.u.swizzle = $4;
|
|
}
|
|
| '-' sreg_name rel_reg swizzle
|
|
{
|
|
$$.type = $2.type;
|
|
$$.regnum = $2.regnum;
|
|
$$.srcmod = BWRITERSPSM_NEG;
|
|
set_rel_reg(&$$, &$3);
|
|
$$.u.swizzle = $4;
|
|
}
|
|
| '-' sreg_name rel_reg smod swizzle
|
|
{
|
|
$$.type = $2.type;
|
|
$$.regnum = $2.regnum;
|
|
set_rel_reg(&$$, &$3);
|
|
switch($4) {
|
|
case BWRITERSPSM_BIAS: $$.srcmod = BWRITERSPSM_BIASNEG; break;
|
|
case BWRITERSPSM_X2: $$.srcmod = BWRITERSPSM_X2NEG; break;
|
|
case BWRITERSPSM_SIGN: $$.srcmod = BWRITERSPSM_SIGNNEG; break;
|
|
case BWRITERSPSM_ABS: $$.srcmod = BWRITERSPSM_ABSNEG; break;
|
|
case BWRITERSPSM_DZ:
|
|
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DZ\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
break;
|
|
case BWRITERSPSM_DW:
|
|
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DW\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
break;
|
|
default:
|
|
FIXME("Unhandled combination of NEGATE and %u\n", $4);
|
|
}
|
|
$$.u.swizzle = $5;
|
|
}
|
|
| IMMVAL '-' sreg_name rel_reg swizzle
|
|
{
|
|
if($1.val != 1.0 || (!$1.integer)) {
|
|
asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP, "
|
|
"%g - reg found\n", asm_ctx.line_no, $1.val);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
/* Complement - not compatible with other source modifiers */
|
|
$$.type = $3.type;
|
|
$$.regnum = $3.regnum;
|
|
$$.srcmod = BWRITERSPSM_COMP;
|
|
set_rel_reg(&$$, &$4);
|
|
$$.u.swizzle = $5;
|
|
}
|
|
| IMMVAL '-' sreg_name rel_reg smod swizzle
|
|
{
|
|
/* For nicer error reporting */
|
|
if($1.val != 1.0 || (!$1.integer)) {
|
|
asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
} else {
|
|
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: D3DSPSM_COMP and %s\n",
|
|
asm_ctx.line_no,
|
|
debug_print_srcmod($5));
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
}
|
|
| SMOD_NOT sreg_name swizzle
|
|
{
|
|
$$.type = $2.type;
|
|
$$.regnum = $2.regnum;
|
|
$$.rel_reg = NULL;
|
|
$$.srcmod = BWRITERSPSM_NOT;
|
|
$$.u.swizzle = $3;
|
|
}
|
|
|
|
rel_reg: /* empty */
|
|
{
|
|
$$.has_rel_reg = FALSE;
|
|
$$.additional_offset = 0;
|
|
}
|
|
| '[' immsum ']'
|
|
{
|
|
$$.has_rel_reg = FALSE;
|
|
$$.additional_offset = $2.val;
|
|
}
|
|
| '[' relreg_name swizzle ']'
|
|
{
|
|
$$.has_rel_reg = TRUE;
|
|
$$.type = $2.type;
|
|
$$.additional_offset = 0;
|
|
$$.rel_regnum = $2.regnum;
|
|
$$.swizzle = $3;
|
|
}
|
|
| '[' immsum '+' relreg_name swizzle ']'
|
|
{
|
|
$$.has_rel_reg = TRUE;
|
|
$$.type = $4.type;
|
|
$$.additional_offset = $2.val;
|
|
$$.rel_regnum = $4.regnum;
|
|
$$.swizzle = $5;
|
|
}
|
|
| '[' relreg_name swizzle '+' immsum ']'
|
|
{
|
|
$$.has_rel_reg = TRUE;
|
|
$$.type = $2.type;
|
|
$$.additional_offset = $5.val;
|
|
$$.rel_regnum = $2.regnum;
|
|
$$.swizzle = $3;
|
|
}
|
|
| '[' immsum '+' relreg_name swizzle '+' immsum ']'
|
|
{
|
|
$$.has_rel_reg = TRUE;
|
|
$$.type = $4.type;
|
|
$$.additional_offset = $2.val + $7.val;
|
|
$$.rel_regnum = $4.regnum;
|
|
$$.swizzle = $5;
|
|
}
|
|
|
|
immsum: IMMVAL
|
|
{
|
|
if(!$1.integer) {
|
|
asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
|
|
asm_ctx.line_no, $1.val);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
$$.val = $1.val;
|
|
}
|
|
| immsum '+' IMMVAL
|
|
{
|
|
if(!$3.integer) {
|
|
asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
|
|
asm_ctx.line_no, $3.val);
|
|
set_parse_status(&asm_ctx.status, PARSE_ERR);
|
|
}
|
|
$$.val = $1.val + $3.val;
|
|
}
|
|
|
|
smod: SMOD_BIAS
|
|
{
|
|
$$ = BWRITERSPSM_BIAS;
|
|
}
|
|
| SHIFT_X2
|
|
{
|
|
$$ = BWRITERSPSM_X2;
|
|
}
|
|
| SMOD_SCALEBIAS
|
|
{
|
|
$$ = BWRITERSPSM_SIGN;
|
|
}
|
|
| SMOD_DZ
|
|
{
|
|
$$ = BWRITERSPSM_DZ;
|
|
}
|
|
| SMOD_DW
|
|
{
|
|
$$ = BWRITERSPSM_DW;
|
|
}
|
|
| SMOD_ABS
|
|
{
|
|
$$ = BWRITERSPSM_ABS;
|
|
}
|
|
|
|
relreg_name: REG_ADDRESS
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
|
|
}
|
|
| REG_LOOP
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_LOOP;
|
|
}
|
|
|
|
sreg_name: REG_TEMP
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEMP;
|
|
}
|
|
| REG_OUTPUT
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register o%u is not a valid source register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_INPUT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
|
|
}
|
|
| REG_CONSTFLOAT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_CONST;
|
|
}
|
|
| REG_CONSTINT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_CONSTINT;
|
|
}
|
|
| REG_CONSTBOOL
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_CONSTBOOL;
|
|
}
|
|
| REG_TEXTURE
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
|
|
}
|
|
| REG_TEXCRDOUT
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oT%u is not a valid source register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_SAMPLER
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_SAMPLER;
|
|
}
|
|
| REG_OPOS
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oPos is not a valid source register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_OFOG
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oFog is not a valid source register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_VERTEXCOLOR
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oD%u is not a valid source register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_FRAGCOLOR
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oC%u is not a valid source register\n",
|
|
asm_ctx.line_no, $1);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_FRAGDEPTH
|
|
{
|
|
asmparser_message(&asm_ctx, "Line %u: Register oDepth is not a valid source register\n",
|
|
asm_ctx.line_no);
|
|
set_parse_status(&asm_ctx.status, PARSE_WARN);
|
|
}
|
|
| REG_PREDICATE
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
|
|
}
|
|
| REG_VPOS
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_MISCTYPE;
|
|
}
|
|
| REG_VFACE
|
|
{
|
|
$$.regnum = 1; $$.type = BWRITERSPR_MISCTYPE;
|
|
}
|
|
| REG_ADDRESS
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
|
|
}
|
|
| REG_LOOP
|
|
{
|
|
$$.regnum = 0; $$.type = BWRITERSPR_LOOP;
|
|
}
|
|
| REG_LABEL
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_LABEL;
|
|
}
|
|
|
|
comp: COMP_GT { $$ = BWRITER_COMPARISON_GT; }
|
|
| COMP_LT { $$ = BWRITER_COMPARISON_LT; }
|
|
| COMP_GE { $$ = BWRITER_COMPARISON_GE; }
|
|
| COMP_LE { $$ = BWRITER_COMPARISON_LE; }
|
|
| COMP_EQ { $$ = BWRITER_COMPARISON_EQ; }
|
|
| COMP_NE { $$ = BWRITER_COMPARISON_NE; }
|
|
|
|
dclusage: USAGE_POSITION
|
|
{
|
|
TRACE("dcl_position%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_POSITION;
|
|
}
|
|
| USAGE_BLENDWEIGHT
|
|
{
|
|
TRACE("dcl_blendweight%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_BLENDWEIGHT;
|
|
}
|
|
| USAGE_BLENDINDICES
|
|
{
|
|
TRACE("dcl_blendindices%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_BLENDINDICES;
|
|
}
|
|
| USAGE_NORMAL
|
|
{
|
|
TRACE("dcl_normal%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_NORMAL;
|
|
}
|
|
| USAGE_PSIZE
|
|
{
|
|
TRACE("dcl_psize%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_PSIZE;
|
|
}
|
|
| USAGE_TEXCOORD
|
|
{
|
|
TRACE("dcl_texcoord%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_TEXCOORD;
|
|
}
|
|
| USAGE_TANGENT
|
|
{
|
|
TRACE("dcl_tangent%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_TANGENT;
|
|
}
|
|
| USAGE_BINORMAL
|
|
{
|
|
TRACE("dcl_binormal%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_BINORMAL;
|
|
}
|
|
| USAGE_TESSFACTOR
|
|
{
|
|
TRACE("dcl_tessfactor%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_TESSFACTOR;
|
|
}
|
|
| USAGE_POSITIONT
|
|
{
|
|
TRACE("dcl_positiont%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_POSITIONT;
|
|
}
|
|
| USAGE_COLOR
|
|
{
|
|
TRACE("dcl_color%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_COLOR;
|
|
}
|
|
| USAGE_FOG
|
|
{
|
|
TRACE("dcl_fog%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_FOG;
|
|
}
|
|
| USAGE_DEPTH
|
|
{
|
|
TRACE("dcl_depth%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_DEPTH;
|
|
}
|
|
| USAGE_SAMPLE
|
|
{
|
|
TRACE("dcl_sample%u\n", $1);
|
|
$$.regnum = $1;
|
|
$$.dclusage = BWRITERDECLUSAGE_SAMPLE;
|
|
}
|
|
|
|
dcl_inputreg: REG_INPUT
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
|
|
}
|
|
| REG_TEXTURE
|
|
{
|
|
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
|
|
}
|
|
|
|
sampdcl: SAMPTYPE_1D
|
|
{
|
|
$$ = BWRITERSTT_1D;
|
|
}
|
|
| SAMPTYPE_2D
|
|
{
|
|
$$ = BWRITERSTT_2D;
|
|
}
|
|
| SAMPTYPE_CUBE
|
|
{
|
|
$$ = BWRITERSTT_CUBE;
|
|
}
|
|
| SAMPTYPE_VOLUME
|
|
{
|
|
$$ = BWRITERSTT_VOLUME;
|
|
}
|
|
|
|
predicate: '(' REG_PREDICATE swizzle ')'
|
|
{
|
|
$$.type = BWRITERSPR_PREDICATE;
|
|
$$.regnum = 0;
|
|
$$.rel_reg = NULL;
|
|
$$.srcmod = BWRITERSPSM_NONE;
|
|
$$.u.swizzle = $3;
|
|
}
|
|
| '(' SMOD_NOT REG_PREDICATE swizzle ')'
|
|
{
|
|
$$.type = BWRITERSPR_PREDICATE;
|
|
$$.regnum = 0;
|
|
$$.rel_reg = NULL;
|
|
$$.srcmod = BWRITERSPSM_NOT;
|
|
$$.u.swizzle = $4;
|
|
}
|
|
|
|
%%
|
|
|
|
struct bwriter_shader *parse_asm_shader(char **messages)
|
|
{
|
|
struct bwriter_shader *ret = NULL;
|
|
|
|
asm_ctx.shader = NULL;
|
|
asm_ctx.status = PARSE_SUCCESS;
|
|
asm_ctx.messages.size = asm_ctx.messages.capacity = 0;
|
|
asm_ctx.line_no = 1;
|
|
|
|
asmshader_parse();
|
|
|
|
if (asm_ctx.status != PARSE_ERR)
|
|
ret = asm_ctx.shader;
|
|
else if (asm_ctx.shader)
|
|
SlDeleteShader(asm_ctx.shader);
|
|
|
|
if (messages)
|
|
{
|
|
if (asm_ctx.messages.size)
|
|
{
|
|
/* Shrink the buffer to the used size */
|
|
*messages = d3dcompiler_realloc(asm_ctx.messages.string, asm_ctx.messages.size + 1);
|
|
if (!*messages)
|
|
{
|
|
ERR("Out of memory, no messages reported\n");
|
|
d3dcompiler_free(asm_ctx.messages.string);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
*messages = NULL;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (asm_ctx.messages.capacity)
|
|
d3dcompiler_free(asm_ctx.messages.string);
|
|
}
|
|
|
|
return ret;
|
|
}
|