d "halt" 4ac8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x3)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pulse" 4acc 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x4)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "plpaw (a0)" f588 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "plpar (a0)" f5c8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "move16 (a0)+, (a1)+" f6209000 0x0 (seq (set src_addr (var a0)) (set dst_addr (var a1)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10)))) (set a1 (cast 32 false (+ (var dst_addr) (bv 32 0x10)))))
d "lpstop 0x0" f80001c00000 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (&& (&& (ule (var format) (bv 16 0x5)) (! (== (var format) (bv 16 0x5)))) (! (== (var format) (bv 16 0x1)))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr))))
