d "msac.l d0, d0, >>, acc2" a0000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0)))))
d "mac.w d1l, d0l, acc0" a0010000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.w d1l, d0l, acc0" a0010100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.w d1l, d0u, <<, acc0" a0010280 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var d0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var d0) (bv 8 0x10) false))) (cast 16 false (>> (var d0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var d0) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.w d2l, d0l, >>, acc0" a0020600 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d2) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d2))) (cast 16 false (var d2))) (cast 32 false (cast 16 false (var d2)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.w a0l, d0l, acc0" a0080000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.w a0l, d0l, acc0" a0080100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.l a0, d0, acc0" a0080800 0x0 (seq (set src0 (var a0)) (set src1 (var d0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.l a0, d0, >>, acc2" a0080fff 0x0 (seq (set src0 (var a0)) (set src1 (var d0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0)))))
d "mac.w d0l, d0l, (a0), d0, acc1" a0100000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, (a0)&, d0, acc3" a010007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, (a0), d0, acc1" a0100100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, (a0)&, d0, acc3" a010017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, (a0), d0, acc1" a0100800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, (a0)&, d0, acc3" a0100fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, (a0)&, d0, acc3" a0101234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, (a0)&, d0, acc3" a0105678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, (a0), d0, acc1" a0108000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, (a0), d0, acc1" a0108100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, (a0)&, d0, acc3" a01091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, (a0)&, d0, acc3" a0109abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, (a0)&, d0, acc3" a010ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, d0l, (a0)+, d0, acc1" a0180000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w a7u, d0l, (a0)+&, d0, acc3" a018007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w d0l, d0l, (a0)+, d0, acc1" a0180100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w a7u, d0l, (a0)+&, d0, acc3" a018017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.l d0, d0, (a0)+, d0, acc1" a0180800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.l a7, d0, >>, (a0)+&, d0, acc3" a0180fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d4l, d1l, <<, (a0)+&, d0, acc3" a0181234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w a0u, d5l, >>, (a0)+&, d0, acc3" a0185678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d0l, a0l, (a0)+, d0, acc1" a0188000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w d0l, a0l, (a0)+, d0, acc1" a0188100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w a7u, a1u, (a0)+&, d0, acc3" a01891ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.l a4, a1, <<, (a0)+&, d0, acc3" a0189abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.l a7, a7, >>, (a0)+&, d0, acc3" a018ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d0l, d0l, -(a0), d0, acc1" a0200000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, -(a0)&, d0, acc3" a020007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, -(a0), d0, acc1" a0200100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, -(a0)&, d0, acc3" a020017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, -(a0), d0, acc1" a0200800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, -(a0)&, d0, acc3" a0200fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, -(a0)&, d0, acc3" a0201234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, -(a0)&, d0, acc3" a0205678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, -(a0), d0, acc1" a0208000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, -(a0), d0, acc1" a0208100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, -(a0)&, d0, acc3" a02091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, -(a0)&, d0, acc3" a0209abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, -(a0)&, d0, acc3" a020ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, d0l, 0x1(a0), d0, acc1" a02800000001 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, 0x80(a0)&, d0, acc3" a028007f0080 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x80))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, 0x17f(a0), d0, acc1" a0280100017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, 0x180(a0)&, d0, acc3" a028017f0180 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, 0xfff(a0), d0, acc1" a02808000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, 0x1000(a0)&, d0, acc3" a0280fff1000 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, 0x5678(a0)&, d0, acc3" a02812345678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x5678))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, -0x6544(a0)&, d0, acc3" a02856789abc 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff9abc))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, -0x7f00(a0), d0, acc1" a02880008100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, -0x7e90(a0), d0, acc1" a02881008170 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8170))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, -0x5f00(a0)&, d0, acc3" a02891ffa100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffa100))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, 0x0(a0)&, d0, acc3" a0289abc0000 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, 0x1234(a0)&, d0, acc3" a028ffff1234 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1234))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, acc0" a0400000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.w d0l, a0l, acc0" a0400100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.l d0, a0, acc0" a0400800 0x0 (seq (set src0 (var d0)) (set src1 (var a0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.l d0, a0, >>, acc2" a0400fff 0x0 (seq (set src0 (var d0)) (set src1 (var a0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0)))))
d "mac.w a0l, a0l, acc0" a0480000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.w a0l, a0l, acc0" a0480100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.l a0, a0, acc0" a0480800 0x0 (seq (set src0 (var a0)) (set src1 (var a0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.l a0, a0, >>, acc2" a0480fff 0x0 (seq (set src0 (var a0)) (set src1 (var a0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0)))))
d "mac.w d0l, d0l, (a0), a0, acc1" a0500000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, (a0)&, a0, acc3" a050007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, (a0), a0, acc1" a0500100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, (a0)&, a0, acc3" a050017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, (a0), a0, acc1" a0500800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, (a0)&, a0, acc3" a0500fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, (a0)&, a0, acc3" a0501234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, (a0)&, a0, acc3" a0505678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, (a0), a0, acc1" a0508000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, (a0), a0, acc1" a0508100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, (a0)&, a0, acc3" a05091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, (a0)&, a0, acc3" a0509abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, (a0)&, a0, acc3" a050ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d0l, d0l, (a0)+, a0, acc1" a0580000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w a7u, d0l, (a0)+&, a0, acc3" a058007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w d0l, d0l, (a0)+, a0, acc1" a0580100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w a7u, d0l, (a0)+&, a0, acc3" a058017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.l d0, d0, (a0)+, a0, acc1" a0580800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.l a7, d0, >>, (a0)+&, a0, acc3" a0580fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d4l, d1l, <<, (a0)+&, a0, acc3" a0581234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w a0u, d5l, >>, (a0)+&, a0, acc3" a0585678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d0l, a0l, (a0)+, a0, acc1" a0588000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w d0l, a0l, (a0)+, a0, acc1" a0588100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.w a7u, a1u, (a0)+&, a0, acc3" a05891ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.l a4, a1, <<, (a0)+&, a0, acc3" a0589abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "msac.l a7, a7, >>, (a0)+&, a0, acc3" a058ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4)))))
d "mac.w d0l, d0l, -(a0), a0, acc1" a0600000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, -(a0)&, a0, acc3" a060007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, -(a0), a0, acc1" a0600100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, -(a0)&, a0, acc3" a060017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, -(a0), a0, acc1" a0600800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, -(a0)&, a0, acc3" a0600fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, -(a0)&, a0, acc3" a0601234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, -(a0)&, a0, acc3" a0605678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, -(a0), a0, acc1" a0608000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, -(a0), a0, acc1" a0608100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, -(a0)&, a0, acc3" a06091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, -(a0)&, a0, acc3" a0609abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, -(a0)&, a0, acc3" a060ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d0l, d0l, 0x1(a0), a0, acc1" a06800000001 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a7u, d0l, 0x80(a0)&, a0, acc3" a068007f0080 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x80))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, d0l, 0x17f(a0), a0, acc1" a0680100017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, d0l, 0x180(a0)&, a0, acc3" a068017f0180 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l d0, d0, 0xfff(a0), a0, acc1" a06808000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, d0, >>, 0x1000(a0)&, a0, acc3" a0680fff1000 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d4l, d1l, <<, 0x5678(a0)&, a0, acc3" a06812345678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x5678))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w a0u, d5l, >>, -0x6544(a0)&, a0, acc3" a06856789abc 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff9abc))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.w d0l, a0l, -0x7f00(a0), a0, acc1" a06880008100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w d0l, a0l, -0x7e90(a0), a0, acc1" a06881008170 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8170))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.w a7u, a1u, -0x5f00(a0)&, a0, acc3" a06891ffa100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffa100))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "mac.l a4, a1, <<, 0x0(a0)&, a0, acc3" a0689abc0000 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "msac.l a7, a7, >>, 0x1234(a0)&, a0, acc3" a068ffff1234 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1234))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))))
d "move.l d0, acc0" a100 0x0 (seq (set src (var d0)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0)))))
d "move.l a0, acc0" a108 0x0 (seq (set src (var a0)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0)))))
d "move.l 0x12345678, acc0" a13c12345678 0x0 (seq (set src (bv 32 0x12345678)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0)))))
d "move.l acc0, d0" a180 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set d0 (cast 32 false (var stored))))
d "move.l acc0, a0" a188 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set a0 (cast 32 false (var stored))))
d "move.l acc0, acc1" a310 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set acc1 (cast 32 false (var src))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (& (var macsr) (bv 32 0xfffffdf0)) (ite (! (is_zero (& (cast 32 false (var ext16)) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0))) (ite (! (is_zero (& (var macsr) (bv 32 0x100)))) (bv 32 0x202) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (! (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (! (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff)))) (! (is_zero (var ext16))))) (bv 32 0x1) (bv 32 0x0)))))
d "movclr.l acc0, d0" a1c0 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set d0 (cast 32 false (var stored))) (set acc0 (cast 32 false (bv 32 0x0))) (set accext01 (cast 32 false (& (var accext01) (bv 32 0xffff0000)))) (set macsr (& (var macsr) (bv 32 0xfffffeff))))
d "movclr.l acc0, a0" a1c8 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set a0 (cast 32 false (var stored))) (set acc0 (cast 32 false (bv 32 0x0))) (set accext01 (cast 32 false (& (var accext01) (bv 32 0xffff0000)))) (set macsr (& (var macsr) (bv 32 0xfffffeff))))
d "mac.w a1l, a2u, (a3), d1, acc0" a293a089 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load))))
d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load))))
d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load))))
d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load))))
d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load))))
d "mac.l d2, d3, acc0" a6020800 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "msac.l d2, d3, acc0" a6020900 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))))
d "mac.l d2, d3, acc1" a6820800 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))))
d "move.l d0, macsr" a900 0x0 (seq (set src (var d0)) (set vis (& (var src) (bv 32 0xfff))) (set macsr (cast 32 false (var vis))))
d "move.l 0x7, macsr" a93c00000007 0x0 (seq (set src (bv 32 0x7)) (set vis (& (var src) (bv 32 0xfff))) (set macsr (cast 32 false (var vis))))
d "move.l macsr, d0" a980 0x0 (seq (set src (var macsr)) (set vis (& (var src) (bv 32 0xfff))) (set d0 (cast 32 false (var vis))))
d "move.l macsr, ccr" a9c0 0x0 (seq (set macsr_src (var macsr)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (bv 8 0x0) (bv 8 0xf7)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x8)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x4)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x2)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x1)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "move.l d0, accext01" ab00 0x0 (seq (set src (var d0)) (set accext01 (cast 32 false (var src))))
d "move.l 0x7, accext01" ab3c00000007 0x0 (seq (set src (bv 32 0x7)) (set accext01 (cast 32 false (var src))))
d "move.l accext01, d0" ab80 0x0 (seq (set src (var accext01)) (set d0 (cast 32 false (var src))))
d "move.l d0, mask" ad00 0x0 (seq (set src (var d0)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set mask (cast 32 false (var masked))))
d "move.l 0x7, mask" ad3c00000007 0x0 (seq (set src (bv 32 0x7)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set mask (cast 32 false (var masked))))
d "move.l mask, d0" ad80 0x0 (seq (set src (var mask)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set d0 (cast 32 false (var masked))))
d "move.l d0, accext23" af00 0x0 (seq (set src (var d0)) (set accext23 (cast 32 false (var src))))
d "fbf.w 0x12" f2800010
d "fbf.l 0x12" f2c000000010
