# TMS320C28x (SPRU430F) native disassembler.
# Instruction words are little-endian; addresses are byte addresses, i.e.
# twice the C28x word address, matching the scaling the loaders apply.
# Every vector below was cross-checked against TI dis2000 (c2000 v6.2.0).
# Vectors carrying a fourth column also assert the lifted RzIL; the rest decode
# but are not lifted yet.

# control transfer and stack
d "lretr" 0600 0x0 (seq (set rt (var rpc)) (set sp (- (var sp) (bv 16 0x1))) (set hi (cast 32 false (loadw 0 16 (* (cast 32 false (var sp)) (bv 32 0x2))))) (set sp (- (var sp) (bv 16 0x1))) (set np (& (| (<< (var hi) (bv 6 0x10) false) (cast 32 false (loadw 0 16 (* (cast 32 false (var sp)) (bv 32 0x2))))) (bv 32 0x3fffff))) (set rpc (var np)) (jmp (* (cast 32 false (var rt)) (bv 32 0x2))))
d "aborti" 0100 0x0
d "push rpc" 0400 0x0
d "pop rpc" 0700 0x0
d "lb *xar7" 2076 0x0 (jmp (* (cast 32 false (& (var xar7) (bv 32 0x3fffff))) (bv 32 0x2)))
d "lcr *xar4" 643e 0x100 (seq (set ra (var rpc)) (storew 0 (* (cast 32 false (var sp)) (bv 32 0x2)) (cast 16 false (var ra))) (set sp (+ (var sp) (bv 16 0x1))) (storew 0 (* (cast 32 false (var sp)) (bv 32 0x2)) (cast 16 false (>> (var ra) (bv 6 0x10) false))) (set sp (+ (var sp) (bv 16 0x1))) (set rpc (bv 32 0x81)) (jmp (* (cast 32 false (& (var xar4) (bv 32 0x3fffff))) (bv 32 0x2))))

# loc16 addressing modes
d "mov al, @0x00" 0092 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))))
d "mov al, *-sp[0]" 4092 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x0)))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))))
d "mov al, *xar0++" 8092 0x0 (seq (set _ea (var xar0)) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))) (set xar0 (+ (var xar0) (bv 32 0x1))))
d "mov al, *+xar0[0]" c092 0x0 (seq (set _ea (+ (var xar0) (bv 32 0x0))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))))
d "mov al, *arp0" b092 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))) (set arp (bv 3 0x0)))
d "mov al, *sp++" bd92 0x0 (seq (set _ea (cast 32 false (var sp))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))) (set sp (+ (var sp) (bv 16 0x1))))
d "mov al, *--sp" be92 0x0 (seq (set sp (- (var sp) (bv 16 0x1))) (set _ea (cast 32 false (var sp))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))))
d "mov al, @ar0" a092 0x0 (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (cast 16 false (var xar0)))))

# AX select bit (A=0 is AL)
d "mov ah, @0x00" 0093 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set acc (| (& (var acc) (bv 32 0xffff)) (<< (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (bv 6 0x10) false))))
d "andb ah, #0x0" 0091 0x0 (seq (set acc (| (& (var acc) (bv 32 0xffff)) (<< (cast 32 false (& (cast 16 false (>> (var acc) (bv 6 0x10) false)) (bv 16 0x0))) (bv 6 0x10) false))) (set n (msb (cast 16 false (>> (var acc) (bv 6 0x10) false)))) (set z (is_zero (cast 16 false (>> (var acc) (bv 6 0x10) false)))))
d "andb ah, #0x1" 0191 0x0 (seq (set acc (| (& (var acc) (bv 32 0xffff)) (<< (cast 32 false (& (cast 16 false (>> (var acc) (bv 6 0x10) false)) (bv 16 0x1))) (bv 6 0x10) false))) (set n (msb (cast 16 false (>> (var acc) (bv 6 0x10) false)))) (set z (is_zero (cast 16 false (>> (var acc) (bv 6 0x10) false)))))
d "lsr al, 1" c0ff 0x0 (seq (set sv (cast 16 false (var acc))) (set c (lsb (>> (var sv) (bv 6 0x0) false))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (>> (var sv) (bv 6 0x1) false)))) (set n (msb (cast 16 false (var acc)))) (set z (is_zero (cast 16 false (var acc)))))
d "lsr ah, 1" d0ff 0x0 (seq (set sv (cast 16 false (>> (var acc) (bv 6 0x10) false))) (set c (lsb (>> (var sv) (bv 6 0x0) false))) (set acc (| (& (var acc) (bv 32 0xffff)) (<< (cast 32 false (>> (var sv) (bv 6 0x1) false)) (bv 6 0x10) false))) (set n (msb (cast 16 false (>> (var acc) (bv 6 0x10) false)))) (set z (is_zero (cast 16 false (>> (var acc) (bv 6 0x10) false)))))
d "lsr al, t" 62ff 0x0
d "lsr ah, t" 63ff 0x0

# accumulator and 32-bit moves
d "movl acc, @acc" a806 0x0 (set acc (var acc))
d "movl acc, @xar0" a006 0x0 (set acc (var xar0))
d "movl @xar7, acc" a71e 0x0 (set xar7 (var acc))
d "cmpl acc, @xar6" a60f 0x0 (seq (set cl (var acc)) (set cr (var xar6)) (set cd (- (var cl) (var cr))) (set n (msb (var cd))) (set z (is_zero (var cd))) (set c (! (&& (ule (var cl) (var cr)) (! (== (var cl) (var cr)))))))
d "mov acc, @0x00" 0085 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (ite (var sxm) (cast 32 (msb (var _val)) (var _val)) (cast 32 false (var _val)))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "dmov @0x00" 00a5 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x1))) (bv 32 0x2)) (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))))

# two-word immediate forms
d "movl xar0, #0x7700" 008d0077 0x0 (set xar0 (bv 32 0x7700))
d "movl xar5, #0x7700" 408f0077 0x0 (set xar5 (bv 32 0x7700))
d "movl xar6, #0x7700" 80760077 0x0 (set xar6 (bv 32 0x7700))
d "movl xar7, #0x7700" c0760077 0x0 (set xar7 (bv 32 0x7700))
d "mov @0x00, #0x7700" 00280077 0x0 (seq (set mv (bv 16 0x7700)) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var mv)) nop)
d "subcu acc, *-sp[54]" 761f 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x36)))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set tq (- (<< (cast 33 false (var acc)) (bv 6 0x1) false) (<< (cast 33 false (var _val)) (bv 6 0x10) false))) (set c (! (msb (var tq)))) (branch (msb (var tq)) (set acc (<< (var acc) (bv 6 0x1) false)) (set acc (+ (cast 32 false (var tq)) (bv 32 0x1)))) (set n (msb (var acc))) (set z (is_zero (var acc))))

# multiply
d "mpy acc, t, @0x00" 0012 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (* (cast 32 (msb (cast 16 false (>> (var xt) (bv 6 0x10) false))) (cast 16 false (>> (var xt) (bv 6 0x10) false))) (cast 32 (msb (var _val)) (var _val)))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "mpy acc, @0x00, #0x7700" 00340077 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (* (cast 32 (msb (var _val)) (var _val)) (cast 32 (msb (bv 16 0x7700)) (bv 16 0x7700)))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "mpyxu acc, t, @0x00" 0030 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (* (cast 32 (msb (cast 16 false (>> (var xt) (bv 6 0x10) false))) (cast 16 false (>> (var xt) (bv 6 0x10) false))) (cast 32 false (var _val)))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "mpyu acc, t, @0x00" 0036 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (* (cast 32 false (cast 16 false (>> (var xt) (bv 6 0x10) false))) (cast 32 false (var _val)))) (set n (msb (var acc))) (set z (is_zero (var acc))))

# 0x56 extended plane
d "sub acc, @0x0a" 00560a00 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0xa))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set oa (var acc)) (set av (ite (var sxm) (cast 32 (msb (var _val)) (var _val)) (cast 32 false (var _val)))) (set na (- (var oa) (var av))) (set ovf (msb (& (^ (var oa) (var av)) (^ (var oa) (var na))))) (set acc (ite (&& (var ovm) (var ovf)) (ite (msb (var oa)) (bv 32 0x80000000) (bv 32 0x7fffffff)) (var na))) (set v (|| (var v) (var ovf))) (set c (! (&& (ule (var oa) (var av)) (! (== (var oa) (var av)))))) (set ovc (ite (&& (var ovf) (! (var ovm))) (ite (msb (var na)) (+ (var ovc) (bv 6 0x1)) (- (var ovc) (bv 6 0x1))) (var ovc))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "addl @0x0a, acc" 01560a00 0x0
d "asrl acc, t" 1056 0x0 (seq (set sv (var acc)) (set sc (cast 32 false (& (cast 16 false (>> (var xt) (bv 6 0x10) false)) (bv 16 0x1f)))) (set sr (ite true (>> (var sv) (var sc) (msb (var sv))) (>> (var sv) (var sc) false))) (set c (ite (is_zero (var sc)) false (lsb (>> (var sv) (- (var sc) (bv 32 0x1)) false)))) (set acc (var sr)) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "zapa" 3356 0x0 (seq (set acc (bv 32 0x0)) (set p (bv 32 0x0)) (set ovc (bv 6 0x0)) (set n false) (set z true))
d "mov pm, al" 3856 0x0 (set pm (cast 3 false (cast 16 false (var acc))))
d "mov pm, ah" 3956 0x0 (set pm (cast 3 false (cast 16 false (>> (var acc) (bv 6 0x10) false))))

# shift
d "lsl acc, 1" 30ff 0x0 (seq (set sv (var acc)) (set c (lsb (>> (var sv) (bv 6 0x1f) false))) (set acc (<< (var acc) (bv 6 0x1) false)) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "asr al, 1" a0ff 0x0 (seq (set sv (cast 16 false (var acc))) (set c (lsb (>> (var sv) (bv 6 0x0) false))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (>> (var sv) (bv 6 0x1) (msb (var sv)))))) (set n (msb (cast 16 false (var acc)))) (set z (is_zero (cast 16 false (var acc)))))
d "lsrl acc, t" 2256 0x0 (seq (set sv (var acc)) (set sc (cast 32 false (& (cast 16 false (>> (var xt) (bv 6 0x10) false)) (bv 16 0x1f)))) (set sr (>> (var sv) (var sc) false)) (set c (ite (is_zero (var sc)) false (lsb (>> (var sv) (- (var sc) (bv 32 0x1)) false)))) (set acc (var sr)) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "lsl al, t" 66ff 0x0 (seq (set sv (cast 16 false (var acc))) (set sc (cast 16 false (& (cast 16 false (>> (var xt) (bv 6 0x10) false)) (bv 16 0xf)))) (set sr (<< (var sv) (var sc) false)) (set c (ite (is_zero (var sc)) false (lsb (>> (var sv) (- (bv 16 0x10) (var sc)) false)))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (var sr)))) (set n (msb (cast 16 false (var acc)))) (set z (is_zero (cast 16 false (var acc)))))

# bit test and mode bits
d "tbit @0x00, #0x0" 0040 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set tc (lsb (>> (var _val) (bv 5 0x0) false))))
d "tbit @ar0, #0x0" a040 0x0
d "clrc sxm|ovm" 0329 0x0 (seq (set sxm false) (set ovm false))
d "setc sxm|ovm" 033b 0x0 (seq (set sxm true) (set ovm true))

# loops and byte moves with a post-modified pointer
d "loopz *xar4++, #0x7700" 842c0077 0x0 (seq (set _ea (var xar4)) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set lp (is_zero (& (var _val) (bv 16 0x7700)))) (set loop (var lp)) (set xar4 (+ (var xar4) (bv 32 0x1))) (branch (var lp) (jmp (bv 32 0x0)) nop))
d "loopnz *br0--, #0x7700" af2e0077 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set lp (! (is_zero (& (var _val) (bv 16 0x7700))))) (set loop (var lp)) (set ao (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set rva (cast 16 false (var ao))) (set rv0 (cast 16 false (var xar0))) (set rvs (- (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rva) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rva) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rva) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rva) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rva) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rva) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rva) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rva) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rva) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rva) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rva) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rva) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rva) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rva) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rva) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rva) (bv 16 0x8000)) (bv 4 0xf) false)) (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rv0) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rv0) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rv0) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rv0) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rv0) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rv0) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rv0) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rv0) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rv0) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rv0) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rv0) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rv0) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rv0) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rv0) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rv0) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rv0) (bv 16 0x8000)) (bv 4 0xf) false)))) (set rvn (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rvs) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rvs) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rvs) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rvs) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rvs) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rvs) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rvs) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rvs) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rvs) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rvs) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rvs) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rvs) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rvs) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rvs) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rvs) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rvs) (bv 16 0x8000)) (bv 4 0xf) false))) (set an (| (& (var ao) (bv 32 0xffff0000)) (cast 32 false (var rvn)))) (branch (== (var arp) (bv 3 0x0)) (set xar0 (var an)) (branch (== (var arp) (bv 3 0x1)) (set xar1 (var an)) (branch (== (var arp) (bv 3 0x2)) (set xar2 (var an)) (branch (== (var arp) (bv 3 0x3)) (set xar3 (var an)) (branch (== (var arp) (bv 3 0x4)) (set xar4 (var an)) (branch (== (var arp) (bv 3 0x5)) (set xar5 (var an)) (branch (== (var arp) (bv 3 0x6)) (set xar6 (var an)) (set xar7 (var an))))))))) (branch (var lp) (jmp (bv 32 0x0)) nop))
d "movb al.lsb, *br0++" aec6 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set bs false) (set bw (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set av (cast 16 false (var acc))) (set nv (cast 16 false (ite (var bs) (cast 8 false (>> (var bw) (bv 4 0x8) false)) (cast 8 false (var bw))))) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (var nv)))) (set n (msb (var nv))) (set z (is_zero (var nv))) (set ao (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set rva (cast 16 false (var ao))) (set rv0 (cast 16 false (var xar0))) (set rvs (+ (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rva) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rva) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rva) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rva) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rva) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rva) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rva) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rva) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rva) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rva) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rva) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rva) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rva) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rva) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rva) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rva) (bv 16 0x8000)) (bv 4 0xf) false)) (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rv0) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rv0) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rv0) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rv0) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rv0) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rv0) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rv0) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rv0) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rv0) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rv0) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rv0) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rv0) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rv0) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rv0) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rv0) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rv0) (bv 16 0x8000)) (bv 4 0xf) false)))) (set rvn (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (<< (& (var rvs) (bv 16 0x1)) (bv 4 0xf) false) (<< (& (var rvs) (bv 16 0x2)) (bv 4 0xd) false)) (<< (& (var rvs) (bv 16 0x4)) (bv 4 0xb) false)) (<< (& (var rvs) (bv 16 0x8)) (bv 4 0x9) false)) (<< (& (var rvs) (bv 16 0x10)) (bv 4 0x7) false)) (<< (& (var rvs) (bv 16 0x20)) (bv 4 0x5) false)) (<< (& (var rvs) (bv 16 0x40)) (bv 4 0x3) false)) (<< (& (var rvs) (bv 16 0x80)) (bv 4 0x1) false)) (>> (& (var rvs) (bv 16 0x100)) (bv 4 0x1) false)) (>> (& (var rvs) (bv 16 0x200)) (bv 4 0x3) false)) (>> (& (var rvs) (bv 16 0x400)) (bv 4 0x5) false)) (>> (& (var rvs) (bv 16 0x800)) (bv 4 0x7) false)) (>> (& (var rvs) (bv 16 0x1000)) (bv 4 0x9) false)) (>> (& (var rvs) (bv 16 0x2000)) (bv 4 0xb) false)) (>> (& (var rvs) (bv 16 0x4000)) (bv 4 0xd) false)) (>> (& (var rvs) (bv 16 0x8000)) (bv 4 0xf) false))) (set an (| (& (var ao) (bv 32 0xffff0000)) (cast 32 false (var rvn)))) (branch (== (var arp) (bv 3 0x0)) (set xar0 (var an)) (branch (== (var arp) (bv 3 0x1)) (set xar1 (var an)) (branch (== (var arp) (bv 3 0x2)) (set xar2 (var an)) (branch (== (var arp) (bv 3 0x3)) (set xar3 (var an)) (branch (== (var arp) (bv 3 0x4)) (set xar4 (var an)) (branch (== (var arp) (bv 3 0x5)) (set xar5 (var an)) (branch (== (var arp) (bv 3 0x6)) (set xar6 (var an)) (set xar7 (var an))))))))))

# branch displacements are relative to the branch's own address
d "sb 0xac, los" 1369 0x86 (branch (|| (! (var c)) (var z)) (jmp (bv 32 0xac)) nop)
d "sb 0x88, hi" ef66 0xaa (branch (&& (var c) (! (var z))) (jmp (bv 32 0x88)) nop)
d "sb 0x6, unc" 036f 0x0 (jmp (bv 32 0x6))
d "banz 0xee00, ar0" 08000077 0x0 (seq (set t (cast 16 false (var xar0))) (set xar0 (| (& (var xar0) (bv 32 0xffff0000)) (cast 32 false (- (var t) (bv 16 0x1))))) (branch (! (is_zero (var t))) (jmp (bv 32 0xee00)) nop))

# A program address used as a branch target prints bare; one read as data is
# wrapped; MAC qualifies it with the page instead. dis2000 draws the same
# three-way distinction, and collapsing it is what a single operand kind gets
# wrong. The address itself is scaled from words to bytes, as everywhere else in
# this engine, so 0x7700 in the encoding prints as 0xee00.
d "mac p, @0x00, 0:0xee00" 00140077 0x0
d "xmac p, @0x00, *(0x7eee00)" 00840077 0x0
d "xpread @0x00, *(0x7eee00)" 00ac0077 0x0 (seq (set mv (loadw 0 16 (bv 32 0x7eee00))) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var mv)) nop)
d "lcr 0xee00" 40760077 0x0 (seq (set ra (var rpc)) (storew 0 (* (cast 32 false (var sp)) (bv 32 0x2)) (cast 16 false (var ra))) (set sp (+ (var sp) (bv 16 0x1))) (storew 0 (* (cast 32 false (var sp)) (bv 32 0x2)) (cast 16 false (>> (var ra) (bv 6 0x10) false))) (set sp (+ (var sp) (bv 16 0x1))) (set rpc (bv 32 0x2)) (jmp (bv 32 0xee00)))
d "ffc xar7, 0xee00" c0000077 0x0 (seq (set xar7 (bv 32 0x2)) (jmp (bv 32 0xee00)))

# OR ACC,#16bit<<shift sits between the AND and XOR forms of the same block and
# was the one of the three left out. MAX, MIN and SXTB take the AX select in the
# low bit; for MAX and MIN the loc16 is the low byte of the second word and the
# rest of that word is reserved, which dis2000 ignores.
d "or acc, #0x7700" 103e0077 0x0 (seq (set na (| (var acc) (cast 32 false (bv 16 0x7700)))) (set acc (var na)) (set n (msb (var na))) (set z (is_zero (var na))))
d "or acc, #0x7700 << #15" 1f3e0077 0x0 (seq (set na (| (var acc) (<< (cast 32 false (bv 16 0x7700)) (bv 6 0xf) false))) (set acc (var na)) (set n (msb (var na))) (set z (is_zero (var na))))
d "max al, @0x00" 72560077 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set mo (cast 16 false (var acc))) (set rp (&& (sle (var mo) (var _val)) (! (== (var mo) (var _val))))) (set n (&& (sle (var mo) (var _val)) (! (== (var mo) (var _val))))) (set z (== (var mo) (var _val))) (set v (|| (var v) (var rp))) (branch (var rp) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (var _val)))) nop))
d "min al, @0x00" 74560077 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set mo (cast 16 false (var acc))) (set rp (&& (sle (var _val) (var mo)) (! (== (var _val) (var mo))))) (set n (&& (sle (var mo) (var _val)) (! (== (var mo) (var _val))))) (set z (== (var mo) (var _val))) (set v (|| (var v) (var rp))) (branch (var rp) (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (var _val)))) nop))
d "sxtb al" 60ff 0x0 (seq (set acc (| (& (var acc) (bv 32 0xffff0000)) (cast 32 false (cast 16 (msb (cast 8 false (cast 16 false (var acc)))) (cast 8 false (cast 16 false (var acc))))))) (set n (msb (cast 16 false (var acc)))) (set z (is_zero (cast 16 false (var acc)))))
d "mov acc, @0x12 << #3" 03561203 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x12))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (<< (ite (var sxm) (cast 32 (msb (var _val)) (var _val)) (cast 32 false (var _val))) (bv 6 0x3) false)) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "mov acc, *-sp[2] << #15" 0356420f 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x2)))) (set _val (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set acc (<< (ite (var sxm) (cast 32 (msb (var _val)) (var _val)) (cast 32 false (var _val))) (bv 6 0xf) false)) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "dmac acc:p, @0x12, *xar7++" 4b561287 0x0
d "imacl p, *-sp[2], *xar7" 4d5642c7 0x0
d "qmacl p, *ar6%++, *xar7++" 4f56bf87 0x0
d "sbf 0x20, eq" 10ec 0x0 (branch (var z) (jmp (bv 32 0x20)) nop)
d "sbf 0x20, neq" 10ed 0x0 (branch (! (var z)) (jmp (bv 32 0x20)) nop)
d "sbf 0x20, tc" 10ee 0x0 (branch (var tc) (jmp (bv 32 0x20)) nop)
d "sbf 0x20, ntc" 10ef 0x0 (branch (! (var tc)) (jmp (bv 32 0x20)) nop)
d "bar 0x0, ar0, ar0, eq" 808f0000 0x0 (branch (== (cast 16 false (var xar0)) (cast 16 false (var xar0))) (jmp (bv 32 0x0)) nop)
d "bar 0x0, ar1, ar1, neq" c98f0000 0x0 (branch (! (== (cast 16 false (var xar1)) (cast 16 false (var xar1)))) (jmp (bv 32 0x0)) nop)

# VCU (SPRUHS1), the co-processor on F2806x and F2837x parts. The result
# register is selected by a field, and dis2000 leaves the operand off for the
# reserved numbers above VR8, which these pin. VMOV32 reaches memory through the
# ordinary loc16 byte rather than anything VCU-specific.
d "vmov32 *(0:0xee00), @0x0d" 0dbd0077 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0xd))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (storew 0 (* (cast 32 false (bv 32 0x7700)) (bv 32 0x2)) (var mv)))
d "vmov32 *(0:0xee00), ?" adbd0077 0x0
d "vmov32 ?, *(0:0xee00)" adbf0077 0x0
d "vmov32 @0x00, *(0:0xee00)" 00bf0077 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x0))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (loadw 0 32 (* (cast 32 false (bv 32 0x7700)) (bv 32 0x2)))))
d "vmov32 *(0:0x1e1e), @acc" a9bd0f0f 0x0 (storew 0 (* (cast 32 false (bv 32 0xf0f)) (bv 32 0x2)) (var acc))
d "vmov32 *(0:0x1e60), @acc" a9bd300f 0x0 (storew 0 (* (cast 32 false (bv 32 0xf30)) (bv 32 0x2)) (var acc))
d "vcflip vr0" 00a1 0x0
d "vcflip vr8" 08a1 0x0
d "vcflip" 09a1 0x0
d "vmovzi vr0, #0xc770" fce70077 0x0 (set vr0 (bv 32 0xc770))
d "vmovxi vr0, #0x770" 70e70077 0x0 (set vr0 (| (& (var vr0) (bv 32 0xffff0000)) (bv 32 0x770)))
d "vitdladdsub vr4, vr3, vr2, vr1" 31e5 0x0
d "vitdladdsub vr4, vr3, vr2, vr8" 38e5 0x0
d "vitdladdsub vr4, vr3, vr2" 3fe5 0x0
d "vgfmac4 vr0, vr1, vr7" 80e60f22 0x0
d "vgfmpy4 vr2, vr6, vr7" 80e6b720 0x0
d "vgfacc vr0, vr1, vr7" 81e60104 0x0
d "vdec vr3l" f2e60b0b 0x0 (set vr3 (| (& (var vr3) (bv 32 0xffff0000)) (cast 32 false (- (cast 16 false (var vr3)) (bv 16 0x1)))))
d "vcadd vr5, vr4, vr3, vr2" 02e5 0x0
d "vcmac vr5, vr4, vr3, vr2, vr1, vr0" 01e5 0x0
d "vccmac vr5, vr4, vr3, vr2, vr1, vr0" 0fe5 0x0
d "vitbm2 vr0" 0ce5 0x0
d "vitbm3 vr0, vr1, vr2" 0de5 0x0
# FPU32, FPU64, TMU and fast integer division; texts agree with TI dis2000 20.2.6.LTS
d "mov32 r0h, @acc" a9bd120f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var acc)) (bv 8 0x20) false)))
d "mov32 r0l, @acc" a9bd100f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff00000000)) (cast 64 false (var acc))))
d "mov32 r0h, @acc" a9bd110f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var acc)) (bv 8 0x20) false)))
d "mov32 r7h, @xt" acbd2e0f 0x0 (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var xt)) (bv 8 0x20) false)))
d "mov32 r4l, @p" abbd200f 0x0 (set r4 (| (& (var r4) (bv 64 0xffffffff00000000)) (cast 64 false (var p))))
d "mov32 r0h, *xar4++" 84bd120f 0x0 (seq (set _ea (var xar4)) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (bv 8 0x20) false))) (set xar4 (+ (var xar4) (bv 32 0x2))))
d "mov32 @acc, r0h" a9bf120f 0x0 (seq (set acc (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set n (msb (var acc))) (set z (is_zero (var acc))))
d "mov32 @xar5, r7h" a5bf2e0f 0x0 (set xar5 (cast 32 false (>> (var r7) (bv 8 0x20) false)))
d "movst0 lvf,ni,zi,ci" 69ad 0x0 (seq nop (set v (|| (var lvf) false)) (set lvf false) (set n (|| false (var ni))) (set z (|| false (var zi))))
d "mpyf32 r3h, r7h, r2h || mov32 *-sp[30], r7h" 05e05edf 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x1e)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "addf32 r3h, r7h, r1h || mov32 @0x1f, r2h" 13e01fda 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x1f))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "subf32 r5h, r7h, r4h || mov32 *-sp[38], r2h" 29e066ea 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "mpyf64 r6, r3, r5 || mov32 @0x14, r6h" 4ae014f6 0x0 (seq (set xa (var r3)) (set xb (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x14))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r5, r1, r2 || mov32 *-sp[5], r3h" 54e0456b 0x0 (seq (set xa (var r1)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x5)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r7, r6, r2 || mov32 *-sp[48], r0h" 65e070b8 0x0 (seq (set xa (var r6)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x30)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "mpyf64 r6, r7, r4 || mov32 *-sp[2], r5l" 89e042f5 0x0 (seq (set xa (var r7)) (set xb (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x2)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r5))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r5, r7, r1 || mov32 *+xar1[2], r6l" 93e0d1ee 0x0 (seq (set xa (var r7)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (+ (var xar1) (bv 32 0x2))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r6))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r6, r6, r3 || mov32 *sp++, r5l" a7e0bdb5 0x0 (seq (set xa (var r6)) (set xb (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (var sp))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r5))) (set sp (+ (var sp) (bv 16 0x2))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "mov32 *+xar1[3], stf" 00e2d9dd 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x3))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (| (| (| (| (| (| (| (| (| (ite (var shdws) (bv 32 0x80000000) (bv 32 0x0)) (ite (var lvf) (bv 32 0x1) (bv 32 0x0))) (ite (var luf) (bv 32 0x2) (bv 32 0x0))) (ite (var nf) (bv 32 0x4) (bv 32 0x0))) (ite (var zf) (bv 32 0x8) (bv 32 0x0))) (ite (var ni) (bv 32 0x10) (bv 32 0x0))) (ite (var zi) (bv 32 0x20) (bv 32 0x0))) (ite (var tf) (bv 32 0x40) (bv 32 0x0))) (ite (var rnd32) (bv 32 0x200) (bv 32 0x0))) (ite (var rnd64) (bv 32 0x400) (bv 32 0x0)))))
d "mov32 *+xar4[2], r3l" 02e2d4eb 0x0 (seq (set _ea (+ (var xar4) (bv 32 0x2))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r3))))
d "mov32 *+xar2[ar0], r5h" 03e29295 0x0 (seq (set _ea (+ (var xar2) (cast 32 false (cast 16 false (var xar0))))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r5) (bv 8 0x20) false))))
d "mov16 *-sp[28], r5h" 13e25c05 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1c)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 16 false (cast 32 false (>> (var r5) (bv 8 0x20) false)))))
d "f32dtof64 r1, *+xar6[0]" 21e2c601 0x0 (seq (set _ea (+ (var xar6) (bv 32 0x0))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x2))) (bv 32 0x2)) (var xa)) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r1 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))))))
d "movd32 r7h, *+xar5[5]" 23e2ed2f 0x0 (seq (set _ea (+ (var xar5) (bv 32 0x5))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x2))) (bv 32 0x2)) (var mv)) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))))
d "movdd32 r0l, @0x36" 42e23618 0x0
d "movdd32 r6h, @0x28" 43e22866 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x28))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x4))) (bv 32 0x2)) (var mv)) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))))
d "macf32 r0h, r2h, *+xar1[1], *xar7++" 50e2c990 0x0
d "mpy2pif32 r2h, r4h" 70e22200 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dp (*. rne (fconvert ieee754-bin64 rne (var fa)) (float 1 (bv 64 0x401921fb54442d18) ))) (set dx (! (<. (fabs (var dp)) (float 1 (bv 64 0x47effffff0000000) )))) (set dv (ite (var dx) (ite (is_fneg (var dp)) (bv 32 0xff800000) (bv 32 0x7f800000)) (fbits (fconvert ieee754-bin32 rne (var dp))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (var dx))))
d "div2pif32 r0h, r4h" 71e22000 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dp (*. rne (fconvert ieee754-bin64 rne (var fa)) (float 1 (bv 64 0x3fc45f306dc9c883) ))) (set dx (&& (! (is_fzero (var dp))) (<. (fabs (var dp)) (float 1 (bv 64 0x3810000000000000) )))) (set dv (ite (var dx) (bv 32 0x0) (fbits (fconvert ieee754-bin32 rne (var dp))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set luf (|| (var luf) (var dx))))
d "log2f32 r7h, r4h" 72e22700 0x0
d "iexp2f32 r0h, r1h" 73e20800 0x0
d "divf32 r0h, r6h, r0h" 74e23000 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set za (is_fzero (var fa))) (set zb (is_fzero (var fb))) (set ia (is_inf (var fa))) (set ib (is_inf (var fb))) (set na (&& (! (var za)) (! (var ia)))) (set fin (&& (var na) (&& (! (var zb)) (! (var ib))))) (set dq (/. rne (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set dov (&& (var fin) (! (<. (fabs (var dq)) (float 1 (bv 64 0x47f0000000000000) ))))) (set dun (&& (var fin) (<. (fabs (var dq)) (float 1 (bv 64 0x3810000000000000) )))) (set dv (ite (var za) (bv 32 0x0) (ite (|| (var ia) (var zb)) (ite (^^ (is_fneg (var fa)) (is_fneg (var fb))) (bv 32 0xff800000) (bv 32 0x7f800000)) (ite (var ib) (bv 32 0x0) (ite (var dun) (bv 32 0x0) (ite (var dov) (ite (^^ (is_fneg (var fa)) (is_fneg (var fb))) (bv 32 0xff800000) (bv 32 0x7f800000)) (fbits (/. rne (var fa) (var fb))))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (|| (|| (&& (var za) (var zb)) (&& (var ia) (! (var ib)))) (|| (&& (var na) (var zb)) (var dov))))) (set luf (|| (var luf) (|| (var ib) (var dun)))))
d "sqrtf32 r3h, r2h" 77e21300 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dneg (is_fneg (var fa))) (set dinf (&& (is_inf (var fa)) (! (var dneg)))) (set dv (ite (var dneg) (bv 32 0x0) (ite (var dinf) (bv 32 0x7f800000) (fbits (fsqrt rne (var fa)))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (|| (var dneg) (var dinf)))))
d "sinpuf32 r2h, r1h" 78e20a00 0x0
d "cospuf32 r3h, r7h" 79e23b00 0x0
d "atanpuf32 r5h, r1h" 7ae20d00 0x0
d "quadf32 r5h, r7h, r3h, r4h" 7ce2fd08 0x0
d "mov32 stf, *-sp[53]" 80e27500 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x35)))) (set sw (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) nop (set lvf (! (is_zero (& (var sw) (bv 32 0x1))))) (set luf (! (is_zero (& (var sw) (bv 32 0x2))))) (set nf (! (is_zero (& (var sw) (bv 32 0x4))))) (set zf (! (is_zero (& (var sw) (bv 32 0x8))))) (set ni (! (is_zero (& (var sw) (bv 32 0x10))))) (set zi (! (is_zero (& (var sw) (bv 32 0x20))))) (set tf (! (is_zero (& (var sw) (bv 32 0x40))))) (set rnd32 (! (is_zero (& (var sw) (bv 32 0x200))))) (set rnd64 (! (is_zero (& (var sw) (bv 32 0x400))))))
d "ui32tof32 r5h, *-sp[31]" 84e25f05 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1f)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "ui32tof64 r1, *-sp[1]" 85e24101 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (fbits (fcast_float ieee754-bin64 rne (var xa)))))
d "i32tof32 r7h, *-sp[3]" 88e24307 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x3)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "i32tof64 r3, *arp0" 89e2b003 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r3 (fbits (fcast_sfloat ieee754-bin64 rne (var xa)))) (set arp (bv 3 0x0)))
d "f32tof64 r3, @0x12" 8ce21203 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x12))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r3 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))))))
d "mov32 r2l, *+xar7[1]" 98e2cfc2 0x0
d "mov32 r6h, *-sp[38], unc" aee2660e 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (branch true (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) nop))
d "ui16tof32 r7h, *arp7" c4e2b707 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set xa (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))) (set arp (bv 3 0x7)))
d "i16tof32 r2h, *-sp[49]" c8e27102 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x31)))) (set xa (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "mpyf32 r1h, r7h, r1h || mov32 r1h, *+xar7[7]" 03e3ffc9 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (+ (var xar7) (bv 32 0x7))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "addf32 r7h, r2h, r2h || mov32 r3h, *--xar4" 14e38cbb 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set xar4 (- (var xar4) (bv 32 0x2))) (set _ea (var xar4)) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "subf32 r4h, r4h, r3h || mov32 r7h, *-sp[22]" 27e35627 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x16)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "macf32 r3h, r2h, r0h, r5h, r0h || mov32 r2h, *-sp[40]" 31e36842 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x28)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (*. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false))))
d "mpyf64 r0, r3, r2 || mov32 r1h, *-sp[28]" 44e35cc1 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x1c)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r7, r5, r6 || mov32 r4h, @0x35" 5de3357c 0x0 (seq (set xa (var r5)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x35))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r4, r4, r2 || mov32 r0h, *+xar7[2]" 65e3d720 0x0 (seq (set xa (var r4)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (+ (var xar7) (bv 32 0x2))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r4 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "macf64 r3, r2, r0, r7, r6 || mov32 r1h, @0x0e" 7de30ec1 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r7)) (set yb (var r6)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0xe))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r0 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "mpyf64 r0, r6, r4 || mov32 r2l, @0x3c" 89e33c82 0x0 (seq (set xa (var r6)) (set xb (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x3c))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r3, r4, r2 || mov32 r6l, *-sp[38]" 95e3661e 0x0 (seq (set xa (var r4)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r1, r0, r2 || mov32 r2l, @0x33" a4e3330a 0x0 (seq (set xa (var r0)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x33))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r1 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "macf64 r3, r2, r0, r6, r4 || mov32 r5l, @0x20" b9e32085 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r4)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x20))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r0 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "macf32 r7h, r6h, r4h, r1h, r2h || mov32 r2h, @0x1b" c4e31b62 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x1b))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (*. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false))))
d "macf64 r7, r6, r1, r6, r1 || mov32 r6h, @0x22" d3e3228e 0x0 (seq (set xa (var r7)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r1)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x22))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r1 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "macf64 r7, r6, r5, r2, r5 || mov32 r5l, *-sp[11]" eae34bad 0x0 (seq (set xa (var r7)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r2)) (set yb (var r5)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0xb)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r5 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "restore" 62e5 0x0 (seq (set sw (var stfs)) nop (set lvf (! (is_zero (& (var sw) (bv 32 0x1))))) (set luf (! (is_zero (& (var sw) (bv 32 0x2))))) (set nf (! (is_zero (& (var sw) (bv 32 0x4))))) (set zf (! (is_zero (& (var sw) (bv 32 0x8))))) (set ni (! (is_zero (& (var sw) (bv 32 0x10))))) (set zi (! (is_zero (& (var sw) (bv 32 0x20))))) (set tf (! (is_zero (& (var sw) (bv 32 0x40))))) (set rnd32 (! (is_zero (& (var sw) (bv 32 0x200))))) (set rnd64 (! (is_zero (& (var sw) (bv 32 0x400))))) (set r0 (var r0s)) (set r1 (var r1s)) (set r2 (var r2s)) (set r3 (var r3s)) (set r4 (var r4s)) (set r5 (var r5s)) (set r6 (var r6s)) (set r7 (var r7s)) (set shdws false))
d "zeroa" 63e5 0x0 (seq (set r0 (bv 64 0x0)) (set r1 (bv 64 0x0)) (set r2 (bv 64 0x0)) (set r3 (bv 64 0x0)) (set r4 (bv 64 0x0)) (set r5 (bv 64 0x0)) (set r6 (bv 64 0x0)) (set r7 (bv 64 0x0)))
d "subc4ui32 r2h, r1h, r3h" 64e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set zi false) (set lvf (|| (var lvf) (is_zero (var dd)))) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set zi (is_zero (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h" 65e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set zi false) (set lvf (|| (var lvf) (is_zero (var dd)))) (set dt (- (+ (<< (cast 65 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 65 0x1) (bv 65 0x0))) (cast 65 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 64 0x1) (bv 64 0x0))) (cast 64 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 64 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 65 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 65 0x1) (bv 65 0x0))) (cast 65 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 64 0x1) (bv 64 0x0))) (cast 64 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 64 0x1)))) (set dr (var dq)) (set zi (is_zero (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "subc3f64 r2, r1, r3" 66e5 0x0
d "absi32div32 r2h, r1h, r3h" 68e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 32 0x80000000)) (== (var dd) (bv 32 0x80000000))))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dd)) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "absi32div32u r2h, r1h" 69e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 32 0x80000000)))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "negi32div32 r1h, r2h" 6ae5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "enegi32div32 r1h, r2h, r3h" 6be5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 32 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "mnegi32div32 r1h, r2h, r3h" 6ce5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 32 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "testtf tf" 8ae5 0x0 (set tf (var tf))
d "zero r5" 95e5 0x0 (set r5 (bv 64 0x0))
d "cmpf32 r1h, #0.0" a1e5 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set xb (bv 32 0x0)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "absi64div32 r2h, r1h:r0h, r3h" a8e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 64 0x8000000000000000)) (== (var dd) (bv 32 0x80000000))))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dd)) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "absi64div32u r2h, r1h:r0h" a9e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 64 0x8000000000000000)))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "negi64div32 r1h:r0h, r2h" aae5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "enegi64div32 r1h:r0h, r2h, r3h" abe5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "mnegi64div32 r1h:r0h, r2h, r3h" ace5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false))))
d "cmpf64 r2, #0.0" b2e5 0x0 (seq (set xa (var r2)) (set xb (bv 64 0x0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "absi64div64 r2h:r4h, r1h:r0h, r3h:r5h" b8e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 64 0x8000000000000000)) (== (var dd) (bv 64 0x8000000000000000))))) (set dr (bv 64 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dd) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dd))) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "absi64div64u r2h:r4h, r1h:r0h" b9e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 64 0x8000000000000000)))) (set dr (bv 64 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "negi64div64 r1h:r0h, r2h:r4h" bae5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "enegi64div64 r1h:r0h, r2h:r4h, r3h:r5h" bbe5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "mnegi64div64 r1h:r0h, r2h:r4h, r3h:r5h" bce5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false))))
d "predivf64 r0h, r2, r1, r3" bee5 0x0
d "postdivf64 r1, r0h" bfe5 0x0
d "setflg luf=0,zf=0,ni=1,zi=0,rndq32=1,rndf32=1" 19e695d7 0x0 (seq nop (set luf false) (set zf false) (set ni true) (set zi false) (set rnd32 true))
d "save nf=0,zf=1,ni=1,zi=0,tf=1,rndq16=1" 47e6dae1 0x0 (seq (set stfs (| (| (| (| (| (| (| (| (| (ite (var shdws) (bv 32 0x80000000) (bv 32 0x0)) (ite (var lvf) (bv 32 0x1) (bv 32 0x0))) (ite (var luf) (bv 32 0x2) (bv 32 0x0))) (ite (var nf) (bv 32 0x4) (bv 32 0x0))) (ite (var zf) (bv 32 0x8) (bv 32 0x0))) (ite (var ni) (bv 32 0x10) (bv 32 0x0))) (ite (var zi) (bv 32 0x20) (bv 32 0x0))) (ite (var tf) (bv 32 0x40) (bv 32 0x0))) (ite (var rnd32) (bv 32 0x200) (bv 32 0x0))) (ite (var rnd64) (bv 32 0x400) (bv 32 0x0)))) (set r0s (var r0)) (set r1s (var r1)) (set r2s (var r2)) (set r3s (var r3)) (set r4s (var r4)) (set r5s (var r5)) (set r6s (var r6)) (set r7s (var r7)) nop (set nf false) (set zf true) (set ni true) (set zi false) (set tf true) (set shdws true))
d "f64toi32 r0h, r1" 84e60800 0x0 (seq (set xa (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_sfloat ieee754-bin64 rtz (bv 32 0x7fffffff)) (var fr)) (bv 32 0x7fffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin64 rtz (bv 32 0x80000000))) (bv 32 0x80000000) (fcast_sint 32 rtz (var fr))))) (bv 8 0x20) false))))
d "f64toi64 r3, r5" 84e62b80 0x0 (seq (set xa (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r3 (ite (<. (fcast_sfloat ieee754-bin64 rtz (bv 64 0x7fffffffffffffff)) (var fr)) (bv 64 0x7fffffffffffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin64 rtz (bv 64 0x8000000000000000))) (bv 64 0x8000000000000000) (fcast_sint 64 rtz (var fr))))))
d "i32tof64 r2, r5h" 85e62a00 0x0 (seq (set xa (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set r2 (fbits (fcast_sfloat ieee754-bin64 rne (var xa)))))
d "i64tof64 r6, r7" 85e63e80 0x0 (seq (set xa (var r7)) (set r6 (fbits (fcast_sfloat ieee754-bin64 rne (var xa)))))
d "f64toui32 r5h, r3" 86e61d00 0x0 (seq (set xa (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_float ieee754-bin64 rtz (bv 32 0xffffffff)) (var fr)) (bv 32 0xffffffff) (ite (<. (var fr) (fcast_float ieee754-bin64 rtz (bv 32 0x0))) (bv 32 0x0) (fcast_int 32 rtz (var fr))))) (bv 8 0x20) false))))
d "f64toui64 r1, r4" 86e62180 0x0 (seq (set xa (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (ite (<. (fcast_float ieee754-bin64 rtz (bv 64 0xffffffffffffffff)) (var fr)) (bv 64 0xffffffffffffffff) (ite (<. (var fr) (fcast_float ieee754-bin64 rtz (bv 64 0x0))) (bv 64 0x0) (fcast_int 64 rtz (var fr))))))
d "ui32tof64 r0, r1h" 87e60800 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set r0 (fbits (fcast_float ieee754-bin64 rne (var xa)))))
d "ui64tof64 r0, r4" 87e62080 0x0 (seq (set xa (var r4)) (set r0 (fbits (fcast_float ieee754-bin64 rne (var xa)))))
d "f32toi32 r1h, r6h" 88e63100 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 32 0x7fffffff)) (var fr)) (bv 32 0x7fffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 32 0x80000000))) (bv 32 0x80000000) (fcast_sint 32 rtz (var fr))))) (bv 8 0x20) false))))
d "i32tof32 r1h, r6h" 89e63100 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "f32toui32 r1h, r4h" 8ae62100 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 32 0xffffffff)) (var fr)) (bv 32 0xffffffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 32 0x0))) (bv 32 0x0) (fcast_int 32 rtz (var fr))))) (bv 8 0x20) false))))
d "ui32tof32 r4h, r2h" 8be61400 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "f32toi16 r6h, r0h" 8ce60600 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 (msb (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr))))) (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr)))))) (bv 8 0x20) false))))
d "f32toi16r r2h, r7h" 8ce63a80 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rne (var fa))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 (msb (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr))))) (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr)))))) (bv 8 0x20) false))))
d "i16tof32 r0h, r5h" 8de62800 0x0 (seq (set xa (cast 16 false (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "f32toui16 r7h, r7h" 8ee63f00 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 16 0xffff)) (var fr)) (bv 16 0xffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 16 0x0))) (bv 16 0x0) (fcast_int 16 rtz (var fr)))))) (bv 8 0x20) false))))
d "f32toui16r r2h, r5h" 8ee62a80 0x0 (seq (set xa (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rne (var fa))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 16 0xffff)) (var fr)) (bv 16 0xffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 16 0x0))) (bv 16 0x0) (fcast_int 16 rtz (var fr)))))) (bv 8 0x20) false))))
d "ui16tof32 r2h, r1h" 8fe60a00 0x0 (seq (set xa (cast 16 false (cast 32 false (>> (var r1) (bv 8 0x20) false)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))))
d "f64tof32 r1h, r4" 90e62100 0x0 (seq (set xa (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set xr (fbits (fconvert ieee754-bin32 (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "f32tof64 r4, r4h" 91e62400 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r4 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))))))
d "eisqrtf32 r0h, r5h" 92e62800 0x0
d "eisqrtf64 r6, r4" 92e62680 0x0
d "einvf32 r4h, r0h" 93e60400 0x0
d "einvf64 r4, r6" 93e63480 0x0
d "cmpf32 r3h, r2h" 94e61300 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "absf32 r1h, r0h" 95e60100 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xr (& (var xa) (bv 32 0x7fffffff))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var xr)) (bv 8 0x20) false))) (set zf (is_zero (& (var xr) (bv 32 0x7f800000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 32 0x7f800000)))))))
d "maxf32 r3h, r7h" 96e63b00 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "minf32 r3h, r3h" 97e61b00 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "cmpf64 r0, r7" 98e63800 0x0 (seq (set xa (var r0)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "absf64 r6, r5" 99e62e00 0x0 (seq (set xa (var r5)) (set xr (& (var xa) (bv 64 0x7fffffffffffffff))) (set r6 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))))))
d "maxf64 r1, r0" 9ae60100 0x0 (seq (set xa (var r1)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r1 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))))
d "minf64 r5, r2" 9be61500 0x0 (seq (set xa (var r5)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))))
d "maxf32 r4h, r5h || mov32 r0h, r7h" 9ce62cae 0x0 (seq (set pd (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))) (branch (var mt) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var pd)) (bv 8 0x20) false))) nop))
d "minf32 r3h, r1h || mov32 r5h, r2h" 9de64bb5 0x0 (seq (set pd (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))) (branch (var mt) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (var pd)) (bv 8 0x20) false))) nop))
d "maxf64 r1, r1 || mov64 r3, r2" 9ee6c9c4 0x0 (seq (set pd (var r2)) (set xa (var r1)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r1 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))) (branch (var mt) (set r3 (var pd)) nop))
d "minf64 r5, r7 || mov64 r3, r5" 9fe6fd9a 0x0 (seq (set pd (var r5)) (set xa (var r5)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))) (branch (var mt) (set r3 (var pd)) nop))
d "negf32 r0h, r1h, geq" a3e68817 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set xr (ite (! (var nf)) (^ (var xa) (bv 32 0x80000000)) (var xa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var xr)) (bv 8 0x20) false))))
d "negf64 r5, r5" b7e6adb9 0x0
d "mov32 r6h, r4h, lu" cce666ec 0x0 (seq (set mv (cast 32 false (>> (var r4) (bv 8 0x20) false))) (branch (var luf) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) nop))
d "mov64 r4, r0" d6e6c471 0x0
d "swapf r3, r1, unc" eee68be1 0x0 (branch true (seq (set sa (var r3)) (set r3 (var r1)) (set r1 (var sa))) nop)
d "fracf32 r0h, r4h" f1e62000 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set xr (fbits (-. rne (var fa) (fround rtz (var fa))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "fracf64 r6, r5" f1e62e80 0x0 (seq (set xa (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set xr (fbits (-. rne (var fa) (fround rtz (var fa))))) (set r6 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))))
d "mov32 r0h, r5l" f4e62800 0x0
d "mov32 r7l, r3h" f5e61f00 0x0
d "mpyf32 r0h, r6h, r0h" 00e730a8 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "addf32 r3h, r3h, r3h" 10e7dbde 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "subf32 r6h, r4h, r5h" 20e766b3 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "mpyf32 r7h, r7h, r5h || addf32 r7h, r7h, r6h" 43e77f7f 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (+. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false))))
d "mpyf32 r2h, r3h, r1h || subf32 r5h, r6h, r4h" 52e75a6a 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (-. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false))))
d "mpyf64 r2, r7, r1" 80e77afa 0x0 (seq (set xa (var r7)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r2 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r6, r0, r1" 90e746ac 0x0 (seq (set xa (var r0)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r3, r6, r3" a0e7f374 0x0 (seq (set xa (var r6)) (set xb (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "mpyf64 r0, r7, r7 || addf64 r6, r6, r0" cce7f86d 0x0 (seq (set xa (var r7)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r0)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (+. rne (var ga) (var gb))) (set gr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r6 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "mpyf64 r0, r0, r0 || subf64 r5, r6, r4" dee7006a 0x0 (seq (set xa (var r0)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r4)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (-. rne (var ga) (var gb))) (set gr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r5 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr)))))
d "moviz r0, #0x67c5" 03e8283e 0x0 (set r0 (bv 64 0x67c5000000000000))
d "movxi r3h, #0x2c77" 09e8bb63 0x0 (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (| (& (cast 32 false (>> (var r3) (bv 8 0x20) false)) (bv 32 0xffff0000)) (bv 32 0x2c77))) (bv 8 0x20) false)))
d "cmpf32 r0h, #0x34dc" 11e8e0a6 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xb (bv 32 0x34dc0000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "maxf32 r0h, #0x7914" 23e8a0c8 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xb (bv 32 0x79140000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "minf32 r3h, #0x63ce" 33e8731e 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (bv 32 0x63ce0000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))))
d "mpyf32 r7h, #0x4b81, r7h" 52e87fe0 0x0 (seq (set xa (bv 32 0x4b810000)) (set xb (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "addf32 r0h, #0x6187, r0h" 98e8c061 0x0 (seq (set xa (bv 32 0x61870000)) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "subf32 r2h, #0xc674, r0h" f1e8029d 0x0 (seq (set xa (bv 32 0xc6740000)) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))))
d "movix r7l, #0x22cb" 01e95f16 0x0 (set r7 (| (& (var r7) (bv 64 0xffffffff00000000)) (cast 64 false (| (& (cast 32 false (var r7)) (bv 32 0xffff)) (bv 32 0x22cb0000)))))
d "movxi r4l, #0xcc36" 0ee9b461 0x0 (set r4 (| (& (var r4) (bv 64 0xffffffff00000000)) (cast 64 false (| (& (cast 32 false (var r4)) (bv 32 0xffff0000)) (bv 32 0xcc36)))))
d "cmpf64 r7, #0xa9e4" 15e9274f 0x0 (seq (set xa (var r7)) (set xb (bv 64 0xa9e4000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))))
d "maxf64 r7, #0x9d41" 24e90fea 0x0 (seq (set xa (var r7)) (set xb (bv 64 0x9d41000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r7 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))))
d "minf64 r5, #0x884f" 34e97d42 0x0 (seq (set xa (var r5)) (set xb (bv 64 0x884f000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))))
d "mpyf64 r6, #0x8675, r0" 61e9469d 0x0 (seq (set xa (bv 64 0x8675000000000000)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "addf64 r1, #0x8516, r1" a1e98945 0x0 (seq (set xa (bv 64 0x8516000000000000)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r1 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "subf64 r5, #0x55a9, r7" d5e97d6a 0x0 (seq (set xa (bv 64 0x55a9000000000000)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))))
d "push rb" f0ff 0x0 (seq (set _ea (cast 32 false (var sp))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var rb)) (set sp (+ (var sp) (bv 16 0x2))))
d "pop rb" f1ff 0x0 (seq (set sp (- (var sp) (bv 16 0x2))) (set _ea (cast 32 false (var sp))) (set rb (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))))
d "mov32 r2h, @0x34" a6e23412 0x0
d "setflg" 00e60000 0x0 nop
d "movst0 #0" 00ad 0x0 nop
# VCU parallel forms, second-word operands, FFT and CRC; texts agree with TI dis2000 20.2.6.LTS
d "vcfft2 vr7, vr6, vr4, vr2, vr1, vr0, #0x1" 31a1 0x0
d "vcfft3 vr5, vr4, vr3, vr2, vr0, #0x1" 33a1 0x0
d "vcfft4 vr4, vr2, vr1, vr0, #0x0" 34a1 0x0
d "vcfft8 vr3, vr2, #0x0" 36a1 0x0
d "vcfft9 vr5, vr4, vr3, vr2, vr1, vr0, #0x1" 39a1 0x0
d "vcfft10 vr7, vr6, vr3, vr2, vr1, vr0, #0x0" 3aa1 0x0
d "vmov32 *+xar6[5], vr1" 04e2ee01 0x0 (seq (set _ea (+ (var xar6) (bv 32 0x5))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var vr1)))
d "vmov32 @0x00" 05e20002 0x0
d "vmov32 *+xar0[7], vcrc" 06e2f800 0x0 (seq (set _ea (+ (var xar0) (bv 32 0x7))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var vcrc)))
d "vmov32 *+xar6[3], vcrcpoly" 06e2de01 0x0 (seq (set _ea (+ (var xar6) (bv 32 0x3))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var vcrcpoly)))
d "vmov32 *+xar1[6], vcrcsize" 06e2f102 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x6))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var vcrcsize)))
d "vcmpy vr3, vr2, vr1, vr0 || vmov32 *xar4++, vr7" 07e28407 0x0
d "vccmpy vr3, vr2, vr1, vr0 || vmov32 *arp2, vr5" 07e2b215 0x0
d "vcfft2 vr7, vr6, vr4, vr2, vr1, vr0, #0x1 || vmov32 *+xar5[3], vr1" 07e2dd21 0x0
d "vcfft5 vr5, vr4, vr3, vr2, vr1, vr0, #0x1 || vmov32 *+xar6[1], vr1" 07e2ce23 0x0
d "vcfft6 vr3, vr2, vr1, vr0, #0x1 || vmov32 *-sp[26], vr1" 07e25a25 0x0
d "vcfft8 vr3, vr2, #0x0 || vmov32 *+xar3[4], vr4" 07e2e326 0x0
d "vcfft9 vr5, vr4, vr3, vr2, vr1, vr0, #0x1 || vmov32 @0x22, vr5" 07e22229 0x0
d "vitdladdsub vr4, vr3, vr2, vr2 || vmov32 *+xar4[2], vr3" 08e2d432 0x0
d "vitdhaddsub vr4, vr3, vr2, vr7 || vmov32 *+xar2[1], vr5" 09e2ca57 0x0
d "vitdlsubadd vr4, vr3, vr2, vr5 || vmov32 *arp3, vr2" 0ae2b325 0x0
d "vitdhsubadd vr4, vr3, vr2, vr5 || vmov32 *--xar5, vr1" 0be28d15 0x0
d "vtrace *--xar6, vr0, vt0, vt1" 0ce28e00 0x0
d "vmov32 @0x3a, vstatus" 0de23a00 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x3a))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var vstatus)))
d "vmov32 *-sp[1], vsm25:vsm24" 0ee2410c 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (append (var vsm25) (var vsm24))))
d "vmov16 *0++, vr0l" 18e2bb00 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 16 false (var vr0))) (set ao (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set an (+ (var ao) (cast 32 false (cast 16 false (var xar0))))) (branch (== (var arp) (bv 3 0x0)) (set xar0 (var an)) (branch (== (var arp) (bv 3 0x1)) (set xar1 (var an)) (branch (== (var arp) (bv 3 0x2)) (set xar2 (var an)) (branch (== (var arp) (bv 3 0x3)) (set xar3 (var an)) (branch (== (var arp) (bv 3 0x4)) (set xar4 (var an)) (branch (== (var arp) (bv 3 0x5)) (set xar5 (var an)) (branch (== (var arp) (bv 3 0x6)) (set xar6 (var an)) (set xar7 (var an))))))))))
d "vmov16 *-sp[15], vr8h" 18e24f18 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0xf)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 16 false (>> (var vr8) (bv 8 0x10) false))))
d "vmovd32 vr4, *+xar5[3]" 24e2dd04 0x0 (seq (set _ea (+ (var xar5) (bv 32 0x3))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vr4 (var mv)) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x2))) (bv 32 0x2)) (var mv)))
d "vcmac vr7, vr6, vr5, vr4, *-sp[28], *xar7++" 51e25c00 0x0
d "vitbm2 vr0, *+xar0[1]" 80e2c801 0x0
d "vitstage || vitbm2 vr0, @0x38" 80e23802 0x0
d "vmov32 vsm47:vsm46, *xar5++" 80e28537 0x0 (seq (set _ea (var xar5)) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vsm47 (cast 16 false (>> (var mv) (bv 8 0x10) false))) (set vsm46 (cast 16 false (var mv))) (set xar5 (+ (var xar5) (bv 32 0x2))))
d "vinc vr1l || vmov32 vr1, *+xar3[1]" 81e2cb09 0x0 (seq (set _ea (+ (var xar3) (bv 32 0x1))) (set vr1 (| (& (var vr1) (bv 32 0xffff0000)) (cast 32 false (+ (cast 16 false (var vr1)) (bv 16 0x1))))) (set vr1 (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))))
d "vdec vr2l || vmov32 vr7, @0x3f" 81e23f7a 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x3f))) (set vr2 (| (& (var vr2) (bv 32 0xffff0000)) (cast 32 false (- (cast 16 false (var vr2)) (bv 16 0x1))))) (set vr7 (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))))
d "vmov32 vstatus, @0x19" b0e21900 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x19))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vstatus (var mv)))
d "vtrace vr1, vr0, vt0, vt1 || vmov32 vt0, @0x28" b0e22801 0x0
d "vcfft3 vr5, vr4, vr3, vr2, vr0, #0x1 || vmov32 vr5, *-sp[19]" b0e25303 0x0
d "vcfft4 vr4, vr2, vr1, vr0, #0x0 || vmov32 vr7, *+xar0[7]" b0e2f804 0x0
d "vcfft7 vr1, vr0, #0x0 || vmov32 vr2, *-sp[19]" b0e25306 0x0
d "vcfft10 vr7, vr6, vr3, vr2, vr1, vr0, #0x0 || vmov32 vr0, *+xar0[2]" b0e2d008 0x0
d "vpack4 vr4, *-sp[48], #0x1" b1e27011 0x0
d "vgfmpy4 vr0, vr6, vr2 || vmov32 vr0, *xar1++" b4e28132 0x0
d "vgfacc vr2, vr1, vr7 || vmov32 vr0, *+xar0[ar0]" b6e29048 0x0
d "vgfmac4 vr1, vr6, vr4 || vpack4 vr0, *+xar1[7], #0x1" bbe2f934 0x0
d "vcrc32l_1 *+xar5[1]" c1e2cd00 0x0 (seq (set _ea (+ (var xar5) (bv 32 0x1))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffffff)) (<< (var cd) (bv 8 0x18) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0x0)) (var cr))))
d "vcrc32h_1 @0x36" c2e23600 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x36))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffffff)) (<< (var cd) (bv 8 0x18) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x4c11db7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0x0)) (var cr))))
d "vgfinit *+xar6[7]" c5e2fe00 0x0
d "vsminit *+xar3[1]" c5e2cb01 0x0
d "vitbm3 vr0l, vr1l, *+xar4[ar1]" c5e29c02 0x0
d "vitstage || vmov16 vr0l, *-sp[55]" c5e27703 0x0
d "vmov16 vr5l, @0x12" c9e21205 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x12))) (set mv (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vr5 (| (& (var vr5) (bv 32 0xffff0000)) (cast 32 false (var mv)))))
d "vmov16 vr2h, @0x20" c9e22012 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x20))) (set mv (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vr2 (| (& (var vr2) (bv 32 0xffff)) (<< (cast 32 false (var mv)) (bv 8 0x10) false))))
d "vcrc8l_1 *+xar1[2]" cbe2d100 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x2))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xff)) (<< (var cd) (bv 8 0x0) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffffff00)) (var cr))))
d "vcrc24l_1 @0x18" cbe21801 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x18))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffff)) (<< (var cd) (bv 8 0x10) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xff000000)) (var cr))))
d "vcrc24h_1 *+xar0[ar0]" cbe29002 0x0 (seq (set _ea (+ (var xar0) (cast 32 false (cast 16 false (var xar0))))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffff)) (<< (var cd) (bv 8 0x10) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x800000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)) (bv 32 0x5d6dcb)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xff000000)) (var cr))))
d "vcrc32p2l_1 *+xar1[6]" cbe2f103 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x6))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffffff)) (<< (var cd) (bv 8 0x18) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0x0)) (var cr))))
d "vcrc32p2h_1 @0x35" cbe23504 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x35))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffffffff)) (<< (var cd) (bv 8 0x18) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80000000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)) (bv 32 0x1edc6f41)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffffffff)))) (set vcrc (| (& (var vcrc) (bv 32 0x0)) (var cr))))
d "vmov16 vcrcdsize, *-sp[45]" cbe26d05 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x2d)))) (set mv (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vcrcsize (| (& (var vcrcsize) (bv 32 0xfffffff8)) (& (<< (cast 32 false (var mv)) (bv 8 0x0) false) (bv 32 0x7)))))
d "vcrcl *-sp[38]" cbe26606 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (set gd (+ (& (var vcrcsize) (bv 32 0x7)) (bv 32 0x1))) (set gw (+ (& (>> (var vcrcsize) (bv 8 0x10) false) (bv 32 0x1f)) (bv 32 0x1))) (set gm (cast 32 false (- (<< (bv 64 0x1) (var gw) false) (bv 64 0x1)))) (set gp (& (var vcrcpoly) (var gm))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (& (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (>> (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (- (bv 32 0x8) (var gd)) false) (var cd)) (- (<< (bv 32 0x1) (var gd) false) (bv 32 0x1)))) (set cr (& (var vcrc) (var gm))) (set cr (ite (&& (ule (bv 32 0x0) (var gd)) (! (== (bv 32 0x0) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x0)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x1) (var gd)) (! (== (bv 32 0x1) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x1)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x2) (var gd)) (! (== (bv 32 0x2) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x2)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x3) (var gd)) (! (== (bv 32 0x3) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x3)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x4) (var gd)) (! (== (bv 32 0x4) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x4)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x5) (var gd)) (! (== (bv 32 0x5) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x5)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x6) (var gd)) (! (== (bv 32 0x6) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x6)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x7) (var gd)) (! (== (bv 32 0x7) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x7)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set vcrc (| (& (var vcrc) (~ (var gm))) (var cr))))
d "vcrch *-sp[6]" cbe24607 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x6)))) (set gd (+ (& (var vcrcsize) (bv 32 0x7)) (bv 32 0x1))) (set gw (+ (& (>> (var vcrcsize) (bv 8 0x10) false) (bv 32 0x1f)) (bv 32 0x1))) (set gm (cast 32 false (- (<< (bv 64 0x1) (var gw) false) (bv 64 0x1)))) (set gp (& (var vcrcpoly) (var gm))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (& (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (>> (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (- (bv 32 0x8) (var gd)) false) (var cd)) (- (<< (bv 32 0x1) (var gd) false) (bv 32 0x1)))) (set cr (& (var vcrc) (var gm))) (set cr (ite (&& (ule (bv 32 0x0) (var gd)) (! (== (bv 32 0x0) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x0)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x1) (var gd)) (! (== (bv 32 0x1) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x1)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x2) (var gd)) (! (== (bv 32 0x2) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x2)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x3) (var gd)) (! (== (bv 32 0x3) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x3)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x4) (var gd)) (! (== (bv 32 0x4) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x4)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x5) (var gd)) (! (== (bv 32 0x5) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x5)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x6) (var gd)) (! (== (bv 32 0x6) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x6)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set cr (ite (&& (ule (bv 32 0x7) (var gd)) (! (== (bv 32 0x7) (var gd)))) (ite (! (is_zero (^ (& (>> (var cd) (- (- (var gd) (bv 32 0x1)) (bv 32 0x7)) false) (bv 32 0x1)) (& (>> (var cr) (- (var gw) (bv 32 0x1)) false) (bv 32 0x1))))) (^ (& (<< (var cr) (bv 8 0x1) false) (var gm)) (var gp)) (& (<< (var cr) (bv 8 0x1) false) (var gm))) (var cr))) (set vcrc (| (& (var vcrc) (~ (var gm))) (var cr))))
d "vmov16 vcrcpsize, *+xar1[3]" cbe2d908 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x3))) (set mv (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vcrcsize (| (& (var vcrcsize) (bv 32 0xffe0ffff)) (& (<< (cast 32 false (var mv)) (bv 8 0x10) false) (bv 32 0x1f0000)))))
d "vcrc8h_1 *+xar7[5]" cce2ef00 0x0 (seq (set _ea (+ (var xar7) (bv 32 0x5))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xff)) (<< (var cd) (bv 8 0x0) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x80)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)) (bv 32 0x7)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffffff00)) (var cr))))
d "vcrc16p1l_1 @0x0c" cee20c00 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0xc))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffff)) (<< (var cd) (bv 8 0x8) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffff0000)) (var cr))))
d "vcrc16p2l_1 @0x27" cee22710 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x27))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (var cb) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffff)) (<< (var cd) (bv 8 0x8) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffff0000)) (var cr))))
d "vcrc16p1h_1 @0x3a" cfe23a00 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x3a))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffff)) (<< (var cd) (bv 8 0x8) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x8005)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffff0000)) (var cr))))
d "vcrc16p2h_1 *-sp[13]" cfe24d10 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0xd)))) (set cb (cast 32 false (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2))))) (set cd (& (>> (var cb) (bv 8 0x8) false) (bv 32 0xff))) (set cd (ite (! (is_zero (& (var vstatus) (bv 32 0x80000000)))) (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var cd) (bv 8 0x0) false) (bv 32 0x1)) (bv 8 0x7) false)) (<< (& (>> (var cd) (bv 8 0x1) false) (bv 32 0x1)) (bv 8 0x6) false)) (<< (& (>> (var cd) (bv 8 0x2) false) (bv 32 0x1)) (bv 8 0x5) false)) (<< (& (>> (var cd) (bv 8 0x3) false) (bv 32 0x1)) (bv 8 0x4) false)) (<< (& (>> (var cd) (bv 8 0x4) false) (bv 32 0x1)) (bv 8 0x3) false)) (<< (& (>> (var cd) (bv 8 0x5) false) (bv 32 0x1)) (bv 8 0x2) false)) (<< (& (>> (var cd) (bv 8 0x6) false) (bv 32 0x1)) (bv 8 0x1) false)) (<< (& (>> (var cd) (bv 8 0x7) false) (bv 32 0x1)) (bv 8 0x0) false)) (var cd))) (set cr (^ (& (var vcrc) (bv 32 0xffff)) (<< (var cd) (bv 8 0x8) false))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set cr (ite (! (is_zero (& (var cr) (bv 32 0x8000)))) (^ (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)) (bv 32 0x1021)) (& (<< (var cr) (bv 8 0x1) false) (bv 32 0xffff)))) (set vcrc (| (& (var vcrc) (bv 32 0xffff0000)) (var cr))))
d "vmov32 vr4, *+xar7[0]" f0e3c704 0x0 (seq (set _ea (+ (var xar7) (bv 32 0x0))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vr4 (var mv)))
d "vxormov32 vr8, *+xar3[6]" f0e3f318 0x0 (seq (set _ea (+ (var xar3) (bv 32 0x6))) (set vr8 (^ (var vr8) (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2))))))
d "vmov32 vt0, *-sp[3]" f1e34300 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x3)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vt0 (var mv)))
d "vmov32 vcrc, *+xar4[0]" f2e3c400 0x0 (seq (set _ea (+ (var xar4) (bv 32 0x0))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vcrc (var mv)))
d "vmov32 vcrcpoly, *+xar1[ar0]" f2e39101 0x0 (seq (set _ea (+ (var xar1) (cast 32 false (cast 16 false (var xar0))))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vcrcpoly (var mv)))
d "vmov32 vcrcsize, *-sp[2]" f2e34202 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x2)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set vcrcsize (var mv)))
d "vcmpy vr3, vr2, vr1, vr0 || vmov32 vr5, *-sp[30]" f6e35e05 0x0
d "vccmpy vr3, vr2, vr1, vr0 || vmov32 vr5, *+xar5[6]" f6e3f515 0x0
d "vcmac vr5, vr4, vr3, vr2, vr1, vr0 || vmov32 vr6, *+xar1[3]" f7e3d906 0x0
d "vccmac vr5, vr4, vr3, vr2, vr1, vr0 || vmov32 vr8, @0x0c" f7e30c18 0x0
d "vcadd vr5, vr4, vr3, vr2 || vmov32 vr1, *+xar7[4]" f8e3e701 0x0
d "vcsub vr5, vr4, vr3, vr2 || vmov32 vr4, @0x2f" f9e32f04 0x0
d "vcdadd16 vr5, vr4, vr3, vr2 || vmov32 vr7, @0x1b" fae31b07 0x0
d "vcdsub16 vr6, vr4, vr3, vr2 || vmov32 vr7, @0x23" fbe32307 0x0
d "vitbm2 vr0 || vmov32 vr2, *xar3++" fce38300 0x0
d "vitbm3 vr0, vr1, vr2 || vmov32 vr2, @0x17" fde31700 0x0
d "vitlsel vr1, vr8, vr4, vr3 || vmov32 vr2, *arp0" fee3b081 0x0
d "vithsel vr4, vr5, vr4, vr3 || vmov32 vr2, @0x25" ffe32554 0x0
d "vcmpy vr3, vr2, vr1, vr0" 00e5 0x0
d "vcsub vr5, vr4, vr3, vr2" 03e5 0x0
d "vcdadd16 vr5, vr4, vr3, vr2" 04e5 0x0
d "vcdsub16 vr6, vr4, vr3, vr2" 05e5 0x0
d "a_vclrovfr" 0ae5 0x0 (set vstatus (| (& (var vstatus) (bv 32 0xffffefff)) (& (<< (cast 32 false (bv 8 0x0)) (bv 8 0xc) false) (bv 32 0x1000))))
d "a_vclrovfi" 0be5 0x0 (set vstatus (| (& (var vstatus) (bv 32 0xffffdfff)) (& (<< (cast 32 false (bv 8 0x0)) (bv 8 0xd) false) (bv 32 0x2000))))
d "vccmpy vr3, vr2, vr1, vr0" 0ee5 0x0
d "vtrace vr1, vr0, vt0, vt1" 28e5 0x0
d "vcadd vr7, vr6, vr5, vr4" 2ae5 0x0
d "vswapcrc" 2ee5 0x0 (set vcrc (| (& (var vcrc) (bv 32 0xffff0000)) (| (<< (& (var vcrc) (bv 32 0xff)) (bv 8 0x8) false) (& (>> (var vcrc) (bv 8 0x8) false) (bv 32 0xff)))))
d "vgfadd4 vr4, vr0, vr2, #0x8" 80e62810 0x0
d "vrevb vr7" 80e60724 0x0 (seq (set rv (var vr7)) (set rv (| (<< (& (var rv) (bv 32 0xff00ff)) (bv 8 0x8) false) (& (>> (var rv) (bv 8 0x8) false) (bv 32 0xff00ff)))) (set rv (| (<< (& (var rv) (bv 32 0xffff)) (bv 8 0x10) false) (& (>> (var rv) (bv 8 0x10) false) (bv 32 0xffff)))) (set vr7 (var rv)))
d "vshlmb vr7, vr4" 80e67c24 0x0
d "vmod32 vr7h, vr6, vr5l" 80e6f527 0x0
d "vmod32 vr7h, vr3, vr4h" 80e6dc29 0x0
d "vgfacc vr7, vr0, #0x0" 81e68003 0x0
d "vcshl16 vr8 << #7" f2e67800 0x0
d "vcshr16 vr0 >> #2" f2e62001 0x0
d "vmov32 vr8, vr3" f2e68302 0x0 (set vr8 (var vr3))
d "vswap32 vr5, vr7" f2e65703 0x0 (seq (set sa (var vr5)) (set vr5 (var vr7)) (set vr7 (var sa)))
d "vcmag vr2, vr4" f2e62404 0x0
d "vlshl32 vr1 << #13" f2e66905 0x0 (set vr1 (<< (var vr1) (bv 8 0xd) false))
d "vlshr32 vr5 >> #14" f2e67506 0x0 (set vr5 (>> (var vr5) (bv 8 0xe) false))
d "vashl32 vr6 << #19" f2e69e07 0x0 (seq (set sw (<< (cast 64 (msb (var vr6)) (var vr6)) (bv 8 0x13) false)) (set so (! (== (var sw) (cast 64 (msb (cast 32 false (var sw))) (cast 32 false (var sw)))))) (set vstatus (| (& (var vstatus) (bv 32 0xffffefff)) (& (<< (cast 32 false (ite (|| (! (is_zero (& (var vstatus) (bv 32 0x1000)))) (var so)) (bv 8 0x1) (bv 8 0x0))) (bv 8 0xc) false) (bv 32 0x1000)))) (set vr6 (ite (&& (! (is_zero (& (var vstatus) (bv 32 0x400)))) (var so)) (ite (msb (var vr6)) (bv 32 0x80000000) (bv 32 0x7fffffff)) (cast 32 false (var sw)))))
d "vashr32 vr7 >> #9" f2e64f08 0x0 (set vr7 (ite (! (is_zero (& (var vstatus) (bv 32 0x800)))) (cast 32 false (>> (+ (cast 64 (msb (var vr7)) (var vr7)) (bv 64 0x100)) (bv 8 0x9) (msb (+ (cast 64 (msb (var vr7)) (var vr7)) (bv 64 0x100))))) (cast 32 false (>> (cast 64 (msb (var vr7)) (var vr7)) (bv 8 0x9) (msb (cast 64 (msb (var vr7)) (var vr7)))))))
d "vsetk #0x6" f2e60609 0x0 (set vstatus (| (& (var vstatus) (bv 32 0xc7ffffff)) (& (<< (cast 32 false (bv 8 0x6)) (bv 8 0x1b) false) (bv 32 0x38000000))))
d "vmov16 vr5l, vr4h" f2e6250a 0x0 (set vr5 (| (& (var vr5) (bv 32 0xffff0000)) (cast 32 false (cast 16 false (>> (var vr4) (bv 8 0x10) false)))))
d "vmov16 vr1h, vr3l" f2e6590a 0x0 (set vr1 (| (& (var vr1) (bv 32 0xffff)) (<< (cast 32 false (cast 16 false (var vr3))) (bv 8 0x10) false)))
d "vmov16 vr7h, vr5h" f2e6af0a 0x0 (set vr7 (| (& (var vr7) (bv 32 0xffff)) (<< (cast 32 false (cast 16 false (>> (var vr5) (bv 8 0x10) false))) (bv 8 0x10) false)))
d "vmov16 vr7l, vr2l" f2e6d70a 0x0 (set vr7 (| (& (var vr7) (bv 32 0xffff0000)) (cast 32 false (cast 16 false (var vr2)))))
d "vinc vr2l" f2e6020b 0x0 (set vr2 (| (& (var vr2) (bv 32 0xffff0000)) (cast 32 false (+ (cast 16 false (var vr2)) (bv 16 0x1)))))
d "vmpyadd vr4, vr4l, vr4h, vr5h" f2e62c0c 0x0
d "vmpyadd vr1, vr1l, vr1h, vr6l" f2e6710c 0x0
d "vmod32 vr2h, vr0, vr1l || vmov32 vr0, vr5" f3e64250 0x0
d "vmod32 vr5h, vr6, vr4h || vmov32 vr1, vr0" f3e63583 0x0
d "vitlsel vr6, vr6, vr4, vr3" f6e66600 0x0
d "vithsel vr8, vr4, vr4, vr3" f7e64800 0x0
d "vclear vr0" f8e60000 0x0 (set vr0 (bv 32 0x0))
d "vclearall" f9e60000 0x0 (seq (set vt0 (bv 32 0x0)) (set vt1 (bv 32 0x0)) (set vr0 (bv 32 0x0)) (set vr1 (bv 32 0x0)) (set vr2 (bv 32 0x0)) (set vr3 (bv 32 0x0)) (set vr4 (bv 32 0x0)) (set vr5 (bv 32 0x0)) (set vr6 (bv 32 0x0)) (set vr7 (bv 32 0x0)) (set vr8 (bv 32 0x0)))
d "vmovzi vcrcpoly, #0x24d0" 54e7d024 0x0 (set vcrcpoly (bv 32 0x24d0))
d "vmovix vcrcpoly, #0x2d12" 55e7122d 0x0 (set vcrcpoly (| (& (var vcrcpoly) (bv 32 0xffff)) (bv 32 0x2d120000)))
d "vsetcrcsize #3:#2" 56e7238a 0x0 (seq (set vcrcsize (| (& (var vcrcsize) (bv 32 0xffe0ffff)) (& (<< (cast 32 false (bv 8 0x3)) (bv 8 0x10) false) (bv 32 0x1f0000)))) (set vcrcsize (| (& (var vcrcsize) (bv 32 0xfffffff8)) (& (<< (cast 32 false (bv 8 0x2)) (bv 8 0x0) false) (bv 32 0x7)))))
