NAME=C28x RzIL VM: ALU, bit and shift operations
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 54ff @ 0
ara0
ar acc=0x80000000
ar ovm=0x1
aezi
pi 1
aezs 1
echo -- NEG ACC, 0x80000000 with OVM
ar acc
ar v
ar c
ar n
ar z
w0 8192 @ 0
wx 54ff @ 0
ara0
ar acc=0x80000000
aezi
pi 1
aezs 1
echo -- NEG ACC, 0x80000000 without OVM
ar acc
ar v
ar n
w0 8192 @ 0
wx 54ff @ 0
ara0
ar acc=0x0
aezi
pi 1
aezs 1
echo -- NEG ACC, 0
ar acc
ar c
ar z
w0 8192 @ 0
wx 56ff @ 0
ara0
ar acc=0xfffffffe
ar c=0x1
aezi
pi 1
aezs 1
echo -- ABS ACC, -2
ar acc
ar c
ar n
w0 8192 @ 0
wx 57ff @ 0
ara0
ar acc=0x1234
ar ovc=0x3f
aezi
pi 1
aezs 1
echo -- SAT ACC, OVC -1
ar acc
ar v
ar ovc
ar c
ar n
w0 8192 @ 0
wx 57ff @ 0
ara0
ar acc=0x1234
ar v=0x1
aezi
pi 1
aezs 1
echo -- SAT ACC, OVC 0
ar acc
ar v
w0 8192 @ 0
wx a90a @ 0
ara0
ar acc=0x7fff
aezi
pi 1
aezs 1
echo -- INC AL, 0x7fff
ar acc
ar v
ar n
ar c
ar z
w0 8192 @ 0
wx a90b @ 0
ara0
ar acc=0x0
aezi
pi 1
aezs 1
echo -- DEC AL, 0
ar acc
ar c
ar n
ar v
w0 8192 @ 0
wx a90c @ 0
ara0
ar acc=0xffffffff
ar c=0x1
aezi
pi 1
aezs 1
echo -- ADDCU ACC,AL, C 1
ar acc
ar c
ar v
ar n
w0 8192 @ 0
wx a91d @ 0
ara0
ar acc=0x10
aezi
pi 1
aezs 1
echo -- SBBU ACC,AL, C 0
ar acc
ar c
ar n
w0 8192 @ 0
wx 3b56 @ 0
ara0
ar acc=0x10000001
ar xt=0x40000
aezi
pi 1
aezs 1
echo -- LSLL ACC,T, T 4
ar acc
ar c
w0 8192 @ 0
wx 53ff @ 0
ara0
ar acc=0x80000000
aezi
pi 1
aezs 1
echo -- ROL ACC, C 0
ar acc
ar c
ar z
w0 8192 @ 0
wx 3356 @ 0
ara0
ar acc=0x5
ar p=0x7
ar ovc=0x3
aezi
pi 1
aezs 1
echo -- ZAPA
ar acc
ar p
ar ovc
ar n
ar z
w0 8192 @ 0
wx ae92ae92ae92ae92ae92 @ 0
ara0
ar arp=0x3
ar xar3=0x0
ar xar0=0x8
aezi
pi 1
aezs 1
echo -- BR0++ step 1, AR0 8
ar xar3
w0 8192 @ 0
wx ae92ae92ae92ae92ae92 @ 0
ara0
ar arp=0x3
ar xar3=0x0
ar xar0=0x8
aezi
pi 2
aezs 2
echo -- BR0++ step 2, AR0 8
ar xar3
w0 8192 @ 0
wx ae92ae92ae92ae92ae92 @ 0
ara0
ar arp=0x3
ar xar3=0x0
ar xar0=0x8
aezi
pi 3
aezs 3
echo -- BR0++ step 3, AR0 8
ar xar3
w0 8192 @ 0
wx ae92ae92ae92ae92ae92 @ 0
ara0
ar arp=0x3
ar xar3=0x0
ar xar0=0x8
aezi
pi 4
aezs 4
echo -- BR0++ step 4, AR0 8
ar xar3
w0 8192 @ 0
wx ae92ae92ae92ae92ae92 @ 0
ara0
ar arp=0x3
ar xar3=0x0
ar xar0=0x8
aezi
pi 5
aezs 5
echo -- BR0++ step 5, AR0 8
ar xar3
w0 8192 @ 0
wx bf92bf92bf92bf92 @ 0
ara0
ar xar6=0x100
ar xar1=0x2
aezi
pi 1
aezs 1
echo -- AR6++ step 1, AR1 2
ar xar6
ar arp
w0 8192 @ 0
wx bf92bf92bf92bf92 @ 0
ara0
ar xar6=0x100
ar xar1=0x2
aezi
pi 2
aezs 2
echo -- AR6++ step 2, AR1 2
ar xar6
ar arp
w0 8192 @ 0
wx bf92bf92bf92bf92 @ 0
ara0
ar xar6=0x100
ar xar1=0x2
aezi
pi 3
aezs 3
echo -- AR6++ step 3, AR1 2
ar xar6
ar arp
w0 8192 @ 0
wx bf92bf92bf92bf92 @ 0
ara0
ar xar6=0x100
ar xar1=0x2
aezi
pi 4
aezs 4
echo -- AR6++ step 4, AR1 2
ar xar6
ar arp
w0 8192 @ 0
wx b592 @ 0
wx 3412 @ 128
ara0
ar arp=0x2
ar xar2=0x40
aezi
pi 1
aezs 1
echo -- MOV AL,,ARP5 with ARP 2
ar arp
ar acc
EOF
EXPECT=<<EOF
neg acc
-- NEG ACC, 0x80000000 with OVM
acc = 0x7fffffff
v = 0x1
c = 0x0
n = 0x0
z = 0x0
neg acc
-- NEG ACC, 0x80000000 without OVM
acc = 0x80000000
v = 0x1
n = 0x1
neg acc
-- NEG ACC, 0
acc = 0x00000000
c = 0x1
z = 0x1
abs acc
-- ABS ACC, -2
acc = 0x00000002
c = 0x0
n = 0x0
sat acc
-- SAT ACC, OVC -1
acc = 0x80000000
v = 0x1
ovc = 0x00
c = 0x0
n = 0x1
sat acc
-- SAT ACC, OVC 0
acc = 0x00001234
v = 0x0
inc @al
-- INC AL, 0x7fff
acc = 0x00008000
v = 0x1
n = 0x1
c = 0x0
z = 0x0
dec @al
-- DEC AL, 0
acc = 0x0000ffff
c = 0x0
n = 0x1
v = 0x0
addcu acc, @al
-- ADDCU ACC,AL, C 1
acc = 0x0000ffff
c = 0x1
v = 0x0
n = 0x0
sbbu acc, @al
-- SBBU ACC,AL, C 0
acc = 0xffffffff
c = 0x0
n = 0x1
lsll acc, t
-- LSLL ACC,T, T 4
acc = 0x00000010
c = 0x1
rol acc
-- ROL ACC, C 0
acc = 0x00000000
c = 0x1
z = 0x1
zapa
-- ZAPA
acc = 0x00000000
p = 0x00000000
ovc = 0x00
n = 0x0
z = 0x1
mov al, *br0++
-- BR0++ step 1, AR0 8
xar3 = 0x00000008
mov al, *br0++
mov al, *br0++
-- BR0++ step 2, AR0 8
xar3 = 0x00000004
mov al, *br0++
mov al, *br0++
mov al, *br0++
-- BR0++ step 3, AR0 8
xar3 = 0x0000000c
mov al, *br0++
mov al, *br0++
mov al, *br0++
mov al, *br0++
-- BR0++ step 4, AR0 8
xar3 = 0x00000002
mov al, *br0++
mov al, *br0++
mov al, *br0++
mov al, *br0++
mov al, *br0++
-- BR0++ step 5, AR0 8
xar3 = 0x0000000a
mov al, *ar6%++
-- AR6++ step 1, AR1 2
xar6 = 0x00000101
arp = 0x6
mov al, *ar6%++
mov al, *ar6%++
-- AR6++ step 2, AR1 2
xar6 = 0x00000102
arp = 0x6
mov al, *ar6%++
mov al, *ar6%++
mov al, *ar6%++
-- AR6++ step 3, AR1 2
xar6 = 0x00000100
arp = 0x6
mov al, *ar6%++
mov al, *ar6%++
mov al, *ar6%++
mov al, *ar6%++
-- AR6++ step 4, AR1 2
xar6 = 0x00000101
arp = 0x6
mov al, *arp5
-- MOV AL,,ARP5 with ARP 2
arp = 0x5
acc = 0x00001234
EOF
RUN

NAME=C28x RzIL VM: moves, AX arithmetic, calls and returns
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx a894 @ 0
ara0
ar acc=0x17fff
aezi
pi 1
aezs 1
echo -- ADD AL,AH overflow
ar acc
ar v
ar n
ar c
w0 8192 @ 0
wx a89e @ 0
ara0
ar acc=0x10000
aezi
pi 1
aezs 1
echo -- SUB AL,AH borrow
ar acc
ar c
ar n
w0 8192 @ 0
wx a908ffff @ 0
ara0
ar acc=0x1
ar v=0x1
aezi
pi 1
aezs 1
echo -- ADD AL,-1 clears V
ar acc
ar z
ar c
ar v
w0 8192 @ 0
wx 0856ff00 @ 0
ara0
ar acc=0xffffffff
aezi
pi 1
aezs 1
echo -- AND ACC,0xff16
ar acc
ar n
ar z
w0 8192 @ 0
wx 24ff0080 @ 0
ara0
ar sxm=0x1
aezi
pi 1
aezs 1
echo -- MOV ACC,0x80004, SXM
ar acc
ar n
w0 8192 @ 0
wx 24ff0080 @ 0
ara0
ar sxm=0x0
aezi
pi 1
aezs 1
echo -- MOV ACC,0x80004, no SXM
ar acc
ar n
w0 8192 @ 0
wx 0256a900 @ 0
ara0
ar acc=0xfc00
aezi
pi 1
aezs 1
echo -- MOV OVC,AL
ar ovc
w0 8192 @ 0
wx 2956a900 @ 0
ara0
ar ovc=0x21
aezi
pi 1
aezs 1
echo -- MOV AL,OVC
ar acc
ar n
w0 8192 @ 0
wx a9280080 @ 0
ara0
ar acc=0x12340000
aezi
pi 1
aezs 1
echo -- MOV AL,0x8000 sets N
ar acc
ar n
ar z
w0 8192 @ 0
wx 50ff @ 0
ara0
ar acc=0x80000000
ar c=0x1
aezi
pi 1
aezs 1
echo -- LSL ACC,T with T 0
ar acc
ar c
ar n
w0 8192 @ 0
wx 2b56a901 @ 0
ara0
ar acc=0x12340000
ar z=0x1
aezi
pi 1
aezs 1
echo -- MOV AL,AH,EQ taken
ar acc
w0 8192 @ 0
wx 2b56a901 @ 0
ara0
ar acc=0x12340000
ar z=0x0
aezi
pi 1
aezs 1
echo -- MOV AL,AH,EQ not taken
ar acc
ar pc
w0 8192 @ 0
wx 2b56a90b @ 0
ara0
ar acc=0x10000
ar v=0x1
aezi
pi 1
aezs 1
echo -- MOV AL,AH,OV clears V
ar acc
ar v
w0 8192 @ 0
wx 40764000 @ 0
ara0
ar sp=0x100
ar rpc=0x123456
aezi
pi 1
aezs 1
echo -- LCR keeps a word address
ar rpc
ar sp
ar pc
w0 8192 @ 0
wx 0600 @ 0
ara0
ar rpc=0x3f8000
ar sp=0x102
aezi
pi 1
aezs 1
echo -- LRETR into boot ROM
ar pc
ar sp
w0 8192 @ 0
wx 80004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001476 @ 0
ara0
ar sp=0x100
aezi
pi 1
pi 1 @ 0x80
aezs 2
echo -- LC 22bit then LRET
ar pc
ar sp
w0 8192 @ 0
wx 0600 @ 0
wx 0080 @ 512
wx 3f00 @ 514
ara0
ar rpc=0x40
ar sp=0x102
aezi
pi 1
aezs 1
echo -- LRETR reloads RPC from the stack
ar pc
ar sp
ar rpc
w0 8192 @ 0
wx c0004000 @ 0
ara0
aezi
pi 1
aezs 1
echo -- FFC XAR7,22bit
ar xar7
ar pc
w0 8192 @ 0
wx ebff1000 @ 0
ara0
ar v=0x1
aezi
pi 1
aezs 1
echo -- B OV clears V
ar v
ar pc
w0 8192 @ 0
wx 2076 @ 0
ara0
ar xar7=0xffc00040
aezi
pi 1
aezs 1
echo -- LB *XAR7 branches to XAR7(21:0)
ar pc
w0 8192 @ 0
wx 643e @ 0
ara0
ar xar4=0x40
ar rpc=0x123456
ar sp=0x100
aezi
pi 1
aezs 1
echo -- LCR *XAR4 pushes RPC and keeps the return word address
ar rpc
ar sp
ar pc
w0 8192 @ 0
wx 643e @ 0
wx 0600 @ 128
ara0
ar xar4=0x40
ar rpc=0x3f8000
ar sp=0x100
aezi
pi 1
pi 1 @ 0x80
aezs 2
echo -- LCR *XAR4 then LRETR returns past the call
ar pc
ar sp
ar rpc
EOF
EXPECT=<<EOF
add al, @ah
-- ADD AL,AH overflow
acc = 0x00018000
v = 0x1
n = 0x1
c = 0x0
sub al, @ah
-- SUB AL,AH borrow
acc = 0x0001ffff
c = 0x0
n = 0x1
add @al, #-0x1
-- ADD AL,-1 clears V
acc = 0x00000000
z = 0x1
c = 0x1
v = 0x0
and acc, #0xff << #16
-- AND ACC,0xff16
acc = 0x00ff0000
n = 0x0
z = 0x0
mov acc, #0x8000 << #4
-- MOV ACC,0x80004, SXM
acc = 0xfff80000
n = 0x1
mov acc, #0x8000 << #4
-- MOV ACC,0x80004, no SXM
acc = 0x00080000
n = 0x0
mov ovc, @al
-- MOV OVC,AL
ovc = 0x3f
mov @al, ovc
-- MOV AL,OVC
acc = 0x00008400
n = 0x1
mov @al, #0x8000
-- MOV AL,0x8000 sets N
acc = 0x12348000
n = 0x1
z = 0x0
lsl acc, t
-- LSL ACC,T with T 0
acc = 0x80000000
c = 0x0
n = 0x1
mov @al, ah, eq
-- MOV AL,AH,EQ taken
acc = 0x12341234
mov @al, ah, eq
-- MOV AL,AH,EQ not taken
acc = 0x12340000
pc = 0x00000004
mov @al, ah, ov
-- MOV AL,AH,OV clears V
acc = 0x00010001
v = 0x0
lcr 0x80
-- LCR keeps a word address
rpc = 0x00000002
sp = 0x0102
pc = 0x00000080
lretr
-- LRETR into boot ROM
pc = 0x007f0000
sp = 0x0100
lc 0x80
lret
-- LC 22bit then LRET
pc = 0x00000004
sp = 0x0100
lretr
-- LRETR reloads RPC from the stack
pc = 0x00000080
sp = 0x0100
rpc = 0x003f8000
ffc xar7, 0x80
-- FFC XAR7,22bit
xar7 = 0x00000002
pc = 0x00000080
b 0x20, ov
-- B OV clears V
v = 0x0
pc = 0x00000020
lb *xar7
-- LB *XAR7 branches to XAR7(21:0)
pc = 0x00000080
lcr *xar4
-- LCR *XAR4 pushes RPC and keeps the return word address
rpc = 0x00000001
sp = 0x0102
pc = 0x00000080
lcr *xar4
lretr
-- LCR *XAR4 then LRETR returns past the call
pc = 0x00000002
sp = 0x0100
rpc = 0x003f8000
EOF
RUN

NAME=C28x RzIL VM: multiplies and the product shift mode
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx a912 @ 0
ara0
ar xt=0xfffd0000
ar acc=0x7
aezi
pi 1
aezs 1
echo -- MPY ACC,T,AL signed
ar acc
ar n
w0 8192 @ 0
wx a937 @ 0
ara0
ar xt=0xffff0000
ar acc=0xffff
aezi
pi 1
aezs 1
echo -- MPYU P,T,AL
ar p
w0 8192 @ 0
wx a932 @ 0
ara0
ar xt=0xffff0000
ar acc=0xffff
aezi
pi 1
aezs 1
echo -- MPYXU P,T,AL
ar p
w0 8192 @ 0
wx a917 @ 0
ara0
ar acc=0x3
ar p=0x5
ar xt=0x20000
ar pm=0x1
aezi
pi 1
aezs 1
echo -- MPYA P,T,AL, PM 1
ar acc
ar p
w0 8192 @ 0
wx a917 @ 0
ara0
ar acc=0x3
ar p=0x5
ar xt=0x20000
ar pm=0x0
aezi
pi 1
aezs 1
echo -- MPYA P,T,AL, PM 0 shifts left
ar acc
ar p
w0 8192 @ 0
wx a913 @ 0
ara0
ar acc=0xa
ar p=0xfffffff8
ar xt=0x10000
ar pm=0x2
aezi
pi 1
aezs 1
echo -- MPYS P,T,AL, PM 2 shifts right
ar acc
ar p
w0 8192 @ 0
wx a916 @ 0
ara0
ar acc=0xabcd
ar p=0x1
ar pm=0x5
ar amode=0x1
aezi
pi 1
aezs 1
echo -- MOVP T,AL, PM 5 with AMODE
ar acc
ar xt
w0 8192 @ 0
wx a916 @ 0
ara0
ar acc=0xabcd
ar p=0x100
ar pm=0x5
aezi
pi 1
aezs 1
echo -- MOVP T,AL, PM 5 without AMODE
ar acc
w0 8192 @ 0
wx 1556a900 @ 0
ara0
ar acc=0xfffd
ar p=0x0
ar pm=0x1
aezi
pi 1
aezs 1
echo -- SQRA AL
ar p
ar xt
ar acc
w0 8192 @ 0
wx 0556a900 @ 0
ara0
ar xt=0x10000
ar acc=0x10000
ar pm=0x1
ar p=0x5555
aezi
pi 1
aezs 1
echo -- IMPYL P,XT,ACC, PM 1
ar p
w0 8192 @ 0
wx 0556a900 @ 0
ara0
ar xt=0x10000
ar acc=0x10000
ar pm=0x2
aezi
pi 1
aezs 1
echo -- IMPYL P,XT,ACC, PM 2
ar p
w0 8192 @ 0
wx 6756a900 @ 0
ara0
ar xt=0x10000
ar acc=0x10000
aezi
pi 1
aezs 1
echo -- QMPYL P,XT,ACC
ar p
w0 8192 @ 0
wx 4756a900 @ 0
ara0
ar xt=0xffffffff
ar acc=0xffffffff
aezi
pi 1
aezs 1
echo -- QMPYUL P,XT,ACC
ar p
w0 8192 @ 0
wx 4256a900 @ 0
ara0
ar xt=0xffffffff
ar acc=0xffffffff
aezi
pi 1
aezs 1
echo -- QMPYXUL P,XT,ACC
ar p
w0 8192 @ 0
wx 4c56a400 @ 0
ara0
ar acc=0xffffffff
ar p=0x1
ar xt=0x2
ar xar4=0xffffffff
ar pm=0x1
aezi
pi 1
aezs 1
echo -- IMPYAL P,XT,XAR4 counts OVCU
ar acc
ar c
ar z
ar ovc
ar p
w0 8192 @ 0
wx 5356a400 @ 0
ara0
ar acc=0xffffffff
ar xar4=0x1
aezi
pi 1
aezs 1
echo -- ADDUL ACC,XAR4 carry
ar acc
ar c
ar z
ar ovc
ar v
w0 8192 @ 0
wx 5556a400 @ 0
ara0
ar acc=0x0
ar xar4=0x1
aezi
pi 1
aezs 1
echo -- SUBUL ACC,XAR4 borrow
ar acc
ar c
ar n
ar ovc
w0 8192 @ 0
wx a93f @ 0
ara0
ar p=0x4001
ar pm=0x0
aezi
pi 1
aezs 1
echo -- MOV AL,P, PM 0
ar acc
ar n
w0 8192 @ 0
wx a957 @ 0
ara0
ar p=0x12345678
ar pm=0x1
aezi
pi 1
aezs 1
echo -- MOVH AL,P, PM 1
ar acc
w0 8192 @ 0
wx ac16 @ 0
ara0
ar p=0x80000000
ar pm=0x7
aezi
pi 1
aezs 1
echo -- MOVL ACC,PPM, PM 7
ar acc
ar n
w0 8192 @ 0
wx 8035 @ 0
ara0
ar xt=0xfffe0000
ar p=0x1234
aezi
pi 1
aezs 1
echo -- MPYB ACC,T,0x80 writes ACC
ar acc
ar n
ar p
w0 8192 @ 0
wx a9150400 @ 0
ara0
ar acc=0x3
ar p=0x5
ar pm=0x1
aezi
pi 1
aezs 1
echo -- MPYA P,AL,4
ar acc
ar p
w0 8192 @ 0
wx ac10 @ 0
ara0
ar acc=0x10
ar p=0x20
ar pm=0x1
aezi
pi 1
aezs 1
echo -- ADDL ACC,P << PM, PM 1
ar acc
ar c
ar v
w0 8192 @ 0
wx ac10 @ 0
ara0
ar acc=0x7fffffff
ar p=0x1
ar pm=0x0
aezi
pi 1
aezs 1
echo -- ADDL ACC,P << PM, PM 0 overflows
ar acc
ar v
ar ovc
ar c
ar n
w0 8192 @ 0
wx ac11 @ 0
ara0
ar acc=0x100
ar p=0xfffffff0
ar pm=0x2
aezi
pi 1
aezs 1
echo -- SUBL ACC,P << PM, PM 2 shifts right
ar acc
ar c
ar v
w0 8192 @ 0
wx ac16 @ 0
ara0
ar p=0x1234567
ar pm=0x5
ar amode=0x1
aezi
pi 1
aezs 1
echo -- MOVL ACC,P << PM, PM 5 with AMODE
ar acc
w0 8192 @ 0
wx 59ff @ 0
ara0
ar acc=0x5
ar p=0x5
ar pm=0x1
aezi
pi 1
aezs 1
echo -- CMPL ACC,P << PM, equal
ar acc
ar z
ar c
w0 8192 @ 0
wx 59ff @ 0
ara0
ar acc=0x1
ar p=0x1
ar pm=0x0
aezi
pi 1
aezs 1
echo -- CMPL ACC,P << PM, PM 0 borrows
ar acc
ar n
ar z
ar c
w0 8192 @ 0
wx 4656c400 @ 0
wx 08000000 @ 128
ara0
ar acc=0x100
ar p=0x10
ar pm=0x1
ar xt=0x40000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- QMPYAL P,XT,*+XAR4[0], PM 1
ar acc
ar p
w0 8192 @ 0
wx 4556c400 @ 0
wx 10000000 @ 128
ara0
ar acc=0x100
ar p=0x10
ar pm=0x0
ar xt=0xffffffff
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- QMPYSL P,XT,*+XAR4[0], PM 0
ar acc
ar p
ar c
EOF
EXPECT=<<EOF
mpy acc, t, @al
-- MPY ACC,T,AL signed
acc = 0xffffffeb
n = 0x1
mpyu p, t, @al
-- MPYU P,T,AL
p = 0xfffe0001
mpyxu p, t, @al
-- MPYXU P,T,AL
p = 0xffff0001
mpya p, t, @al
-- MPYA P,T,AL, PM 1
acc = 0x00000008
p = 0x00000006
mpya p, t, @al
-- MPYA P,T,AL, PM 0 shifts left
acc = 0x0000000d
p = 0x00000006
mpys p, t, @al
-- MPYS P,T,AL, PM 2 shifts right
acc = 0x0000000e
p = 0x0000000a
movp t, @al
-- MOVP T,AL, PM 5 with AMODE
acc = 0x00000010
xt = 0xabcd0000
movp t, @al
-- MOVP T,AL, PM 5 without AMODE
acc = 0x00000010
sqra @al
-- SQRA AL
p = 0x00000009
xt = 0xfffd0000
acc = 0x0000fffd
impyl p, xt, @acc
-- IMPYL P,XT,ACC, PM 1
p = 0x00000000
impyl p, xt, @acc
-- IMPYL P,XT,ACC, PM 2
p = 0x80000000
qmpyl p, xt, @acc
-- QMPYL P,XT,ACC
p = 0x00000001
qmpyul p, xt, @acc
-- QMPYUL P,XT,ACC
p = 0xfffffffe
qmpyxul p, xt, @acc
-- QMPYXUL P,XT,ACC
p = 0xffffffff
impyal p, xt, @xar4
-- IMPYAL P,XT,XAR4 counts OVCU
acc = 0x00000000
c = 0x1
z = 0x1
ovc = 0x01
p = 0xfffffffe
addul acc, @xar4
-- ADDUL ACC,XAR4 carry
acc = 0x00000000
c = 0x1
z = 0x1
ovc = 0x01
v = 0x0
subul acc, @xar4
-- SUBUL ACC,XAR4 borrow
acc = 0xffffffff
c = 0x0
n = 0x1
ovc = 0x3f
mov @al, p
-- MOV AL,P, PM 0
acc = 0x00008002
n = 0x1
movh @al, p
-- MOVH AL,P, PM 1
acc = 0x00001234
movl acc, p << pm
-- MOVL ACC,PPM, PM 7
acc = 0xfe000000
n = 0x1
mpyb acc, t, #0x80
-- MPYB ACC,T,0x80 writes ACC
acc = 0xffffff00
n = 0x1
p = 0x00001234
mpya p, @al, #0x4
-- MPYA P,AL,4
acc = 0x00000008
p = 0x0000000c
addl acc, p << pm
-- ADDL ACC,P << PM, PM 1
acc = 0x00000030
c = 0x0
v = 0x0
addl acc, p << pm
-- ADDL ACC,P << PM, PM 0 overflows
acc = 0x80000001
v = 0x1
ovc = 0x01
c = 0x0
n = 0x1
subl acc, p << pm
-- SUBL ACC,P << PM, PM 2 shifts right
acc = 0x00000108
c = 0x0
v = 0x0
movl acc, p << pm
-- MOVL ACC,P << PM, PM 5 with AMODE
acc = 0x12345670
cmpl acc, p << pm
-- CMPL ACC,P << PM, equal
acc = 0x00000005
z = 0x1
c = 0x1
cmpl acc, p << pm
-- CMPL ACC,P << PM, PM 0 borrows
acc = 0x00000001
n = 0x1
z = 0x0
c = 0x0
qmpyal p, xt, *+xar4[0]
-- QMPYAL P,XT,*+XAR4[0], PM 1
acc = 0x00000110
p = 0x00000002
qmpysl p, xt, *+xar4[0]
-- QMPYSL P,XT,*+XAR4[0], PM 0
acc = 0x000000e0
p = 0xffffffff
c = 0x1
EOF
RUN

NAME=C28x RzIL VM: min/max, division steps and status bits
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 7256a800 @ 0
ara0
ar acc=0x3fffb
aezi
pi 1
aezs 1
echo -- MAX AL,AH takes the larger
ar acc
ar n
ar z
ar v
w0 8192 @ 0
wx 7456a800 @ 0
ara0
ar acc=0xfffb0003
aezi
pi 1
aezs 1
echo -- MIN AL,AH takes the smaller
ar acc
ar n
ar v
w0 8192 @ 0
wx 6156a400 @ 0
ara0
ar acc=0x80000000
ar xar4=0x1
aezi
pi 1
aezs 1
echo -- MAXL ACC,XAR4, infinite precision
ar acc
ar n
ar c
ar v
ar z
w0 8192 @ 0
wx a9eb @ 0
ara0
ar acc=0x50001
aezi
pi 1
aezs 1
echo -- SUBR AL,AH
ar acc
ar c
ar n
w0 8192 @ 0
wx 4956a400 @ 0
ara0
ar acc=0xa
ar xar4=0x3
aezi
pi 1
aezs 1
echo -- SUBRL XAR4,ACC
ar xar4
ar acc
ar c
ar n
ar z
w0 8192 @ 0
wx a01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01f @ 0
ara0
ar acc=0x4
ar xar0=0x2
aezi
pi 16
aezs 16
echo -- SUBCU x16: 4 / 2
ar acc
w0 8192 @ 0
wx a01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01fa01f @ 0
ara0
ar acc=0x7
ar xar0=0x2
aezi
pi 16
aezs 16
echo -- SUBCU x16: 7 / 2
ar acc
w0 8192 @ 0
wx 1756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a4001756a400 @ 0
ara0
ar acc=0x0
ar p=0x64
ar xar4=0x7
aezi
pi 32
aezs 32
echo -- SUBCUL x32: 100 / 7
ar acc
ar p
w0 8192 @ 0
wx 1356a800 @ 0
ara0
ar acc=0x12340000
aezi
pi 1
aezs 1
echo -- ZALR ACC,AH
ar acc
ar n
w0 8192 @ 0
wx 3556 @ 0
ara0
ar acc=0x1234
aezi
pi 1
aezs 1
echo -- CSB ACC, 19 sign bits
ar xt
ar tc
w0 8192 @ 0
wx 3556 @ 0
ara0
ar acc=0xffffffff
aezi
pi 1
aezs 1
echo -- CSB ACC, all sign bits
ar xt
ar tc
ar n
w0 8192 @ 0
wx 5856 @ 0
ara0
ar acc=0x0
ar p=0x1
aezi
pi 1
aezs 1
echo -- NEG64 ACC:P
ar acc
ar p
ar n
ar c
w0 8192 @ 0
wx 5e56 @ 0
ara0
ar acc=0x80000000
ar p=0x0
ar v=0x1
aezi
pi 1
aezs 1
echo -- CMP64 ACC:P after overflow
ar n
ar z
ar v
w0 8192 @ 0
wx 6bff @ 0
ara0
ar pm=0x0
aezi
pi 1
aezs 1
echo -- SPM -2 loads PM 3
ar pm
w0 8192 @ 0
wx 7056 @ 0
ara0
ar acc=0x1
aezi
pi 1
aezs 1
echo -- FLIP AL
ar acc
ar n
w0 8192 @ 0
wx 84a6 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MOVDL XT,XAR4
ar xt
w0 8192 @ 0
wx a924 @ 0
wx efbe @ 128
ara0
ar xar7=0x40
aezi
pi 1
aezs 1
echo -- PREAD AL,XAR7
ar acc
ar n
EOF
EXPECT=<<EOF
max al, @ah
-- MAX AL,AH takes the larger
acc = 0x00030003
n = 0x1
z = 0x0
v = 0x1
min al, @ah
-- MIN AL,AH takes the smaller
acc = 0xfffbfffb
n = 0x0
v = 0x1
maxl acc, @xar4
-- MAXL ACC,XAR4, infinite precision
acc = 0x00000001
n = 0x1
c = 0x1
v = 0x1
z = 0x0
subr @al, ah
-- SUBR AL,AH
acc = 0x00050004
c = 0x1
n = 0x0
subrl @xar4, acc
-- SUBRL XAR4,ACC
xar4 = 0x00000007
acc = 0x0000000a
c = 0x1
n = 0x0
z = 0x0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
-- SUBCU x16: 4 / 2
acc = 0x00000002
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
subcu acc, @ar0
-- SUBCU x16: 7 / 2
acc = 0x00010003
subcul acc, @xar4
subcul acc, @xar4
mpya p, t, @0x00
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
xmacd p, *-sp[22], *(0x7e2e00)
-- SUBCUL x32: 100 / 7
acc = 0x00000002
p = 0x0000000e
zalr acc, @ah
-- ZALR ACC,AH
acc = 0x12348000
n = 0x0
csb acc
-- CSB ACC, 19 sign bits
xt = 0x00120000
tc = 0x0
csb acc
-- CSB ACC, all sign bits
xt = 0x001f0000
tc = 0x1
n = 0x1
neg64 acc:p
-- NEG64 ACC:P
acc = 0xffffffff
p = 0xffffffff
n = 0x1
c = 0x0
cmp64 acc:p
-- CMP64 ACC:P after overflow
n = 0x0
z = 0x0
v = 0x0
spm #-0x2
-- SPM -2 loads PM 3
pm = 0x3
flip al
-- FLIP AL
acc = 0x00008000
n = 0x1
movdl xt, *xar4++
-- MOVDL XT,XAR4
xt = 0x12345678
pread @al, *xar7
-- PREAD AL,XAR7
acc = 0x0000beef
n = 0x1
EOF
RUN

NAME=C28x RzIL VM: C2xLP control flow, NORM, CMPR and loops
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx d1561000 @ 0
ara0
ar z=0x1
aezi
pi 1
aezs 1
echo -- XB pma,EQ taken into page 0x3F
ar pc
w0 8192 @ 0
wx d1561000 @ 0
ara0
ar z=0x0
aezi
pi 1
aezs 1
echo -- XB pma,EQ not taken stays in page 0x3F
ar pc
w0 8192 @ 0
wx ef561000 @ 0
ara0
ar sp=0x100
aezi
pi 1
aezs 1
echo -- XCALL pma pushes one word
ar pc
ar sp
w0 8192 @ 0
wx ff56 @ 0
wx 3412 @ 512
ara0
ar sp=0x101
aezi
pi 1
aezs 1
echo -- XRETC UNC returns into page 0x3F
ar pc
ar sp
w0 8192 @ 0
wx 0a561000 @ 0
ara0
ar arp=0x2
ar xar2=0x5
aezi
pi 1
aezs 1
echo -- XBANZ ++ taken
ar pc
ar xar2
w0 8192 @ 0
wx 0a561000 @ 0
ara0
ar arp=0x2
ar xar2=0x0
aezi
pi 1
aezs 1
echo -- XBANZ ++ not taken
ar pc
ar xar2
w0 8192 @ 0
wx 5156a400 @ 0
ara0
ar n=0x0
ar z=0x1
ar p=0x5
ar xar4=0x7
aezi
pi 1
aezs 1
echo -- MAXCUL P, equal high halves
ar p
ar v
w0 8192 @ 0
wx 5956a400 @ 0
ara0
ar n=0x0
ar z=0x0
ar p=0x5
ar xar4=0x7
aezi
pi 1
aezs 1
echo -- MINCUL P, higher high half
ar p
w0 8192 @ 0
wx 7aff @ 0
ara0
ar acc=0x20000000
ar xar2=0x9
aezi
pi 1
aezs 1
echo -- NORM ACC,XAR2++ shifts
ar acc
ar tc
ar xar2
w0 8192 @ 0
wx 7aff @ 0
ara0
ar acc=0x40000000
ar xar2=0x9
aezi
pi 1
aezs 1
echo -- NORM ACC,XAR2++ stops
ar acc
ar tc
ar xar2
w0 8192 @ 0
wx 1956 @ 0
ara0
ar arp=0x3
ar xar3=0x2
ar xar0=0x5
aezi
pi 1
aezs 1
echo -- CMPR 1: ARARP AR0
ar tc
w0 8192 @ 0
wx 1856 @ 0
ara0
ar arp=0x3
ar xar3=0x2
ar xar0=0x5
ar tc=0x1
aezi
pi 1
aezs 1
echo -- CMPR 2: ARARP AR0
ar tc
w0 8192 @ 0
wx a92c0100 @ 0
ara0
ar acc=0x0
aezi
pi 1
aezs 1
echo -- LOOPZ AL,1 loops
ar pc
ar loop
w0 8192 @ 0
wx a92c0100 @ 0
ara0
ar acc=0x1
aezi
pi 1
aezs 1
echo -- LOOPZ AL,1 exits
ar pc
ar loop
w0 8192 @ 0
wx 22761a76 @ 0
ara0
aezi
pi 1
aezs 1
echo -- EALLOW then EDIS
ar eallow
w0 8192 @ 0
wx 00775b3e @ 0
ara0
aezi
pi 2
aezs 2
echo -- MOV XAR3,PC after a NOP
ar xar3
w0 8192 @ 0
wx 842c0100 @ 0
wx 000000000100 @ 512
ara0
ar xar4=0x100
aezi
pi 1
aezs 1
echo -- LOOPZ *XAR4++,1 steps the pointer while it loops
ar pc
ar xar4
ar loop
w0 8192 @ 0
wx 842c0100 @ 0
wx 000000000100 @ 512
ara0
ar xar4=0x100
aezi
pi 1
aezs 3
echo -- LOOPZ *XAR4++,1 exits past the first word with bit 0 set
ar pc
ar xar4
ar loop
EOF
EXPECT=<<EOF
xb 0x7e0020, eq
-- XB pma,EQ taken into page 0x3F
pc = 0x007e0020
xb 0x7e0020, eq
-- XB pma,EQ not taken stays in page 0x3F
pc = 0x007e0004
xcall 0x7e0020, unc
-- XCALL pma pushes one word
pc = 0x007e0020
sp = 0x0101
xret
-- XRETC UNC returns into page 0x3F
pc = 0x007e2468
sp = 0x0100
xbanz 0x7e0020, *++
-- XBANZ ++ taken
pc = 0x007e0020
xar2 = 0x00000006
xbanz 0x7e0020, *++
-- XBANZ ++ not taken
pc = 0x00000004
xar2 = 0x00000001
maxcul p, @xar4
-- MAXCUL P, equal high halves
p = 0x00000007
v = 0x1
mincul p, @xar4
-- MINCUL P, higher high half
p = 0x00000007
norm acc, xar2++
-- NORM ACC,XAR2++ shifts
acc = 0x40000000
tc = 0x0
xar2 = 0x0000000a
norm acc, xar2++
-- NORM ACC,XAR2++ stops
acc = 0x40000000
tc = 0x1
xar2 = 0x00000009
cmpr #0x1
-- CMPR 1: ARARP AR0
tc = 0x1
cmpr #0x2
-- CMPR 2: ARARP AR0
tc = 0x0
loopz @al, #0x1
-- LOOPZ AL,1 loops
pc = 0x00000000
loop = 0x1
loopz @al, #0x1
-- LOOPZ AL,1 exits
pc = 0x00000004
loop = 0x0
eallow
-- EALLOW then EDIS
eallow = 0x1
nop
mov xar3, pc
-- MOV XAR3,PC after a NOP
xar3 = 0x00000001
loopz *xar4++, #0x1
-- LOOPZ *XAR4++,1 steps the pointer while it loops
pc = 0x00000000
xar4 = 0x00000101
loop = 0x1
loopz *xar4++, #0x1
-- LOOPZ *XAR4++,1 exits past the first word with bit 0 set
pc = 0x00000004
xar4 = 0x00000103
loop = 0x0
EOF
RUN

NAME=C28x RzIL VM: interrupts and status saves
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 250000000000000000000000000100000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033560276 @ 0
ara0
ar sp=0x80
ar vmap=0x0
aezi
pi 1
aezs 1
echo -- TRAP 5 saves 7 pairs and vectors
ar pc
ar sp
ar intm
ar dbgm
w0 8192 @ 0
wx 250000000000000000000000000100000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033560276 @ 0
ara0
ar sp=0x80
ar acc=0x12345678
ar n=0x1
ar vmap=0x0
aezi
pi 1
pi 2 @ 0x200
aezs 3
echo -- TRAP 5, ISR, IRET restores all
ar pc
ar sp
ar acc
ar n
ar z
ar intm
ar dbgm
w0 8192 @ 0
wx 120000000000000000000000000100000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033560276 @ 0
ara0
ar sp=0x80
ar ier=0xffff
ar ifr=0x4
ar vmap=0x0
aezi
pi 1
aezs 1
echo -- INTR INT3 clears IFR and IER bit 2
ar pc
ar ier
ar ifr
ar intm
w0 8192 @ 0
wx 187633561376 @ 0
ara0
ar sp=0x80
ar acc=0x7
ar n=0x1
ar c=0x1
ar ovc=0x5
ar pm=0x2
aezi
pi 3
aezs 3
echo -- PUSH ST0, ZAPA, POP ST0
ar pc
ar acc
ar n
ar z
ar c
ar ovc
ar pm
ar sp
w0 8192 @ 0
wx 0876227600763356 @ 0
ara0
ar sp=0x80
ar acc=0x7
ar arp=0x5
ar intm=0x1
aezi
pi 4
aezs 4
echo -- PUSH ST1, EALLOW, POP ST1, ZAPA
ar pc
ar acc
ar eallow
ar arp
ar intm
ar sp
EOF
EXPECT=<<EOF
trap #0x5
-- TRAP 5 saves 7 pairs and vectors
pc = 0x00000200
sp = 0x008f
intm = 0x1
dbgm = 0x1
trap #0x5
zapa
iret
-- TRAP 5, ISR, IRET restores all
pc = 0x00000002
sp = 0x0080
acc = 0x12345678
n = 0x1
z = 0x0
intm = 0x0
dbgm = 0x0
intr int3
-- INTR INT3 clears IFR and IER bit 2
pc = 0x00000200
ier = 0xfffb
ifr = 0x0000
intm = 0x1
push st0
zapa
pop st0
-- PUSH ST0, ZAPA, POP ST0
pc = 0x00000006
acc = 0x00000000
n = 0x1
z = 0x0
c = 0x1
ovc = 0x05
pm = 0x2
sp = 0x0080
push st1
eallow
pop st1
zapa
-- PUSH ST1, EALLOW, POP ST1, ZAPA
pc = 0x00000008
acc = 0x00000000
eallow = 0x0
arp = 0x5
intm = 0x1
sp = 0x0080
EOF
RUN

NAME=C28x RzIL VM: byte moves, with SPRU430F's byte-swap example
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx dac6cac7d238c239 @ 0
wx 11223344 @ 128
ara0
ar xar2=0x40
ar acc=0xffffffff
aezi
pi 4
aezs 4
echo -- MOVB byte swap SPRU430F example
ar acc
ar pc
w0 8192 @ 0
wx ca3ccac7 @ 0
wx 11223344 @ 128
ara0
ar xar2=0x40
ar acc=0xab
aezi
pi 2
aezs 2
echo -- MOVB store to an odd byte, reload
ar acc
w0 8192 @ 0
wx d238 @ 0
wx 11223344 @ 128
ara0
ar xar2=0x40
ar acc=0xcd
aezi
pi 1
aezs 1
echo -- MOVB AL.MSB keeps AL.LSB
ar acc
ar n
w0 8192 @ 0
wx aec6aec7 @ 0
wx 3412 @ 512
wx 7856 @ 528
ara0
ar arp=0x2
ar xar2=0x100
ar xar0=0x8
ar acc=0x0
aezi
pi 2
aezs 2
echo -- MOVB AL.LSB then AH.LSB,*BR0++ with AR0 8
ar acc
ar xar2
EOF
EXPECT=<<EOF
movb al.lsb, *+xar2[3]
movb ah.lsb, *+xar2[1]
movb al.msb, *+xar2[2]
movb ah.msb, *+xar2[0]
-- MOVB byte swap SPRU430F example
acc = 0x11223344
pc = 0x00000008
movb *+xar2[1], al.lsb
movb ah.lsb, *+xar2[1]
-- MOVB store to an odd byte, reload
acc = 0x00ab00ab
movb al.msb, *+xar2[2]
-- MOVB AL.MSB keeps AL.LSB
acc = 0x000033cd
n = 0x0
movb al.lsb, *br0++
movb ah.lsb, *br0++
-- MOVB AL.LSB then AH.LSB,*BR0++ with AR0 8
acc = 0x00780034
xar2 = 0x00000104
EOF
RUN

# VCU

NAME=C28x RzIL VM: VCU status fields and clears
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 45e5 @ 0
ara0
ar vstatus=0x3000
aezi
pi 1
aezs 1
echo -- VSETSHR 5 keeps the other fields
ar vstatus
w0 8192 @ 0
wx c3e5 @ 0
ara0
aezi
pi 1
aezs 1
echo -- VSETSHL 3
ar vstatus
w0 8192 @ 0
wx 06e5 @ 0
ara0
aezi
pi 1
aezs 1
echo -- VSATON
ar vstatus
w0 8192 @ 0
wx 07e5 @ 0
ara0
ar vstatus=0x400
aezi
pi 1
aezs 1
echo -- VSATOFF
ar vstatus
w0 8192 @ 0
wx 08e5 @ 0
ara0
aezi
pi 1
aezs 1
echo -- VRNDON
ar vstatus
w0 8192 @ 0
wx 0be5 @ 0
ara0
ar vstatus=0x3000
aezi
pi 1
aezs 1
echo -- A_VCLROVFI clears the imaginary flag
ar vstatus
w0 8192 @ 0
wx 0ae5 @ 0
ara0
ar vstatus=0x3000
aezi
pi 1
aezs 1
echo -- A_VCLROVFR clears the real flag
ar vstatus
w0 8192 @ 0
wx 21e523e52ce520e5 @ 0
ara0
ar vstatus=0x40000000
aezi
pi 4
aezs 4
echo -- VSETCPACK, VSETOPACK, VSETCRCMSGFLIP, VCLRDIVE
ar vstatus
w0 8192 @ 0
wx f2e60509 @ 0
ara0
ar vstatus=0x38000000
aezi
pi 1
aezs 1
echo -- VSETK 5
ar vstatus
w0 8192 @ 0
wx f8e60300 @ 0
ara0
ar vr3=0x1234
ar vr4=0x7
aezi
pi 1
aezs 1
echo -- VCLEAR VR3
ar vr3
ar vr4
w0 8192 @ 0
wx f9e60000 @ 0
ara0
ar vr0=0x1
ar vr8=0x2
ar vt1=0x3
ar vcrc=0x4
aezi
pi 1
aezs 1
echo -- VCLEARALL
ar vr0
ar vr8
ar vt1
ar vcrc
w0 8192 @ 0
wx 29e524e5 @ 0
ara0
ar vt0=0x5
ar vt1=0x6
ar vcrc=0xdeadbeef
aezi
pi 2
aezs 2
echo -- VTCLEAR, VCRCCLR
ar vt0
ar vt1
ar vcrc
EOF
EXPECT=<<EOF
vsetshr #0x5
-- VSETSHR 5 keeps the other fields
vstatus = 0x00003005
vsetshl #0x3
-- VSETSHL 3
vstatus = 0x00000060
vsaton
-- VSATON
vstatus = 0x00000400
vsatoff
-- VSATOFF
vstatus = 0x00000000
vrndon
-- VRNDON
vstatus = 0x00000800
a_vclrovfi
-- A_VCLROVFI clears the imaginary flag
vstatus = 0x00001000
a_vclrovfr
-- A_VCLROVFR clears the real flag
vstatus = 0x00002000
vsetcpack
vsetopack
vsetcrcmsgflip
vclrdive
-- VSETCPACK, VSETOPACK, VSETCRCMSGFLIP, VCLRDIVE
vstatus = 0x8000c000
vsetk #0x5
-- VSETK 5
vstatus = 0x28000000
vclear vr3
-- VCLEAR VR3
vr3 = 0x00000000
vr4 = 0x00000007
vclearall
-- VCLEARALL
vr0 = 0x00000000
vr8 = 0x00000000
vt1 = 0x00000000
vcrc = 0x00000004
vtclear
vcrcclr
-- VTCLEAR, VCRCCLR
vt0 = 0x00000000
vt1 = 0x00000000
vcrc = 0x00000000
EOF
RUN

NAME=C28x RzIL VM: VCU moves
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx f0e38401 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- VMOV32 VR1,XAR4++
ar vr1
ar xar4
w0 8192 @ 0
wx 04e28402f0e38c03 @ 0
ara0
ar xar4=0x40
ar vr2=0xcafef00d
aezi
pi 2
aezs 2
echo -- VMOV32 XAR4++,VR2 read back
ar vr3
ar xar4
w0 8192 @ 0
wx c9e28401 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
ar vr1=0xaaaaaaaa
aezi
pi 1
aezs 1
echo -- VMOV16 VR1L,XAR4++ keeps VR1H
ar vr1
ar xar4
w0 8192 @ 0
wx c9e28411 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
ar vr1=0xaaaaaaaa
aezi
pi 1
aezs 1
echo -- VMOV16 VR1H,XAR4++ keeps VR1L
ar vr1
w0 8192 @ 0
wx 18e28412c9e28c03 @ 0
ara0
ar xar4=0x40
ar vr2=0xbeef0000
aezi
pi 2
aezs 2
echo -- VMOV16 XAR4++,VR2H read back
ar vr3
ar xar4
w0 8192 @ 0
wx f2e6080a @ 0
ara0
ar vr0=0x11112222
ar vr1=0x33334444
aezi
pi 1
aezs 1
echo -- VMOV16 VR0L,VR1H
ar vr0
w0 8192 @ 0
wx f2e64502 @ 0
ara0
ar vr5=0x12345678
aezi
pi 1
aezs 1
echo -- VMOV32 VR4,VR5
ar vr4
w0 8192 @ 0
wx f2e61203 @ 0
ara0
ar vr1=0x1
ar vr2=0x2
aezi
pi 1
aezs 1
echo -- VSWAP32 VR1,VR2
ar vr1
ar vr2
w0 8192 @ 0
wx f1e74123 @ 0
ara0
ar vr1=0xffffffff
aezi
pi 1
aezs 1
echo -- VMOVZI VR1,0x1234 clears the high half
ar vr1
w0 8192 @ 0
wx 7be7f1ee @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VMOVXI VR1,0xbeef
ar vr1
w0 8192 @ 0
wx ede7d1ea @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VMOVIX VR1,0xdead
ar vr1
w0 8192 @ 0
wx 24e2c401f0e3d402 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 2
aezs 2
echo -- VMOVD32 copies two words up
ar vr1
ar vr2
w0 8192 @ 0
wx f0e3c411 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
ar vr1=0xffff0000
aezi
pi 1
aezs 1
echo -- VXORMOV32 VR1,+XAR40
ar vr1
w0 8192 @ 0
wx b0e2c400 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- VMOV32 VSTATUS,mem32
ar vstatus
w0 8192 @ 0
wx f1e3c401 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- VMOV32 VT1,mem32
ar vt1
w0 8192 @ 0
wx 80e2c421 @ 0
wx 78563412 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- VMOV32 VSM3:VSM2,mem32
ar vsm3
ar vsm2
w0 8192 @ 0
wx 0ee2c401f0e3c401 @ 0
ara0
ar xar4=0x40
ar vsm3=0xaaaa
ar vsm2=0xbbbb
aezi
pi 2
aezs 2
echo -- VMOV32 mem32,VSM3:VSM2 read back
ar vr1
w0 8192 @ 0
wx 84bd4000f0e3c501 @ 0
wx bebafeca @ 160
ara0
ar xar4=0x50
ar xar5=0x40
aezi
pi 2
aezs 2
echo -- VMOV32 0:16bit,XAR4++ read back
ar vr1
ar xar4
w0 8192 @ 0
wx 56e70503 @ 0
ara0
aezi
pi 1
aezs 1
echo -- VSETCRCSIZE 5:3
ar vcrcsize
w0 8192 @ 0
wx cbe2c405 @ 0
wx 0600 @ 128
ara0
ar xar4=0x40
ar vcrcsize=0x1f0001
aezi
pi 1
aezs 1
echo -- VMOV16 VCRCDSIZE,mem16 sets DSIZE only
ar vcrcsize
EOF
EXPECT=<<EOF
vmov32 vr1, *xar4++
-- VMOV32 VR1,XAR4++
vr1 = 0x12345678
xar4 = 0x00000042
vmov32 *xar4++, vr2
vmov32 vr3, *--xar4
-- VMOV32 XAR4++,VR2 read back
vr3 = 0xcafef00d
xar4 = 0x00000040
vmov16 vr1l, *xar4++
-- VMOV16 VR1L,XAR4++ keeps VR1H
vr1 = 0xaaaa5678
xar4 = 0x00000041
vmov16 vr1h, *xar4++
-- VMOV16 VR1H,XAR4++ keeps VR1L
vr1 = 0x5678aaaa
vmov16 *xar4++, vr2h
vmov16 vr3l, *--xar4
-- VMOV16 XAR4++,VR2H read back
vr3 = 0x0000beef
xar4 = 0x00000040
vmov16 vr0l, vr1h
-- VMOV16 VR0L,VR1H
vr0 = 0x11113333
vmov32 vr4, vr5
-- VMOV32 VR4,VR5
vr4 = 0x12345678
vswap32 vr1, vr2
-- VSWAP32 VR1,VR2
vr1 = 0x00000002
vr2 = 0x00000001
vmovzi vr1, #0x1234
-- VMOVZI VR1,0x1234 clears the high half
vr1 = 0x00001234
vmovxi vr1, #0xbeef
-- VMOVXI VR1,0xbeef
vr1 = 0x1234beef
vmovix vr1, #0xdead
-- VMOVIX VR1,0xdead
vr1 = 0xdead5678
vmovd32 vr1, *+xar4[0]
vmov32 vr2, *+xar4[2]
-- VMOVD32 copies two words up
vr1 = 0x12345678
vr2 = 0x12345678
vxormov32 vr1, *+xar4[0]
-- VXORMOV32 VR1,+XAR40
vr1 = 0xedcb5678
vmov32 vstatus, *+xar4[0]
-- VMOV32 VSTATUS,mem32
vstatus = 0x12345678
vmov32 vt1, *+xar4[0]
-- VMOV32 VT1,mem32
vt1 = 0x12345678
vmov32 vsm3:vsm2, *+xar4[0]
-- VMOV32 VSM3:VSM2,mem32
vsm3 = 0x1234
vsm2 = 0x5678
vmov32 *+xar4[0], vsm3:vsm2
vmov32 vr1, *+xar4[0]
-- VMOV32 mem32,VSM3:VSM2 read back
vr1 = 0xaaaabbbb
vmov32 *(0:0x80), *xar4++
vmov32 vr1, *+xar5[0]
-- VMOV32 0:16bit,XAR4++ read back
vr1 = 0xcafebabe
xar4 = 0x00000052
vsetcrcsize #5:#3
-- VSETCRCSIZE 5:3
vcrcsize = 0x00050003
vmov16 vcrcdsize, *+xar4[0]
-- VMOV16 VCRCDSIZE,mem16 sets DSIZE only
vcrcsize = 0x001f0006
EOF
RUN

NAME=C28x RzIL VM: VCU CRC, against TI linker CRC tables
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 24e5cbe2c400cce28400cbe2c400cce28400cbe2c400cce28400cbe2c400cce28400 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC8 over 12345678: TI linker CRC8_PRIME
ar vcrc
w0 8192 @ 0
wx 24e5cee2c400cfe28400cee2c400cfe28400cee2c400cfe28400cee2c400cfe28400 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC16P1: TI linker CRC16_ALT
ar vcrc
w0 8192 @ 0
wx 24e5cee2c410cfe28410cee2c410cfe28410cee2c410cfe28410cee2c410cfe28410 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC16P2: TI linker CRC16_802_15_4
ar vcrc
w0 8192 @ 0
wx 24e5cbe2c401cbe28402cbe2c401cbe28402cbe2c401cbe28402cbe2c401cbe28402 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC24: TI linker CRC24_FLEXRAY
ar vcrc
w0 8192 @ 0
wx 24e5c1e2c400c2e28400c1e2c400c2e28400c1e2c400c2e28400c1e2c400c2e28400 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC32: TI linker CRC32_PRIME
ar vcrc
ar xar4
w0 8192 @ 0
wx 24e5cbe2c403cbe28404cbe2c403cbe28404cbe2c403cbe28404cbe2c403cbe28404 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 9
aezs 9
echo -- VCRC32P2: TI linker CRC32_C
ar vcrc
w0 8192 @ 0
wx 24e5cbe2c400cce28400cbe2c400cce28400cbe2c400cce28400cbe2c400cce28400 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
ar vstatus=0x80000000
aezi
pi 9
aezs 9
echo -- VCRC8 with CRCMSGFLIP
ar vcrc
w0 8192 @ 0
wx cbe2c400 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
ar vcrc=0xabcd0000
aezi
pi 1
aezs 1
echo -- VCRC8 keeps VCRC31:8
ar vcrc
w0 8192 @ 0
wx 54e7211056e70f0724e5cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 11
aezs 11
echo -- VCRCL/VCRCH 16-bit poly 0x1021 CRC16_802_15_4
ar vcrc
w0 8192 @ 0
wx 54e7070056e7070324e5cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
aezi
pi 11
aezs 11
echo -- VCRCL/VCRCH 8-bit CRC of 4-bit data
ar vcrc
w0 8192 @ 0
wx 54e7070056e7070324e5cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407cbe2c406cbe28407 @ 0
wx 3132333435363738 @ 128
ara0
ar xar4=0x40
ar vstatus=0x80000000
aezi
pi 11
aezs 11
echo -- VCRCL/VCRCH 4-bit data, flipped
ar vcrc
w0 8192 @ 0
wx 2ee5 @ 0
ara0
ar vcrc=0x12345678
aezi
pi 1
aezs 1
echo -- VSWAPCRC
ar vcrc
EOF
EXPECT=<<EOF
vcrcclr
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
-- VCRC8 over 12345678: TI linker CRC8_PRIME
vcrc = 0x000000c7
vcrcclr
vcrc16p1l_1 *+xar4[0]
vcrc16p1h_1 *xar4++
vcrc16p1l_1 *+xar4[0]
vcrc16p1h_1 *xar4++
vcrc16p1l_1 *+xar4[0]
vcrc16p1h_1 *xar4++
vcrc16p1l_1 *+xar4[0]
vcrc16p1h_1 *xar4++
-- VCRC16P1: TI linker CRC16_ALT
vcrc = 0x000095fd
vcrcclr
vcrc16p2l_1 *+xar4[0]
vcrc16p2h_1 *xar4++
vcrc16p2l_1 *+xar4[0]
vcrc16p2h_1 *xar4++
vcrc16p2l_1 *+xar4[0]
vcrc16p2h_1 *xar4++
vcrc16p2l_1 *+xar4[0]
vcrc16p2h_1 *xar4++
-- VCRC16P2: TI linker CRC16_802_15_4
vcrc = 0x00009015
vcrcclr
vcrc24l_1 *+xar4[0]
vcrc24h_1 *xar4++
vcrc24l_1 *+xar4[0]
vcrc24h_1 *xar4++
vcrc24l_1 *+xar4[0]
vcrc24h_1 *xar4++
vcrc24l_1 *+xar4[0]
vcrc24h_1 *xar4++
-- VCRC24: TI linker CRC24_FLEXRAY
vcrc = 0x00fe2631
vcrcclr
vcrc32l_1 *+xar4[0]
vcrc32h_1 *xar4++
vcrc32l_1 *+xar4[0]
vcrc32h_1 *xar4++
vcrc32l_1 *+xar4[0]
vcrc32h_1 *xar4++
vcrc32l_1 *+xar4[0]
vcrc32h_1 *xar4++
-- VCRC32: TI linker CRC32_PRIME
vcrc = 0x20e779a2
xar4 = 0x00000044
vcrcclr
vcrc32p2l_1 *+xar4[0]
vcrc32p2h_1 *xar4++
vcrc32p2l_1 *+xar4[0]
vcrc32p2h_1 *xar4++
vcrc32p2l_1 *+xar4[0]
vcrc32p2h_1 *xar4++
vcrc32p2l_1 *+xar4[0]
vcrc32p2h_1 *xar4++
-- VCRC32P2: TI linker CRC32_C
vcrc = 0xf9ef9da2
vcrcclr
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
vcrc8l_1 *+xar4[0]
vcrc8h_1 *xar4++
-- VCRC8 with CRCMSGFLIP
vcrc = 0x000000f1
vcrc8l_1 *+xar4[0]
-- VCRC8 keeps VCRC31:8
vcrc = 0xabcd0097
vmovzi vcrcpoly, #0x1021
vsetcrcsize #15:#7
vcrcclr
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
-- VCRCL/VCRCH 16-bit poly 0x1021 CRC16_802_15_4
vcrc = 0x00009015
vmovzi vcrcpoly, #0x7
vsetcrcsize #7:#3
vcrcclr
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
-- VCRCL/VCRCH 8-bit CRC of 4-bit data
vcrc = 0x0000001c
vmovzi vcrcpoly, #0x7
vsetcrcsize #7:#3
vcrcclr
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
vcrcl *+xar4[0]
vcrch *xar4++
-- VCRCL/VCRCH 4-bit data, flipped
vcrc = 0x000000fd
vswapcrc
-- VSWAPCRC
vcrc = 0x12347856
EOF
RUN

NAME=C28x RzIL VM: VCU shifts, increments and reversals
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx f2e62105 @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VLSHL32 VR14
ar vr1
w0 8192 @ 0
wx f2e62106 @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VLSHR32 VR14
ar vr1
w0 8192 @ 0
wx f2e61908 @ 0
ara0
ar vr1=0xd
aezi
pi 1
aezs 1
echo -- VASHR32 133 truncates to 1
ar vr1
w0 8192 @ 0
wx f2e61908 @ 0
ara0
ar vr1=0xd
ar vstatus=0x800
aezi
pi 1
aezs 1
echo -- VASHR32 133 rounds to 2 SPRUHS1C 1.625
ar vr1
w0 8192 @ 0
wx f2e61908 @ 0
ara0
ar vr1=0xfffffff3
ar vstatus=0x800
aezi
pi 1
aezs 1
echo -- VASHR32 -133 rounds to -2
ar vr1
w0 8192 @ 0
wx f2e62107 @ 0
ara0
ar vr1=0x8000000
aezi
pi 1
aezs 1
echo -- VASHL32 overflow wraps, OVFR
ar vr1
ar vstatus
w0 8192 @ 0
wx f2e62107 @ 0
ara0
ar vr1=0x8000000
ar vstatus=0x400
aezi
pi 1
aezs 1
echo -- VASHL32 overflow saturates with SAT
ar vr1
ar vstatus
w0 8192 @ 0
wx f2e62107 @ 0
ara0
ar vr1=0xf0000000
ar vstatus=0x400
aezi
pi 1
aezs 1
echo -- VASHL32 negative saturates
ar vr1
ar vstatus
w0 8192 @ 0
wx f2e62107 @ 0
ara0
ar vr1=0x100000
aezi
pi 1
aezs 1
echo -- VASHL32 no overflow
ar vr1
ar vstatus
w0 8192 @ 0
wx f2e6010b @ 0
ara0
ar vr1=0x1234ffff
aezi
pi 1
aezs 1
echo -- VINC VR1L wraps
ar vr1
w0 8192 @ 0
wx f2e6090b @ 0
ara0
ar vr1=0x12340000
aezi
pi 1
aezs 1
echo -- VDEC VR1L wraps
ar vr1
w0 8192 @ 0
wx 81e28411 @ 0
wx 78563412 @ 128
ara0
ar vr1=0x5
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- VINC VR1L par VMOV32 VR2,XAR4++
ar vr1
ar vr2
ar xar4
w0 8192 @ 0
wx 21a10000 @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VBITFLIP VR1
ar vr1
w0 8192 @ 0
wx 80e60124 @ 0
ara0
ar vr1=0x12345678
aezi
pi 1
aezs 1
echo -- VREVB VR1
ar vr1
EOF
EXPECT=<<EOF
vlshl32 vr1 << #4
-- VLSHL32 VR14
vr1 = 0x23456780
vlshr32 vr1 >> #4
-- VLSHR32 VR14
vr1 = 0x01234567
vashr32 vr1 >> #3
-- VASHR32 133 truncates to 1
vr1 = 0x00000001
vashr32 vr1 >> #3
-- VASHR32 133 rounds to 2 SPRUHS1C 1.625
vr1 = 0x00000002
vashr32 vr1 >> #3
-- VASHR32 -133 rounds to -2
vr1 = 0xfffffffe
vashl32 vr1 << #4
-- VASHL32 overflow wraps, OVFR
vr1 = 0x80000000
vstatus = 0x00001000
vashl32 vr1 << #4
-- VASHL32 overflow saturates with SAT
vr1 = 0x7fffffff
vstatus = 0x00001400
vashl32 vr1 << #4
-- VASHL32 negative saturates
vr1 = 0x80000000
vstatus = 0x00001400
vashl32 vr1 << #4
-- VASHL32 no overflow
vr1 = 0x01000000
vstatus = 0x00000000
vinc vr1l
-- VINC VR1L wraps
vr1 = 0x12340000
vdec vr1l
-- VDEC VR1L wraps
vr1 = 0x1234ffff
vinc vr1l || vmov32 vr2, *xar4++
-- VINC VR1L par VMOV32 VR2,XAR4++
vr1 = 0x00000006
vr2 = 0x12345678
xar4 = 0x00000042
vbitflip vr1
-- VBITFLIP VR1
vr1 = 0x1e6a2c48
vrevb vr1
-- VREVB VR1
vr1 = 0x78563412
EOF
RUN

# FPU32, FPU64 and TMU

NAME=C28x RzIL VM: FPU arithmetic, compare and 32-bit conversions
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 10e78800 @ 0
ara0
ar r1=0x3fc0000000000000
ar r2=0x4010000000000000
aezi
pi 1
aezs 1
echo -- ADDF32 1.5 + 2.25
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 00e78800 @ 0
ara0
ar r1=0x7f00000000000000
ar r2=0x4000000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 overflow, truncating: max, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 00e78800 @ 0
ara0
ar r1=0x7f00000000000000
ar r2=0x4000000000000000
ar rnd32=0x1
aezi
pi 1
aezs 1
echo -- MPYF32 overflow, to nearest: +inf, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 00e78800 @ 0
ara0
ar r1=0x7f7fffff00000000
ar r2=0x3f80000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 max1: exact, no LVF
ar r0
ar lvf
w0 8192 @ 0
wx 00e78800 @ 0
ara0
ar r1=0x80000000000000
ar r2=0x3f00000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 tiny product: +0, LUF
ar r0
ar luf
w0 8192 @ 0
wx 10e78800 @ 0
ara0
ar r1=0x100000000
ar r2=0x4010000000000000
aezi
pi 1
aezs 1
echo -- ADDF32 denormal operand counts as 0
ar r0
ar luf
w0 8192 @ 0
wx 94e61100 @ 0
ara0
ar r1=0x3fc0000000000000
ar r2=0x4010000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- CMPF32 1.5 2.25
ar nf
ar zf
w0 8192 @ 0
wx 89e60800 @ 0
ara0
ar r1=0xfffffffd00000000
aezi
pi 1
aezs 1
echo -- I32TOF32 -3
ar r0
w0 8192 @ 0
wx 88e60800 @ 0
ara0
ar r1=0xc060000000000000
aezi
pi 1
aezs 1
echo -- F32TOI32 -3.5 truncates
ar r0
EOF
EXPECT=<<EOF
addf32 r0h, r1h, r2h
-- ADDF32 1.5 + 2.25
r0 = 0x4070000000000000
lvf = 0x0
luf = 0x0
mpyf32 r0h, r1h, r2h
-- MPYF32 overflow, truncating: max, LVF
r0 = 0x7f7fffff00000000
lvf = 0x1
mpyf32 r0h, r1h, r2h
-- MPYF32 overflow, to nearest: +inf, LVF
r0 = 0x7f80000000000000
lvf = 0x1
mpyf32 r0h, r1h, r2h
-- MPYF32 max1: exact, no LVF
r0 = 0x7f7fffff00000000
lvf = 0x0
mpyf32 r0h, r1h, r2h
-- MPYF32 tiny product: +0, LUF
r0 = 0x0000000000000000
luf = 0x1
addf32 r0h, r1h, r2h
-- ADDF32 denormal operand counts as 0
r0 = 0x4010000000000000
luf = 0x0
cmpf32 r1h, r2h
-- CMPF32 1.5 2.25
nf = 0x1
zf = 0x0
i32tof32 r0h, r1h
-- I32TOF32 -3
r0 = 0xc040000000000000
f32toi32 r0h, r1h
-- F32TOI32 -3.5 truncates
r0 = 0xfffffffd00000000
EOF
RUN

NAME=C28x RzIL VM: FPU moves between CPU and FPU registers
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx a9bd120f @ 0
wx 00000040 @ 128
ara0
ar acc=0x12345678
ar r0=0xaaaaaaaa
aezi
pi 1
aezs 1
echo -- MOV32 R0H,ACC keeps R0L
ar r0
w0 8192 @ 0
wx a9bd100f @ 0
wx 00000040 @ 128
ara0
ar acc=0x12345678
ar r0=0xbbbbbbbb00000000
aezi
pi 1
aezs 1
echo -- MOV32 R0L,ACC keeps R0H
ar r0
w0 8192 @ 0
wx a9bf2e0f @ 0
wx 00000040 @ 128
ara0
ar r7=0x8000000100000000
ar z=0x1
aezi
pi 1
aezs 1
echo -- MOV32 ACC,R7H sets N/Z
ar acc
ar n
ar z
w0 8192 @ 0
wx a5bf2e0f @ 0
wx 00000040 @ 128
ara0
ar r7=0x123400000000
ar z=0x1
ar n=0x1
aezi
pi 1
aezs 1
echo -- MOV32 XAR5,R7H no flags
ar xar5
ar z
ar n
w0 8192 @ 0
wx 84bd120f @ 0
wx 00000040 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MOV32 R0H,XAR4++ steps 2
ar r0
ar xar4
w0 8192 @ 0
wx afe28401 @ 0
wx 00000040 @ 128
ara0
ar xar4=0x40
ar zf=0x1
ar zi=0x1
aezi
pi 1
aezs 1
echo -- MOV32 R1H,XAR4++,UNCF steps 2, flags
ar r1
ar xar4
ar zf
ar nf
ar zi
ar ni
EOF
EXPECT=<<EOF
mov32 r0h, @acc
-- MOV32 R0H,ACC keeps R0L
r0 = 0x12345678aaaaaaaa
mov32 r0l, @acc
-- MOV32 R0L,ACC keeps R0H
r0 = 0xbbbbbbbb12345678
mov32 @acc, r7h
-- MOV32 ACC,R7H sets N/Z
acc = 0x80000001
n = 0x1
z = 0x0
mov32 @xar5, r7h
-- MOV32 XAR5,R7H no flags
xar5 = 0x00001234
z = 0x1
n = 0x1
mov32 r0h, *xar4++
-- MOV32 R0H,XAR4++ steps 2
r0 = 0x4000000000000000
xar4 = 0x00000042
mov32 r1h, *xar4++, uncf
-- MOV32 R1H,XAR4++,UNCF steps 2, flags
r1 = 0x4000000000000000
xar4 = 0x00000042
zf = 0x0
nf = 0x0
zi = 0x0
ni = 0x0
EOF
RUN

NAME=C28x RzIL VM: FPU immediates, sign operations, max/min and conversions
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 01e888ff0ce8c8cc04e9c8cc0ce9d0cc @ 0
wx feff @ 128
ara0
ar r0=0x123456789abcdef0
aezi
pi 4
aezs 4
echo -- MOVIZ/MOVXI/MOVIX/MOVXI: TI-compiled double 1.1
ar r0
w0 8192 @ 0
wx 02e82000 @ 0
wx feff @ 128
ara0
ar r0=0xffffffffffffffff
aezi
pi 1
aezs 1
echo -- MOVIZ R0,0x4004 alone is double 2.5
ar r0
w0 8192 @ 0
wx 90e5 @ 0
wx feff @ 128
ara0
ar r0=0xffffffffffffffff
aezi
pi 1
aezs 1
echo -- ZERO R0 clears all 64 bits
ar r0
w0 8192 @ 0
wx 63e5 @ 0
wx feff @ 128
ara0
ar r0=0x1111111111111111
ar r7=0x7777777777777777
aezi
pi 1
aezs 1
echo -- ZEROA clears R0-R7
ar r0
ar r7
w0 8192 @ 0
wx aee60800 @ 0
wx feff @ 128
ara0
ar r0=0x12345678
ar r1=0x4020000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- NEGF32 UNC flips the sign, keeps flags
ar r0
ar nf
ar zf
w0 8192 @ 0
wx afe60800 @ 0
wx feff @ 128
ara0
ar r1=0x4020000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- NEGF32 UNCF sets NF/ZF
ar r0
ar nf
ar zf
w0 8192 @ 0
wx a1e60800 @ 0
wx feff @ 128
ara0
ar r1=0x4020000000000000
ar zf=0x0
ar nf=0x1
aezi
pi 1
aezs 1
echo -- NEGF32 EQ false copies, keeps flags
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 95e60800 @ 0
wx feff @ 128
ara0
ar r1=0xc040000000000000
ar nf=0x1
aezi
pi 1
aezs 1
echo -- ABSF32 -3.0
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 95e60800 @ 0
wx feff @ 128
ara0
ar r1=0x8000000000000000
aezi
pi 1
aezs 1
echo -- ABSF32 -0.0: ZF
ar r0
ar zf
ar nf
w0 8192 @ 0
wx 96e60800 @ 0
wx feff @ 128
ara0
ar r0=0x3f80000000000000
ar r1=0x4000000000000000
aezi
pi 1
aezs 1
echo -- MAXF32 1 2
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 97e60800 @ 0
wx feff @ 128
ara0
ar r0=0x3f80000000000000
ar r1=0x4000000000000000
aezi
pi 1
aezs 1
echo -- MINF32 1 2 keeps
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 9ce68806 @ 0
wx feff @ 128
ara0
ar r0=0x3f80000000000000
ar r1=0x4000000000000000
ar r2=0x0
ar r3=0x700000000
aezi
pi 1
aezs 1
echo -- MAXF32 par MOV32 moves when replaced
ar r0
ar r2
w0 8192 @ 0
wx 9ce68806 @ 0
wx feff @ 128
ara0
ar r0=0x4040000000000000
ar r1=0x4000000000000000
ar r2=0x500000000
ar r3=0x700000000
aezi
pi 1
aezs 1
echo -- MAXF32 par MOV32 holds when kept
ar r0
ar r2
ar nf
ar zf
w0 8192 @ 0
wx 22e80000 @ 0
wx feff @ 128
ara0
ar r0=0x3f80000000000000
aezi
pi 1
aezs 1
echo -- MAXF32 R0H,2.0
ar r0
w0 8192 @ 0
wx 8be60800 @ 0
wx feff @ 128
ara0
ar r1=0xffffffff00000000
aezi
pi 1
aezs 1
echo -- UI32TOF32 0xffffffff
ar r0
w0 8192 @ 0
wx 8de60800 @ 0
wx feff @ 128
ara0
ar r1=0x1234ffff00000000
aezi
pi 1
aezs 1
echo -- I16TOF32 low half -1
ar r0
w0 8192 @ 0
wx 8fe60800 @ 0
wx feff @ 128
ara0
ar r1=0x1ffff00000000
aezi
pi 1
aezs 1
echo -- UI16TOF32 low half 65535
ar r0
w0 8192 @ 0
wx 8ce60800 @ 0
wx feff @ 128
ara0
ar r1=0xc02ccccd00000000
aezi
pi 1
aezs 1
echo -- F32TOI16 -2.7 truncates, sign-extends
ar r0
w0 8192 @ 0
wx 8ce60880 @ 0
wx feff @ 128
ara0
ar r1=0x4020000000000000
aezi
pi 1
aezs 1
echo -- F32TOI16R 2.5 to even
ar r0
w0 8192 @ 0
wx 8ce60880 @ 0
wx feff @ 128
ara0
ar r1=0xc71c400000000000
aezi
pi 1
aezs 1
echo -- F32TOI16R -40000 saturates
ar r0
w0 8192 @ 0
wx 8ee60800 @ 0
wx feff @ 128
ara0
ar r1=0x48927c0000000000
aezi
pi 1
aezs 1
echo -- F32TOUI16 300000 saturates SPRUHS1C
ar r0
w0 8192 @ 0
wx 8ee60880 @ 0
wx feff @ 128
ara0
ar r1=0x4060000000000000
aezi
pi 1
aezs 1
echo -- F32TOUI16R 3.5 to even
ar r0
w0 8192 @ 0
wx 8ae60800 @ 0
wx feff @ 128
ara0
ar r1=0xc0a0000000000000
aezi
pi 1
aezs 1
echo -- F32TOUI32 -5 saturates to 0
ar r0
w0 8192 @ 0
wx 8ae60800 @ 0
wx feff @ 128
ara0
ar r1=0x4f32d05e00000000
aezi
pi 1
aezs 1
echo -- F32TOUI32 3e9
ar r0
w0 8192 @ 0
wx 88e60800 @ 0
wx feff @ 128
ara0
ar r1=0x4f00000000000000
aezi
pi 1
aezs 1
echo -- F32TOI32 231 saturates
ar r0
w0 8192 @ 0
wx f1e60800 @ 0
wx feff @ 128
ara0
ar r1=0xc030000000000000
aezi
pi 1
aezs 1
echo -- FRACF32 -2.75
ar r0
w0 8192 @ 0
wx c8e28400 @ 0
wx feff @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- I16TOF32 R0H,XAR4++: mem16 steps 1
ar r0
ar xar4
EOF
EXPECT=<<EOF
moviz r0, #0x3ff1
movxi r0h, #0x9999
movix r0l, #0x9999
movxi r0l, #0x999a
-- MOVIZ/MOVXI/MOVIX/MOVXI: TI-compiled double 1.1
r0 = 0x3ff199999999999a
moviz r0, #0x4004
-- MOVIZ R0,0x4004 alone is double 2.5
r0 = 0x4004000000000000
zero r0
-- ZERO R0 clears all 64 bits
r0 = 0x0000000000000000
zeroa
-- ZEROA clears R0-R7
r0 = 0x0000000000000000
r7 = 0x0000000000000000
negf32 r0h, r1h, unc
-- NEGF32 UNC flips the sign, keeps flags
r0 = 0xc020000012345678
nf = 0x0
zf = 0x1
negf32 r0h, r1h, uncf
-- NEGF32 UNCF sets NF/ZF
r0 = 0xc020000000000000
nf = 0x1
zf = 0x0
negf32 r0h, r1h, eq
-- NEGF32 EQ false copies, keeps flags
r0 = 0x4020000000000000
nf = 0x1
zf = 0x0
absf32 r0h, r1h
-- ABSF32 -3.0
r0 = 0x4040000000000000
nf = 0x0
zf = 0x0
absf32 r0h, r1h
-- ABSF32 -0.0: ZF
r0 = 0x0000000000000000
zf = 0x1
nf = 0x0
maxf32 r0h, r1h
-- MAXF32 1 2
r0 = 0x4000000000000000
nf = 0x1
zf = 0x0
minf32 r0h, r1h
-- MINF32 1 2 keeps
r0 = 0x3f80000000000000
nf = 0x1
zf = 0x0
maxf32 r0h, r1h || mov32 r2h, r3h
-- MAXF32 par MOV32 moves when replaced
r0 = 0x4000000000000000
r2 = 0x0000000700000000
maxf32 r0h, r1h || mov32 r2h, r3h
-- MAXF32 par MOV32 holds when kept
r0 = 0x4040000000000000
r2 = 0x0000000500000000
nf = 0x0
zf = 0x0
maxf32 r0h, #0x4000
-- MAXF32 R0H,2.0
r0 = 0x4000000000000000
ui32tof32 r0h, r1h
-- UI32TOF32 0xffffffff
r0 = 0x4f80000000000000
i16tof32 r0h, r1h
-- I16TOF32 low half -1
r0 = 0xbf80000000000000
ui16tof32 r0h, r1h
-- UI16TOF32 low half 65535
r0 = 0x477fff0000000000
f32toi16 r0h, r1h
-- F32TOI16 -2.7 truncates, sign-extends
r0 = 0xfffffffe00000000
f32toi16r r0h, r1h
-- F32TOI16R 2.5 to even
r0 = 0x0000000200000000
f32toi16r r0h, r1h
-- F32TOI16R -40000 saturates
r0 = 0xffff800000000000
f32toui16 r0h, r1h
-- F32TOUI16 300000 saturates SPRUHS1C
r0 = 0x0000ffff00000000
f32toui16r r0h, r1h
-- F32TOUI16R 3.5 to even
r0 = 0x0000000400000000
f32toui32 r0h, r1h
-- F32TOUI32 -5 saturates to 0
r0 = 0x0000000000000000
f32toui32 r0h, r1h
-- F32TOUI32 3e9
r0 = 0xb2d05e0000000000
f32toi32 r0h, r1h
-- F32TOI32 231 saturates
r0 = 0x7fffffff00000000
fracf32 r0h, r1h
-- FRACF32 -2.75
r0 = 0xbf40000000000000
i16tof32 r0h, *xar4++
-- I16TOF32 R0H,XAR4++: mem16 steps 1
r0 = 0xc000000000000000
xar4 = 0x00000041
EOF
RUN

NAME=C28x RzIL VM: FPU status flags, SAVE/RESTORE, swaps, delay-line moves and RB
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 12e64002 @ 0
ara0
ar lvf=0x1
aezi
pi 1
aezs 1
echo -- SETFLG RNDF321,TF1
ar rnd32
ar tf
ar lvf
w0 8192 @ 0
wx 00e60008 @ 0
ara0
ar lvf=0x1
aezi
pi 1
aezs 1
echo -- SETFLG LVF0
ar lvf
w0 8192 @ 0
wx 91ad @ 0
ara0
ar lvf=0x1
ar luf=0x1
ar zf=0x1
ar tf=0x1
ar n=0x1
aezi
pi 1
aezs 1
echo -- MOVST0 LVF,ZF,TF: copies, clears LVF
ar v
ar z
ar c
ar tc
ar lvf
ar luf
ar n
w0 8192 @ 0
wx 0cad @ 0
ara0
ar ni=0x1
aezi
pi 1
aezs 1
echo -- MOVST0 NF,NI: N from NI
ar n
w0 8192 @ 0
wx 0cad @ 0
ara0
ar n=0x1
aezi
pi 1
aezs 1
echo -- MOVST0 NF,NI: N cleared
ar n
w0 8192 @ 0
wx 80e28400 @ 0
wx 45020080 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MOV32 STF,XAR4++: SHDWS kept
ar lvf
ar luf
ar nf
ar zf
ar tf
ar rnd32
ar shdws
ar xar4
w0 8192 @ 0
wx 00e28400afe28c00 @ 0
ara0
ar xar4=0x40
ar lvf=0x1
ar nf=0x1
ar tf=0x1
ar rnd32=0x1
aezi
pi 2
aezs 2
echo -- MOV32 XAR4++,STF read back
ar r0
ar xar4
w0 8192 @ 0
wx 50e60002 @ 0
ara0
ar r1=0xaabbccddeeff0011
ar tf=0x1
aezi
pi 1
aezs 1
echo -- SAVE RNDF321 shadows, sets SHDWS
ar r1s
ar stfs
ar rnd32
ar shdws
w0 8192 @ 0
wx 50e6000290e562e5 @ 0
ara0
ar r0=0x1122334455667788
ar tf=0x1
aezi
pi 3
aezs 3
echo -- SAVE, ZERO R0, RESTORE
ar r0
ar rnd32
ar tf
ar shdws
w0 8192 @ 0
wx 81e5 @ 0
ara0
ar zf=0x1
aezi
pi 1
aezs 1
echo -- TESTTF EQ true
ar tf
w0 8192 @ 0
wx 81e5 @ 0
ara0
ar tf=0x1
aezi
pi 1
aezs 1
echo -- TESTTF EQ false
ar tf
w0 8192 @ 0
wx eee60800 @ 0
ara0
ar r0=0x1111111122222222
ar r1=0x3333333344444444
aezi
pi 1
aezs 1
echo -- SWAPF R0,R1,UNC swaps whole registers
ar r0
ar r1
w0 8192 @ 0
wx 13e284008c92 @ 0
ara0
ar r0=0x1234567800000000
ar xar4=0x40
aezi
pi 2
aezs 2
echo -- MOV16 XAR4++,R0H stores 16 bits
ar acc
ar xar4
w0 8192 @ 0
wx 23e2c400afe2d401 @ 0
wx db0f4940 @ 128
ara0
ar xar4=0x40
ar zf=0x1
ar zi=0x1
aezi
pi 2
aezs 2
echo -- MOVD32 copies two words up
ar r0
ar r1
w0 8192 @ 0
wx 43e2c400afe2e401 @ 0
wx db0f4940 @ 128
ara0
ar xar4=0x40
aezi
pi 2
aezs 2
echo -- MOVDD32 copies four words up
ar r0
ar r1
w0 8192 @ 0
wx f0ffbe06 @ 0
ara0
ar rb=0xdeadbeef
ar sp=0x100
aezi
pi 2
aezs 2
echo -- PUSH RB, POP ACC
ar acc
ar sp
w0 8192 @ 0
wx f1ff @ 0
wx 0df0feca @ 512
ara0
ar sp=0x102
aezi
pi 1
aezs 1
echo -- POP RB
ar rb
ar sp
EOF
EXPECT=<<EOF
setflg tf=1,rndf32=1
-- SETFLG RNDF321,TF1
rnd32 = 0x1
tf = 0x1
lvf = 0x1
setflg lvf=0
-- SETFLG LVF0
lvf = 0x0
movst0 lvf,zf,tf
-- MOVST0 LVF,ZF,TF: copies, clears LVF
v = 0x1
z = 0x1
c = 0x1
tc = 0x1
lvf = 0x0
luf = 0x1
n = 0x1
movst0 nf,ni
-- MOVST0 NF,NI: N from NI
n = 0x1
movst0 nf,ni
-- MOVST0 NF,NI: N cleared
n = 0x0
mov32 stf, *xar4++
-- MOV32 STF,XAR4++: SHDWS kept
lvf = 0x1
luf = 0x0
nf = 0x1
zf = 0x0
tf = 0x1
rnd32 = 0x1
shdws = 0x0
xar4 = 0x00000042
mov32 *xar4++, stf
mov32 r0h, *--xar4, uncf
-- MOV32 XAR4++,STF read back
r0 = 0x0000024500000000
xar4 = 0x00000040
save rndf32=1
-- SAVE RNDF321 shadows, sets SHDWS
r1s = 0xaabbccddeeff0011
stfs = 0x00000040
rnd32 = 0x1
shdws = 0x1
save rndf32=1
zero r0
restore
-- SAVE, ZERO R0, RESTORE
r0 = 0x1122334455667788
rnd32 = 0x0
tf = 0x1
shdws = 0x0
testtf eq
-- TESTTF EQ true
tf = 0x1
testtf eq
-- TESTTF EQ false
tf = 0x0
swapf r0, r1, unc
-- SWAPF R0,R1,UNC swaps whole registers
r0 = 0x3333333344444444
r1 = 0x1111111122222222
mov16 *xar4++, r0h
mov al, *--xar4
-- MOV16 XAR4++,R0H stores 16 bits
acc = 0x00005678
xar4 = 0x00000040
movd32 r0h, *+xar4[0]
mov32 r1h, *+xar4[2], uncf
-- MOVD32 copies two words up
r0 = 0x40490fdb00000000
r1 = 0x40490fdb00000000
movdd32 r0h, *+xar4[0]
mov32 r1h, *+xar4[4], uncf
-- MOVDD32 copies four words up
r0 = 0x40490fdb00000000
r1 = 0x40490fdb00000000
push rb
pop acc
-- PUSH RB, POP ACC
acc = 0xdeadbeef
sp = 0x0100
pop rb
-- POP RB
rb = 0xcafef00d
sp = 0x0100
EOF
RUN

NAME=C28x RzIL VM: FPU parallel forms and MACF32
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 14e38443 @ 0
wx 0000e040 @ 128
ara0
ar r1=0x3fc0000000000000
ar r2=0x4010000000000000
ar xar4=0x40
ar zf=0x1
aezi
pi 1
aezs 1
echo -- ADDF32 par MOV32 RaH,mem32
ar r0
ar r3
ar xar4
ar nf
ar zf
w0 8192 @ 0
wx 14e384c3 @ 0
wx 0000e040 @ 128
ara0
ar r3=0x3f80000000000000
ar r2=0x4000000000000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- ADDF32 reads RaH before the load
ar r0
ar r3
w0 8192 @ 0
wx 04e08440afe28c05 @ 0
ara0
ar r0=0x40a0000000000000
ar r1=0x4000000000000000
ar r2=0x4040000000000000
ar xar4=0x40
aezi
pi 2
aezs 2
echo -- MPYF32 par MOV32 mem32,RaH stores the old RaH
ar r0
ar r5
ar xar4
w0 8192 @ 0
wx 42e788c6 @ 0
ara0
ar r1=0x4000000000000000
ar r2=0x4040000000000000
ar r4=0x3f80000000000000
ar r5=0x3f00000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 par ADDF32
ar r0
ar r3
w0 8192 @ 0
wx 51e78802 @ 0
ara0
ar r0=0x4120000000000000
ar r1=0x4000000000000000
ar r2=0x4040000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 par SUBF32 reads R0H before the product
ar r0
ar r1
w0 8192 @ 0
wx 42e788c6 @ 0
ara0
ar r1=0x7f00000000000000
ar r2=0x4000000000000000
ar r4=0x3f80000000000000
ar r5=0x3f00000000000000
aezi
pi 1
aezs 1
echo -- MPYF32 par ADDF32: the product overflows
ar r0
ar r3
ar lvf
w0 8192 @ 0
wx 38e38445 @ 0
wx 0000e040 @ 128
ara0
ar r3=0x4120000000000000
ar r2=0x4000000000000000
ar r1=0x4040000000000000
ar r4=0x4080000000000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MACF32 R3H,R2H,R0H,R1H,R4H par MOV32
ar r3
ar r0
ar r5
w0 8192 @ 0
wx 38e38455 @ 0
wx 0000e040 @ 128
ara0
ar r3=0x4120000000000000
ar r2=0x4000000000000000
ar r1=0x4040000000000000
ar r4=0x4080000000000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MACF32 accumulates the previous product
ar r3
ar r2
ar r5
w0 8192 @ 0
wx 50e2841f @ 0
wx 00004040 @ 128
wx 00008040 @ 160
ara0
ar r3=0x4120000000000000
ar r2=0x4000000000000000
ar xar4=0x40
ar xar7=0x50
aezi
pi 1
aezs 1
echo -- MACF32 R7H,R3H,XAR4++,XAR7++
ar r3
ar r2
ar xar4
ar xar7
EOF
EXPECT=<<EOF
addf32 r0h, r1h, r2h || mov32 r3h, *xar4++
-- ADDF32 par MOV32 RaH,mem32
r0 = 0x4070000000000000
r3 = 0x40e0000000000000
xar4 = 0x00000042
nf = 0x0
zf = 0x0
addf32 r0h, r3h, r2h || mov32 r3h, *xar4++
-- ADDF32 reads RaH before the load
r0 = 0x4040000000000000
r3 = 0x40e0000000000000
mpyf32 r0h, r1h, r2h || mov32 *xar4++, r0h
mov32 r5h, *--xar4, uncf
-- MPYF32 par MOV32 mem32,RaH stores the old RaH
r0 = 0x40c0000000000000
r5 = 0x40a0000000000000
xar4 = 0x00000040
mpyf32 r0h, r1h, r2h || addf32 r3h, r4h, r5h
-- MPYF32 par ADDF32
r0 = 0x40c0000000000000
r3 = 0x3fc0000000000000
mpyf32 r0h, r1h, r2h || subf32 r1h, r0h, r2h
-- MPYF32 par SUBF32 reads R0H before the product
r0 = 0x40c0000000000000
r1 = 0x40e0000000000000
mpyf32 r0h, r1h, r2h || addf32 r3h, r4h, r5h
-- MPYF32 par ADDF32: the product overflows
r0 = 0x7f7fffff00000000
r3 = 0x3fc0000000000000
lvf = 0x1
macf32 r3h, r2h, r0h, r1h, r4h || mov32 r5h, *xar4++
-- MACF32 R3H,R2H,R0H,R1H,R4H par MOV32
r3 = 0x4140000000000000
r0 = 0x4140000000000000
r5 = 0x40e0000000000000
macf32 r3h, r2h, r2h, r1h, r4h || mov32 r5h, *xar4++
-- MACF32 accumulates the previous product
r3 = 0x4140000000000000
r2 = 0x4140000000000000
r5 = 0x40e0000000000000
macf32 r7h, r3h, *xar4++, *xar7++
-- MACF32 R7H,R3H,XAR4++,XAR7++
r3 = 0x4140000000000000
r2 = 0x4140000000000000
xar4 = 0x00000042
xar7 = 0x00000052
EOF
RUN

NAME=C28x RzIL VM: TMU division, square root and 2pi multiplies
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x40f0000000000000
ar r2=0x4020000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 7.5/2.5
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x3f80000000000000
ar r2=0x4040000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 1/3 rounds to nearest
ar r0
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x3f80000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 Normal/0: Inf, LVF
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0xbf80000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 -1/0: -Inf, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
aezi
pi 1
aezs 1
echo -- DIVF32 0/0: 0, LVF
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x7f80000000000000
ar r2=0x7f80000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 Inf/Inf: Inf, LUF
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x7f80000000000000
ar r2=0x4000000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 Inf/Normal: Inf, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0xc0c0000000000000
ar r2=0x7f80000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 -6/Inf: +0, LUF
ar r0
ar luf
ar lvf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x7f7fffff00000000
ar r2=0x3f00000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 max/0.5 overflows
ar r0
ar lvf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x80000000000000
ar r2=0x4080000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 min normal/4 underflows
ar r0
ar luf
w0 8192 @ 0
wx 74e28800 @ 0
ara0
ar r1=0x100000000
ar r2=0x4000000000000000
aezi
pi 1
aezs 1
echo -- DIVF32 denormal dividend counts as 0
ar r0
ar luf
ar lvf
w0 8192 @ 0
wx 77e20800 @ 0
ara0
ar r1=0x4000000000000000
aezi
pi 1
aezs 1
echo -- SQRTF32 2
ar r0
ar lvf
w0 8192 @ 0
wx 77e20800 @ 0
ara0
ar r1=0xc080000000000000
aezi
pi 1
aezs 1
echo -- SQRTF32 -4: +0, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 77e20800 @ 0
ara0
ar r1=0x7f80000000000000
aezi
pi 1
aezs 1
echo -- SQRTF32 +Inf: +Inf, LVF
ar r0
ar lvf
w0 8192 @ 0
wx 77e20800 @ 0
ara0
ar r1=0x8000000000000000
aezi
pi 1
aezs 1
echo -- SQRTF32 -0: +0
ar r0
ar lvf
w0 8192 @ 0
wx 70e20800 @ 0
ara0
ar r1=0x3e80000000000000
aezi
pi 1
aezs 1
echo -- MPY2PIF32 0.25 is pi/2
ar r0
w0 8192 @ 0
wx 70e20800 @ 0
ara0
ar r1=0x7f7fffff00000000
aezi
pi 1
aezs 1
echo -- MPY2PIF32 max overflows
ar r0
ar lvf
w0 8192 @ 0
wx 71e20800 @ 0
ara0
ar r1=0x40c90fdb00000000
aezi
pi 1
aezs 1
echo -- DIV2PIF32 2pi is 1
ar r0
w0 8192 @ 0
wx 71e20800 @ 0
ara0
ar r1=0x80000000000000
aezi
pi 1
aezs 1
echo -- DIV2PIF32 min normal underflows
ar r0
ar luf
EOF
EXPECT=<<EOF
divf32 r0h, r1h, r2h
-- DIVF32 7.5/2.5
r0 = 0x4040000000000000
lvf = 0x0
luf = 0x0
divf32 r0h, r1h, r2h
-- DIVF32 1/3 rounds to nearest
r0 = 0x3eaaaaab00000000
divf32 r0h, r1h, r2h
-- DIVF32 Normal/0: Inf, LVF
r0 = 0x7f80000000000000
lvf = 0x1
luf = 0x0
divf32 r0h, r1h, r2h
-- DIVF32 -1/0: -Inf, LVF
r0 = 0xff80000000000000
lvf = 0x1
divf32 r0h, r1h, r2h
-- DIVF32 0/0: 0, LVF
r0 = 0x0000000000000000
lvf = 0x1
luf = 0x0
divf32 r0h, r1h, r2h
-- DIVF32 Inf/Inf: Inf, LUF
r0 = 0x7f80000000000000
lvf = 0x0
luf = 0x1
divf32 r0h, r1h, r2h
-- DIVF32 Inf/Normal: Inf, LVF
r0 = 0x7f80000000000000
lvf = 0x1
divf32 r0h, r1h, r2h
-- DIVF32 -6/Inf: +0, LUF
r0 = 0x0000000000000000
luf = 0x1
lvf = 0x0
divf32 r0h, r1h, r2h
-- DIVF32 max/0.5 overflows
r0 = 0x7f80000000000000
lvf = 0x1
divf32 r0h, r1h, r2h
-- DIVF32 min normal/4 underflows
r0 = 0x0000000000000000
luf = 0x1
divf32 r0h, r1h, r2h
-- DIVF32 denormal dividend counts as 0
r0 = 0x0000000000000000
luf = 0x0
lvf = 0x0
sqrtf32 r0h, r1h
-- SQRTF32 2
r0 = 0x3fb504f300000000
lvf = 0x0
sqrtf32 r0h, r1h
-- SQRTF32 -4: +0, LVF
r0 = 0x0000000000000000
lvf = 0x1
sqrtf32 r0h, r1h
-- SQRTF32 +Inf: +Inf, LVF
r0 = 0x7f80000000000000
lvf = 0x1
sqrtf32 r0h, r1h
-- SQRTF32 -0: +0
r0 = 0x0000000000000000
lvf = 0x0
mpy2pif32 r0h, r1h
-- MPY2PIF32 0.25 is pi/2
r0 = 0x3fc90fdb00000000
mpy2pif32 r0h, r1h
-- MPY2PIF32 max overflows
r0 = 0x7f80000000000000
lvf = 0x1
div2pif32 r0h, r1h
-- DIV2PIF32 2pi is 1
r0 = 0x3f80000000000000
div2pif32 r0h, r1h
-- DIV2PIF32 min normal underflows
r0 = 0x0000000000000000
luf = 0x1
EOF
RUN

NAME=C28x RzIL VM: FPU64 arithmetic, compares, moves and MACF64
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 90e78800 @ 0
ara0
ar r1=0x3ff8000000000000
ar r2=0x4002000000000000
aezi
pi 1
aezs 1
echo -- ADDF64 1.5 + 2.25
ar r0
ar lvf
ar luf
w0 8192 @ 0
wx 90e78800 @ 0
ara0
ar r1=0x3ff0000000000000
ar r2=0x3ca8000000000000
aezi
pi 1
aezs 1
echo -- ADDF64 1 + 1.5 ulp truncates RND64 0
ar r0
w0 8192 @ 0
wx 90e78800 @ 0
ara0
ar r1=0x3ff0000000000000
ar r2=0x3ca8000000000000
ar rnd64=0x1
aezi
pi 1
aezs 1
echo -- ADDF64 1 + 1.5 ulp rounds up RND64 1
ar r0
w0 8192 @ 0
wx 80e78800 @ 0
ara0
ar r1=0x3ff8000000000000
ar r2=0x4008000000000000
aezi
pi 1
aezs 1
echo -- MPYF64 1.5 3
ar r0
w0 8192 @ 0
wx a0e78800 @ 0
ara0
ar r1=0x4024000000000000
ar r2=0x3fd0000000000000
aezi
pi 1
aezs 1
echo -- SUBF64 10 - 0.25
ar r0
w0 8192 @ 0
wx 8fe908fe @ 0
ara0
ar r1=0x4000000000000000
aezi
pi 1
aezs 1
echo -- ADDF64 R0,1.5,R1
ar r0
w0 8192 @ 0
wx 80e78800 @ 0
ara0
ar r1=0x7fefffffffffffff
ar r2=0x4000000000000000
aezi
pi 1
aezs 1
echo -- MPYF64 max 2 overflows, truncating
ar r0
ar lvf
w0 8192 @ 0
wx 80e78800 @ 0
ara0
ar r1=0x10000000000000
ar r2=0x3fe0000000000000
aezi
pi 1
aezs 1
echo -- MPYF64 min normal / 2 flushes
ar r0
ar luf
w0 8192 @ 0
wx 98e61100 @ 0
ara0
ar r1=0x3ff8000000000000
ar r2=0x4000000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- CMPF64 1.5 2
ar nf
ar zf
w0 8192 @ 0
wx 9ae60800 @ 0
ara0
ar r0=0x3ff0000000000000
ar r1=0x4000000000000000
aezi
pi 1
aezs 1
echo -- MAXF64 1 2
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 9ee68806 @ 0
ara0
ar r0=0x3ff0000000000000
ar r1=0x4000000000000000
ar r3=0x401c000000000000
aezi
pi 1
aezs 1
echo -- MAXF64 par MOV64 moves when replaced
ar r0
ar r2
w0 8192 @ 0
wx dfe60800 @ 0
ara0
ar r1=0xc004000000000000
ar zf=0x1
ar zi=0x1
aezi
pi 1
aezs 1
echo -- MOV64 UNCF: NF/ZF of the double, NI/ZI of 64 bits
ar r0
ar nf
ar zf
ar ni
ar zi
w0 8192 @ 0
wx bfe60800 @ 0
ara0
ar r1=0x4004000000000000
aezi
pi 1
aezs 1
echo -- NEGF64 UNCF sets NF
ar r0
ar nf
ar zf
w0 8192 @ 0
wx bee60800 @ 0
ara0
ar r1=0x4004000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- NEGF64 UNC keeps flags
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 99e60800 @ 0
ara0
ar r1=0xc008000000000000
ar nf=0x1
aezi
pi 1
aezs 1
echo -- ABSF64 -3
ar r0
ar nf
ar zf
w0 8192 @ 0
wx f1e60880 @ 0
ara0
ar r1=0xc006000000000000
aezi
pi 1
aezs 1
echo -- FRACF64 -2.75
ar r0
w0 8192 @ 0
wx c2e788c6 @ 0
ara0
ar r1=0x4000000000000000
ar r2=0x4008000000000000
ar r4=0x3ff0000000000000
ar r5=0x3fe0000000000000
aezi
pi 1
aezs 1
echo -- MPYF64 par ADDF64
ar r0
ar r3
w0 8192 @ 0
wx 54e38446 @ 0
wx 0000e040 @ 128
ara0
ar r1=0x3ff8000000000000
ar r2=0x4002000000000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- ADDF64 par MOV32 R6H,XAR4++
ar r0
ar r6
ar xar4
w0 8192 @ 0
wx 78e38445 @ 0
wx 0000e040 @ 128
ara0
ar r3=0x4024000000000000
ar r2=0x4000000000000000
ar r1=0x4008000000000000
ar r4=0x4010000000000000
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- MACF64 R3,R2,R0,R1,R4 par MOV32 R5H
ar r3
ar r0
ar r5
EOF
EXPECT=<<EOF
addf64 r0, r1, r2
-- ADDF64 1.5 + 2.25
r0 = 0x400e000000000000
lvf = 0x0
luf = 0x0
addf64 r0, r1, r2
-- ADDF64 1 + 1.5 ulp truncates RND64 0
r0 = 0x3ff0000000000000
addf64 r0, r1, r2
-- ADDF64 1 + 1.5 ulp rounds up RND64 1
r0 = 0x3ff0000000000001
mpyf64 r0, r1, r2
-- MPYF64 1.5 3
r0 = 0x4012000000000000
subf64 r0, r1, r2
-- SUBF64 10 - 0.25
r0 = 0x4023800000000000
addf64 r0, #0x3ff8, r1
-- ADDF64 R0,1.5,R1
r0 = 0x400c000000000000
mpyf64 r0, r1, r2
-- MPYF64 max 2 overflows, truncating
r0 = 0x7fefffffffffffff
lvf = 0x1
mpyf64 r0, r1, r2
-- MPYF64 min normal / 2 flushes
r0 = 0x0000000000000000
luf = 0x1
cmpf64 r1, r2
-- CMPF64 1.5 2
nf = 0x1
zf = 0x0
maxf64 r0, r1
-- MAXF64 1 2
r0 = 0x4000000000000000
nf = 0x1
zf = 0x0
maxf64 r0, r1 || mov64 r2, r3
-- MAXF64 par MOV64 moves when replaced
r0 = 0x4000000000000000
r2 = 0x401c000000000000
mov64 r0, r1, uncf
-- MOV64 UNCF: NF/ZF of the double, NI/ZI of 64 bits
r0 = 0xc004000000000000
nf = 0x1
zf = 0x0
ni = 0x1
zi = 0x0
negf64 r0, r1, uncf
-- NEGF64 UNCF sets NF
r0 = 0xc004000000000000
nf = 0x1
zf = 0x0
negf64 r0, r1, unc
-- NEGF64 UNC keeps flags
r0 = 0xc004000000000000
nf = 0x0
zf = 0x1
absf64 r0, r1
-- ABSF64 -3
r0 = 0x4008000000000000
nf = 0x0
zf = 0x0
fracf64 r0, r1
-- FRACF64 -2.75
r0 = 0xbfe8000000000000
mpyf64 r0, r1, r2 || addf64 r3, r4, r5
-- MPYF64 par ADDF64
r0 = 0x4018000000000000
r3 = 0x3ff8000000000000
addf64 r0, r1, r2 || mov32 r6h, *xar4++
-- ADDF64 par MOV32 R6H,XAR4++
r0 = 0x400e000000000000
r6 = 0x40e0000000000000
xar4 = 0x00000042
macf64 r3, r2, r0, r1, r4 || mov32 r5h, *xar4++
-- MACF64 R3,R2,R0,R1,R4 par MOV32 R5H
r3 = 0x4028000000000000
r0 = 0x4028000000000000
r5 = 0x40e0000000000000
EOF
RUN

NAME=C28x RzIL VM: FPU64 conversions
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 91e60800 @ 0
ara0
ar r1=0xbfc0000000000000
ar zf=0x1
aezi
pi 1
aezs 1
echo -- F32TOF64 R0,R1H
ar r0
ar nf
ar zf
w0 8192 @ 0
wx 8ce28400 @ 0
wx 0000e040 @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- F32TOF64 R0,XAR4++
ar r0
ar xar4
w0 8192 @ 0
wx 21e2c400afe2d401 @ 0
wx 0000e040 @ 128
ara0
ar xar4=0x40
aezi
pi 2
aezs 2
echo -- F32DTOF64 copies two words up
ar r0
ar r1
w0 8192 @ 0
wx 90e60800 @ 0
ara0
ar r1=0x3fd5555555555555
aezi
pi 1
aezs 1
echo -- F64TOF32 1/3 truncates RND32 0
ar r0
w0 8192 @ 0
wx 90e60800 @ 0
ara0
ar r1=0x3fd5555555555555
ar rnd32=0x1
aezi
pi 1
aezs 1
echo -- F64TOF32 1/3 rounds RND32 1
ar r0
w0 8192 @ 0
wx 90e60800 @ 0
ara0
ar r1=0x48078287f49c4a1d
aezi
pi 1
aezs 1
echo -- F64TOF32 1e39 truncates to max
ar r0
w0 8192 @ 0
wx 90e60800 @ 0
ara0
ar r1=0x48078287f49c4a1d
ar rnd32=0x1
aezi
pi 1
aezs 1
echo -- F64TOF32 1e39 rounds to Inf
ar r0
w0 8192 @ 0
wx 90e60800 @ 0
ara0
ar r1=0x37a16c262777579c
aezi
pi 1
aezs 1
echo -- F64TOF32 1e-40 flushes
ar r0
ar luf
w0 8192 @ 0
wx 84e60800 @ 0
ara0
ar r1=0xc00599999999999a
aezi
pi 1
aezs 1
echo -- F64TOI32 -2.7 truncates
ar r0
w0 8192 @ 0
wx 84e60800 @ 0
ara0
ar r1=0x41e65a0bc0000000
aezi
pi 1
aezs 1
echo -- F64TOI32 3e9 saturates
ar r0
w0 8192 @ 0
wx 86e60800 @ 0
ara0
ar r1=0x41e65a0bc0000000
aezi
pi 1
aezs 1
echo -- F64TOUI32 3e9
ar r0
w0 8192 @ 0
wx 86e60800 @ 0
ara0
ar r1=0xbff0000000000000
aezi
pi 1
aezs 1
echo -- F64TOUI32 -1 saturates to 0
ar r0
w0 8192 @ 0
wx 84e60880 @ 0
ara0
ar r1=0xc270000000000800
aezi
pi 1
aezs 1
echo -- F64TOI64 -240 + 0.5 truncates
ar r0
w0 8192 @ 0
wx 84e60880 @ 0
ara0
ar r1=0x43e0000000000000
aezi
pi 1
aezs 1
echo -- F64TOI64 263 saturates
ar r0
w0 8192 @ 0
wx 86e60880 @ 0
ara0
ar r1=0x43e158e460913d00
aezi
pi 1
aezs 1
echo -- F64TOUI64 1e19
ar r0
w0 8192 @ 0
wx 86e60880 @ 0
ara0
ar r1=0x43f0000000000000
aezi
pi 1
aezs 1
echo -- F64TOUI64 264 saturates
ar r0
w0 8192 @ 0
wx 85e60800 @ 0
ara0
ar r1=0x8000000000000000
aezi
pi 1
aezs 1
echo -- I32TOF64 -231
ar r0
w0 8192 @ 0
wx 87e60800 @ 0
ara0
ar r1=0xffffffff00000000
aezi
pi 1
aezs 1
echo -- UI32TOF64 232 - 1
ar r0
w0 8192 @ 0
wx 89e28400 @ 0
wx fbffffff @ 128
ara0
ar xar4=0x40
aezi
pi 1
aezs 1
echo -- I32TOF64 R0,XAR4++
ar r0
ar xar4
w0 8192 @ 0
wx 85e60880 @ 0
ara0
ar r1=0x7fffffffffffffff
aezi
pi 1
aezs 1
echo -- I64TOF64 263 - 1 rounds to 263
ar r0
w0 8192 @ 0
wx 87e60880 @ 0
ara0
ar r1=0xffffffffffffffff
aezi
pi 1
aezs 1
echo -- UI64TOF64 264 - 1 rounds to 264
ar r0
w0 8192 @ 0
wx 87e60880 @ 0
ara0
ar r1=0x3039
aezi
pi 1
aezs 1
echo -- UI64TOF64 12345
ar r0
EOF
EXPECT=<<EOF
f32tof64 r0, r1h
-- F32TOF64 R0,R1H
r0 = 0xbff8000000000000
nf = 0x1
zf = 0x0
f32tof64 r0, *xar4++
-- F32TOF64 R0,XAR4++
r0 = 0x401c000000000000
xar4 = 0x00000042
f32dtof64 r0, *+xar4[0]
mov32 r1h, *+xar4[2], uncf
-- F32DTOF64 copies two words up
r0 = 0x401c000000000000
r1 = 0x40e0000000000000
f64tof32 r0h, r1
-- F64TOF32 1/3 truncates RND32 0
r0 = 0x3eaaaaaa00000000
f64tof32 r0h, r1
-- F64TOF32 1/3 rounds RND32 1
r0 = 0x3eaaaaab00000000
f64tof32 r0h, r1
-- F64TOF32 1e39 truncates to max
r0 = 0x7f7fffff00000000
f64tof32 r0h, r1
-- F64TOF32 1e39 rounds to Inf
r0 = 0x7f80000000000000
f64tof32 r0h, r1
-- F64TOF32 1e-40 flushes
r0 = 0x0000000000000000
luf = 0x0
f64toi32 r0h, r1
-- F64TOI32 -2.7 truncates
r0 = 0xfffffffe00000000
f64toi32 r0h, r1
-- F64TOI32 3e9 saturates
r0 = 0x7fffffff00000000
f64toui32 r0h, r1
-- F64TOUI32 3e9
r0 = 0xb2d05e0000000000
f64toui32 r0h, r1
-- F64TOUI32 -1 saturates to 0
r0 = 0x0000000000000000
f64toi64 r0, r1
-- F64TOI64 -240 + 0.5 truncates
r0 = 0xffffff0000000000
f64toi64 r0, r1
-- F64TOI64 263 saturates
r0 = 0x7fffffffffffffff
f64toui64 r0, r1
-- F64TOUI64 1e19
r0 = 0x8ac7230489e80000
f64toui64 r0, r1
-- F64TOUI64 264 saturates
r0 = 0xffffffffffffffff
i32tof64 r0, r1h
-- I32TOF64 -231
r0 = 0xc1e0000000000000
ui32tof64 r0, r1h
-- UI32TOF64 232 - 1
r0 = 0x41efffffffe00000
i32tof64 r0, *xar4++
-- I32TOF64 R0,XAR4++
r0 = 0xc014000000000000
xar4 = 0x00000042
i64tof64 r0, r1
-- I64TOF64 263 - 1 rounds to 263
r0 = 0x43e0000000000000
ui64tof64 r0, r1
-- UI64TOF64 264 - 1 rounds to 264
r0 = 0x43f0000000000000
ui64tof64 r0, r1
-- UI64TOF64 12345
r0 = 0x40c81c8000000000
EOF
RUN

NAME=C28x RzIL VM: fast integer division, whole divisions
FILE=malloc://8192
CMDS=<<EOF
e asm.arch=tms320
e asm.bits=32
e asm.cpu=c28x
e analysis.cpu=c28x
w0 8192 @ 0
wx 68e564e564e564e564e564e564e564e564e56ae5 @ 0
ara0
ar r1=0xfffffff900000000
ar r3=0x200000000
aezi
pi 10
aezs 10
echo -- -7/2 truncated: -3 r -1
ar r1
ar r2
ar r3
w0 8192 @ 0
wx 68e564e564e564e564e564e564e564e564e56be5 @ 0
ara0
ar r1=0xfffffff900000000
ar r3=0x200000000
aezi
pi 10
aezs 10
echo -- -7/2 euclidean: -4 r 1
ar r1
ar r2
w0 8192 @ 0
wx 68e564e564e564e564e564e564e564e564e56ce5 @ 0
ara0
ar r1=0xfffffff900000000
ar r3=0x200000000
aezi
pi 10
aezs 10
echo -- -7/2 floored: -4 r 1
ar r1
ar r2
w0 8192 @ 0
wx 68e564e564e564e564e564e564e564e564e56ce5 @ 0
ara0
ar r1=0x700000000
ar r3=0xfffffffe00000000
aezi
pi 10
aezs 10
echo -- 7/-2 floored: -4 r -1
ar r1
ar r2
w0 8192 @ 0
wx 64e564e564e564e564e564e564e564e5 @ 0
ara0
ar r1=0x6400000000
ar r3=0x700000000
ar zi=0x1
aezi
pi 8
aezs 8
echo -- SUBC4UI32 x8: 100/7 unsigned
ar r1
ar r2
ar zi
w0 8192 @ 0
wx 64e564e564e564e564e564e564e564e5 @ 0
ara0
ar r1=0x6400000000
ar r3=0x500000000
aezi
pi 8
aezs 8
echo -- SUBC4UI32 x8: 100/5 sets ZI
ar r1
ar r2
ar zi
w0 8192 @ 0
wx 64e5 @ 0
ara0
ar r1=0x6400000000
aezi
pi 1
aezs 1
echo -- SUBC4UI32 by zero latches LVF
ar lvf
w0 8192 @ 0
wx 68e5 @ 0
ara0
ar r1=0x8000000000000000
ar r3=0x300000000
aezi
pi 1
aezs 1
echo -- ABSI32DIV32 0x80000000: LVF, NI, TF
ar lvf
ar ni
ar tf
ar r2
w0 8192 @ 0
wx 69e5 @ 0
ara0
ar r1=0xfffffff600000000
ar r3=0xfffffff000000000
aezi
pi 1
aezs 1
echo -- ABSI32DIV32U: TF from the numerator only
ar ni
ar tf
ar r1
ar r3
w0 8192 @ 0
wx b8e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e565e5bae5 @ 0
ara0
ar r1=0xffffff1700000000
ar r0=0x2b5af00000000000
ar r3=0x0
ar r5=0x700000000
aezi
pi 34
aezs 34
echo -- -1012/7 over 64 bits: truncated
ar r1
ar r0
ar r2
ar r4
w0 8192 @ 0
wx a8e5 @ 0
ara0
ar r1=0xffffffff00000000
ar r0=0xfffffffb00000000
ar r3=0xfffffffd00000000
aezi
pi 1
aezs 1
echo -- ABSI64DIV32: TF from both signs
ar r1
ar r0
ar r3
ar ni
ar tf
ar r2
w0 8192 @ 0
wx aae5 @ 0
ara0
ar r1=0x0
ar r0=0x500000000
ar r2=0x200000000
ar tf=0x1
ar ni=0x1
aezi
pi 1
aezs 1
echo -- NEGI64DIV32 signs both
ar r1
ar r0
ar r2
w0 8192 @ 0
wx bbe5 @ 0
ara0
ar r1=0x0
ar r0=0x300000000
ar r2=0x0
ar r4=0x100000000
ar r3=0x0
ar r5=0x200000000
ar ni=0x1
ar tf=0x1
aezi
pi 1
aezs 1
echo -- ENEGI64DIV64 adjusts
ar r1
ar r0
ar r2
ar r4
EOF
EXPECT=<<EOF
absi32div32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
negi32div32 r1h, r2h
-- -7/2 truncated: -3 r -1
r1 = 0xfffffffd00000000
r2 = 0xffffffff00000000
r3 = 0x0000000200000000
absi32div32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
enegi32div32 r1h, r2h, r3h
-- -7/2 euclidean: -4 r 1
r1 = 0xfffffffc00000000
r2 = 0x0000000100000000
absi32div32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
mnegi32div32 r1h, r2h, r3h
-- -7/2 floored: -4 r 1
r1 = 0xfffffffc00000000
r2 = 0x0000000100000000
absi32div32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
mnegi32div32 r1h, r2h, r3h
-- 7/-2 floored: -4 r -1
r1 = 0xfffffffc00000000
r2 = 0xffffffff00000000
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
-- SUBC4UI32 x8: 100/7 unsigned
r1 = 0x0000000e00000000
r2 = 0x0000000200000000
zi = 0x0
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
subc4ui32 r2h, r1h, r3h
-- SUBC4UI32 x8: 100/5 sets ZI
r1 = 0x0000001400000000
r2 = 0x0000000000000000
zi = 0x1
subc4ui32 r2h, r1h, r3h
-- SUBC4UI32 by zero latches LVF
lvf = 0x1
absi32div32 r2h, r1h, r3h
-- ABSI32DIV32 0x80000000: LVF, NI, TF
lvf = 0x1
ni = 0x1
tf = 0x1
r2 = 0x0000000000000000
absi32div32u r2h, r1h
-- ABSI32DIV32U: TF from the numerator only
ni = 0x1
tf = 0x1
r1 = 0x0000000a00000000
r3 = 0xfffffff000000000
absi64div64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h
negi64div64 r1h:r0h, r2h:r4h
-- -1012/7 over 64 bits: truncated
r1 = 0xffffffde00000000
r0 = 0xbd0cfdb700000000
r2 = 0xffffffff00000000
r4 = 0xffffffff00000000
absi64div32 r2h, r1h:r0h, r3h
-- ABSI64DIV32: TF from both signs
r1 = 0x0000000000000000
r0 = 0x0000000500000000
r3 = 0x0000000300000000
ni = 0x1
tf = 0x0
r2 = 0x0000000000000000
negi64div32 r1h:r0h, r2h
-- NEGI64DIV32 signs both
r1 = 0xffffffff00000000
r0 = 0xfffffffb00000000
r2 = 0xfffffffe00000000
enegi64div64 r1h:r0h, r2h:r4h, r3h:r5h
-- ENEGI64DIV64 adjusts
r1 = 0xffffffff00000000
r0 = 0xfffffffc00000000
r2 = 0x0000000000000000
r4 = 0x0000000100000000
EOF
RUN
