From e16786f7991b120e146d64b3c6139e70804aa91d Mon Sep 17 00:00:00 2001 From: billow Date: Sun, 11 Oct 2026 20:06:06 +0800 Subject: [PATCH] M68k rzil base (#6706) --- librz/arch/isa/m68k/m68k_cs.c | 675 ++++ librz/arch/isa/m68k/m68k_cs.h | 64 +- librz/arch/isa/m68k/m68k_il.c | 4556 ++++++++++++++++++++++ librz/arch/isa/m68k/m68k_il.h | 14 + librz/arch/isa/m68k/m68k_il_helpers.c | 970 +++++ librz/arch/isa/m68k/m68k_il_helpers.h | 177 + librz/arch/meson.build | 3 + librz/arch/p/analysis/analysis_m68k_cs.c | 442 ++- librz/arch/p/asm/asm_m68k_cs.c | 72 +- librz/core/cfile.c | 9 + meson.build | 20 + test/db/analysis/m68k | 2377 ++++------- test/db/asm/m68k_68000_32 | 1993 +++++++++- test/db/asm/m68k_68010_32 | 127 + test/db/asm/m68k_68020_32 | 656 +++- test/db/asm/m68k_68030_32 | 90 +- test/db/asm/m68k_68040_32 | 44 + test/db/asm/m68k_68060_32 | 16 +- test/db/asm/m68k_cfv1_32 | 381 +- test/db/asm/m68k_cfv2_32 | 104 +- test/db/asm/m68k_cfv3_32 | 91 +- test/db/asm/m68k_cfv4_32 | 109 +- test/db/asm/m68k_cfv4e_32 | 357 +- test/db/asm/m68k_cfv5_32 | 146 +- test/db/asm/m68k_coldfire_32 | 212 +- test/db/asm/m68k_cpu32_32 | 80 +- test/db/cmd/cmd_aL | 2 +- test/db/cmd/cmd_list | 11 +- test/db/cmd/m68k | 31 - test/db/formats/elf/core | 31 +- test/db/rzil/m68k | 3448 ++++++++++++++++ test/unit/meson.build | 2 +- test/unit/test_analysis_m68k.c | 682 ++++ 33 files changed, 15239 insertions(+), 2753 deletions(-) create mode 100644 librz/arch/isa/m68k/m68k_cs.c create mode 100644 librz/arch/isa/m68k/m68k_il.c create mode 100644 librz/arch/isa/m68k/m68k_il.h create mode 100644 librz/arch/isa/m68k/m68k_il_helpers.c create mode 100644 librz/arch/isa/m68k/m68k_il_helpers.h create mode 100644 test/db/asm/m68k_68010_32 create mode 100644 test/db/asm/m68k_68040_32 delete mode 100644 test/db/cmd/m68k create mode 100644 test/db/rzil/m68k create mode 100644 test/unit/test_analysis_m68k.c diff --git a/librz/arch/isa/m68k/m68k_cs.c b/librz/arch/isa/m68k/m68k_cs.c new file mode 100644 index 0000000000..1ef9ec66a7 --- /dev/null +++ b/librz/arch/isa/m68k/m68k_cs.c @@ -0,0 +1,675 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#include "m68k/m68k_cs.h" + +#include + +#include + +#define M68K_FPU_EXT_DST(ext) (((ext) >> 7) & 7) + +RZ_IPI bool rz_m68k_reg_is_dreg(m68k_reg reg) { + return reg >= M68K_REG_D0 && reg <= M68K_REG_D7; +} + +RZ_IPI bool rz_m68k_reg_is_areg(m68k_reg reg) { + return reg >= M68K_REG_A0 && reg <= M68K_REG_A7; +} + +RZ_IPI bool rz_m68k_reg_is_gpr(m68k_reg reg) { + return rz_m68k_reg_is_dreg(reg) || rz_m68k_reg_is_areg(reg); +} + +RZ_IPI bool rz_m68k_reg_is_control(m68k_reg reg) { + switch (reg) { + case M68K_REG_SFC: + case M68K_REG_DFC: + case M68K_REG_USP: + case M68K_REG_VBR: + case M68K_REG_CACR: + case M68K_REG_CAAR: + case M68K_REG_MSP: + case M68K_REG_ISP: + case M68K_REG_TC: + case M68K_REG_ITT0: + case M68K_REG_ITT1: + case M68K_REG_DTT0: + case M68K_REG_DTT1: + case M68K_REG_MMUSR: + case M68K_REG_URP: + case M68K_REG_SRP: + return true; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_op_is_control_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_control(op->reg); +} + +RZ_IPI bool rz_m68k_mode_is_coldfire(cs_mode mode) { +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + return mode == CS_MODE_M68K_CFV1 || + mode == CS_MODE_M68K_CFV2 || + mode == CS_MODE_M68K_CFV3 || + mode == CS_MODE_M68K_CFV4 || + mode == CS_MODE_M68K_CFV4E || + mode == CS_MODE_M68K_CFV5 || + mode == CS_MODE_M68K_COLDFIRE; +#else + (void)mode; + return false; +#endif +} + +RZ_IPI bool rz_m68k_mode_has_fsave(cs_mode mode) { + return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 || + mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060; +} + +RZ_IPI bool rz_m68k_mode_has_emac(cs_mode mode) { +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + return mode == CS_MODE_M68K_CFV4E || mode == CS_MODE_M68K_CFV5; +#else + (void)mode; + return false; +#endif +} + +RZ_IPI bool rz_m68k_control_reg_implemented(cs_mode mode, m68k_reg reg) { + if (rz_m68k_mode_is_coldfire(mode)) { + return reg == M68K_REG_CACR || reg == M68K_REG_VBR; + } + switch (reg) { + case M68K_REG_SFC: + case M68K_REG_DFC: + case M68K_REG_USP: + case M68K_REG_VBR: + return mode == CS_MODE_M68K_010 || mode == CS_MODE_M68K_020 || + mode == CS_MODE_M68K_030 || mode == CS_MODE_M68K_040 || + mode == CS_MODE_M68K_060 +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + || mode == CS_MODE_M68K_CPU32 +#endif + ; + case M68K_REG_CACR: + return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 || + mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060; + case M68K_REG_CAAR: + return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030; + case M68K_REG_MSP: + case M68K_REG_ISP: + return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 || + mode == CS_MODE_M68K_040; + case M68K_REG_TC: + case M68K_REG_ITT0: + case M68K_REG_ITT1: + case M68K_REG_DTT0: + case M68K_REG_DTT1: + case M68K_REG_URP: + case M68K_REG_SRP: + return mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060; + case M68K_REG_MMUSR: + return mode == CS_MODE_M68K_040; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_reg_name_is_mmu_root_pointer(RZ_NULLABLE const char *name) { + return RZ_STR_EQ(name, "srp") || RZ_STR_EQ(name, "crp"); +} + +RZ_IPI bool rz_m68k_reg_is_fpu(m68k_reg reg) { + return reg >= M68K_REG_FP0 && reg <= M68K_REG_FP7; +} + +RZ_IPI bool rz_m68k_op_is_fpu_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_fpu(op->reg); +} + +RZ_IPI bool rz_m68k_reg_is_fpu_control(m68k_reg reg) { + return reg == M68K_REG_FPCR || reg == M68K_REG_FPSR || reg == M68K_REG_FPIAR; +} + +RZ_IPI bool rz_m68k_reg_is_acc(m68k_reg reg) { +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + return reg == M68K_REG_ACC || (reg >= M68K_REG_ACC0 && reg <= M68K_REG_ACC3); +#else + return false; +#endif +} + +RZ_IPI bool rz_m68k_op_is_predec_areg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->address_mode != M68K_AM_REGI_ADDR_PRE_DEC) { + return false; + } + return rz_m68k_reg_is_areg(op->reg); +} + +RZ_IPI bool rz_m68k_op_is_data_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_dreg(op->reg); +} + +RZ_IPI bool rz_m68k_op_is_addr_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_areg(op->reg); +} + +RZ_IPI bool rz_m68k_op_is_gpr(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_gpr(op->reg); +} + +RZ_IPI bool rz_m68k_op_is_status_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return op->reg == M68K_REG_CCR || op->reg == M68K_REG_SR; +} + +RZ_IPI bool rz_m68k_op_is_acc_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_acc(op->reg); +} + +RZ_IPI bool rz_m68k_op_is_fpu_control_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG) { + return false; + } + return rz_m68k_reg_is_fpu_control(op->reg); +} + +RZ_IPI bool rz_m68k_insn_uses_fpu_operand(RZ_NONNULL const cs_m68k *m68k) { + rz_return_val_if_fail(m68k, false); + for (ut8 i = 0; i < m68k->op_count; i++) { + const cs_m68k_op *op = &m68k->operands[i]; + switch (op->type) { + case M68K_OP_INVALID: + // Capstone can leave M68K_OP_INVALID on malformed FPU encodings. + continue; + case M68K_OP_FP_SINGLE: + case M68K_OP_FP_DOUBLE: +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + case M68K_OP_FP_EXTENDED: + case M68K_OP_FP_PACKED: +#endif + return true; + case M68K_OP_REG: + if (rz_m68k_reg_is_fpu(op->reg)) { + return true; + } + break; + default: + break; + } + } + return false; +} + +RZ_IPI ut32 rz_m68k_detail_op_bits(RZ_NONNULL const cs_m68k *m68k, ut32 fallback_bits) { + rz_return_val_if_fail(m68k, fallback_bits); + if (m68k->op_size.type == M68K_SIZE_TYPE_CPU) { + switch (m68k->op_size.cpu_size) { + case M68K_CPU_SIZE_BYTE: + return 8; + case M68K_CPU_SIZE_WORD: + return 16; + case M68K_CPU_SIZE_LONG: + return 32; + default: + break; + } + } + if (m68k->op_size.type == M68K_SIZE_TYPE_FPU) { + switch (m68k->op_size.fpu_size) { + case M68K_FPU_SIZE_SINGLE: + return 32; + case M68K_FPU_SIZE_DOUBLE: + return 64; + case M68K_FPU_SIZE_EXTENDED: + return 80; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + case M68K_FPU_SIZE_PACKED: + return 80; +#endif + default: + break; + } + } + return fallback_bits; +} + +RZ_IPI ut32 rz_m68k_bits_access_bytes(ut32 bits) { + return RZ_MAX(1, bits / 8); +} + +RZ_IPI ut32 rz_m68k_reg_stack_access_bytes(cs_mode mode, m68k_reg reg, ut32 bits) { + ut32 bytes = rz_m68k_bits_access_bytes(bits); + // A7 is 32 bits; this is the address-register delta, not its width. A + // byte-sized predecrement/postincrement adjusts A7 by 2 bytes to preserve + // stack word alignment on classic M680x0. ColdFire treats A7 like every + // other address register and adjusts it by one for byte operands (CFPRM). + return reg == M68K_REG_A7 && bytes == 1 && !rz_m68k_mode_is_coldfire(mode) ? 2 : bytes; +} + +RZ_IPI m68k_reg rz_m68k_op_base_reg(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, M68K_REG_INVALID); + if (op->mem.base_reg != M68K_REG_INVALID) { + return op->mem.base_reg; + } + return rz_m68k_reg_is_areg(op->reg) ? op->reg : M68K_REG_INVALID; +} + +RZ_IPI ut32 rz_m68k_op_absolute_address(RZ_NONNULL const cs_m68k_op *op, bool short_addr) { + rz_return_val_if_fail(op, 0); +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + st64 address = op->mem.address; +#else + st64 address = op->imm ? op->imm : op->mem.disp; +#endif + return short_addr ? (ut32)(st32)(st16)address : (ut32)address; +} + +RZ_IPI bool rz_m68k_op_is_mem_addr(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + switch (op->address_mode) { + case M68K_AM_REGI_ADDR: + case M68K_AM_REGI_ADDR_POST_INC: + case M68K_AM_REGI_ADDR_PRE_DEC: + case M68K_AM_REGI_ADDR_DISP: + case M68K_AM_AREGI_INDEX_8_BIT_DISP: + case M68K_AM_AREGI_INDEX_BASE_DISP: + case M68K_AM_MEMI_PRE_INDEX: + case M68K_AM_MEMI_POST_INDEX: + case M68K_AM_PCI_DISP: + case M68K_AM_PCI_INDEX_8_BIT_DISP: + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_PC_MEMI_POST_INDEX: + case M68K_AM_ABSOLUTE_DATA_SHORT: + case M68K_AM_ABSOLUTE_DATA_LONG: + return true; + default: + return op->type == M68K_OP_MEM; + } +} + +RZ_IPI ut64 rz_m68k_op_absolute_mem_address(RZ_NONNULL const cs_m68k_op *operand) { + rz_return_val_if_fail(operand, 0); + if (operand->type != M68K_OP_MEM) { + return 0; + } + // M68000PRM 2.2.16: an absolute short address is sign-extended to 32 bits. + if (operand->address_mode == M68K_AM_ABSOLUTE_DATA_SHORT) { + return rz_m68k_op_absolute_address(operand, true); + } +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + return operand->mem.address; +#else + if (operand->imm) { + return operand->imm; + } + return (ut64)(st64)(operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp); +#endif +} + +RZ_IPI bool rz_m68k_op_is_absolute_mem(RZ_NONNULL const cs_m68k_op *operand) { + rz_return_val_if_fail(operand, false); + if (operand->type != M68K_OP_MEM) { + return false; + } + switch (operand->address_mode) { + case M68K_AM_ABSOLUTE_DATA_SHORT: + case M68K_AM_ABSOLUTE_DATA_LONG: + return true; + default: + break; + } + return operand->mem.base_reg == M68K_REG_INVALID && + operand->mem.index_reg == M68K_REG_INVALID && + operand->mem.in_base_reg == M68K_REG_INVALID; +} + +RZ_IPI bool rz_m68k_insn_cache_requires_address(ut32 insn_id) { + switch (insn_id) { +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + case M68K_INS_INTOUCH: +#endif + case M68K_INS_CINVL: + case M68K_INS_CINVP: + case M68K_INS_CPUSHL: + case M68K_INS_CPUSHP: + return true; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_op_is_data_reg_pair(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG_PAIR) { + return false; + } + return rz_m68k_reg_is_dreg(op->reg_pair.reg_0) && rz_m68k_reg_is_dreg(op->reg_pair.reg_1); +} + +RZ_IPI bool rz_m68k_op_is_gpr_reg_pair(RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(op, false); + if (op->type != M68K_OP_REG_PAIR) { + return false; + } + m68k_reg r0 = op->reg_pair.reg_0; + m68k_reg r1 = op->reg_pair.reg_1; + return rz_m68k_reg_is_gpr(r0) && rz_m68k_reg_is_gpr(r1); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 +RZ_IPI bool rz_m68k_tbl_insn_is_signed(m68k_insn insn) { + return insn == M68K_INS_TBLS || insn == M68K_INS_TBLSN; +} + +RZ_IPI bool rz_m68k_tbl_insn_is_unrounded(m68k_insn insn) { + return insn == M68K_INS_TBLSN || insn == M68K_INS_TBLUN; +} +#endif + +RZ_IPI bool rz_m68k_fpu_insn_extension_word(RZ_NONNULL const cs_insn *insn, RZ_NONNULL ut16 *extension) { + rz_return_val_if_fail(insn && extension, false); + if (insn->size < 4) { + return false; + } + *extension = ((ut16)insn->bytes[2] << 8) | insn->bytes[3]; + return true; +} + +RZ_IPI m68k_reg rz_m68k_fpu_insn_extension_dst_reg(RZ_NONNULL const cs_insn *insn) { + rz_return_val_if_fail(insn, M68K_REG_INVALID); + ut16 extension = 0; + if (!rz_m68k_fpu_insn_extension_word(insn, &extension)) { + return M68K_REG_INVALID; + } + return M68K_REG_FP0 + M68K_FPU_EXT_DST(extension); +} + +// Capstone collapses some FPU read-modify-write instructions to one operand +// when source and destination are the same (for example "frem fp0"). The +// destination remains encoded in the FPU extension word; materialize it as a +// synthetic second operand so analysis and IL can use a uniform two-operand +// form. + +RZ_IPI bool rz_m68k_fpu_insn_hidden_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *dst) { + rz_return_val_if_fail(insn && dst, false); + m68k_reg reg = rz_m68k_fpu_insn_extension_dst_reg(insn); + if (!rz_m68k_reg_is_fpu(reg)) { + return false; + } + memset(dst, 0, sizeof(*dst)); + dst->type = M68K_OP_REG; + dst->reg = reg; + return true; +} + +RZ_IPI bool rz_m68k_fpu_op_from_reg(RZ_NONNULL cs_m68k_op *op, m68k_reg reg) { + rz_return_val_if_fail(op, false); + if (!rz_m68k_reg_is_fpu(reg)) { + return false; + } + memset(op, 0, sizeof(*op)); + op->type = M68K_OP_REG; + op->reg = reg; + return true; +} + +RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_second_op_or_hidden_dst(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *hidden_dst) { + rz_return_val_if_fail(insn && insn->detail && hidden_dst, NULL); + const cs_m68k *m68k = &insn->detail->m68k; + if (m68k->op_count > 1) { + return &m68k->operands[1]; + } + return rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst) ? hidden_dst : NULL; +} + +RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_unary_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL const cs_m68k_op *src, RZ_NONNULL cs_m68k_op *hidden_dst) { + rz_return_val_if_fail(insn && insn->detail && src && hidden_dst, NULL); + const cs_m68k *m68k = &insn->detail->m68k; + if (m68k->op_count > 1) { + return &m68k->operands[1]; + } + if (rz_m68k_op_is_fpu_reg(src)) { + m68k_reg reg = rz_m68k_fpu_insn_extension_dst_reg(insn); + if (rz_m68k_reg_is_fpu(reg) && reg != src->reg && rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst)) { + return hidden_dst; + } + return src; + } + return rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst) ? hidden_dst : NULL; +} + +RZ_IPI bool rz_m68k_fpu_insn_has_data_dst(ut32 insn_id) { + switch (insn_id) { + case M68K_INS_FMOVECR: + case M68K_INS_FABS: + case M68K_INS_FSABS: + case M68K_INS_FDABS: + case M68K_INS_FACOS: + case M68K_INS_FASIN: + case M68K_INS_FATAN: + case M68K_INS_FATANH: + case M68K_INS_FCOS: + case M68K_INS_FCOSH: + case M68K_INS_FETOX: + case M68K_INS_FETOXM1: + case M68K_INS_FLOG10: + case M68K_INS_FLOG2: + case M68K_INS_FLOGN: + case M68K_INS_FLOGNP1: + case M68K_INS_FNEG: + case M68K_INS_FSNEG: + case M68K_INS_FDNEG: + case M68K_INS_FSIN: + case M68K_INS_FSINH: + case M68K_INS_FSQRT: + case M68K_INS_FSSQRT: + case M68K_INS_FDSQRT: + case M68K_INS_FTAN: + case M68K_INS_FTANH: + case M68K_INS_FTENTOX: + case M68K_INS_FTWOTOX: + case M68K_INS_FINT: + case M68K_INS_FINTRZ: + case M68K_INS_FGETEXP: + case M68K_INS_FGETMAN: + case M68K_INS_FADD: + case M68K_INS_FSADD: + case M68K_INS_FDADD: + case M68K_INS_FSUB: + case M68K_INS_FSSUB: + case M68K_INS_FDSUB: + case M68K_INS_FMUL: + case M68K_INS_FSMUL: + case M68K_INS_FDMUL: + case M68K_INS_FSGLMUL: + case M68K_INS_FDIV: + case M68K_INS_FSDIV: + case M68K_INS_FDDIV: + case M68K_INS_FSGLDIV: + case M68K_INS_FMOD: + case M68K_INS_FREM: + case M68K_INS_FSCALE: + case M68K_INS_FCMP: + return true; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_fpu_insn_single_op_is_complete(RZ_NONNULL const cs_insn *insn) { + rz_return_val_if_fail(insn && insn->detail, false); + if (insn->detail->m68k.op_count != 1) { + return false; + } + const cs_m68k_op *operand = &insn->detail->m68k.operands[0]; + if (!rz_m68k_op_is_fpu_reg(operand)) { + return false; + } + switch (insn->id) { + case M68K_INS_FABS: + case M68K_INS_FSABS: + case M68K_INS_FDABS: + case M68K_INS_FACOS: + case M68K_INS_FASIN: + case M68K_INS_FATAN: + case M68K_INS_FATANH: + case M68K_INS_FCOS: + case M68K_INS_FCOSH: + case M68K_INS_FETOX: + case M68K_INS_FETOXM1: + case M68K_INS_FLOG10: + case M68K_INS_FLOG2: + case M68K_INS_FLOGN: + case M68K_INS_FLOGNP1: + case M68K_INS_FNEG: + case M68K_INS_FSNEG: + case M68K_INS_FDNEG: + case M68K_INS_FSIN: + case M68K_INS_FSINH: + case M68K_INS_FSQRT: + case M68K_INS_FSSQRT: + case M68K_INS_FDSQRT: + case M68K_INS_FTAN: + case M68K_INS_FTANH: + case M68K_INS_FTENTOX: + case M68K_INS_FTWOTOX: + case M68K_INS_FINT: + case M68K_INS_FINTRZ: + case M68K_INS_FGETEXP: + case M68K_INS_FGETMAN: + case M68K_INS_FTST: + return rz_m68k_fpu_insn_extension_dst_reg(insn) == operand->reg; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_fpu_insn_needs_hidden_dst(RZ_NONNULL const cs_insn *insn) { + rz_return_val_if_fail(insn && insn->detail, false); + if (insn->detail->m68k.op_count != 1 || !rz_m68k_fpu_insn_has_data_dst(insn->id)) { + return false; + } + if (rz_m68k_fpu_insn_single_op_is_complete(insn)) { + return false; + } + return rz_m68k_reg_is_fpu(rz_m68k_fpu_insn_extension_dst_reg(insn)); +} + +RZ_IPI bool rz_m68k_fpu_size_is_extended(RZ_NONNULL const cs_m68k *m68k) { + rz_return_val_if_fail(m68k, false); + return m68k->op_size.type == M68K_SIZE_TYPE_FPU && m68k->op_size.fpu_size == M68K_FPU_SIZE_EXTENDED; +} + +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS +RZ_IPI bool rz_m68k_fpu_size_is_packed(RZ_NONNULL const cs_m68k *m68k) { + rz_return_val_if_fail(m68k, false); + return m68k->op_size.type == M68K_SIZE_TYPE_FPU && m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED; +} +#endif + +RZ_IPI bool rz_m68k_op_detail_is_invalid(RZ_NULLABLE const cs_m68k_op *op) { + return !op || + op->type == M68K_OP_INVALID || + (op->type == M68K_OP_REG && op->reg == M68K_REG_INVALID) || + (op->type == M68K_OP_MEM && op->address_mode == M68K_AM_NONE); +} + +RZ_IPI bool rz_m68k_fpu_op_is_illegal_read(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(m68k && op, false); + if (rz_m68k_op_is_fpu_reg(op)) { + return false; + } + // Capstone produced no usable operand data; there is nothing to read. + if (rz_m68k_op_detail_is_invalid(op)) { + return true; + } + // A GPR cannot supply an FPU-sized operand (e.g. fmove.x d0, fp0 is illegal). + if (m68k->op_size.type == M68K_SIZE_TYPE_FPU && rz_m68k_op_is_gpr(op)) { + return true; + } + // FP immediates use dedicated M68K_OP_FP_* types; an integer immediate + // cannot encode an FPU-sized value. + if (m68k->op_size.type == M68K_SIZE_TYPE_FPU && op->type == M68K_OP_IMM) { + return true; + } + // An immediate cannot encode an 80-bit extended precision value. + if (op->type == M68K_OP_IMM && rz_m68k_detail_op_bits(m68k, 80) == 80) { + return true; + } + return false; +} + +static bool m68k_address_mode_is_pc_relative(m68k_address_mode mode) { + switch (mode) { + case M68K_AM_PCI_DISP: + case M68K_AM_PCI_INDEX_8_BIT_DISP: + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_PC_MEMI_POST_INDEX: + return true; + default: + return false; + } +} + +RZ_IPI bool rz_m68k_fpu_op_is_illegal_write(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op) { + rz_return_val_if_fail(m68k && op, false); + if (rz_m68k_op_is_fpu_reg(op)) { + return false; + } + if (rz_m68k_op_detail_is_invalid(op)) { + return true; + } + // PC-relative addressing is never alterable and cannot be a destination. + if (m68k_address_mode_is_pc_relative(op->address_mode)) { + return true; + } + if (m68k->op_size.type == M68K_SIZE_TYPE_FPU) { + return !rz_m68k_op_is_mem_addr(op); + } + return op->type != M68K_OP_REG && !rz_m68k_op_is_mem_addr(op); +} + +RZ_IPI bool rz_m68k_fpu_insn_data_alias_has_dst(RZ_NONNULL const cs_insn *insn) { + rz_return_val_if_fail(insn && insn->detail, false); + if (insn->detail->m68k.op_count < 1) { + return false; + } + cs_m68k_op hidden_dst; + const cs_m68k_op *dst = rz_m68k_fpu_insn_second_op_or_hidden_dst(insn, &hidden_dst); + return dst && rz_m68k_op_is_fpu_reg(dst); +} diff --git a/librz/arch/isa/m68k/m68k_cs.h b/librz/arch/isa/m68k/m68k_cs.h index ba0829d356..860cc6e8f0 100644 --- a/librz/arch/isa/m68k/m68k_cs.h +++ b/librz/arch/isa/m68k/m68k_cs.h @@ -4,12 +4,14 @@ #ifndef RZ_M68K_CS_H #define RZ_M68K_CS_H +#include #include #include -#define M68K_LONGEST_INSTRUCTION 22 +#define M68K_MIN_OP_SIZE 2 +#define M68K_MAX_OP_SIZE 22 -static inline cs_mode rz_m68k_cs_mode(const char *cpu) { +static inline cs_mode rz_m68k_cs_mode(RZ_NULLABLE const char *cpu) { if (!cpu) { return CS_MODE_M68K_040; } @@ -62,4 +64,62 @@ static inline cs_mode rz_m68k_cs_mode(const char *cpu) { return CS_MODE_M68K_040; } +RZ_IPI bool rz_m68k_reg_is_dreg(m68k_reg reg); +RZ_IPI bool rz_m68k_reg_is_areg(m68k_reg reg); +RZ_IPI bool rz_m68k_reg_is_gpr(m68k_reg reg); +RZ_IPI bool rz_m68k_reg_is_control(m68k_reg reg); +RZ_IPI bool rz_m68k_op_is_control_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_mode_is_coldfire(cs_mode mode); +RZ_IPI bool rz_m68k_mode_has_fsave(cs_mode mode); +RZ_IPI bool rz_m68k_mode_has_emac(cs_mode mode); +RZ_IPI bool rz_m68k_control_reg_implemented(cs_mode mode, m68k_reg reg); +RZ_IPI bool rz_m68k_reg_name_is_mmu_root_pointer(RZ_NULLABLE const char *name); +RZ_IPI bool rz_m68k_reg_is_fpu(m68k_reg reg); +RZ_IPI bool rz_m68k_op_is_fpu_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_reg_is_fpu_control(m68k_reg reg); +RZ_IPI bool rz_m68k_reg_is_acc(m68k_reg reg); +RZ_IPI bool rz_m68k_op_is_predec_areg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_data_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_addr_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_gpr(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_status_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_acc_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_fpu_control_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_insn_uses_fpu_operand(RZ_NONNULL const cs_m68k *m68k); + +RZ_IPI ut32 rz_m68k_detail_op_bits(RZ_NONNULL const cs_m68k *m68k, ut32 fallback_bits); +RZ_IPI ut32 rz_m68k_bits_access_bytes(ut32 bits); +RZ_IPI ut32 rz_m68k_reg_stack_access_bytes(cs_mode mode, m68k_reg reg, ut32 bits); +RZ_IPI m68k_reg rz_m68k_op_base_reg(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI ut32 rz_m68k_op_absolute_address(RZ_NONNULL const cs_m68k_op *op, bool short_addr); +RZ_IPI bool rz_m68k_op_is_mem_addr(RZ_NONNULL const cs_m68k_op *op); + +RZ_IPI ut64 rz_m68k_op_absolute_mem_address(RZ_NONNULL const cs_m68k_op *operand); +RZ_IPI bool rz_m68k_op_is_absolute_mem(RZ_NONNULL const cs_m68k_op *operand); +RZ_IPI bool rz_m68k_insn_cache_requires_address(ut32 insn_id); +RZ_IPI bool rz_m68k_op_is_data_reg_pair(RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_op_is_gpr_reg_pair(RZ_NONNULL const cs_m68k_op *op); +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 +RZ_IPI bool rz_m68k_tbl_insn_is_signed(m68k_insn insn); +RZ_IPI bool rz_m68k_tbl_insn_is_unrounded(m68k_insn insn); #endif + +RZ_IPI bool rz_m68k_fpu_insn_extension_word(RZ_NONNULL const cs_insn *insn, RZ_NONNULL ut16 *extension); +RZ_IPI m68k_reg rz_m68k_fpu_insn_extension_dst_reg(RZ_NONNULL const cs_insn *insn); +RZ_IPI bool rz_m68k_fpu_insn_hidden_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *dst); +RZ_IPI bool rz_m68k_fpu_op_from_reg(RZ_NONNULL cs_m68k_op *op, m68k_reg reg); +RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_second_op_or_hidden_dst(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *hidden_dst); +RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_unary_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL const cs_m68k_op *src, RZ_NONNULL cs_m68k_op *hidden_dst); +RZ_IPI bool rz_m68k_fpu_insn_has_data_dst(ut32 insn_id); +RZ_IPI bool rz_m68k_fpu_insn_single_op_is_complete(RZ_NONNULL const cs_insn *insn); +RZ_IPI bool rz_m68k_fpu_insn_needs_hidden_dst(RZ_NONNULL const cs_insn *insn); +RZ_IPI bool rz_m68k_fpu_size_is_extended(RZ_NONNULL const cs_m68k *m68k); +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS +RZ_IPI bool rz_m68k_fpu_size_is_packed(RZ_NONNULL const cs_m68k *m68k); +#endif +RZ_IPI bool rz_m68k_op_detail_is_invalid(RZ_NULLABLE const cs_m68k_op *op); +RZ_IPI bool rz_m68k_fpu_op_is_illegal_read(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_fpu_op_is_illegal_write(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op); +RZ_IPI bool rz_m68k_fpu_insn_data_alias_has_dst(RZ_NONNULL const cs_insn *insn); + +#endif // RZ_M68K_CS_H diff --git a/librz/arch/isa/m68k/m68k_il.c b/librz/arch/isa/m68k/m68k_il.c new file mode 100644 index 0000000000..992598b6ab --- /dev/null +++ b/librz/arch/isa/m68k/m68k_il.c @@ -0,0 +1,4556 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#include "m68k/m68k_il.h" +#include "m68k/m68k_cs.h" +#include "m68k/m68k_il_helpers.h" + +#include +#include +#include + +static RzILOpEffect *lift_move(M68KILCtx *ctx, bool address_dst) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + bool uses_usp = (src->type == M68K_OP_REG && src->reg == M68K_REG_USP) || + (dst->type == M68K_OP_REG && dst->reg == M68K_REG_USP); + bool reads_sr = src->type == M68K_OP_REG && src->reg == M68K_REG_SR; + bool reads_ccr = src->type == M68K_OP_REG && src->reg == M68K_REG_CCR; + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, bits, &seq)) { + return NULL; + } + if (rz_m68k_op_is_status_reg(dst)) { + RzILOpEffect *write = m68k_write_status_reg_unchecked(ctx, dst->reg, VARL("src")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return dst->reg == M68K_REG_SR ? BRANCH(m68k_supervisor_mode(), seq, m68k_label("m68k_privilege")) : seq; + } + RzILOpEffect *write = m68k_write_operand(ctx, dst, bits, VARL("src")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (!address_dst && !uses_usp && !reads_sr && !reads_ccr) { + seq = SEQ2(seq, m68k_set_flags_nzvcx(VARL("src"), bits, IL_FALSE, IL_FALSE, NULL)); + } + if (uses_usp || (reads_sr && ctx->mode != CS_MODE_M68K_000)) { + return BRANCH(m68k_supervisor_mode(), seq, m68k_label("m68k_privilege")); + } + return seq; +} + +static RzILOpEffect *lift_moveq(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (ctx->m68k->operands[1].type != M68K_OP_REG) { + return NULL; + } + RzILOpPure *value = S32((st8)ctx->m68k->operands[0].imm); + return SEQ3( + SETL("res", DUP(value)), + m68k_write_reg_sized(ctx, ctx->m68k->operands[1].reg, 32, value), + m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_movec(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (ctx->insn->size < 4 || ctx->m68k->operands[0].type != M68K_OP_REG || ctx->m68k->operands[1].type != M68K_OP_REG) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + bool src_control = rz_m68k_op_is_control_reg(src); + bool dst_control = rz_m68k_op_is_control_reg(dst); + bool src_gpr = rz_m68k_op_is_gpr(src); + bool dst_gpr = rz_m68k_op_is_gpr(dst); + if (src_control == dst_control || + (!src_control && !src_gpr) || + (!dst_control && !dst_gpr)) { + return NULL; + } + const cs_m68k_op *control = src_control ? src : dst; + const cs_m68k_op *gpr = src_gpr ? src : dst; + /* M68000PRM 6-22: operation word bit 0 gives the transfer direction. + * Capstone 4 reports both directions with the GPR first. */ + bool to_control = (ctx->insn->bytes[1] & 1) != 0; + src = to_control ? gpr : control; + dst = to_control ? control : gpr; + if (!rz_m68k_control_reg_implemented(ctx->mode, control->reg)) { + return BRANCH(m68k_supervisor_mode(), m68k_label("m68k_illegal"), m68k_label("m68k_privilege")); + } + RzILOpPure *value = m68k_read_reg_sized(ctx, src->reg, 32); + if (!value) { + return NULL; + } + if (to_control && (dst->reg == M68K_REG_SFC || dst->reg == M68K_REG_DFC)) { + value = LOGAND(value, U32(7)); + } + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, 32, value); + if (!write) { + return NULL; + } + return BRANCH(m68k_supervisor_mode(), write, m68k_label("m68k_privilege")); +} + +static RzILOpEffect *lift_moves(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + bool src_reg = rz_m68k_op_is_gpr(src); + bool dst_reg = rz_m68k_op_is_gpr(dst); + bool src_mem = rz_m68k_op_is_mem_addr(src); + bool dst_mem = rz_m68k_op_is_mem_addr(dst); + if (!((src_reg && dst_mem) || (src_mem && dst_reg))) { + return NULL; + } + + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq; + if (src_mem) { + M68KEA ea = m68k_effective_addr(ctx, src, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + ut32 write_bits = bits; + RzILOpPure *value = VARL("src"); + if (rz_m68k_reg_is_areg(dst->reg) && bits < 32) { + value = SIGNED(32, value); + write_bits = 32; + } + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, write_bits, value); + if (!write) { + m68k_ea_fini(&ea); + return NULL; + } + seq = m68k_effect_pre_post(ea.pre, + SETL("src", LOADW(bits, UNSIGNED(M68K_ADDR_BITS, ea.addr))), + ea.post); + seq = SEQ2(seq, write); + } else { + RzILOpPure *value = m68k_read_reg_sized(ctx, src->reg, bits); + M68KEA ea = m68k_effective_addr(ctx, dst, bits); + if (!value || !ea.addr) { + rz_il_op_pure_free(value); + m68k_ea_fini(&ea); + return NULL; + } + seq = SEQ2( + SETL("src", value), + m68k_effect_pre_post(ea.pre, + STOREW(UNSIGNED(M68K_ADDR_BITS, ea.addr), UNSIGNED(bits, VARL("src"))), + ea.post)); + } + return BRANCH(m68k_supervisor_mode(), seq, m68k_label("m68k_privilege")); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static RzILOpPure *bit_at32(const char *local, ut32 bit) { + return EXTRACT32(VARL(local), U32(bit), U32(1)); +} + +static RzILOpPure *reverse_bits32(const char *local) { + RzILOpPure *res = U32(0); + for (ut32 i = 0; i < 32; i++) { + RzILOpPure *bit = bit_at32(local, i); + if (i != 31) { + bit = SHIFTL0(bit, U8(31 - i)); + } + res = LOGOR(res, bit); + } + return res; +} + +static RzILOpPure *reverse_bytes32(const char *local) { + return LOGOR( + LOGOR( + SHIFTL0(LOGAND(VARL(local), U32(0xff)), U8(24)), + SHIFTL0(LOGAND(VARL(local), U32(0xff00)), U8(8))), + LOGOR( + LOGAND(SHIFTR0(VARL(local), U8(8)), U32(0xff00)), + SHIFTR0(VARL(local), U8(24)))); +} + +static RzILOpPure *ff1_result32(const char *local) { + RzILOpPure *res = U32(32); + for (ut32 bit = 0; bit < 32; bit++) { + res = ITE(NON_ZERO(bit_at32(local, bit)), U32(31 - bit), res); + } + return res; +} + +static RzILOpEffect *set_flags_ff1(RzILOpPure *source) { + RzILOpPure *src = source; + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, MSB(DUP(src))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, IS_ZERO(src)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, IL_FALSE); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE); + ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X))); + return m68k_set_ccr_from_value(ccr); +} + +static RzILOpEffect *set_flags_rem(RzILOpPure *quotient, RzILOpBool *overflow) { + RzILOpPure *quotient32 = UNSIGNED(32, quotient); + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + RzILOpBool *no_overflow = INV((RzILOpBool *)DUP(overflow)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, AND(no_overflow, MSB(DUP(quotient32)))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(INV((RzILOpBool *)DUP(overflow)), IS_ZERO(quotient32))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, overflow); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE); + ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X))); + return m68k_set_ccr_from_value(ccr); +} + +static RzILOpEffect *lift_mov3q(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_IMM) { + return NULL; + } + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + RzILOpPure *value = U32((ut32)ctx->m68k->operands[0].imm); + RzILOpEffect *write = m68k_write_operand_local(ctx, dst, 32, "res", value); + if (!write && dst->type == M68K_OP_IMM) { + write = SEQ2(SETL("res", U32((ut32)ctx->m68k->operands[0].imm)), + STOREW(U32((ut32)dst->imm), UNSIGNED(32, VARL("res")))); + } + if (!write) { + return NULL; + } + return SEQ2(write, m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL)); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static RzILOpBool *macsr_signed(void); + +static int mac_acc_index(m68k_reg reg) { + if (reg == M68K_REG_ACC || reg == M68K_REG_ACC0) { + return 0; + } + if (reg >= M68K_REG_ACC1 && reg <= M68K_REG_ACC3) { + return (int)(reg - M68K_REG_ACC0); + } + return -1; +} + +static RzILOpPure *mac_acc_ext16(M68KILCtx *ctx, int acc_index) { + m68k_reg ext_reg = acc_index < 2 ? M68K_REG_ACCEXT01 : M68K_REG_ACCEXT23; + RzILOpPure *ext = m68k_read_reg_sized(ctx, ext_reg, 32); + if (!ext) { + return NULL; + } + if (acc_index & 1) { + return UNSIGNED(16, SHIFTR0(ext, U8(16))); + } + return UNSIGNED(16, ext); +} + +static RzILOpBool *macsr_flag(ut32 bit) { + return NON_ZERO(LOGAND(VARG("macsr"), U32(1u << bit))); +} + +static RzILOpPure *mac_round_nearest_even32(const char *value, const char *frac, ut32 mid) { + RzILOpBool *tie_up = NON_ZERO(LOGAND(VARL(value), U32(1))); + return ITE(ULT(VARL(frac), U32(mid)), + VARL(value), + ITE(UGT(VARL(frac), U32(mid)), + ADD(VARL(value), U32(1)), + ITE(tie_up, ADD(VARL(value), U32(1)), VARL(value)))); +} + +static RzILOpPure *mac_round_nearest_even64(const char *value, const char *frac32, ut64 mid) { + RzILOpBool *tie_up = NON_ZERO(LOGAND(VARL(value), U64(1))); + RzILOpPure *frac = UNSIGNED(64, VARL(frac32)); + return ITE(ULT(frac, U64(mid)), + VARL(value), + ITE(UGT(UNSIGNED(64, VARL(frac32)), U64(mid)), + ADD(VARL(value), U64(1)), + ITE(tie_up, ADD(VARL(value), U64(1)), VARL(value)))); +} + +/* CFPRM integer MOVCLR/MOVE from ACC with OMC=1 uses the 48-bit accumulator + * {ACCext[15:0], ACC[31:0]}. Signed fits iff ACC[47:31] is all 0 or all 1; + * unsigned fits iff ACC[47:32] is 0. Fractional mode packs + * {ACCext[15:8], ACC[31:0], ACCext[7:0]} and rounds/saturates from that. */ +static RzILOpPure *mac_movclr_integer_store(void) { + RzILOpBool *omc = macsr_flag(M68K_MACSR_OMC); + RzILOpBool *signed_fits = OR(IS_ZERO(VARL("bits_47_31")), EQ(VARL("bits_47_31"), U32(0x1ffff))); + RzILOpBool *unsigned_fits = IS_ZERO(VARL("ext16")); + RzILOpPure *signed_sat = ITE(MSB(VARL("ext16")), U32(0x80000000u), U32(0x7fffffffu)); + return ITE(omc, + ITE(macsr_signed(), + ITE(signed_fits, VARL("src"), signed_sat), + ITE(unsigned_fits, VARL("src"), U32(0xffffffffu))), + VARL("src")); +} + +static RzILOpPure *mac_movclr_fractional_store(void) { + RzILOpBool *acc47 = NON_ZERO(LOGAND(VARL("ext_hi"), U32(0x80))); + RzILOpPure *unsat32 = ITE(macsr_flag(M68K_MACSR_RT), VARL("rnd32"), VARL("src")); + RzILOpBool *fits9 = OR(IS_ZERO(VARL("bits_47_39")), EQ(VARL("bits_47_39"), U32(0x1ff))); + RzILOpPure *sat32_trunc = ITE(fits9, VARL("src"), ITE(acc47, U32(0x80000000u), U32(0x7fffffffu))); + RzILOpBool *rnd32_fits9 = OR(IS_ZERO(VARL("rnd32_bits_47_39")), EQ(VARL("rnd32_bits_47_39"), U32(0x1ff))); + RzILOpBool *rnd32_neg = NON_ZERO(LOGAND(VARL("rnd40"), U64(1ull << 39))); + RzILOpPure *sat32_round = ITE(rnd32_fits9, VARL("rnd32"), ITE(rnd32_neg, U32(0x80000000u), U32(0x7fffffffu))); + RzILOpBool *rnd16_fits9 = OR(IS_ZERO(VARL("rnd16_bits_47_39")), EQ(VARL("rnd16_bits_47_39"), U32(0x1ff))); + RzILOpBool *rnd16_neg = NON_ZERO(LOGAND(VARL("rnd24"), U64(1ull << 23))); + RzILOpPure *sat16 = ITE(rnd16_fits9, LOGAND(VARL("rnd16"), U32(0xffff)), ITE(rnd16_neg, U32(0x8000), U32(0x7fff))); + RzILOpPure *sat32 = ITE(macsr_flag(M68K_MACSR_RT), sat32_round, sat32_trunc); + return ITE(macsr_flag(M68K_MACSR_SU), + ITE(macsr_flag(M68K_MACSR_OMC), sat16, LOGAND(VARL("rnd16"), U32(0xffff))), + ITE(macsr_flag(M68K_MACSR_OMC), sat32, unsat32)); +} + +static RzILOpPure *mac_movclr_store_value(void) { + return ITE(macsr_flag(M68K_MACSR_FI), + mac_movclr_fractional_store(), + mac_movclr_integer_store()); +} + +static RzILOpEffect *mac_clear_extension(M68KILCtx *ctx, int acc_index) { + m68k_reg ext_reg = acc_index < 2 ? M68K_REG_ACCEXT01 : M68K_REG_ACCEXT23; + ut32 keep = (acc_index & 1) ? 0x0000ffffu : 0xffff0000u; + RzILOpPure *ext = m68k_read_reg_sized(ctx, ext_reg, 32); + if (!ext) { + return NULL; + } + return m68k_write_reg_sized(ctx, ext_reg, 32, LOGAND(ext, U32(keep))); +} +#endif + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static RzILOpEffect *mac_bind_acc_store(M68KILCtx *ctx, m68k_reg acc, int acc_index) { + rz_return_val_if_fail(ctx, NULL); + if (!rz_m68k_mode_has_emac(ctx->mode)) { + /* CFPRM 5-6 / MCF5213RM 4.3.1.1: original MAC transfers use only + * ACC[31:0]. Fractional S/U selects a rounded, zero-extended word; + * neither OMC nor R/T changes this transfer. */ + return SEQ4( + SETL("src", m68k_read_reg_sized(ctx, acc, 32)), + SETL("hi16", SHIFTR0(VARL("src"), U8(16))), + SETL("lo16", LOGAND(VARL("src"), U32(0xffff))), + SETL("stored", ITE(AND(macsr_flag(M68K_MACSR_FI), macsr_flag(M68K_MACSR_SU)), LOGAND(mac_round_nearest_even32("hi16", "lo16", 0x8000), U32(0xffff)), VARL("src")))); + } + RzILOpPure *ext16 = mac_acc_ext16(ctx, acc_index); + if (!ext16) { + return NULL; + } + return SEQN(17, + SETL("src", m68k_read_reg_sized(ctx, acc, 32)), + SETL("ext16", ext16), + SETL("ext_hi", SHIFTR0(UNSIGNED(32, VARL("ext16")), U8(8))), + SETL("ext_lo", LOGAND(UNSIGNED(32, VARL("ext16")), U32(0xff))), + SETL("hi16", SHIFTR0(VARL("src"), U8(16))), + SETL("frac24", LOGOR(SHIFTL0(LOGAND(VARL("src"), U32(0xffff)), U8(8)), VARL("ext_lo"))), + SETL("bits_47_31", LOGOR(SHIFTL0(UNSIGNED(32, VARL("ext16")), U8(1)), BOOL_TO_BV(MSB(VARL("src")), 32))), + SETL("bits_47_39", LOGOR(SHIFTL0(VARL("ext_hi"), U8(1)), BOOL_TO_BV(MSB(VARL("src")), 32))), + SETL("field40", LOGOR(SHIFTL0(UNSIGNED(64, VARL("ext_hi")), U8(32)), UNSIGNED(64, VARL("src")))), + SETL("field24", LOGOR(SHIFTL0(UNSIGNED(64, VARL("ext_hi")), U8(16)), UNSIGNED(64, VARL("hi16")))), + SETL("rnd32", mac_round_nearest_even32("src", "ext_lo", 0x80)), + SETL("rnd16", mac_round_nearest_even32("hi16", "frac24", 0x800000u)), + SETL("rnd40", mac_round_nearest_even64("field40", "ext_lo", 0x80)), + SETL("rnd24", mac_round_nearest_even64("field24", "frac24", 0x800000ull)), + SETL("rnd32_bits_47_39", UNSIGNED(32, LOGAND(SHIFTR0(VARL("rnd40"), U8(31)), U64(0x1ff)))), + SETL("rnd16_bits_47_39", UNSIGNED(32, LOGAND(SHIFTR0(VARL("rnd24"), U8(15)), U64(0x1ff)))), + SETL("stored", mac_movclr_store_value())); +} + +static RzILOpEffect *lift_move_from_acc(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_acc_reg(&ctx->m68k->operands[0]) || + !rz_m68k_op_is_gpr(&ctx->m68k->operands[1])) { + return NULL; + } + m68k_reg acc = ctx->m68k->operands[0].reg; + m68k_reg dst = ctx->m68k->operands[1].reg; + int acc_index = mac_acc_index(acc); + if (acc_index < 0) { + return NULL; + } + RzILOpEffect *seq = mac_bind_acc_store(ctx, acc, acc_index); + if (!seq) { + return NULL; + } + RzILOpEffect *write_dst = m68k_write_reg_sized(ctx, dst, 32, VARL("stored")); + if (!write_dst) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write_dst); +} + +static RzILOpEffect *mac_write_ext16(M68KILCtx *ctx, int acc_index) { + m68k_reg ext_reg = acc_index < 2 ? M68K_REG_ACCEXT01 : M68K_REG_ACCEXT23; + RzILOpPure *ext = m68k_read_reg_sized(ctx, ext_reg, 32); + if (!ext) { + return NULL; + } + RzILOpPure *merged = (acc_index & 1) + ? LOGOR(SHIFTL0(UNSIGNED(32, VARL("ext16")), U8(16)), LOGAND(ext, U32(0x0000ffffu))) + : LOGOR(LOGAND(ext, U32(0xffff0000u)), UNSIGNED(32, VARL("ext16"))); + return m68k_write_reg_sized(ctx, ext_reg, 32, merged); +} + +static RzILOpEffect *mac_update_macsr_acc_copy(cs_mode mode, int src_index, int dst_index) { + const bool emac = rz_m68k_mode_has_emac(mode); + ut32 pav_src = 1u << (M68K_MACSR_PAV0 + src_index); + ut32 pav_dst = 1u << (M68K_MACSR_PAV0 + dst_index); + ut32 clear = (1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V) | pav_dst; + if (emac) { + clear |= 1u << M68K_MACSR_EV; + } + RzILOpBool *src_pav = NON_ZERO(LOGAND(VARG("macsr"), U32(pav_src))); + RzILOpBool *n = NON_ZERO(LOGAND(UNSIGNED(32, VARL("ext16")), U32(0x8000))); + RzILOpBool *z = AND(IS_ZERO(VARL("src")), IS_ZERO(VARL("ext16"))); + RzILOpPure *flags = LOGAND(VARG("macsr"), U32(~clear)); + flags = LOGOR(flags, ITE(n, U32(1u << M68K_MACSR_N), U32(0))); + flags = LOGOR(flags, ITE(z, U32(1u << M68K_MACSR_Z), U32(0))); + flags = LOGOR(flags, ITE(src_pav, U32((1u << M68K_MACSR_V) | pav_dst), U32(0))); + if (emac) { + RzILOpBool *int_ev = ITE(macsr_signed(), + INV(OR(IS_ZERO(VARL("bits_47_31")), EQ(VARL("bits_47_31"), U32(0x1ffff)))), + NON_ZERO(VARL("ext16"))); + RzILOpBool *frac_ev = INV(OR(IS_ZERO(VARL("bits_47_39")), EQ(VARL("bits_47_39"), U32(0x1ff)))); + flags = LOGOR(flags, ITE(ITE(macsr_flag(M68K_MACSR_FI), frac_ev, int_ev), U32(1u << M68K_MACSR_EV), U32(0))); + } + return SETG("macsr", flags); +} + +static RzILOpEffect *lift_move_acc_to_acc(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_acc_reg(&ctx->m68k->operands[0]) || + !rz_m68k_op_is_acc_reg(&ctx->m68k->operands[1])) { + return NULL; + } + m68k_reg src = ctx->m68k->operands[0].reg; + m68k_reg dst = ctx->m68k->operands[1].reg; + int src_index = mac_acc_index(src); + int dst_index = mac_acc_index(dst); + if (src_index < 0 || dst_index < 0) { + return NULL; + } + RzILOpPure *ext16 = mac_acc_ext16(ctx, src_index); + if (!ext16) { + return NULL; + } + RzILOpEffect *seq = SEQ5( + SETL("src", m68k_read_reg_sized(ctx, src, 32)), + SETL("ext16", ext16), + SETL("ext_hi", SHIFTR0(UNSIGNED(32, VARL("ext16")), U8(8))), + SETL("bits_47_31", LOGOR(SHIFTL0(UNSIGNED(32, VARL("ext16")), U8(1)), BOOL_TO_BV(MSB(VARL("src")), 32))), + SETL("bits_47_39", LOGOR(SHIFTL0(VARL("ext_hi"), U8(1)), BOOL_TO_BV(MSB(VARL("src")), 32)))); + RzILOpEffect *write_acc = m68k_write_reg_sized(ctx, dst, 32, VARL("src")); + RzILOpEffect *write_ext = mac_write_ext16(ctx, dst_index); + if (!write_acc || !write_ext) { + rz_il_op_effect_free(seq); + rz_il_op_effect_free(write_acc); + rz_il_op_effect_free(write_ext); + return NULL; + } + return SEQ4(seq, write_acc, write_ext, + mac_update_macsr_acc_copy(ctx->mode, src_index, dst_index)); +} + +static RzILOpEffect *lift_move_to_acc(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_acc_reg(&ctx->m68k->operands[1])) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + m68k_reg dst = ctx->m68k->operands[1].reg; + int acc_index = mac_acc_index(dst); + if (acc_index < 0) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, 32, &seq)) { + return NULL; + } + if (!rz_m68k_mode_has_emac(ctx->mode)) { + /* CFPRM 5-10: loading the original 32-bit ACC updates N/Z and + * clears V, without accessing EMAC extension or PAV registers. */ + ut32 clear = (1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V); + RzILOpPure *flags = LOGAND(VARG("macsr"), U32(~clear)); + flags = LOGOR(flags, ITE(MSB(VARL("src")), U32(1u << M68K_MACSR_N), U32(0))); + flags = LOGOR(flags, ITE(IS_ZERO(VARL("src")), U32(1u << M68K_MACSR_Z), U32(0))); + return SEQ3(seq, m68k_write_reg_sized(ctx, dst, 32, VARL("src")), SETG("macsr", flags)); + } + RzILOpPure *signed_ext = ITE(MSB(VARL("src")), U32(0xffff), U32(0)); + RzILOpPure *frac_ext = ITE(MSB(VARL("src")), U32(0xff00), U32(0)); + seq = SEQ2(seq, SETL("ext16", ITE(macsr_flag(M68K_MACSR_FI), frac_ext, ITE(macsr_signed(), signed_ext, U32(0))))); + RzILOpEffect *write_acc = m68k_write_reg_sized(ctx, dst, 32, VARL("src")); + RzILOpEffect *write_ext = mac_write_ext16(ctx, acc_index); + if (!write_acc || !write_ext) { + rz_il_op_effect_free(seq); + rz_il_op_effect_free(write_acc); + rz_il_op_effect_free(write_ext); + return NULL; + } + ut32 pav = 1u << (M68K_MACSR_PAV0 + acc_index); + ut32 clear = (1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V) | + (1u << M68K_MACSR_EV) | pav; + RzILOpBool *n = NON_ZERO(LOGAND(VARL("ext16"), U32(0x8000))); + RzILOpBool *z = AND(IS_ZERO(VARL("src")), IS_ZERO(VARL("ext16"))); + RzILOpPure *flags = LOGAND(VARG("macsr"), U32(~clear)); + flags = LOGOR(flags, ITE(n, U32(1u << M68K_MACSR_N), U32(0))); + flags = LOGOR(flags, ITE(z, U32(1u << M68K_MACSR_Z), U32(0))); + return SEQ4(seq, write_acc, write_ext, SETG("macsr", flags)); +} + +static bool mac_op_is_accext(const cs_m68k_op *op) { + return op && op->type == M68K_OP_REG && + (op->reg == M68K_REG_ACCEXT01 || op->reg == M68K_REG_ACCEXT23); +} + +static RzILOpEffect *lift_move_accext(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + if (dst->type != M68K_OP_REG) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, 32, &seq)) { + return NULL; + } + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, 32, VARL("src")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write); +} + +static bool mac_op_is_mask(const cs_m68k_op *op) { + return op && op->type == M68K_OP_REG && op->reg == M68K_REG_MASK; +} + +static RzILOpEffect *lift_move_mask(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + if (dst->type != M68K_OP_REG) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, 32, &seq)) { + return NULL; + } + seq = SEQ2(seq, SETL("masked", LOGOR(LOGAND(VARL("src"), U32(0xffff)), U32(0xffff0000)))); + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, 32, VARL("masked")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write); +} + +static bool mac_op_is_macsr(const cs_m68k_op *op) { + return op && op->type == M68K_OP_REG && op->reg == M68K_REG_MACSR; +} + +static ut32 macsr_visible_mask(cs_mode mode) { + /* CFPRM MOVE from MACSR: EMAC clears Rx[31:12]; original MAC clears Rx[31:8]. */ + return rz_m68k_mode_has_emac(mode) ? 0xfffu : 0xffu; +} + +static RzILOpEffect *lift_move_macsr(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + if (dst->type != M68K_OP_REG) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, 32, &seq)) { + return NULL; + } + seq = SEQ2(seq, SETL("vis", LOGAND(VARL("src"), U32(macsr_visible_mask(ctx->mode))))); + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, 32, VARL("vis")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write); +} + +static bool mac_op_is_ccr(const cs_m68k_op *op) { + return op && op->type == M68K_OP_REG && op->reg == M68K_REG_CCR; +} + +static RzILOpEffect *lift_move_macsr_to_ccr(M68KILCtx *ctx) { + RzILOpEffect *seq = SETL("macsr_src", VARG("macsr")); + RzILOpPure *ccr = U8(0); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, NON_ZERO(LOGAND(VARL("macsr_src"), U32(1u << M68K_MACSR_N)))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, NON_ZERO(LOGAND(VARL("macsr_src"), U32(1u << M68K_MACSR_Z)))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, NON_ZERO(LOGAND(VARL("macsr_src"), U32(1u << M68K_MACSR_V)))); + if (rz_m68k_mode_has_emac(ctx->mode)) { + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, NON_ZERO(LOGAND(VARL("macsr_src"), U32(1u << M68K_MACSR_EV)))); + } else { + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE); + } + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, IL_FALSE); + return SEQ2(seq, m68k_set_ccr_from_value(ccr)); +} +#endif + +static RzILOpEffect *lift_movclr(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_REG || ctx->m68k->operands[1].type != M68K_OP_REG) { + return NULL; + } + m68k_reg acc = ctx->m68k->operands[0].reg; + m68k_reg dst = ctx->m68k->operands[1].reg; +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + int acc_index = mac_acc_index(acc); + if (acc_index < 0) { + return NULL; + } + ut32 pav = 1u << (M68K_MACSR_PAV0 + acc_index); + RzILOpEffect *seq = mac_bind_acc_store(ctx, acc, acc_index); + if (!seq) { + return NULL; + } + RzILOpEffect *write_dst = m68k_write_reg_sized(ctx, dst, 32, VARL("stored")); + RzILOpEffect *write_acc = m68k_write_reg_sized(ctx, acc, 32, U32(0)); + RzILOpEffect *write_ext = mac_clear_extension(ctx, acc_index); + if (!write_dst || !write_acc || !write_ext) { + rz_il_op_effect_free(seq); + rz_il_op_effect_free(write_dst); + rz_il_op_effect_free(write_acc); + rz_il_op_effect_free(write_ext); + return NULL; + } + return SEQ5(seq, write_dst, write_acc, write_ext, + SETG("macsr", LOGAND(VARG("macsr"), U32(~pav)))); +#else + return SEQ3( + SETL("src", m68k_read_reg_sized(ctx, acc, 32)), + m68k_write_reg_sized(ctx, dst, 32, VARL("src")), + m68k_write_reg_sized(ctx, acc, 32, U32(0))); +#endif +} + +static RzILOpEffect *lift_mvs_mvz(M68KILCtx *ctx, bool sign_extend) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[1])) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 8 && bits != 16) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + seq = SEQ3( + seq, + SETL("res", sign_extend ? SIGNED(32, VARL("src")) : UNSIGNED(32, VARL("src"))), + m68k_write_reg_sized(ctx, ctx->m68k->operands[1].reg, 32, VARL("res"))); + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_coldfire_debug_transfer(M68KILCtx *ctx, ut32 bits) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_mem_addr(&ctx->m68k->operands[0])) { + return NULL; + } + const cs_m68k_op *op = &ctx->m68k->operands[0]; + if (op->type == M68K_OP_MEM && op->address_mode == M68K_AM_NONE) { + return NULL; + } + M68KEA ea = m68k_effective_addr(ctx, op, bits); + if (!ea.addr) { + return NULL; + } + RzILOpEffect *seq = m68k_effect_pre_post(ea.pre, + SEQ2(SETL("debug_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)), + SETL("debug_data", LOADW(bits, VARL("debug_addr")))), + ea.post); + seq = SEQ3( + seq, + SETL("debug_op", U32(ctx->insn->id == M68K_INS_WDEBUG ? M68K_DEBUG_OP_DEBUG : M68K_DEBUG_OP_DATA)), + SETL("debug_bits", U32(bits))); + return SEQ2(seq, m68k_label("m68k_debug")); +} + +static bool coprocessor_number(M68KILCtx *ctx, ut32 *cp_num) { + switch (ctx->insn->id) { + case M68K_INS_CP0BCBUSY: + case M68K_INS_CP0LD: + case M68K_INS_CP0ST: + case M68K_INS_CP0NOP: + *cp_num = 0; + return true; + case M68K_INS_CP1BCBUSY: + case M68K_INS_CP1LD: + case M68K_INS_CP1ST: + case M68K_INS_CP1NOP: + *cp_num = 1; + return true; + default: + return false; + } +} + +static bool coprocessor_operation(ut32 insn_id, M68KCoprocessorOp *op) { + switch (insn_id) { + case M68K_INS_CP0NOP: + case M68K_INS_CP1NOP: + *op = M68K_CP_OP_NOP; + return true; + case M68K_INS_CP0BCBUSY: + case M68K_INS_CP1BCBUSY: + *op = M68K_CP_OP_BRANCH; + return true; + case M68K_INS_CP0LD: + case M68K_INS_CP1LD: + *op = M68K_CP_OP_LOAD; + return true; + case M68K_INS_CP0ST: + case M68K_INS_CP1ST: + *op = M68K_CP_OP_STORE; + return true; + default: + return false; + } +} + +static RzILOpEffect *append_coprocessor_common(M68KILCtx *ctx, RzILOpEffect *seq) { + ut32 cp_num = 0; + if (coprocessor_number(ctx, &cp_num)) { + seq = seq ? SEQ2(seq, SETL("cp_num", U32(cp_num))) : SETL("cp_num", U32(cp_num)); + } + M68KCoprocessorOp cp_op = M68K_CP_OP_NOP; + if (coprocessor_operation(ctx->insn->id, &cp_op)) { + seq = seq ? SEQ2(seq, SETL("cp_op", U32((ut32)cp_op))) : SETL("cp_op", U32((ut32)cp_op)); + } + return seq; +} + +static bool coprocessor_transfer_is_store(M68KILCtx *ctx) { + switch (ctx->insn->id) { + case M68K_INS_CP0ST: + case M68K_INS_CP1ST: + return true; + default: + return false; + } +} + +static RzILOpEffect *append_coprocessor_transfer_metadata(M68KILCtx *ctx, RzILOpEffect *seq, ut32 bits) { + seq = append_coprocessor_common(ctx, seq); + seq = seq ? SEQ2(seq, SETL("cp_store", U32(coprocessor_transfer_is_store(ctx) ? 1 : 0))) : SETL("cp_store", U32(coprocessor_transfer_is_store(ctx) ? 1 : 0)); + seq = SEQ2(seq, SETL("cp_bits", U32(bits))); + if (ctx->m68k->op_count > 2 && ctx->m68k->operands[2].type == M68K_OP_IMM) { + seq = SEQ2(seq, SETL("cp_selector", U32((ut32)ctx->m68k->operands[2].imm))); + } + if (ctx->m68k->op_count > 3 && ctx->m68k->operands[3].type == M68K_OP_IMM) { + seq = SEQ2(seq, SETL("cp_extension", U32((ut32)ctx->m68k->operands[3].imm))); + } + return seq; +} + +static RzILOpEffect *lift_coprocessor_load_transfer(M68KILCtx *ctx, ut32 bits) { + if (ctx->m68k->op_count < 1) { + return m68k_label("m68k_coprocessor"); + } + + const cs_m68k_op *src = &ctx->m68k->operands[0]; + RzILOpEffect *seq = NULL; + if (src->type == M68K_OP_MEM && src->address_mode == M68K_AM_NONE) { + return m68k_label("m68k_coprocessor"); + } + if (rz_m68k_op_is_mem_addr(src)) { + M68KEA ea = m68k_effective_addr(ctx, src, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + rz_il_op_effect_free(seq); + return NULL; + } + seq = m68k_effect_pre_post(ea.pre, + SEQ2(SETL("cp_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)), + SETL("cp_data", LOADW(bits, VARL("cp_addr")))), + ea.post); + } else { + RzILOpPure *value = m68k_read_operand(ctx, src, bits, NULL, NULL); + if (!value) { + return m68k_label("m68k_coprocessor"); + } + seq = SETL("cp_data", value); + } + seq = append_coprocessor_transfer_metadata(ctx, seq, bits); + return seq ? SEQ2(seq, m68k_label("m68k_coprocessor")) : m68k_label("m68k_coprocessor"); +} + +static RzILOpEffect *coprocessor_metadata_only_transfer(M68KILCtx *ctx, ut32 bits) { + RzILOpEffect *seq = NULL; + seq = append_coprocessor_transfer_metadata(ctx, seq, bits); + return seq ? SEQ2(seq, m68k_label("m68k_coprocessor")) : m68k_label("m68k_coprocessor"); +} + +static RzILOpPure *coprocessor_external_data(ut32 bits) { + return bits == 32 ? VARG("cp_external_data") : UNSIGNED(bits, VARG("cp_external_data")); +} + +static RzILOpEffect *lift_coprocessor_store_transfer(M68KILCtx *ctx, ut32 bits) { + if (ctx->m68k->op_count < 2) { + return coprocessor_metadata_only_transfer(ctx, bits); + } + + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + if (dst->type == M68K_OP_MEM && dst->address_mode == M68K_AM_NONE) { + return m68k_label("m68k_coprocessor"); + } + + RzILOpEffect *seq = SETL("cp_data", coprocessor_external_data(bits)); + if (rz_m68k_op_is_mem_addr(dst)) { + M68KEA ea = m68k_effective_addr(ctx, dst, bits); + if (!ea.addr) { + return NULL; + } + seq = SEQ2(seq, + m68k_effect_pre_post(ea.pre, + SEQ2(SETL("cp_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)), + STOREW(VARL("cp_addr"), UNSIGNED(bits, VARL("cp_data")))), + ea.post)); + } else if (dst->type == M68K_OP_REG) { + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, bits, VARL("cp_data")); + if (!write) { + return coprocessor_metadata_only_transfer(ctx, bits); + } + seq = SEQ2(seq, write); + } else { + return coprocessor_metadata_only_transfer(ctx, bits); + } + + seq = append_coprocessor_transfer_metadata(ctx, seq, bits); + return seq ? SEQ2(seq, m68k_label("m68k_coprocessor")) : m68k_label("m68k_coprocessor"); +} + +static RzILOpEffect *lift_coprocessor_transfer(M68KILCtx *ctx) { + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (coprocessor_transfer_is_store(ctx)) { + return lift_coprocessor_store_transfer(ctx, bits); + } + return lift_coprocessor_load_transfer(ctx, bits); +} + +static RzILOpEffect *lift_coprocessor_branch(M68KILCtx *ctx) { + RzILOpEffect *seq = append_coprocessor_common(ctx, NULL); + if (ctx->m68k->op_count > 0 && ctx->m68k->operands[0].type == M68K_OP_BR_DISP) { + seq = seq ? SEQ2(seq, SETL("cp_branch", m68k_read_operand(ctx, &ctx->m68k->operands[0], 32, NULL, NULL))) : SETL("cp_branch", m68k_read_operand(ctx, &ctx->m68k->operands[0], 32, NULL, NULL)); + } + return SEQ2(seq, m68k_label("m68k_coprocessor")); +} + +static RzILOpEffect *lift_coprocessor_nop(M68KILCtx *ctx) { + RzILOpEffect *seq = append_coprocessor_common(ctx, NULL); + if (ctx->m68k->op_count > 0 && ctx->m68k->operands[0].type == M68K_OP_IMM) { + seq = seq ? SEQ2(seq, SETL("cp_extension", U32((ut32)ctx->m68k->operands[0].imm))) : SETL("cp_extension", U32((ut32)ctx->m68k->operands[0].imm)); + } + return SEQ2(seq, m68k_label("m68k_coprocessor")); +} +#endif + +static RzILOpPure *callm_frame_addr(ut32 offset) { + return offset ? ADD(VARL("callm_frame"), U32(offset)) : VARL("callm_frame"); +} + +static const m68k_reg m68k_data_addr_regs[] = { + M68K_REG_D0, + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, +}; + +static m68k_reg callm_reg_from_code(ut32 code) { + return code < RZ_ARRAY_SIZE(m68k_data_addr_regs) ? m68k_data_addr_regs[code] : M68K_REG_INVALID; +} + +static RzILOpBool *callm_reg_code_is(ut32 code) { + return EQ(VARL("callm_reg_code"), U32(code)); +} + +static RzILOpEffect *callm_store_selected_reg(M68KILCtx *ctx) { + RzILOpEffect *effect = EMPTY(); + for (st32 code = 15; code >= 0; code--) { + m68k_reg reg = callm_reg_from_code((ut32)code); + RzILOpPure *value = m68k_read_reg_sized(ctx, reg, 32); + RzILOpEffect *store = value ? STOREW(callm_frame_addr(0x10), value) : NULL; + if (!store) { + rz_warn_if_reached(); + return NULL; + } + effect = BRANCH(callm_reg_code_is((ut32)code), store, effect); + } + return effect; +} + +static RzILOpEffect *callm_load_selected_reg(M68KILCtx *ctx) { + RzILOpEffect *effect = EMPTY(); + for (st32 code = 14; code >= 0; code--) { + m68k_reg reg = callm_reg_from_code((ut32)code); + RzILOpEffect *write = m68k_write_reg_sized(ctx, reg, 32, VARL("callm_data")); + if (!write) { + rz_warn_if_reached(); + return NULL; + } + effect = BRANCH(callm_reg_code_is((ut32)code), write, effect); + } + return effect; +} + +static RzILOpEffect *lift_callm_type0(M68KILCtx *ctx) { + return SEQN(11, + callm_store_selected_reg(ctx), + STOREW(callm_frame_addr(0), UNSIGNED(16, VARL("callm_frame_info"))), + SETL("callm_ccr_arg", LOGOR(SHIFTL0(UNSIGNED(16, UNSIGNED(8, VARG("sr"))), U8(8)), UNSIGNED(16, VARL("callm_count")))), + STOREW(callm_frame_addr(2), UNSIGNED(16, VARL("callm_ccr_arg"))), + STOREW(callm_frame_addr(4), UNSIGNED(32, VARL("callm_addr"))), + STOREW(callm_frame_addr(8), m68k_reg_value(ctx, M68K_REG_A7)), + STOREW(callm_frame_addr(0x0c), U32(ctx->next_addr)), + STOREW(callm_frame_addr(0x14), U32(0)), + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, VARL("callm_frame")), + callm_load_selected_reg(ctx), + JMP(ADD(VARL("callm_entry"), U32(2)))); +} + +static RzILOpEffect *lift_callm_address_effects(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2 || + ctx->m68k->operands[0].type != M68K_OP_IMM) { + return m68k_label("m68k_callm"); + } + + const cs_m68k_op *target = &ctx->m68k->operands[1]; + if (!rz_m68k_op_is_mem_addr(target)) { + return m68k_label("m68k_callm"); + } + + M68KEA ea = m68k_effective_addr(ctx, target, 32); + if (!ea.addr) { + return NULL; + } + + RzILOpEffect *seq = SEQ8( + SETL("callm_count", U32((ut32)(ctx->m68k->operands[0].imm & 0xff))), + SETL("callm_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)), + SETL("callm_frame_info", LOADW(16, VARL("callm_addr"))), + SETL("callm_entry", LOADW(32, ADD(VARL("callm_addr"), U32(4)))), + SETL("callm_data", LOADW(32, ADD(VARL("callm_addr"), U32(8)))), + SETL("callm_entry_word", LOADW(16, VARL("callm_entry"))), + SETL("callm_reg_code", UNSIGNED(32, SHIFTR0(VARL("callm_entry_word"), U8(12)))), + SETL("callm_frame", SUB(m68k_reg_value(ctx, M68K_REG_A7), U32(0x18)))); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + return SEQ2(seq, BRANCH(IS_ZERO(LOGAND(VARL("callm_frame_info"), U16(0xff00))), lift_callm_type0(ctx), m68k_label("m68k_callm"))); +} + +static ut32 pmove_address_bits(M68KILCtx *ctx) { + for (ut8 i = 0; i < ctx->m68k->op_count; i++) { + const cs_m68k_op *op = &ctx->m68k->operands[i]; + if (op->type != M68K_OP_REG) { + continue; + } + const char *name = cs_reg_name(ctx->handle, op->reg); + if (!name) { + continue; + } + if (RZ_STR_EQ(name, "srp") || RZ_STR_EQ(name, "crp")) { + return 64; + } + if (RZ_STR_EQ(name, "mmusr")) { + return 16; + } + } + return 32; +} + +static ut32 pmove_transfer_bits(M68KILCtx *ctx, m68k_reg reg) { + const char *name = cs_reg_name(ctx->handle, reg); + if (!name) { + return 0; + } + if (RZ_STR_EQ(name, "mmusr")) { + return 16; + } + if (RZ_STR_EQ(name, "srp") || RZ_STR_EQ(name, "crp")) { + return 64; + } + if (RZ_STR_EQ(name, "tc") || + RZ_STR_EQ(name, "itt0") || RZ_STR_EQ(name, "itt1") || + RZ_STR_EQ(name, "dtt0") || RZ_STR_EQ(name, "dtt1") || + RZ_STR_EQ(name, "tt0") || RZ_STR_EQ(name, "tt1")) { + return 32; + } + return 0; +} + +static const cs_m68k_op *mmu_address_operand(M68KILCtx *ctx) { + switch (ctx->insn->id) { + case M68K_INS_PLOADR: + case M68K_INS_PLOADW: + case M68K_INS_PTESTR: + case M68K_INS_PTESTW: + if (ctx->m68k->op_count > 1) { + return &ctx->m68k->operands[1]; + } + return ctx->m68k->op_count ? &ctx->m68k->operands[0] : NULL; + case M68K_INS_PFLUSH: + case M68K_INS_PFLUSHN: + return ctx->m68k->op_count ? &ctx->m68k->operands[ctx->m68k->op_count - 1] : NULL; + case M68K_INS_PLPAR: + case M68K_INS_PLPAW: + return ctx->m68k->op_count ? &ctx->m68k->operands[0] : NULL; + case M68K_INS_PMOVE: + case M68K_INS_PMOVEFD: + for (ut8 i = 0; i < ctx->m68k->op_count; i++) { + if (ctx->m68k->operands[i].type == M68K_OP_MEM) { + return &ctx->m68k->operands[i]; + } + } + return NULL; + default: + return NULL; + } +} + +static M68KMMUOp mmu_operation(ut32 insn_id) { + switch (insn_id) { + case M68K_INS_PLOADR: + case M68K_INS_PLOADW: + return M68K_MMU_OP_LOAD; + case M68K_INS_PFLUSH: + case M68K_INS_PFLUSHN: + case M68K_INS_PFLUSHA: + case M68K_INS_PFLUSHAN: + return M68K_MMU_OP_FLUSH; + case M68K_INS_PTESTR: + case M68K_INS_PTESTW: + return M68K_MMU_OP_TEST; + case M68K_INS_PMOVE: + case M68K_INS_PMOVEFD: + return M68K_MMU_OP_MOVE; + case M68K_INS_PLPAR: + case M68K_INS_PLPAW: + return M68K_MMU_OP_LOAD_PHYSICAL; + default: + return M68K_MMU_OP_MOVE; + } +} + +/** + * \brief Transfer direction encoded by an MMU instruction. + * \return 0 for a read, 1 for a write, or -1 when the instruction has no direction. + */ +static int mmu_read_write_access(ut32 insn_id) { + switch (insn_id) { + case M68K_INS_PLOADR: + case M68K_INS_PTESTR: + case M68K_INS_PLPAR: + return 0; + case M68K_INS_PLOADW: + case M68K_INS_PTESTW: + case M68K_INS_PLPAW: + return 1; + default: + return -1; + } +} + +static RzILOpPure *mmu_function_code_value(M68KILCtx *ctx, const cs_m68k_op *op) { + if (op->type == M68K_OP_IMM) { + return U32((ut32)op->imm); + } + if (op->type == M68K_OP_REG) { + RzILOpPure *value = m68k_read_reg_sized(ctx, op->reg, 32); + return value; + } + return NULL; +} + +static RzILOpEffect *append_mmu_operand_metadata(M68KILCtx *ctx, RzILOpEffect *seq) { + switch (ctx->insn->id) { + case M68K_INS_PLOADR: + case M68K_INS_PLOADW: + case M68K_INS_PTESTR: + case M68K_INS_PTESTW: + if (ctx->m68k->op_count > 0) { + RzILOpPure *fc = mmu_function_code_value(ctx, &ctx->m68k->operands[0]); + if (fc) { + seq = seq ? SEQ2(seq, SETL("mmu_fc", fc)) : SETL("mmu_fc", fc); + } + } + if ((ctx->insn->id == M68K_INS_PTESTR || ctx->insn->id == M68K_INS_PTESTW) && + ctx->m68k->op_count > 2 && ctx->m68k->operands[2].type == M68K_OP_IMM) { + seq = SEQ2(seq, SETL("mmu_level", U32((ut32)ctx->m68k->operands[2].imm))); + } + break; + case M68K_INS_PFLUSH: + case M68K_INS_PFLUSHN: + if (ctx->m68k->op_count > 2) { + RzILOpPure *fc = mmu_function_code_value(ctx, &ctx->m68k->operands[0]); + if (fc) { + seq = SEQ2(seq, SETL("mmu_fc", fc)); + } + if (ctx->m68k->operands[1].type == M68K_OP_IMM) { + seq = SEQ2(seq, SETL("mmu_mask", U32((ut32)ctx->m68k->operands[1].imm))); + } + } + break; + default: + break; + } + return seq; +} + +static RzILOpEffect *append_mmu_metadata(M68KILCtx *ctx, RzILOpEffect *seq) { + seq = seq ? SEQ2(seq, SETL("mmu_op", U32((ut32)mmu_operation(ctx->insn->id)))) : SETL("mmu_op", U32((ut32)mmu_operation(ctx->insn->id))); + int rw = mmu_read_write_access(ctx->insn->id); + if (rw >= 0) { + seq = SEQ2(seq, SETL("mmu_rw", U32((ut32)rw))); + } + switch (ctx->insn->id) { + case M68K_INS_PFLUSH: + case M68K_INS_PFLUSHN: + case M68K_INS_PFLUSHA: + case M68K_INS_PFLUSHAN: + seq = SEQ2(seq, SETL("mmu_flush_non_global", U32(ctx->insn->id == M68K_INS_PFLUSHN || ctx->insn->id == M68K_INS_PFLUSHAN ? 1 : 0))); + break; + case M68K_INS_PMOVEFD: + seq = SEQ2(seq, SETL("mmu_fd", U32(1))); + break; + default: + break; + } + return append_mmu_operand_metadata(ctx, seq); +} + +static RzILOpEffect *lift_mmu_address_effects(M68KILCtx *ctx, ut32 bits) { + RzILOpEffect *seq = NULL; + const cs_m68k_op *op = mmu_address_operand(ctx); + if (op) { + if (op->type == M68K_OP_MEM && !op->address_mode) { + return NULL; + } + if (rz_m68k_op_is_gpr(op)) { + RzILOpPure *addr = m68k_read_reg_sized(ctx, op->reg, M68K_ADDR_BITS); + if (!addr) { + return NULL; + } + seq = SETL("mmu_addr", UNSIGNED(M68K_ADDR_BITS, addr)); + } else if (op->type == M68K_OP_IMM) { + seq = SETL("mmu_addr", U32((ut32)op->imm)); + } else if (!rz_m68k_op_is_mem_addr(op)) { + return m68k_label("m68k_mmu"); + } else { + M68KEA ea = m68k_effective_addr(ctx, op, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + seq = SETL("mmu_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + } + } + seq = append_mmu_metadata(ctx, seq); + return SEQ2(seq, m68k_label("m68k_mmu")); +} + +static RzILOpEffect *lift_mmu_flush_all(M68KILCtx *ctx) { + RzILOpEffect *seq = NULL; + seq = append_mmu_metadata(ctx, seq); + seq = SEQ2(seq, SETL("mmu_flush_all", U32(1))); + return SEQ2(seq, m68k_label("m68k_mmu")); +} + +static M68KCacheOp cache_operation(ut32 insn_id) { + switch (insn_id) { +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + case M68K_INS_INTOUCH: + return M68K_CACHE_OP_TOUCH; +#endif + case M68K_INS_CINVL: + case M68K_INS_CINVP: + case M68K_INS_CINVA: + return M68K_CACHE_OP_INVALIDATE; + case M68K_INS_CPUSHL: + case M68K_INS_CPUSHP: + case M68K_INS_CPUSHA: + return M68K_CACHE_OP_PUSH; + default: + return M68K_CACHE_OP_TOUCH; + } +} + +static RzILOpEffect *append_cache_metadata(M68KILCtx *ctx, RzILOpEffect *seq, bool all_scope) { + seq = seq ? SEQ2(seq, SETL("cache_op", U32((ut32)cache_operation(ctx->insn->id)))) : SETL("cache_op", U32((ut32)cache_operation(ctx->insn->id))); + if (ctx->m68k->op_count > 0 && ctx->m68k->operands[0].type == M68K_OP_IMM) { + seq = SEQ2(seq, SETL("cache_selector", U32((ut32)ctx->m68k->operands[0].imm))); + } + if (all_scope) { + seq = SEQ2(seq, SETL("cache_all", U32(1))); + } + return seq; +} + +static const cs_m68k_op *cache_address_operand(M68KILCtx *ctx) { + for (ut8 i = 0; i < ctx->m68k->op_count; i++) { + const cs_m68k_op *op = &ctx->m68k->operands[i]; + if (rz_m68k_op_is_addr_reg(op)) { + return op; + } + if (rz_m68k_op_is_mem_addr(op)) { + return op; + } + } + return NULL; +} + +static RzILOpEffect *lift_cache_address_effects(M68KILCtx *ctx) { + RzILOpEffect *seq = NULL; + const cs_m68k_op *op = cache_address_operand(ctx); + const bool needs_address = rz_m68k_insn_cache_requires_address(ctx->insn->id); + if (!op) { + if (needs_address) { + return NULL; + } + seq = append_cache_metadata(ctx, seq, true); + return SEQ2(seq, m68k_label("m68k_cache")); + } + if (op->type == M68K_OP_MEM && !op->address_mode) { + if (needs_address) { + return NULL; + } + seq = append_cache_metadata(ctx, seq, true); + return SEQ2(seq, m68k_label("m68k_cache")); + } + if (rz_m68k_op_is_addr_reg(op)) { + RzILOpPure *addr = m68k_read_reg_sized(ctx, op->reg, M68K_ADDR_BITS); + if (!addr) { + return NULL; + } + seq = SETL("cache_addr", UNSIGNED(M68K_ADDR_BITS, addr)); + seq = append_cache_metadata(ctx, seq, false); + return SEQ2(seq, m68k_label("m68k_cache")); + } + if (!rz_m68k_op_is_mem_addr(op)) { + return m68k_label(needs_address ? "m68k_illegal" : "m68k_cache"); + } + + M68KEA ea = m68k_effective_addr(ctx, op, 32); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + seq = SETL("cache_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + seq = append_cache_metadata(ctx, seq, false); + return SEQ2(seq, m68k_label("m68k_cache")); +} + +static RzILOpEffect *lift_pmove(M68KILCtx *ctx) { + if (ctx->m68k->op_count != 2) { + return lift_mmu_address_effects(ctx, pmove_address_bits(ctx)); + } + + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + const cs_m68k_op *mem = NULL; + const cs_m68k_op *reg = NULL; + bool mem_to_reg = false; + + if (src->type == M68K_OP_MEM && dst->type == M68K_OP_REG) { + mem = src; + reg = dst; + mem_to_reg = true; + } else if (src->type == M68K_OP_REG && dst->type == M68K_OP_MEM) { + reg = src; + mem = dst; + } else if ((src->type == M68K_OP_REG || src->type == M68K_OP_IMM) && dst->type == M68K_OP_REG) { + ut32 bits = pmove_transfer_bits(ctx, dst->reg); + if (!bits) { + return lift_mmu_address_effects(ctx, pmove_address_bits(ctx)); + } + RzILOpPure *value = m68k_read_operand(ctx, src, bits, NULL, NULL); + if (!value) { + return NULL; + } + RzILOpEffect *write = m68k_write_reg_sized(ctx, dst->reg, bits, VARL("src")); + if (!write) { + rz_il_op_pure_free(value); + return NULL; + } + return SEQ2(SETL("src", value), write); + } else { + return lift_mmu_address_effects(ctx, pmove_address_bits(ctx)); + } + + ut32 bits = pmove_transfer_bits(ctx, reg->reg); + if (!bits) { + return lift_mmu_address_effects(ctx, pmove_address_bits(ctx)); + } + if (mem->type == M68K_OP_MEM && !mem->address_mode) { + return NULL; + } + if (!rz_m68k_op_is_mem_addr(mem)) { + return lift_mmu_address_effects(ctx, bits); + } + + M68KEA ea = m68k_effective_addr(ctx, mem, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + + RzILOpEffect *seq = SETL("mmu_addr", UNSIGNED(M68K_ADDR_BITS, ea.addr)); + if (mem_to_reg) { + seq = m68k_effect_pre_post(ea.pre, + SEQ2(seq, SETL("src", LOADW(bits, VARL("mmu_addr")))), + ea.post); + RzILOpEffect *write = m68k_write_reg_sized(ctx, reg->reg, bits, VARL("src")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write); + } + + RzILOpPure *value = m68k_read_reg_sized(ctx, reg->reg, bits); + if (!value) { + rz_il_op_effect_free(seq); + rz_il_op_effect_free(ea.pre); + rz_il_op_effect_free(ea.post); + return NULL; + } + return m68k_effect_pre_post(ea.pre, + SEQ3(seq, SETL("src", value), STOREW(VARL("mmu_addr"), UNSIGNED(bits, VARL("src")))), + ea.post); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static RzILOpEffect *lift_coldfire_bitop_reg(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[0])) { + return NULL; + } + m68k_reg reg = ctx->m68k->operands[0].reg; + RzILOpEffect *seq = SEQ2( + SETL("src", m68k_read_reg_sized(ctx, reg, 32)), + SETL("res", ctx->insn->id == M68K_INS_BITREV ? reverse_bits32("src") : ctx->insn->id == M68K_INS_BYTEREV ? reverse_bytes32("src") + : ff1_result32("src"))); + seq = seq ? SEQ2(seq, m68k_write_reg_sized(ctx, reg, 32, VARL("res"))) : m68k_write_reg_sized(ctx, reg, 32, VARL("res")); + if (ctx->insn->id == M68K_INS_FF1) { + seq = SEQ2(seq, set_flags_ff1(VARL("src"))); + } + return seq; +} + +static RzILOpEffect *lift_rem(M68KILCtx *ctx, bool sign) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_data_reg_pair(&ctx->m68k->operands[1])) { + return NULL; + } + m68k_reg dw = ctx->m68k->operands[1].reg_pair.reg_0; + m68k_reg dx = ctx->m68k->operands[1].reg_pair.reg_1; + if (dw == dx) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], 32, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *dst = m68k_read_reg_sized(ctx, dx, 32); + if (!dst) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("dst", dst)); + + RzILOpPure *dividend = sign ? SIGNED(64, VARL("dst")) : UNSIGNED(64, VARL("dst")); + RzILOpPure *divisor = sign ? SIGNED(64, VARL("src")) : UNSIGNED(64, VARL("src")); + RzILOpEffect *write_remainder = m68k_write_reg_sized(ctx, dw, 32, UNSIGNED(32, VARL("rem"))); + if (!write_remainder) { + rz_il_op_pure_free(dividend); + rz_il_op_pure_free(divisor); + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *normal = SEQ4( + SETL("quot", sign ? SDIV(dividend, divisor) : DIV(dividend, divisor)), + SETL("rem", SUB(sign ? SIGNED(64, VARL("dst")) : UNSIGNED(64, VARL("dst")), MUL(VARL("quot"), sign ? SIGNED(64, VARL("src")) : UNSIGNED(64, VARL("src"))))), + write_remainder, + set_flags_rem(VARL("quot"), IL_FALSE)); + RzILOpBool *overflow = sign + ? AND(EQ(VARL("dst"), U32(0x80000000)), EQ(VARL("src"), U32(0xffffffff))) + : UGT(DIV(UNSIGNED(64, VARL("dst")), UNSIGNED(64, VARL("src"))), U64(0x7fffffff)); + RzILOpEffect *do_divide = BRANCH(overflow, set_flags_rem(U32(0), IL_TRUE), normal); + return SEQ2(seq, BRANCH(IS_ZERO(VARL("src")), m68k_exception(M68K_TRAP_OP_DIV_ZERO, M68K_VECTOR_ZERO_DIVIDE, "m68k_trap"), do_divide)); +} + +static RzILOpEffect *lift_sats(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[0])) { + return NULL; + } + m68k_reg reg = ctx->m68k->operands[0].reg; + return SEQ4( + SETL("src", m68k_read_reg_sized(ctx, reg, 32)), + SETL("res", ITE(m68k_ccr_bit(M68K_CCR_V), ITE(MSB(VARL("src")), U32(0x7fffffffu), U32(0x80000000u)), VARL("src"))), + m68k_write_reg_sized(ctx, reg, 32, VARL("res")), + m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpBool *macsr_signed(void) { + /* ColdFire PRM integer mode: S/U=0 signed, S/U=1 unsigned. + * QEMU treats MACSR_SU the other way around; do not follow QEMU. */ + return IS_ZERO(LOGAND(VARG("macsr"), U32(1u << M68K_MACSR_SU))); +} + +static RzILOpBool *mac_mode_signed(void) { + /* Fractional operands are always two's-complement signed. In fractional + * mode S/U selects the store width rather than operand signedness. */ + return OR(macsr_flag(M68K_MACSR_FI), macsr_signed()); +} + +static RzILOpPure *mac_read_reg_part(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits) { + if (!rz_m68k_op_is_gpr(op)) { + return NULL; + } + RzILOpPure *value = m68k_read_reg_sized(ctx, op->reg, 32); + if (!value) { + return NULL; + } + if (bits == 16) { + const bool upper = op->flags & M68K_OP_FLAG_REG_UPPER; + RzILOpPure *fractional_half = upper + ? LOGAND(DUP(value), U32(0xffff0000)) + : SHIFTL0(DUP(value), U8(16)); + value = upper ? SHIFTR0(value, U8(16)) : value; + value = UNSIGNED(16, value); + RzILOpPure *unsigned_half = DUP(value); + RzILOpPure *integer_half = ITE(macsr_signed(), SIGNED(32, value), UNSIGNED(32, unsigned_half)); + return ITE(macsr_flag(M68K_MACSR_FI), fractional_half, integer_half); + } + return value; +} + +static RzILOpBool *mac_local_out_of_range(const char *local, ut32 bits) { + return ITE(mac_mode_signed(), + NE(SIGNED(80, SIGNED(bits, VARL(local))), VARL(local)), + NON_ZERO(SHIFTR0(VARL(local), U8((ut8)bits)))); +} + +static RzILOpEffect *mac_bind_product(cs_mode mode, const cs_m68k_op *shift) { + const ut32 product_bits = rz_m68k_mode_has_emac(mode) ? 40 : 32; + const ut32 fractional_shift = 64 - product_bits; + const ut64 remainder_mask = (1ULL << fractional_shift) - 1; + const ut64 halfway = 1ULL << (fractional_shift - 1); + + RzILOpEffect *seq = SETL("prod_wide", + ITE(mac_mode_signed(), + MUL(SIGNED(80, VARL("src0")), SIGNED(80, VARL("src1"))), + MUL(UNSIGNED(80, VARL("src0")), UNSIGNED(80, VARL("src1"))))); + RzILOpPure *scaled = VARL("prod_wide"); + if (shift) { + if (shift->flags & M68K_OP_FLAG_SHIFT_LEFT) { + scaled = SHIFTL0(scaled, U8(1)); + } else { + scaled = ITE(mac_mode_signed(), SHIFTRA(DUP(scaled), U8(1)), SHIFTR0(scaled, U8(1))); + } + } + seq = SEQ2(seq, SETL("prod_scaled", scaled)); + + /* The CFPRM specifies that the encoded scale factor is ignored for + * fractional operands, so truncation and rounding use prod_wide. */ + RzILOpPure *fractional_truncated = SHIFTR0(VARL("prod_wide"), U8((ut8)fractional_shift)); + RzILOpPure *remainder = LOGAND(VARL("prod_wide"), UN(80, remainder_mask)); + RzILOpBool *round_fractional = AND( + macsr_flag(M68K_MACSR_RT), + OR( + UGT(DUP(remainder), UN(80, halfway)), + AND(EQ(remainder, UN(80, halfway)), NON_ZERO(LOGAND(DUP(fractional_truncated), UN(80, 1)))))); + RzILOpPure *fractional_product = SIGNED(64, + UNSIGNED(product_bits, + ADD(fractional_truncated, ITE(round_fractional, UN(80, 1), UN(80, 0))))); + RzILOpPure *integer_product_bits = UNSIGNED(product_bits, VARL("prod_scaled")); + RzILOpPure *integer_product = ITE(macsr_signed(), + SIGNED(64, DUP(integer_product_bits)), + UNSIGNED(64, integer_product_bits)); + return SEQ3(seq, + SETL("prod", ITE(macsr_flag(M68K_MACSR_FI), fractional_product, integer_product)), + SETL("prod_overflow", ITE(macsr_flag(M68K_MACSR_FI), U32(0), ITE(mac_local_out_of_range("prod_scaled", product_bits), U32(1), U32(0))))); +} + +static RzILOpEffect *mac_bind_acc(M68KILCtx *ctx, m68k_reg acc_reg, int acc_index) { + rz_return_val_if_fail(ctx, NULL); + RzILOpPure *acc = m68k_read_reg_sized(ctx, acc_reg, 32); + if (!acc) { + return NULL; + } + if (!rz_m68k_mode_has_emac(ctx->mode)) { + return SEQ2( + SETL("acc_full", acc), + SETL("acc", ITE(mac_mode_signed(), SIGNED(64, VARL("acc_full")), UNSIGNED(64, VARL("acc_full"))))); + } + RzILOpPure *ext = mac_acc_ext16(ctx, acc_index); + if (!ext) { + rz_il_op_pure_free(acc); + return NULL; + } + RzILOpPure *fractional = LOGOR( + SHIFTL0(UNSIGNED(48, SHIFTR0(VARL("acc_ext"), U8(8))), U8(40)), + LOGOR( + SHIFTL0(UNSIGNED(48, VARL("acc_word")), U8(8)), + UNSIGNED(48, LOGAND(VARL("acc_ext"), U16(0xff))))); + RzILOpPure *integer = LOGOR( + SHIFTL0(UNSIGNED(48, VARL("acc_ext")), U8(32)), + UNSIGNED(48, VARL("acc_word"))); + return SEQ4( + SETL("acc_word", acc), + SETL("acc_ext", ext), + SETL("acc_full", ITE(macsr_flag(M68K_MACSR_FI), fractional, integer)), + SETL("acc", ITE(mac_mode_signed(), SIGNED(64, VARL("acc_full")), UNSIGNED(64, VARL("acc_full"))))); +} + +static RzILOpPure *mac_accumulate_result(bool subtract) { + RzILOpPure *signed_result = subtract + ? SUB(SIGNED(80, VARL("acc")), SIGNED(80, VARL("prod"))) + : ADD(SIGNED(80, VARL("acc")), SIGNED(80, VARL("prod"))); + RzILOpPure *unsigned_result = subtract + ? SUB(UNSIGNED(80, VARL("acc")), UNSIGNED(80, VARL("prod"))) + : ADD(UNSIGNED(80, VARL("acc")), UNSIGNED(80, VARL("prod"))); + return ITE(mac_mode_signed(), signed_result, unsigned_result); +} + +static RzILOpEffect *mac_bind_result(cs_mode mode) { + if (!rz_m68k_mode_has_emac(mode)) { + return SEQ2( + SETL("res_full", UNSIGNED(32, VARL("res_wide"))), + SETL("res", VARL("res_full"))); + } + RzILOpPure *fractional_ext = LOGOR( + SHIFTL0(UNSIGNED(16, SHIFTR0(VARL("res_full"), U8(40))), U8(8)), + UNSIGNED(16, LOGAND(VARL("res_full"), UN(48, 0xff)))); + RzILOpPure *integer_ext = UNSIGNED(16, SHIFTR0(VARL("res_full"), U8(32))); + RzILOpPure *fractional_acc = UNSIGNED(32, SHIFTR0(VARL("res_full"), U8(8))); + RzILOpPure *integer_acc = UNSIGNED(32, VARL("res_full")); + return SEQ3( + SETL("res_full", UNSIGNED(48, VARL("res_wide"))), + SETL("res", ITE(macsr_flag(M68K_MACSR_FI), fractional_acc, integer_acc)), + SETL("ext16", ITE(macsr_flag(M68K_MACSR_FI), fractional_ext, integer_ext))); +} + +static RzILOpEffect *mac_write_result(M68KILCtx *ctx, m68k_reg acc_reg, int acc_index) { + rz_return_val_if_fail(ctx, NULL); + RzILOpEffect *write_acc = m68k_write_reg_sized(ctx, acc_reg, 32, VARL("res")); + if (!write_acc) { + return NULL; + } + if (!rz_m68k_mode_has_emac(ctx->mode)) { + return write_acc; + } + RzILOpEffect *write_ext = mac_write_ext16(ctx, acc_index); + if (!write_ext) { + rz_il_op_effect_free(write_acc); + return NULL; + } + return SEQ2(write_acc, write_ext); +} + +static RzILOpBool *mac_result_out_of_range(ut32 bits) { + return mac_local_out_of_range("res_wide", bits); +} + +static RzILOpBool *mac_accumulation_overflow(cs_mode mode) { + return mac_result_out_of_range(rz_m68k_mode_has_emac(mode) ? 48 : 32); +} + +static RzILOpBool *mac_operation_overflow(cs_mode mode) { + return OR(NON_ZERO(VARL("prod_overflow")), mac_accumulation_overflow(mode)); +} + +static RzILOpBool *mac_extension_overflow(void) { + return ITE(macsr_flag(M68K_MACSR_FI), + mac_result_out_of_range(40), + mac_result_out_of_range(32)); +} + +static RzILOpEffect *mac_update_macsr(cs_mode mode, int acc_index) { + const bool emac = rz_m68k_mode_has_emac(mode); + /* CFPRM 5-2/5-13: original MAC V is sticky, unlike EMAC V. */ + ut32 clear = (1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z); + if (emac) { + clear |= (1u << M68K_MACSR_V) | (1u << M68K_MACSR_EV); + } + RzILOpBool *overflow = mac_operation_overflow(mode); + RzILOpPure *flags = LOGAND(VARG("macsr"), U32(~clear)); + flags = LOGOR(flags, ITE(MSB(VARL("res_full")), U32(1u << M68K_MACSR_N), U32(0))); + flags = LOGOR(flags, ITE(IS_ZERO(VARL("res_full")), U32(1u << M68K_MACSR_Z), U32(0))); + if (emac) { + ut32 pav = 1u << (M68K_MACSR_PAV0 + acc_index); + RzILOpBool *past_overflow = NON_ZERO(LOGAND(VARG("macsr"), U32(pav))); + flags = LOGOR(flags, ITE(OR(DUP(overflow), past_overflow), U32(1u << M68K_MACSR_V), U32(0))); + flags = LOGOR(flags, ITE(mac_extension_overflow(), U32(1u << M68K_MACSR_EV), U32(0))); + flags = LOGOR(flags, ITE(overflow, U32(pav), U32(0))); + } else { + flags = LOGOR(flags, ITE(overflow, U32(1u << M68K_MACSR_V), U32(0))); + } + return SETG("macsr", flags); +} + +/* CFPRM MAAAC/MASAC/MSAAC/MSSAC: N/Z/V/EV come from the secondary + * accumulator. V is also set when PAVw was already set. PAVx and PAVw + * are set on overflow of that destination and otherwise left alone. */ +static RzILOpEffect *mac_update_macsr_dual(cs_mode mode, int first_index, int second_index) { + const bool emac = rz_m68k_mode_has_emac(mode); + ut32 clear = (1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V); + if (emac) { + clear |= 1u << M68K_MACSR_EV; + } + ut32 pav_first = 1u << (M68K_MACSR_PAV0 + first_index); + ut32 pav_second = 1u << (M68K_MACSR_PAV0 + second_index); + RzILOpBool *v = OR(NON_ZERO(VARL("ov_second")), + NON_ZERO(LOGAND(VARG("macsr"), U32(pav_second)))); + RzILOpPure *flags = LOGAND(VARG("macsr"), U32(~clear)); + flags = LOGOR(flags, ITE(MSB(VARL("res_full")), U32(1u << M68K_MACSR_N), U32(0))); + flags = LOGOR(flags, ITE(IS_ZERO(VARL("res_full")), U32(1u << M68K_MACSR_Z), U32(0))); + flags = LOGOR(flags, ITE(v, U32(1u << M68K_MACSR_V), U32(0))); + if (emac) { + flags = LOGOR(flags, ITE(NON_ZERO(VARL("ev_second")), U32(1u << M68K_MACSR_EV), U32(0))); + } + flags = LOGOR(flags, ITE(NON_ZERO(VARL("ov_first")), U32(pav_first), U32(0))); + flags = LOGOR(flags, ITE(NON_ZERO(VARL("ov_second")), U32(pav_second), U32(0))); + return SETG("macsr", flags); +} + +static RzILOpEffect *mac_memory_update(M68KILCtx *ctx, RzILOpEffect *seq, const cs_m68k_op *mem, const cs_m68k_op *reg) { + rz_return_val_if_fail(ctx && ctx->insn, NULL); + if (!mem || !reg || !rz_m68k_op_is_gpr(reg)) { + return seq; + } + if (ctx->insn->size < 4) { + rz_il_op_effect_free(seq); + return NULL; + } + /* CFPRM MAC/MSAC with load: extension bit 5 enables MASK for the + * longword load address only. Address writeback uses the unmasked EA. */ + bool use_mask = (ctx->insn->bytes[3] & (1u << 5)) != 0; + M68KEA ea = m68k_effective_addr(ctx, mem, 32); + if (!ea.addr) { + m68k_ea_fini(&ea); + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *write = m68k_write_reg_sized(ctx, reg->reg, 32, VARL("mem_load")); + if (!write) { + m68k_ea_fini(&ea); + rz_il_op_effect_free(seq); + return NULL; + } + /* A parallel load may overwrite its own address register. Base the + * postincrement on the captured, unmasked EA, not the loaded value. */ + if (mem->address_mode == M68K_AM_REGI_ADDR_POST_INC) { + rz_il_op_effect_free(ea.post); + ea.post = m68k_write_reg_sized(ctx, rz_m68k_op_base_reg(mem), 32, ADD(VARL("mac_ea"), U32(4))); + } + RzILOpPure *addr = VARL("mac_ea"); + if (use_mask) { + addr = LOGAND(addr, VARG("mask")); + } + RzILOpEffect *access = m68k_effect_pre_post(ea.pre, + SEQ4(SETL("mac_ea", UNSIGNED(32, ea.addr)), + SETL("mem_addr", addr), + SETL("mem_load", LOADW(32, VARL("mem_addr"))), + write), + ea.post); + return seq ? SEQ2(seq, access) : access; +} + +static RzILOpEffect *lift_mac_msac(M68KILCtx *ctx, bool subtract) { + if (ctx->m68k->op_count < 3) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 16 && bits != 32) { + return NULL; + } + const cs_m68k_op *src0 = &ctx->m68k->operands[0]; + const cs_m68k_op *src1 = &ctx->m68k->operands[1]; + const cs_m68k_op *acc_op = &ctx->m68k->operands[ctx->m68k->op_count - 1]; + if (!rz_m68k_op_is_acc_reg(acc_op)) { + return NULL; + } + int acc_index = mac_acc_index(acc_op->reg); + if (acc_index < 0) { + return NULL; + } + RzILOpPure *src0_value = mac_read_reg_part(ctx, src0, bits); + RzILOpPure *src1_value = mac_read_reg_part(ctx, src1, bits); + if (!src0_value || !src1_value) { + rz_il_op_pure_free(src0_value); + rz_il_op_pure_free(src1_value); + return NULL; + } + + const cs_m68k_op *shift = NULL; + const cs_m68k_op *mem = NULL; + const cs_m68k_op *update_reg = NULL; + for (ut8 i = 2; i + 1 < ctx->m68k->op_count; i++) { + const cs_m68k_op *op = &ctx->m68k->operands[i]; + if (op->type == M68K_OP_SHIFT) { + shift = op; + } else if (op->type == M68K_OP_MEM) { + mem = op; + if (i + 1 < ctx->m68k->op_count - 1) { + update_reg = &ctx->m68k->operands[i + 1]; + } + } + } + + RzILOpEffect *bind_acc = mac_bind_acc(ctx, acc_op->reg, acc_index); + if (!bind_acc) { + rz_il_op_pure_free(src0_value); + rz_il_op_pure_free(src1_value); + return NULL; + } + RzILOpEffect *seq = SEQ6( + SETL("src0", src0_value), + SETL("src1", src1_value), + bind_acc, + mac_bind_product(ctx->mode, shift), + SETL("res_wide", mac_accumulate_result(subtract)), + mac_bind_result(ctx->mode)); + RzILOpEffect *write_result = mac_write_result(ctx, acc_op->reg, acc_index); + if (!write_result) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ3(seq, write_result, mac_update_macsr(ctx->mode, acc_index)); + return mac_memory_update(ctx, seq, mem, update_reg); +} + +static RzILOpEffect *mac_dual_acc_write(M68KILCtx *ctx, RzILOpEffect *seq, const cs_m68k_op *acc_op, bool subtract, const char *overflow_local, const char *extension_overflow_local) { + if (!rz_m68k_op_is_acc_reg(acc_op)) { + rz_il_op_effect_free(seq); + return NULL; + } + int acc_index = mac_acc_index(acc_op->reg); + if (acc_index < 0) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *bind_acc = mac_bind_acc(ctx, acc_op->reg, acc_index); + if (!bind_acc) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ4( + seq, + bind_acc, + SETL("res_wide", mac_accumulate_result(subtract)), + mac_bind_result(ctx->mode)); + RzILOpEffect *write_result = mac_write_result(ctx, acc_op->reg, acc_index); + if (!write_result) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ4(seq, write_result, + SETL(overflow_local, ITE(mac_operation_overflow(ctx->mode), U32(1), U32(0))), + SETL(extension_overflow_local, ITE(mac_extension_overflow(), U32(1), U32(0)))); +} + +static RzILOpEffect *lift_mac_dual_acc(M68KILCtx *ctx, bool subtract_first, bool subtract_second) { + if (ctx->m68k->op_count < 4) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 16 && bits != 32) { + return NULL; + } + const cs_m68k_op *src0 = &ctx->m68k->operands[0]; + const cs_m68k_op *src1 = &ctx->m68k->operands[1]; + const cs_m68k_op *acc0 = &ctx->m68k->operands[ctx->m68k->op_count - 2]; + const cs_m68k_op *acc1 = &ctx->m68k->operands[ctx->m68k->op_count - 1]; + if (!rz_m68k_op_is_acc_reg(acc0) || !rz_m68k_op_is_acc_reg(acc1)) { + return NULL; + } + int first_index = mac_acc_index(acc0->reg); + int second_index = mac_acc_index(acc1->reg); + if (first_index < 0 || second_index < 0) { + return NULL; + } + RzILOpPure *src0_value = mac_read_reg_part(ctx, src0, bits); + RzILOpPure *src1_value = mac_read_reg_part(ctx, src1, bits); + if (!src0_value || !src1_value) { + rz_il_op_pure_free(src0_value); + rz_il_op_pure_free(src1_value); + return NULL; + } + + const cs_m68k_op *shift = NULL; + for (ut8 i = 2; i + 2 < ctx->m68k->op_count; i++) { + const cs_m68k_op *op = &ctx->m68k->operands[i]; + if (op->type == M68K_OP_SHIFT) { + shift = op; + } else { + rz_il_op_pure_free(src0_value); + rz_il_op_pure_free(src1_value); + return NULL; + } + } + + RzILOpEffect *seq = SEQ3( + SETL("src0", src0_value), + SETL("src1", src1_value), + mac_bind_product(ctx->mode, shift)); + seq = mac_dual_acc_write(ctx, seq, acc0, subtract_first, "ov_first", "ev_first"); + if (!seq) { + return NULL; + } + seq = mac_dual_acc_write(ctx, seq, acc1, subtract_second, "ov_second", "ev_second"); + if (!seq) { + return NULL; + } + return SEQ2(seq, mac_update_macsr_dual(ctx->mode, first_index, second_index)); +} +#endif + +static RzILOpPure *div_quotient_expr(bool sign, const char *dividend_local, const char *divisor_local) { + RzILOpPure *dividend = sign ? SIGNED(64, VARL(dividend_local)) : UNSIGNED(64, VARL(dividend_local)); + RzILOpPure *divisor = sign ? SIGNED(64, VARL(divisor_local)) : UNSIGNED(64, VARL(divisor_local)); + return sign ? SDIV(dividend, divisor) : DIV(dividend, divisor); +} + +static RzILOpPure *div_remainder_expr(bool sign, const char *dividend_local, const char *divisor_local) { + /* 680x0 remainder keeps the dividend sign (truncating toward zero). + * RzIL SMOD follows the divisor sign, so derive rem from quot. */ + RzILOpPure *dividend = sign ? SIGNED(64, VARL(dividend_local)) : UNSIGNED(64, VARL(dividend_local)); + RzILOpPure *divisor = sign ? SIGNED(64, VARL(divisor_local)) : UNSIGNED(64, VARL(divisor_local)); + return SUB(dividend, MUL(VARL("quot"), divisor)); +} + +static RzILOpBool *div_quotient_overflows(bool sign, ut32 bits, RzILOpPure *quotient) { + if (sign) { + RzILOpPure *min = bits == 16 ? S64(-0x8000) : S64(-0x80000000LL); + RzILOpPure *max = bits == 16 ? S64(0x7fff) : S64(0x7fffffff); + return OR(SLT(DUP(quotient), min), SGT(quotient, max)); + } + return UGT(quotient, bits == 16 ? U64(0xffff) : U64(0xffffffffULL)); +} + +static RzILOpEffect *lift_div_reg(M68KILCtx *ctx, bool sign, m68k_reg reg, ut32 bits, RzILOpEffect *seq) { + RzILOpPure *dst = m68k_read_reg_sized(ctx, reg, 32); + if (!dst) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = seq ? SEQ2(seq, SETL("dst", dst)) : SETL("dst", dst); + ut32 quotient_bits = bits == 16 ? 16 : 32; + RzILOpEffect *write_result = NULL; + if (bits == 16) { + RzILOpPure *result = LOGOR( + SHIFTL0(UNSIGNED(32, VARL("rem")), U8(16)), + UNSIGNED(32, UNSIGNED(16, VARL("quot")))); + write_result = m68k_write_reg_sized(ctx, reg, 32, result); + } else { + write_result = m68k_write_reg_sized(ctx, reg, 32, UNSIGNED(32, VARL("quot"))); + } + if (!write_result) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *normal = bits == 16 + ? SEQ4( + SETL("quot", div_quotient_expr(sign, "dst", "src")), + SETL("rem", div_remainder_expr(sign, "dst", "src")), + write_result, + m68k_set_flags_div(VARL("quot"), quotient_bits, IL_FALSE)) + : SEQ3( + SETL("quot", div_quotient_expr(sign, "dst", "src")), + write_result, + m68k_set_flags_div(VARL("quot"), quotient_bits, IL_FALSE)); + RzILOpBool *overflow = div_quotient_overflows(sign, quotient_bits, div_quotient_expr(sign, "dst", "src")); + RzILOpEffect *do_divide = BRANCH(overflow, m68k_set_flags_div(UN(quotient_bits, 0), quotient_bits, IL_TRUE), normal); + return SEQ2(seq, BRANCH(IS_ZERO(VARL("src")), m68k_exception(M68K_TRAP_OP_DIV_ZERO, M68K_VECTOR_ZERO_DIVIDE, "m68k_trap"), do_divide)); +} + +static RzILOpEffect *lift_div_long(M68KILCtx *ctx, bool sign, m68k_reg remainder_reg, m68k_reg quotient_reg, bool wide_dividend, RzILOpEffect *seq) { + if (!rz_m68k_reg_is_dreg(remainder_reg) || !rz_m68k_reg_is_dreg(quotient_reg)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *low = m68k_read_reg_sized(ctx, quotient_reg, 32); + RzILOpPure *dividend = low; + if (wide_dividend) { + RzILOpPure *high = m68k_read_reg_sized(ctx, remainder_reg, 32); + if (!high || !low) { + rz_il_op_pure_free(high); + rz_il_op_pure_free(low); + rz_il_op_effect_free(seq); + return NULL; + } + dividend = APPEND(high, low); + } + if (!dividend) { + rz_il_op_effect_free(seq); + return NULL; + } + + RzILOpEffect *write_quotient = m68k_write_reg_sized(ctx, quotient_reg, 32, UNSIGNED(32, VARL("quot"))); + RzILOpEffect *write_remainder = remainder_reg != quotient_reg + ? m68k_write_reg_sized(ctx, remainder_reg, 32, UNSIGNED(32, VARL("rem"))) + : NULL; + if (!write_quotient || (remainder_reg != quotient_reg && !write_remainder)) { + rz_il_op_pure_free(dividend); + rz_il_op_effect_free(write_quotient); + rz_il_op_effect_free(write_remainder); + rz_il_op_effect_free(seq); + return NULL; + } + + seq = seq ? SEQ2(seq, SETL("dst", dividend)) : SETL("dst", dividend); + RzILOpEffect *normal = SETL("quot", div_quotient_expr(sign, "dst", "src")); + if (write_remainder) { + normal = SEQ2(normal, SETL("rem", div_remainder_expr(sign, "dst", "src"))); + } + normal = SEQ2(normal, write_quotient); + if (write_remainder) { + normal = SEQ2(normal, write_remainder); + } + normal = SEQ2(normal, m68k_set_flags_div(VARL("quot"), 32, IL_FALSE)); + RzILOpBool *overflow = div_quotient_overflows(sign, 32, div_quotient_expr(sign, "dst", "src")); + RzILOpEffect *do_divide = BRANCH(overflow, m68k_set_flags_div(U32(0), 32, IL_TRUE), normal); + return SEQ2(seq, BRANCH(IS_ZERO(VARL("src")), m68k_exception(M68K_TRAP_OP_DIV_ZERO, M68K_VECTOR_ZERO_DIVIDE, "m68k_trap"), do_divide)); +} + +static bool decode_classic_long_div(const M68KILCtx *ctx, m68k_reg *remainder_reg, m68k_reg *quotient_reg, bool *wide_dividend) { + rz_return_val_if_fail(ctx && remainder_reg && quotient_reg && wide_dividend, false); + if (rz_m68k_mode_is_coldfire(ctx->mode) || ctx->insn->size < 4) { + return false; + } + /* M68000PRM long DIV extension word: Dq[14:12], size[10], Dr[2:0]. + * Decode it directly because some Capstone versions collapse Dr:Dq. */ + ut16 ext = ((ut16)ctx->insn->bytes[2] << 8) | ctx->insn->bytes[3]; + *quotient_reg = (m68k_reg)(M68K_REG_D0 + ((ext >> 12) & 7)); + *remainder_reg = (m68k_reg)(M68K_REG_D0 + (ext & 7)); + *wide_dividend = ext & (1u << 10); + return true; +} + +static RzILOpEffect *lift_div(M68KILCtx *ctx, bool sign) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 16); + if (bits != 16 && bits != 32) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + if (bits == 32) { + m68k_reg remainder_reg; + m68k_reg quotient_reg; + bool wide_dividend; + if (decode_classic_long_div(ctx, &remainder_reg, "ient_reg, &wide_dividend)) { + return lift_div_long(ctx, sign, remainder_reg, quotient_reg, wide_dividend, seq); + } + } + if (rz_m68k_op_is_data_reg(dst)) { + return lift_div_reg(ctx, sign, dst->reg, bits, seq); + } + if (bits == 32 && dst->type == M68K_OP_REG_PAIR) { + return lift_div_long(ctx, sign, dst->reg_pair.reg_0, dst->reg_pair.reg_1, true, seq); + } + rz_il_op_effect_free(seq); + return NULL; +} + +static RzILOpPure *movep_addr(ut32 offset) { + return offset ? ADD(VARL("addr"), U32(offset)) : VARL("addr"); +} + +static RzILOpPure *movep_read_byte(ut32 offset, ut32 bits, ut32 shift) { + RzILOpPure *byte = UNSIGNED(bits, LOADW(8, movep_addr(offset))); + return shift ? SHIFTL0(byte, U8(shift)) : byte; +} + +static RzILOpEffect *movep_store_byte(ut32 offset, ut32 shift) { + RzILOpPure *byte = shift ? SHIFTR0(VARL("src"), U8(shift)) : VARL("src"); + return STOREW(movep_addr(offset), UNSIGNED(8, byte)); +} + +static RzILOpEffect *lift_movep(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 16); + if (bits != 16 && bits != 32) { + return NULL; + } + bool mem_to_reg = rz_m68k_op_is_mem_addr(src) && rz_m68k_op_is_data_reg(dst); + bool reg_to_mem = rz_m68k_op_is_data_reg(src) && rz_m68k_op_is_mem_addr(dst); + if (!mem_to_reg && !reg_to_mem) { + return NULL; + } + const cs_m68k_op *mem = mem_to_reg ? src : dst; + M68KEA ea = m68k_effective_addr(ctx, mem, bits); + if (!ea.addr) { + return NULL; + } + + RzILOpEffect *seq = SETL("addr", UNSIGNED(32, ea.addr)); + if (mem_to_reg) { + RzILOpPure *res = bits == 16 + ? LOGOR(movep_read_byte(0, 16, 8), movep_read_byte(2, 16, 0)) + : LOGOR(LOGOR(movep_read_byte(0, 32, 24), movep_read_byte(2, 32, 16)), LOGOR(movep_read_byte(4, 32, 8), movep_read_byte(6, 32, 0))); + seq = SEQ3( + seq, + SETL("res", res), + m68k_write_reg_sized(ctx, dst->reg, bits, VARL("res"))); + } else { + seq = SEQ3( + seq, + SETL("src", m68k_read_reg_sized(ctx, src->reg, bits)), + bits == 16 ? SEQ2(movep_store_byte(0, 8), movep_store_byte(2, 0)) : SEQ4(movep_store_byte(0, 24), movep_store_byte(2, 16), movep_store_byte(4, 8), movep_store_byte(6, 0))); + } + return m68k_effect_pre_post(ea.pre, seq, ea.post); +} + +static m68k_reg movem_reg_for_bit(ut32 bit) { + return bit < RZ_ARRAY_SIZE(m68k_data_addr_regs) ? m68k_data_addr_regs[bit] : M68K_REG_INVALID; +} + +static ut32 movem_reg_count(ut32 reg_bits) { + return (ut32)rz_bits_count_ones_ut32(reg_bits); +} + +static RzILOpPure *movem_addr_at(ut32 offset) { + return offset ? ADD(VARL("addr"), U32(offset)) : VARL("addr"); +} + +static RzILOpEffect *write_movem_reg(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value) { + if (bits == 16) { + return m68k_write_reg_sized(ctx, reg, 32, SIGNED(32, value)); + } + return m68k_write_reg_sized(ctx, reg, 32, value); +} + +static RzILOpEffect *lift_movem(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 16 && bits != 32) { + return NULL; + } + bool reg_to_mem = src->type == M68K_OP_REG_BITS && rz_m68k_op_is_mem_addr(dst); + bool mem_to_reg = rz_m68k_op_is_mem_addr(src) && dst->type == M68K_OP_REG_BITS; + if (!reg_to_mem && !mem_to_reg) { + return NULL; + } + const cs_m68k_op *regs_op = reg_to_mem ? src : dst; + const cs_m68k_op *mem = reg_to_mem ? dst : src; + ut32 reg_bits = regs_op->register_bits; + if (reg_bits & ~0xffffu) { + return NULL; + } + ut32 count = movem_reg_count(reg_bits); + if (!count) { + return NOP(); + } + + ut32 bytes = rz_m68k_bits_access_bytes(bits); + bool predec = mem->address_mode == M68K_AM_REGI_ADDR_PRE_DEC; + bool postinc = mem->address_mode == M68K_AM_REGI_ADDR_POST_INC; + m68k_reg base_reg = rz_m68k_op_base_reg(mem); + RzILOpEffect *seq = NULL; + if (predec || postinc) { + if (!rz_m68k_reg_is_areg(base_reg)) { + return NULL; + } + seq = SETL("addr", m68k_reg_value(ctx, base_reg)); + } else { + M68KEA ea = m68k_effective_addr(ctx, mem, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + seq = SETL("addr", UNSIGNED(32, ea.addr)); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + } + + if (reg_to_mem && predec) { + for (int i = 15; i >= 0; i--) { + if (!(reg_bits & (1u << i))) { + continue; + } + m68k_reg reg = movem_reg_for_bit((ut32)i); + RzILOpPure *value = reg == base_reg && m68k_mode_uses_later_movem_base_value(ctx->mode) + ? UNSIGNED(bits, SUB(m68k_reg_value(ctx, base_reg), U32(bytes))) + : m68k_read_reg_sized(ctx, reg, bits); + if (!value) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("addr", SUB(VARL("addr"), U32(bytes)))); + RzILOpEffect *write = STOREW(VARL("addr"), UNSIGNED(bits, value)); + if (!write) { + rz_il_op_pure_free(value); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + } + return SEQ2(seq, m68k_write_reg_sized(ctx, base_reg, 32, VARL("addr"))); + } + + ut32 offset = 0; + for (ut32 i = 0; i < 16; i++) { + if (!(reg_bits & (1u << i))) { + continue; + } + m68k_reg reg = movem_reg_for_bit(i); + RzILOpEffect *op = NULL; + RzILOpPure *value = NULL; + if (reg_to_mem) { + value = m68k_read_reg_sized(ctx, reg, bits); + if (!value) { + rz_il_op_effect_free(seq); + return NULL; + } + op = STOREW(movem_addr_at(offset), UNSIGNED(bits, value)); + } else { + value = LOADW(bits, movem_addr_at(offset)); + op = write_movem_reg(ctx, reg, bits, value); + } + if (!op) { + if (reg_to_mem) { + rz_il_op_pure_free(value); + } + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, op); + offset += bytes; + } + if (postinc) { + seq = SEQ2(seq, m68k_write_reg_sized(ctx, base_reg, 32, ADD(VARL("addr"), U32(offset)))); + } + return seq; +} + +static RzILOpPure *move16_addr_at(const char *addr_local, ut32 offset) { + return offset ? ADD(VARL(addr_local), U32(offset)) : VARL(addr_local); +} + +static bool move16_operand_addr(M68KILCtx *ctx, const cs_m68k_op *op, const char *addr_local, RzILOpEffect **seq, m68k_reg *postinc_reg) { + rz_return_val_if_fail(ctx && op && addr_local && seq && postinc_reg, false); + *postinc_reg = M68K_REG_INVALID; + if (op->type != M68K_OP_MEM) { + return false; + } + if (op->address_mode == M68K_AM_REGI_ADDR_POST_INC) { + m68k_reg base_reg = rz_m68k_op_base_reg(op); + if (!rz_m68k_reg_is_areg(base_reg)) { + return false; + } + *seq = *seq ? SEQ2(*seq, SETL(addr_local, m68k_reg_value(ctx, base_reg))) : SETL(addr_local, m68k_reg_value(ctx, base_reg)); + *postinc_reg = base_reg; + return true; + } + M68KEA ea = m68k_effective_addr(ctx, op, 32); + if (!ea.addr) { + return false; + } + RzILOpEffect *set = m68k_effect_pre_post(ea.pre, + SETL(addr_local, UNSIGNED(32, ea.addr)), ea.post); + *seq = *seq ? SEQ2(*seq, set) : set; + return true; +} + +static RzILOpEffect *lift_move16(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + RzILOpEffect *seq = NULL; + m68k_reg src_postinc = M68K_REG_INVALID; + m68k_reg dst_postinc = M68K_REG_INVALID; + if (!move16_operand_addr(ctx, src, "src_addr", &seq, &src_postinc) || + !move16_operand_addr(ctx, dst, "dst_addr", &seq, &dst_postinc)) { + return NULL; + } + + seq = SEQN(11, + seq, + SETL("src_line", LOGAND(VARL("src_addr"), U32(~0xfu))), + SETL("dst_line", LOGAND(VARL("dst_addr"), U32(~0xfu))), + SETL("word0", LOADW(32, move16_addr_at("src_line", 0))), + SETL("word1", LOADW(32, move16_addr_at("src_line", 4))), + SETL("word2", LOADW(32, move16_addr_at("src_line", 8))), + SETL("word3", LOADW(32, move16_addr_at("src_line", 12))), + STOREW(move16_addr_at("dst_line", 0), UNSIGNED(32, VARL("word0"))), + STOREW(move16_addr_at("dst_line", 4), UNSIGNED(32, VARL("word1"))), + STOREW(move16_addr_at("dst_line", 8), UNSIGNED(32, VARL("word2"))), + STOREW(move16_addr_at("dst_line", 12), UNSIGNED(32, VARL("word3")))); + if (src_postinc != M68K_REG_INVALID) { + seq = SEQ2(seq, m68k_write_reg_sized(ctx, src_postinc, 32, ADD(VARL("src_addr"), U32(16)))); + } + if (dst_postinc != M68K_REG_INVALID && dst_postinc != src_postinc) { + seq = SEQ2(seq, m68k_write_reg_sized(ctx, dst_postinc, 32, ADD(VARL("dst_addr"), U32(16)))); + } + return seq; +} + +static RzILOpEffect *lift_lea(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_mem_addr(&ctx->m68k->operands[0]) || ctx->m68k->operands[1].type != M68K_OP_REG) { + return NULL; + } + M68KEA ea = m68k_effective_addr(ctx, &ctx->m68k->operands[0], 32); + if (!ea.addr) { + return NULL; + } + RzILOpEffect *seq = m68k_write_reg_sized(ctx, ctx->m68k->operands[1].reg, 32, ea.addr); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + return seq; +} + +static RzILOpEffect *push32(M68KILCtx *ctx, RzILOpPure *value) { + return SEQ3( + SETL("push_value", value), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, -4), + STOREW(m68k_reg_value(ctx, M68K_REG_A7), UNSIGNED(32, VARL("push_value")))); +} + +static RzILOpEffect *lift_pea(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_mem_addr(&ctx->m68k->operands[0])) { + return NULL; + } + M68KEA ea = m68k_effective_addr(ctx, &ctx->m68k->operands[0], 32); + RzILOpEffect *seq = push32(ctx, ea.addr); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + return seq; +} + +static RzILOpPure *apply_binop(RzILOpPureCode binop, RzILOpPure *dst, RzILOpPure *src) { + switch (binop) { + case RZ_IL_OP_ADD: + return ADD(dst, src); + case RZ_IL_OP_SUB: + return SUB(dst, src); + case RZ_IL_OP_LOGAND: + return LOGAND(dst, src); + case RZ_IL_OP_LOGOR: + return LOGOR(dst, src); + case RZ_IL_OP_LOGXOR: + return LOGXOR(dst, src); + default: + return NULL; + } +} + +static RzILOpEffect *lift_binop(M68KILCtx *ctx, RzILOpPureCode binop, bool address_dst, bool compare_only) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 op_bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + ut32 bits = address_dst ? 32 : op_bits; + RzILOpEffect *seq = NULL; + if (address_dst && op_bits == 16) { + if (!m68k_operand_to_local(ctx, "src_raw", src, op_bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("src", SIGNED(32, VARL("src_raw")))); + } else if (!m68k_operand_to_local(ctx, "src", src, op_bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", dst, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *res = apply_binop(binop, VARL("dst"), VARL("src")); + if (!res) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("res", res)); + if (!compare_only) { + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, address_dst ? 32 : bits, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + } + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + if (!address_dst || compare_only) { + RzILOpBool *v = NULL; + RzILOpBool *c = NULL; + RzILOpBool *x = NULL; + if (binop == RZ_IL_OP_ADD) { + v = m68k_add_overflow(VARL("dst"), VARL("src"), VARL("res")); + c = ULT(VARL("res"), VARL("dst")); + x = (RzILOpBool *)DUP(c); + } else if (binop == RZ_IL_OP_SUB) { + v = m68k_sub_overflow(VARL("dst"), VARL("src"), VARL("res")); + c = ULT(VARL("dst"), VARL("src")); + x = compare_only ? NULL : (RzILOpBool *)DUP(c); + } else { + v = IL_FALSE; + c = IL_FALSE; + } + seq = SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, v, c, x)); + } + return seq; +} + +static RzILOpEffect *lift_status_binop(M68KILCtx *ctx, RzILOpPureCode binop) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + if (!rz_m68k_op_is_status_reg(dst)) { + return NULL; + } + ut32 bits = dst->reg == M68K_REG_CCR ? 8 : 16; + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("dst", m68k_read_reg_sized(ctx, dst->reg, bits))); + RzILOpPure *res = apply_binop(binop, VARL("dst"), VARL("src")); + if (!res) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("res", res)); + RzILOpEffect *write = m68k_write_status_reg(ctx, dst->reg, VARL("res")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + return SEQ2(seq, write); +} + +static RzILOpEffect *lift_addx_subx(M68KILCtx *ctx, bool subtract) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", src, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", dst, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + + seq = SEQ3( + seq, + SETL("x", BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_X), bits)), + SETL("srcx", ADD(VARL("src"), VARL("x")))); + RzILOpPure *res = subtract ? SUB(VARL("dst"), VARL("srcx")) : ADD(VARL("dst"), VARL("srcx")); + seq = SEQ2(seq, SETL("res", res)); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + + RzILOpPure *wide_dst = UNSIGNED(64, VARL("dst")); + RzILOpPure *wide_src = UNSIGNED(64, VARL("src")); + RzILOpPure *wide_x = UNSIGNED(64, VARL("x")); + RzILOpBool *c = subtract + ? ULT(wide_dst, ADD(wide_src, wide_x)) + : UGT(ADD(ADD(wide_dst, wide_src), wide_x), U64(bits == 32 ? UT32_MAX : ((1ULL << bits) - 1))); + RzILOpBool *v = subtract ? m68k_subx_overflow(bits) : m68k_addx_overflow(bits); + return SEQ2(seq, m68k_set_flags_nzvcx_extend(VARL("res"), bits, v, c)); +} + +static RzILOpPure *bcd_byte_to_decimal(const char *local) { + RzILOpPure *high = UNSIGNED(32, SHIFTR0(LOGAND(VARL(local), U8(0xf0)), U8(4))); + RzILOpPure *low = UNSIGNED(32, LOGAND(VARL(local), U8(0x0f))); + return ADD(MUL(high, U32(10)), low); +} + +static RzILOpPure *bcd_decimal_to_byte(const char *local) { + RzILOpPure *high = SHIFTL0(DIV(UNSIGNED(32, VARL(local)), U32(10)), U8(4)); + RzILOpPure *low = MOD(UNSIGNED(32, VARL(local)), U32(10)); + return UNSIGNED(8, LOGOR(high, low)); +} + +static RzILOpEffect *set_flags_bcd(RzILOpPure *result, RzILOpBool *carry) { + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xea)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(m68k_ccr_bit(M68K_CCR_Z), IS_ZERO(UNSIGNED(8, result)))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, (RzILOpBool *)DUP(carry)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, carry); + return m68k_set_ccr_from_value(ccr); +} + +static RzILOpEffect *lift_abcd_sbcd(M68KILCtx *ctx, bool subtract) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], 8, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[1], 8, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ4( + seq, + SETL("src_dec", bcd_byte_to_decimal("src")), + SETL("dst_dec", bcd_byte_to_decimal("dst")), + SETL("x", BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_X), 32))); + if (subtract) { + seq = SEQ3( + seq, + SETL("diff", SUB(SUB(VARL("dst_dec"), VARL("src_dec")), VARL("x"))), + SETL("res_dec", ITE(SLT(VARL("diff"), S32(0)), ADD(VARL("diff"), S32(100)), VARL("diff")))); + } else { + seq = SEQ3( + seq, + SETL("sum", ADD(ADD(VARL("dst_dec"), VARL("src_dec")), VARL("x"))), + SETL("res_dec", MOD(VARL("sum"), U32(100)))); + } + seq = SEQ2(seq, SETL("res", bcd_decimal_to_byte("res_dec"))); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, 8, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + RzILOpBool *carry = subtract ? SLT(VARL("diff"), S32(0)) : UGT(VARL("sum"), U32(99)); + return SEQ2(seq, set_flags_bcd(VARL("res"), carry)); +} + +static RzILOpEffect *lift_nbcd(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + RzILOpEffect *seq = NULL; + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[0], 8, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ7( + seq, + SETL("dst_dec", bcd_byte_to_decimal("dst")), + SETL("x", BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_X), 32)), + SETL("diff", SUB(S32(0), ADD(VARL("dst_dec"), VARL("x")))), + SETL("borrow", BOOL_TO_BV(SLT(VARL("diff"), S32(0)), 32)), + SETL("res_dec", ITE(NON_ZERO(VARL("borrow")), ADD(VARL("diff"), S32(100)), VARL("diff"))), + SETL("res", bcd_decimal_to_byte("res_dec"))); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, 8, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + return SEQ2(seq, set_flags_bcd(VARL("res"), NON_ZERO(VARL("borrow")))); +} + +static RzILOpPure *pack_adjustment(M68KILCtx *ctx) { + if (ctx->m68k->op_count > 2 && ctx->m68k->operands[2].type == M68K_OP_IMM) { + return U16((ut16)ctx->m68k->operands[2].imm); + } + return U16(0); +} + +static RzILOpEffect *lift_pack_unpk(M68KILCtx *ctx, bool unpack) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + bool reg_to_reg = rz_m68k_op_is_data_reg(src) && rz_m68k_op_is_data_reg(dst); + bool mem_to_mem = rz_m68k_op_is_predec_areg(src) && rz_m68k_op_is_predec_areg(dst); + if (!reg_to_reg && !mem_to_mem) { + return NULL; + } + + RzILOpEffect *seq = NULL; + if (mem_to_mem && !unpack) { + /* M68000PRM PACK: fetch two bytes in predecrement order. Each + * byte access decrements A7 by two, so the bytes are not adjacent. */ + if (!m68k_operand_to_local(ctx, "src_low", src, 8, &seq) || + !m68k_operand_to_local(ctx, "src_high", src, 8, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("src", APPEND(VARL("src_high"), VARL("src_low")))); + } else if (!m68k_operand_to_local(ctx, "src", src, unpack ? 8 : 16, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("adjustment", pack_adjustment(ctx))); + if (unpack) { + RzILOpPure *high = SHIFTL0(UNSIGNED(16, LOGAND(VARL("src"), U8(0xf0))), U8(4)); + RzILOpPure *low = UNSIGNED(16, LOGAND(VARL("src"), U8(0x0f))); + seq = SEQ3( + seq, + SETL("expanded", LOGOR(high, low)), + SETL("res", ADD(VARL("expanded"), VARL("adjustment")))); + } else { + seq = SEQ2(seq, SETL("adjusted", ADD(UNSIGNED(16, VARL("src")), VARL("adjustment")))); + RzILOpPure *high = SHIFTR0(LOGAND(VARL("adjusted"), U16(0x0f00)), U8(4)); + RzILOpPure *low = LOGAND(VARL("adjusted"), U16(0x000f)); + seq = SEQ2(seq, SETL("res", UNSIGNED(8, LOGOR(high, low)))); + } + + RzILOpEffect *write; + if (mem_to_mem && unpack) { + /* UNPK stores the low byte first, then the high byte, with a + * separate predecrement for each (including the A7 byte stride). */ + RzILOpEffect *low = m68k_write_operand(ctx, dst, 8, UNSIGNED(8, VARL("res"))); + RzILOpEffect *high = m68k_write_operand(ctx, dst, 8, UNSIGNED(8, SHIFTR0(VARL("res"), U8(8)))); + if (!low || !high) { + rz_il_op_effect_free(low); + rz_il_op_effect_free(high); + rz_il_op_effect_free(seq); + return NULL; + } + write = SEQ2(low, high); + } else { + write = m68k_write_operand(ctx, dst, unpack ? 16 : 8, VARL("res")); + } + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return seq; +} + +static RzILOpEffect *lift_unary_write_result(M68KILCtx *ctx, RzILOpPure *result, bool set_flags) { + if (ctx->m68k->op_count < 1) { + rz_il_op_pure_free(result); + return NULL; + } + const cs_m68k_op *dst = &ctx->m68k->operands[0]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = m68k_write_operand_local(ctx, dst, bits, "res", result); + if (!seq) { + return NULL; + } + if (set_flags) { + seq = SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, IL_FALSE, IL_FALSE, NULL)); + } + return seq; +} + +static RzILOpEffect *lift_tst(M68KILCtx *ctx) { + RzILOpEffect *seq = NULL; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (!m68k_operand_to_local(ctx, "dst", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("dst"), bits, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_clr(M68KILCtx *ctx) { + return lift_unary_write_result(ctx, UN(rz_m68k_detail_op_bits(ctx->m68k, 32), 0), true); +} + +static RzILOpEffect *lift_not(M68KILCtx *ctx) { + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = NULL; + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + seq = SEQ2(seq, SETL("res", LOGNOT(VARL("dst")))); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("res")); + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_neg(M68KILCtx *ctx, bool with_extend) { + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = NULL; + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + if (with_extend) { + seq = SEQ3( + seq, + SETL("borrow", BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_X), bits)), + SETL("res", SUB(SUB(UN(bits, 0), VARL("dst")), VARL("borrow")))); + } else { + seq = SEQ2(seq, SETL("res", SUB(SUB(UN(bits, 0), VARL("dst")), UN(bits, 0)))); + } + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("res")); + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + RzILOpBool *c = with_extend ? OR(NON_ZERO(VARL("dst")), m68k_ccr_bit(M68K_CCR_X)) : NON_ZERO(VARL("dst")); + RzILOpBool *v = with_extend ? m68k_negx_overflow(bits) : m68k_sub_overflow(UN(bits, 0), VARL("dst"), VARL("res")); + return SEQ2(seq, with_extend ? m68k_set_flags_nzvcx_extend(VARL("res"), bits, v, c) : m68k_set_flags_nzvcx(VARL("res"), bits, v, c, (RzILOpBool *)DUP(c))); +} + +static RzILOpEffect *lift_swap(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[0])) { + return NULL; + } + m68k_reg reg = ctx->m68k->operands[0].reg; + RzILOpPure *v = m68k_reg_value(ctx, reg); + RzILOpPure *res = LOGOR(SHIFTL0(v, U8(16)), SHIFTR0(DUP(v), U8(16))); + return SEQ3( + SETL("res", DUP(res)), + m68k_write_reg_sized(ctx, reg, 32, res), + m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_exg(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_REG || ctx->m68k->operands[1].type != M68K_OP_REG) { + return NULL; + } + m68k_reg a = ctx->m68k->operands[0].reg; + m68k_reg b = ctx->m68k->operands[1].reg; + return SEQ3( + SETL("tmp", m68k_read_reg_sized(ctx, a, 32)), + m68k_write_reg_sized(ctx, a, 32, m68k_read_reg_sized(ctx, b, 32)), + m68k_write_reg_sized(ctx, b, 32, VARL("tmp"))); +} + +static RzILOpBool *cond_code(M68KILCtx *ctx, ut32 insn_id) { + (void)ctx; + switch (insn_id) { + case M68K_INS_DBT: + case M68K_INS_ST: + case M68K_INS_TRAPT: + return IL_TRUE; + case M68K_INS_DBF: + case M68K_INS_DBRA: + case M68K_INS_SF: + case M68K_INS_TRAPF: + return IL_FALSE; + case M68K_INS_BHI: + case M68K_INS_DBHI: + case M68K_INS_SHI: + case M68K_INS_TRAPHI: + return AND(INV(m68k_ccr_bit(M68K_CCR_C)), INV(m68k_ccr_bit(M68K_CCR_Z))); + case M68K_INS_BLS: + case M68K_INS_DBLS: + case M68K_INS_SLS: + case M68K_INS_TRAPLS: + return OR(m68k_ccr_bit(M68K_CCR_C), m68k_ccr_bit(M68K_CCR_Z)); + case M68K_INS_BCC: + case M68K_INS_BHS: + case M68K_INS_DBCC: + case M68K_INS_SCC: + case M68K_INS_SHS: + case M68K_INS_TRAPCC: + case M68K_INS_TRAPHS: + return INV(m68k_ccr_bit(M68K_CCR_C)); + case M68K_INS_BCS: + case M68K_INS_BLO: + case M68K_INS_DBCS: + case M68K_INS_SCS: + case M68K_INS_SLO: + case M68K_INS_TRAPCS: + case M68K_INS_TRAPLO: + return m68k_ccr_bit(M68K_CCR_C); + case M68K_INS_BNE: + case M68K_INS_DBNE: + case M68K_INS_SNE: + case M68K_INS_TRAPNE: + return INV(m68k_ccr_bit(M68K_CCR_Z)); + case M68K_INS_BEQ: + case M68K_INS_DBEQ: + case M68K_INS_SEQ: + case M68K_INS_TRAPEQ: + return m68k_ccr_bit(M68K_CCR_Z); + case M68K_INS_BVC: + case M68K_INS_DBVC: + case M68K_INS_SVC: + case M68K_INS_TRAPVC: + return INV(m68k_ccr_bit(M68K_CCR_V)); + case M68K_INS_BVS: + case M68K_INS_DBVS: + case M68K_INS_SVS: + case M68K_INS_TRAPVS: + return m68k_ccr_bit(M68K_CCR_V); + case M68K_INS_BPL: + case M68K_INS_DBPL: + case M68K_INS_SPL: + case M68K_INS_TRAPPL: + return INV(m68k_ccr_bit(M68K_CCR_N)); + case M68K_INS_BMI: + case M68K_INS_DBMI: + case M68K_INS_SMI: + case M68K_INS_TRAPMI: + return m68k_ccr_bit(M68K_CCR_N); + case M68K_INS_BGE: + case M68K_INS_DBGE: + case M68K_INS_SGE: + case M68K_INS_TRAPGE: + return EQ(BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_N), 1), BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_V), 1)); + case M68K_INS_BLT: + case M68K_INS_DBLT: + case M68K_INS_SLT: + case M68K_INS_TRAPLT: + return NE(BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_N), 1), BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_V), 1)); + case M68K_INS_BGT: + case M68K_INS_DBGT: + case M68K_INS_SGT: + case M68K_INS_TRAPGT: + return AND(INV(m68k_ccr_bit(M68K_CCR_Z)), EQ(BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_N), 1), BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_V), 1))); + case M68K_INS_BLE: + case M68K_INS_DBLE: + case M68K_INS_SLE: + case M68K_INS_TRAPLE: + return OR(m68k_ccr_bit(M68K_CCR_Z), NE(BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_N), 1), BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_V), 1))); + default: + return NULL; + } +} + +static RzILOpEffect *lift_branch(M68KILCtx *ctx, bool unconditional, bool call) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + RzILOpPure *target = m68k_read_operand(ctx, &ctx->m68k->operands[0], 32, NULL, NULL); + if (!target) { + return NULL; + } + RzILOpEffect *jmp = JMP(target); + if (call) { + jmp = SEQ2(push32(ctx, U32(ctx->next_addr)), jmp); + } + if (unconditional) { + return jmp; + } + RzILOpBool *cond = cond_code(ctx, ctx->insn->id); + if (!cond) { + return NULL; + } + return BRANCH(cond, jmp, EMPTY()); +} + +static RzILOpEffect *lift_jmp_jsr(M68KILCtx *ctx, bool call) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + RzILOpPure *target = NULL; + RzILOpEffect *seq = NULL; + if (rz_m68k_op_is_mem_addr(&ctx->m68k->operands[0])) { + M68KEA ea = m68k_effective_addr(ctx, &ctx->m68k->operands[0], 32); + if (ea.pre) { + seq = ea.pre; + } + target = ea.addr; + if (ea.post) { + seq = seq ? SEQ2(seq, ea.post) : ea.post; + } + } else { + target = m68k_read_operand(ctx, &ctx->m68k->operands[0], 32, NULL, NULL); + } + if (!target) { + return NULL; + } + if (call) { + seq = seq ? SEQ2(seq, SETL("target", target)) : SETL("target", target); + seq = SEQ2(seq, push32(ctx, U32(ctx->next_addr))); + target = VARL("target"); + } + seq = seq ? SEQ2(seq, JMP(target)) : JMP(target); + return seq; +} + +static RzILOpEffect *lift_rts(M68KILCtx *ctx) { + return SEQ3( + SETL("target", LOADW(32, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, 4), + JMP(VARL("target"))); +} + +static RzILOpEffect *lift_rtd(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_IMM) { + return NULL; + } + st32 disp = (st16)ctx->m68k->operands[0].imm; + return SEQ3( + SETL("target", LOADW(32, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, 4 + disp), + JMP(VARL("target"))); +} + +static RzILOpEffect *lift_rtr(M68KILCtx *ctx) { + return SEQ5( + SETL("ccr", LOADW(16, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, 2), + SETL("target", LOADW(32, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, 4), + SEQ2(m68k_set_ccr_from_value(VARL("ccr")), JMP(VARL("target")))); +} + +static RzILOpEffect *lift_rte(M68KILCtx *ctx) { + RzILOpEffect *effect; + if (rz_m68k_mode_is_coldfire(ctx->mode)) { + /* CFPRM 11.1.2: F/V and SR share the first longword, PC is the + * second, and format 4-7 records the original A7 low bits. */ + effect = SEQ5( + SETL("frame", m68k_reg_value(ctx, M68K_REG_A7)), + SETL("frame_data", LOADW(32, VARL("frame"))), + SETL("new_sr", UNSIGNED(16, VARL("frame_data"))), + SETL("format", UNSIGNED(16, SHIFTR0(VARL("frame_data"), U8(28)))), + SETL("target", LOADW(32, ADD(VARL("frame"), U32(4))))); + RzILOpEffect *restore = SEQ3( + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, + ADD(ADD(VARL("frame"), U32(8)), UNSIGNED(32, LOGAND(VARL("format"), U16(3))))), + m68k_write_reg_sized(ctx, M68K_REG_SR, 16, VARL("new_sr")), + JMP(VARL("target"))); + RzILOpBool *format_valid = AND(UGE(VARL("format"), U16(4)), ULE(VARL("format"), U16(7))); + effect = SEQ2(effect, BRANCH(format_valid, restore, m68k_exception(M68K_TRAP_OP_FORMAT, M68K_VECTOR_FORMAT_ERROR, "m68k_trap"))); + } else if (m68k_mode_has_format_word(ctx->mode)) { + /* MC68040UM 8.4.2: format 1 restores SR and starts RTE processing + * again on the newly active stack, whose next frame may be any type. */ + RzILOpEffect *parse_frame = SEQ5( + SETL("frame", m68k_reg_value(ctx, M68K_REG_A7)), + SETL("new_sr", LOADW(16, VARL("frame"))), + SETL("target", LOADW(32, ADD(VARL("frame"), U32(2)))), + SETL("format", SHIFTR0(LOADW(16, ADD(VARL("frame"), U32(6))), U8(12))), + SETL("frame_size", m68k_rte_frame_size(ctx->mode))); + RzILOpEffect *restore_frame = SEQ3( + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, ADD(VARL("frame"), VARL("frame_size"))), + m68k_write_reg_sized(ctx, M68K_REG_SR, 16, VARL("new_sr")), + SETL("rte_state", ITE(EQ(VARL("format"), U16(1)), U8(1), U8(0)))); + RzILOpEffect *loop_body = SEQ2( + parse_frame, + BRANCH(m68k_rte_format_valid(ctx->mode), restore_frame, SETL("rte_state", U8(2)))); + effect = SEQ4( + SETL("rte_state", U8(1)), + SETL("target", U32(0)), + REPEAT(EQ(VARL("rte_state"), U8(1)), loop_body), + BRANCH( + EQ(VARL("rte_state"), U8(0)), + JMP(VARL("target")), + m68k_exception(M68K_TRAP_OP_FORMAT, M68K_VECTOR_FORMAT_ERROR, "m68k_trap"))); + } else { + effect = SEQ6( + SETL("frame", m68k_reg_value(ctx, M68K_REG_A7)), + SETL("new_sr", LOADW(16, VARL("frame"))), + SETL("target", LOADW(32, ADD(VARL("frame"), U32(2)))), + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, ADD(VARL("frame"), U32(6))), + m68k_write_reg_sized(ctx, M68K_REG_SR, 16, VARL("new_sr")), + JMP(VARL("target"))); + } + return BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")); +} + +static RzILOpEffect *lift_rtm(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (!rz_m68k_op_is_gpr(&ctx->m68k->operands[0])) { + return NULL; + } + + m68k_reg module_reg = ctx->m68k->operands[0].reg; + RzILOpEffect *restore = SEQ4( + m68k_set_ccr_from_value(SHIFTR0(VARL("ccr_arg"), U8(8))), + m68k_write_reg_sized(ctx, module_reg, 32, VARL("module_data")), + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, ADD(ADD(VARL("frame"), U32(0x18)), VARL("arg_count"))), + JMP(VARL("target"))); + + RzILOpEffect *seq = SEQ6( + SETL("frame", m68k_reg_value(ctx, M68K_REG_A7)), + SETL("frame_info", LOADW(16, VARL("frame"))), + SETL("ccr_arg", LOADW(16, ADD(VARL("frame"), U32(2)))), + SETL("arg_count", UNSIGNED(32, UNSIGNED(8, VARL("ccr_arg")))), + SETL("target", LOADW(32, ADD(VARL("frame"), U32(0x0c)))), + SETL("module_data", LOADW(32, ADD(VARL("frame"), U32(0x10))))); + return SEQ2(seq, BRANCH(IS_ZERO(LOGAND(VARL("frame_info"), U16(0xff00))), restore, m68k_label("m68k_rtm"))); +} + +static RzILOpEffect *lift_stop(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_IMM) { + return NULL; + } + ut16 new_sr = (ut16)ctx->m68k->operands[0].imm; + /* M68000PRM 7-5 and MC68060UM D-19: clearing S in the LPSTOP + * immediate is a privilege violation even in supervisor mode. */ + if (ctx->insn->id == M68K_INS_LPSTOP && !(new_sr & (1u << M68K_SR_S))) { + return m68k_label("m68k_privilege"); + } + RzILOpEffect *load_sr = m68k_write_reg_sized(ctx, M68K_REG_SR, 16, U16(new_sr)); + if (!load_sr) { + return NULL; + } + RzILOpEffect *effect = SEQ4( + SETL("system_op", U32(ctx->insn->id == M68K_INS_LPSTOP ? M68K_SYSTEM_OP_LPSTOP : M68K_SYSTEM_OP_STOP)), + SETL("system_sr", U32(new_sr)), + load_sr, + m68k_label("m68k_system")); + return BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static RzILOpEffect *lift_strldsr(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_IMM) { + return NULL; + } + + ut16 new_sr = (ut16)ctx->m68k->operands[0].imm; + if (!(new_sr & (1u << M68K_SR_S))) { + return m68k_label("m68k_privilege"); + } + + RzILOpEffect *effect = SEQ2( + push32(ctx, UNSIGNED(32, VARG("sr"))), + m68k_write_reg_sized(ctx, M68K_REG_SR, 16, U16(new_sr))); + return BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")); +} +#endif + +static RzILOpEffect *lift_privileged_system(M68KSystemOp op) { + RzILOpEffect *effect = SEQ2( + SETL("system_op", U32((ut32)op)), + m68k_label("m68k_system")); + return BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")); +} + +static RzILOpEffect *lift_link(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_addr_reg(&ctx->m68k->operands[0]) || + ctx->m68k->operands[1].type != M68K_OP_IMM) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 16); + st32 disp = bits == 16 + ? (st32)(st16)(ut16)ctx->m68k->operands[1].imm + : (st32)ctx->m68k->operands[1].imm; + m68k_reg areg = ctx->m68k->operands[0].reg; + return SEQ4( + push32(ctx, m68k_read_reg_sized(ctx, areg, 32)), + m68k_write_reg_sized(ctx, areg, 32, m68k_reg_value(ctx, M68K_REG_A7)), + SETL("new_sp", disp >= 0 ? ADD(m68k_reg_value(ctx, M68K_REG_A7), U32((ut32)disp)) : SUB(m68k_reg_value(ctx, M68K_REG_A7), U32((ut32)-disp))), + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, VARL("new_sp"))); +} + +static RzILOpEffect *lift_unlk(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_REG) { + return NULL; + } + m68k_reg areg = ctx->m68k->operands[0].reg; + /* Sequential op: (An) -> An; An+4 -> SP. When An is A7, the final SP + * write must keep the +4 rather than being overwritten by An = old. */ + if (areg == M68K_REG_A7) { + return SEQ2( + SETL("old", LOADW(32, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, ADD(VARL("old"), U32(4)))); + } + return SEQ4( + m68k_write_reg_sized(ctx, M68K_REG_A7, 32, m68k_read_reg_sized(ctx, areg, 32)), + SETL("old", LOADW(32, m68k_reg_value(ctx, M68K_REG_A7))), + m68k_set_addr_reg_delta(ctx, M68K_REG_A7, 4), + m68k_write_reg_sized(ctx, areg, 32, VARL("old"))); +} + +static RzILOpEffect *lift_scc_cond(M68KILCtx *ctx, RzILOpBool *cond) { + if (ctx->m68k->op_count < 1) { + rz_il_op_pure_free(cond); + return NULL; + } + RzILOpPure *value = ITE(cond, U8(0xff), U8(0)); + return m68k_write_operand(ctx, &ctx->m68k->operands[0], 8, value); +} + +static RzILOpEffect *lift_scc(M68KILCtx *ctx) { + RzILOpBool *cond = cond_code(ctx, ctx->insn->id); + if (!cond) { + return NULL; + } + return lift_scc_cond(ctx, cond); +} + +static RzILOpEffect *lift_dbcc_cond(M68KILCtx *ctx, RzILOpBool *cond) { + if (ctx->m68k->op_count < 2) { + rz_il_op_pure_free(cond); + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[0]) || ctx->m68k->operands[1].type != M68K_OP_BR_DISP) { + rz_il_op_pure_free(cond); + return NULL; + } + m68k_reg reg = ctx->m68k->operands[0].reg; + RzILOpPure *m68k_reg_value = m68k_read_reg_sized(ctx, reg, 32); + if (!m68k_reg_value) { + rz_il_op_pure_free(cond); + return NULL; + } + RzILOpPure *target = m68k_branch_disp_target(ctx, &ctx->m68k->operands[1]); + if (!target) { + rz_il_op_pure_free(cond); + rz_il_op_pure_free(m68k_reg_value); + return NULL; + } + RzILOpEffect *seq = SETL("dec", SUB(UNSIGNED(16, m68k_reg_value), U16(1))); + seq = SEQ3( + seq, + m68k_write_reg_sized(ctx, reg, 16, VARL("dec")), + BRANCH(NE(VARL("dec"), U16(0xffff)), JMP(target), EMPTY())); + return BRANCH(cond, + EMPTY(), + seq); +} + +static RzILOpEffect *lift_dbcc(M68KILCtx *ctx) { + RzILOpBool *cond = cond_code(ctx, ctx->insn->id); + if (!cond) { + return NULL; + } + return lift_dbcc_cond(ctx, cond); +} + +static RzILOpPure *signed_zero_for_bits(ut32 bits) { + return bits == 16 ? S16(0) : S32(0); +} + +static RzILOpEffect *lift_chk(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[1])) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 16); + if (bits != 16 && bits != 32) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "bound", &ctx->m68k->operands[0], bits, &seq)) { + return NULL; + } + RzILOpPure *dst = m68k_read_reg_sized(ctx, ctx->m68k->operands[1].reg, bits); + if (!dst) { + return NULL; + } + seq = SEQ2(seq, SETL("dst", dst)); + + RzILOpEffect *neg_trap = SEQ2( + m68k_set_ccr_from_value(m68k_ccr_with_flag(UNSIGNED(8, VARG("sr")), M68K_CCR_N, IL_TRUE)), + m68k_exception(M68K_TRAP_OP_CHK, M68K_VECTOR_CHK, "m68k_chk")); + RzILOpEffect *high_trap = SEQ2( + m68k_set_ccr_from_value(m68k_ccr_with_flag(UNSIGNED(8, VARG("sr")), M68K_CCR_N, IL_FALSE)), + m68k_exception(M68K_TRAP_OP_CHK, M68K_VECTOR_CHK, "m68k_chk")); + return SEQ2(seq, BRANCH(SLT(VARL("dst"), signed_zero_for_bits(bits)), neg_trap, BRANCH(SGT(VARL("dst"), VARL("bound")), high_trap, EMPTY()))); +} + +static RzILOpPure *cmp2_extend_value(RzILOpPure *value, ut32 bits) { + return bits == 32 ? value : SIGNED(32, value); +} + +static RzILOpBool *cmp2_outside_bounds(void) { + RzILOpBool *ordered = SLE(VARL("lower"), VARL("upper")); + RzILOpBool *outside_ordered = OR(SLT(VARL("rn"), VARL("lower")), SGT(VARL("rn"), VARL("upper"))); + RzILOpBool *outside_wrapped = AND(SGT(VARL("rn"), VARL("upper")), SLT(VARL("rn"), VARL("lower"))); + return OR(AND(ordered, outside_ordered), AND(INV(SLE(VARL("lower"), VARL("upper"))), outside_wrapped)); +} + +static RzILOpEffect *set_flags_cmp2(void) { + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xfa)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, NON_ZERO(VARL("equal"))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, NON_ZERO(VARL("outside"))); + return m68k_set_ccr_from_value(ccr); +} + +static RzILOpEffect *lift_cmp2_chk2(M68KILCtx *ctx, bool trap) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_mem_addr(&ctx->m68k->operands[0]) || !rz_m68k_op_is_gpr(&ctx->m68k->operands[1])) { + return NULL; + } + const cs_m68k_op *bounds = &ctx->m68k->operands[0]; + const cs_m68k_op *reg = &ctx->m68k->operands[1]; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 8 && bits != 16 && bits != 32) { + return NULL; + } + M68KEA ea = m68k_effective_addr(ctx, bounds, bits); + if (!ea.addr) { + return NULL; + } + RzILOpPure *rn = m68k_read_reg_sized(ctx, reg->reg, rz_m68k_reg_is_areg(reg->reg) ? 32 : bits); + if (!rn) { + return NULL; + } + if (rz_m68k_reg_is_dreg(reg->reg)) { + rn = cmp2_extend_value(rn, bits); + } + RzILOpPure *addr = UNSIGNED(32, ea.addr); + RzILOpPure *upper_addr = ADD(VARL("bounds_addr"), U32(rz_m68k_bits_access_bytes(bits))); + RzILOpEffect *seq = SEQ7( + SETL("bounds_addr", addr), + SETL("lower", cmp2_extend_value(LOADW(bits, VARL("bounds_addr")), bits)), + SETL("upper", cmp2_extend_value(LOADW(bits, upper_addr), bits)), + SETL("rn", rn), + SETL("outside", BOOL_TO_BV(cmp2_outside_bounds(), 1)), + SETL("equal", BOOL_TO_BV(OR(EQ(VARL("rn"), VARL("lower")), EQ(VARL("rn"), VARL("upper"))), 1)), + set_flags_cmp2()); + seq = m68k_effect_pre_post(ea.pre, seq, ea.post); + if (trap) { + seq = SEQ2(seq, BRANCH(NON_ZERO(VARL("outside")), m68k_exception(M68K_TRAP_OP_CHK, M68K_VECTOR_CHK, "m68k_chk"), EMPTY())); + } + return seq; +} + +static RzILOpEffect *lift_cas(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 3) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[0]) || + !rz_m68k_op_is_data_reg(&ctx->m68k->operands[1]) || + !rz_m68k_op_is_mem_addr(&ctx->m68k->operands[2])) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 8 && bits != 16 && bits != 32) { + return NULL; + } + RzILOpPure *cmp = m68k_read_reg_sized(ctx, ctx->m68k->operands[0].reg, bits); + RzILOpPure *upd = m68k_read_reg_sized(ctx, ctx->m68k->operands[1].reg, bits); + if (!cmp || !upd) { + return NULL; + } + RzILOpEffect *seq = SEQ2(SETL("cmp", cmp), SETL("upd", upd)); + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[2], bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("res", SUB(VARL("dst"), VARL("cmp")))); + RzILOpEffect *success = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("upd")); + RzILOpEffect *failure = m68k_write_reg_sized(ctx, ctx->m68k->operands[0].reg, bits, VARL("dst")); + if (!success || !failure) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(success); + rz_il_op_effect_free(failure); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, BRANCH(EQ(UNSIGNED(bits, VARL("cmp")), UNSIGNED(bits, VARL("dst"))), success, failure)); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, m68k_sub_overflow(VARL("dst"), VARL("cmp"), VARL("res")), ULT(VARL("dst"), VARL("cmp")), NULL)); +} + +static RzILOpEffect *lift_cas2(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 3) { + return NULL; + } + if (!rz_m68k_op_is_data_reg_pair(&ctx->m68k->operands[0]) || + !rz_m68k_op_is_data_reg_pair(&ctx->m68k->operands[1]) || + !rz_m68k_op_is_gpr_reg_pair(&ctx->m68k->operands[2])) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 16 && bits != 32) { + return NULL; + } + + const cs_m68k_op *cmp = &ctx->m68k->operands[0]; + const cs_m68k_op *upd = &ctx->m68k->operands[1]; + const cs_m68k_op *addr = &ctx->m68k->operands[2]; + RzILOpPure *addr0 = m68k_read_reg_sized(ctx, addr->reg_pair.reg_0, 32); + RzILOpPure *addr1 = m68k_read_reg_sized(ctx, addr->reg_pair.reg_1, 32); + RzILOpPure *cmp0 = m68k_read_reg_sized(ctx, cmp->reg_pair.reg_0, bits); + RzILOpPure *cmp1 = m68k_read_reg_sized(ctx, cmp->reg_pair.reg_1, bits); + RzILOpPure *upd0 = m68k_read_reg_sized(ctx, upd->reg_pair.reg_0, bits); + RzILOpPure *upd1 = m68k_read_reg_sized(ctx, upd->reg_pair.reg_1, bits); + if (!addr0 || !addr1 || !cmp0 || !cmp1 || !upd0 || !upd1) { + return NULL; + } + + RzILOpEffect *success = SEQ2( + STOREW(VARL("addr0"), UNSIGNED(bits, VARL("upd0"))), + STOREW(VARL("addr1"), UNSIGNED(bits, VARL("upd1")))); + RzILOpEffect *fail_second = m68k_write_reg_sized(ctx, cmp->reg_pair.reg_1, bits, VARL("dst1")); + RzILOpEffect *fail_first = m68k_write_reg_sized(ctx, cmp->reg_pair.reg_0, bits, VARL("dst0")); + if (!success || !fail_second || !fail_first) { + rz_il_op_effect_free(success); + rz_il_op_effect_free(fail_second); + rz_il_op_effect_free(fail_first); + return NULL; + } + RzILOpEffect *failure = SEQ2(fail_second, fail_first); + + RzILOpEffect *seq = SEQ9( + SETL("addr0", addr0), + SETL("addr1", addr1), + SETL("cmp0", cmp0), + SETL("cmp1", cmp1), + SETL("upd0", upd0), + SETL("upd1", upd1), + SETL("dst0", LOADW(bits, VARL("addr0"))), + SETL("dst1", LOADW(bits, VARL("addr1"))), + SETL("first_eq", BOOL_TO_BV(EQ(VARL("cmp0"), VARL("dst0")), 1))); + seq = seq ? SEQ2(seq, SETL("second_eq", BOOL_TO_BV(EQ(VARL("cmp1"), VARL("dst1")), 1))) : SETL("second_eq", BOOL_TO_BV(EQ(VARL("cmp1"), VARL("dst1")), 1)); + seq = SEQ7( + seq, + SETL("res0", SUB(VARL("dst0"), VARL("cmp0"))), + SETL("res1", SUB(VARL("dst1"), VARL("cmp1"))), + SETL("flag_cmp", ITE(NON_ZERO(VARL("first_eq")), VARL("cmp1"), VARL("cmp0"))), + SETL("flag_dst", ITE(NON_ZERO(VARL("first_eq")), VARL("dst1"), VARL("dst0"))), + SETL("res", ITE(NON_ZERO(VARL("first_eq")), VARL("res1"), VARL("res0"))), + BRANCH(AND(NON_ZERO(VARL("first_eq")), NON_ZERO(VARL("second_eq"))), success, failure)); + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, m68k_sub_overflow(VARL("flag_dst"), VARL("flag_cmp"), VARL("res")), ULT(VARL("flag_dst"), VARL("flag_cmp")), NULL)); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 +static RzILOpPure *tbl_extend_entry(RzILOpPure *value, bool sign) { + return sign ? SIGNED(64, value) : UNSIGNED(64, value); +} + +static RzILOpPure *tbl_rounded_delta(void) { + RzILOpPure *adjusted = ITE( + MSB(VARL("prod")), + SUB(VARL("prod"), S64(0x80)), + ADD(VARL("prod"), S64(0x80))); + return SDIV(adjusted, S64(0x100)); +} + +static RzILOpPure *tbl_unrounded_result(ut32 bits, bool sign) { + ut32 result_bits = bits == 32 ? 32 : bits + 8; + RzILOpPure *sized = UNSIGNED(result_bits, VARL("fixed")); + return sign ? SIGNED(32, sized) : UNSIGNED(32, sized); +} + +static RzILOpPure *tbl_immediate_base(M68KILCtx *ctx, ut32 bits) { + return U32(ctx->addr + 4 + (bits == 8 ? 1 : 0)); +} + +static RzILOpEffect *lift_tbl(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + if (!rz_m68k_op_is_data_reg(&ctx->m68k->operands[1])) { + return NULL; + } + const cs_m68k_op *src = &ctx->m68k->operands[0]; + m68k_reg dst_reg = ctx->m68k->operands[1].reg; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 8 && bits != 16 && bits != 32) { + return NULL; + } + + bool sign = rz_m68k_tbl_insn_is_signed(ctx->insn->id); + bool unrounded = rz_m68k_tbl_insn_is_unrounded(ctx->insn->id); + RzILOpEffect *seq = SEQ2(SETL("x", m68k_read_reg_sized(ctx, dst_reg, 16)), SETL("frac", UNSIGNED(64, LOGAND(VARL("x"), U16(0xff))))); + + if (rz_m68k_op_is_data_reg_pair(src)) { + seq = SEQ3( + seq, + SETL("entry0", tbl_extend_entry(m68k_read_reg_sized(ctx, src->reg_pair.reg_0, bits), sign)), + SETL("entry1", tbl_extend_entry(m68k_read_reg_sized(ctx, src->reg_pair.reg_1, bits), sign))); + } else if (rz_m68k_op_is_mem_addr(src)) { + M68KEA ea = m68k_effective_addr(ctx, src, bits); + if (!ea.addr) { + return NULL; + } + ut32 bytes = rz_m68k_bits_access_bytes(bits); + seq = SEQ2(seq, + m68k_effect_pre_post(ea.pre, + SEQ5(SETL("base", UNSIGNED(32, ea.addr)), + SETL("index", UNSIGNED(32, SHIFTR0(LOGAND(VARL("x"), U16(0xff00)), U8(8)))), + SETL("entry_addr", ADD(VARL("base"), MUL(VARL("index"), U32(bytes)))), + SETL("entry0", tbl_extend_entry(LOADW(bits, VARL("entry_addr")), sign)), + SETL("entry1", tbl_extend_entry(LOADW(bits, ADD(VARL("entry_addr"), U32(bytes))), sign))), + ea.post)); + } else if (src->type == M68K_OP_IMM) { + ut32 bytes = rz_m68k_bits_access_bytes(bits); + seq = SEQ6( + seq, + SETL("base", tbl_immediate_base(ctx, bits)), + SETL("index", UNSIGNED(32, SHIFTR0(LOGAND(VARL("x"), U16(0xff00)), U8(8)))), + SETL("entry_addr", ADD(VARL("base"), MUL(VARL("index"), U32(bytes)))), + SETL("entry0", tbl_extend_entry(LOADW(bits, VARL("entry_addr")), sign)), + SETL("entry1", tbl_extend_entry(LOADW(bits, ADD(VARL("entry_addr"), U32(bytes))), sign))); + } else { + rz_il_op_effect_free(seq); + return NULL; + } + + seq = SEQ3( + seq, + SETL("diff", SUB(VARL("entry1"), VARL("entry0"))), + SETL("prod", MUL(VARL("diff"), VARL("frac")))); + if (unrounded) { + seq = SEQ4( + seq, + SETL("fixed", ADD(SHIFTL0(VARL("entry0"), U8(8)), VARL("prod"))), + SETL("res", tbl_unrounded_result(bits, sign)), + m68k_write_reg_sized(ctx, dst_reg, 32, VARL("res"))); + /* M68000PRM 7-9/7-13: both TBLSN and TBLUN check the integer + * portion against the signed 24-bit range. With eight fractional + * bits this is a signed 32-bit range check before truncation. */ + RzILOpBool *overflow = bits == 32 ? m68k_signed_out_of_range(VARL("fixed"), 32) : IL_FALSE; + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), 32, overflow, IL_FALSE, NULL)); + } + + seq = SEQ3( + seq, + SETL("res", UNSIGNED(bits, ADD(VARL("entry0"), tbl_rounded_delta()))), + m68k_write_reg_sized(ctx, dst_reg, bits, VARL("res"))); + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, IL_FALSE, IL_FALSE, NULL)); +} +#endif + +static RzILOpEffect *lift_ext(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + if (ctx->m68k->operands[0].type != M68K_OP_REG) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + ut32 src_bits = ctx->insn->id == M68K_INS_EXTB ? 8 : (bits == 32 ? 16 : 8); + m68k_reg reg = ctx->m68k->operands[0].reg; + RzILOpPure *src = UNSIGNED(src_bits, m68k_read_reg_sized(ctx, reg, 32)); + RzILOpPure *res = SIGNED(bits, src); + return SEQ3( + SETL("res", DUP(res)), + m68k_write_reg_sized(ctx, reg, bits, res), + m68k_set_flags_nzvcx(VARL("res"), bits, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_tas(M68KILCtx *ctx) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + RzILOpEffect *seq = NULL; + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", &ctx->m68k->operands[0], 8, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("res", LOGOR(VARL("dst"), U8(0x80)))); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, 8, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("dst"), 8, IL_FALSE, IL_FALSE, NULL)); +} + +static RzILOpEffect *lift_shift(M68KILCtx *ctx, bool left, bool arithmetic) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = NULL; + const cs_m68k_op *dst = NULL; + if (ctx->m68k->op_count == 1) { + dst = &ctx->m68k->operands[0]; + seq = SETL("count", U8(1)); + } else { + dst = &ctx->m68k->operands[1]; + if (!m68k_operand_to_local(ctx, "count", &ctx->m68k->operands[0], bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + } + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", dst, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *count = UNSIGNED(8, VARL("count")); + seq = SEQ2(seq, SETL("count8", LOGAND(count, U8(0x3f)))); + RzILOpPure *res = left ? SHIFTL0(VARL("dst"), VARL("count8")) : (arithmetic ? SHIFTRA(VARL("dst"), VARL("count8")) : SHIFTR0(VARL("dst"), VARL("count8"))); + seq = SEQ2(seq, SETL("res", res)); + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + RzILOpBool *shifted_out = NULL; + if (left) { + shifted_out = NON_ZERO(LOGAND(SHIFTR0(VARL("dst"), SUB(U8(bits), VARL("count8"))), UN(bits, 1))); + } else { + RzILOpBool *right_shifted_out = NON_ZERO(LOGAND(SHIFTR0(VARL("dst"), SUB(VARL("count8"), U8(1))), UN(bits, 1))); + if (arithmetic) { + RzILOpBool *past_width = UGE(VARL("count8"), U8(bits)); + RzILOpBool *within_width = ULT(VARL("count8"), U8(bits)); + shifted_out = OR(AND(past_width, MSB(VARL("dst"))), AND(within_width, right_shifted_out)); + } else { + shifted_out = right_shifted_out; + } + } + RzILOpBool *carry = AND(NON_ZERO(VARL("count8")), (RzILOpBool *)DUP(shifted_out)); + RzILOpBool *extend = OR(AND(IS_ZERO(VARL("count8")), m68k_ccr_bit(M68K_CCR_X)), AND(NON_ZERO(VARL("count8")), shifted_out)); + RzILOpBool *overflow = IL_FALSE; + if (left && arithmetic) { + for (ut32 i = 1; i <= bits; i++) { + RzILOpBool *shift_reached = UGE(VARL("count8"), U8(i)); + RzILOpBool *new_sign = i < bits + ? NON_ZERO(LOGAND(SHIFTR0(VARL("dst"), U8(bits - 1 - i)), UN(bits, 1))) + : IL_FALSE; + RzILOpBool *sign_changed = NE(BOOL_TO_BV(MSB(VARL("dst")), 1), BOOL_TO_BV(new_sign, 1)); + overflow = OR(overflow, AND(shift_reached, sign_changed)); + } + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, overflow, carry, extend)); +} + +static RzILOpPure *rotate_expr(const char *value_local, const char *count_local, ut32 bits, bool left) { + RzILOpPure *res = left + ? LOGOR(SHIFTL0(VARL(value_local), VARL(count_local)), SHIFTR0(VARL(value_local), SUB(U8(bits), VARL(count_local)))) + : LOGOR(SHIFTR0(VARL(value_local), VARL(count_local)), SHIFTL0(VARL(value_local), SUB(U8(bits), VARL(count_local)))); + return ITE(IS_ZERO(VARL(count_local)), VARL(value_local), res); +} + +static RzILOpEffect *lift_rotate(M68KILCtx *ctx, bool left, bool extend) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + RzILOpEffect *seq = NULL; + const cs_m68k_op *dst = NULL; + if (ctx->m68k->op_count == 1) { + dst = &ctx->m68k->operands[0]; + seq = SETL("count", U8(1)); + } else { + dst = &ctx->m68k->operands[1]; + if (!m68k_operand_to_local(ctx, "count", &ctx->m68k->operands[0], bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + } + + M68KRWOperand dst_rw; + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", dst, bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ3( + seq, + SETL("count_raw", LOGAND(UNSIGNED(8, VARL("count")), U8(0x3f))), + SETL("rot_count", MOD(VARL("count_raw"), U8(extend ? bits + 1 : bits)))); + if (extend) { + ut32 wide_bits = bits + 1; + RzILOpPure *wide = APPEND(BOOL_TO_BV(m68k_ccr_bit(M68K_CCR_X), 1), UNSIGNED(bits, VARL("dst"))); + seq = SEQ4( + seq, + SETL("wide", wide), + SETL("wide_res", rotate_expr("wide", "rot_count", wide_bits, left)), + SETL("res", UNSIGNED(bits, VARL("wide_res")))); + } else { + seq = SEQ2(seq, SETL("res", rotate_expr("dst", "rot_count", bits, left))); + } + + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, VARL("res")); + if (!write) { + m68k_rw_operand_fini(&dst_rw); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + + RzILOpBool *did_rotate = NON_ZERO(VARL("count_raw")); + RzILOpBool *carry = NULL; + RzILOpBool *x = NULL; + if (extend) { + RzILOpBool *new_x = MSB(VARL("wide_res")); + carry = OR(AND(INV((RzILOpBool *)DUP(did_rotate)), m68k_ccr_bit(M68K_CCR_X)), + AND(did_rotate, (RzILOpBool *)DUP(new_x))); + x = OR(AND(IS_ZERO(VARL("count_raw")), m68k_ccr_bit(M68K_CCR_X)), + AND(NON_ZERO(VARL("count_raw")), new_x)); + } else { + RzILOpBool *rotated_carry = left ? NON_ZERO(LOGAND(VARL("res"), UN(bits, 1))) : MSB(VARL("res")); + carry = AND(did_rotate, rotated_carry); + } + return SEQ2(seq, m68k_set_flags_nzvcx(VARL("res"), bits, IL_FALSE, carry, x)); +} + +static RzILOpEffect *lift_bitop(M68KILCtx *ctx, ut32 insn_id) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *bitop = &ctx->m68k->operands[0]; + const cs_m68k_op *dst = &ctx->m68k->operands[1]; + ut32 bits = dst->type == M68K_OP_REG ? 32 : 8; + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "bit", bitop, bits, &seq)) { + return NULL; + } + M68KRWOperand dst_rw = { 0 }; + bool writes_dst = insn_id != M68K_INS_BTST; + if (writes_dst) { + if (!m68k_rw_operand_to_local(ctx, &dst_rw, "dst", "dst_addr", dst, bits, &seq)) { + return NULL; + } + } else if (!m68k_operand_to_local(ctx, "dst", dst, bits, &seq)) { + return NULL; + } + RzILOpPure *idx = MOD(UNSIGNED(bits, VARL("bit")), UN(bits, bits)); + RzILOpPure *mask = SHIFTL0(UN(bits, 1), UNSIGNED(8, idx)); + RzILOpBool *was_set = NON_ZERO(LOGAND(VARL("dst"), writes_dst ? DUP(mask) : mask)); + RzILOpPure *res = NULL; + switch (insn_id) { + case M68K_INS_BSET: + res = LOGOR(VARL("dst"), mask); + break; + case M68K_INS_BCLR: + res = LOGAND(VARL("dst"), LOGNOT(mask)); + break; + case M68K_INS_BCHG: + res = LOGXOR(VARL("dst"), mask); + break; + case M68K_INS_BTST: + break; + default: + return NULL; + } + seq = SEQ2(seq, m68k_set_ccr_from_value(m68k_ccr_with_flag(LOGAND(UNSIGNED(8, VARG("sr")), U8(0xfb)), M68K_CCR_Z, INV(was_set)))); + if (res) { + RzILOpEffect *write = m68k_write_rw_operand(ctx, &dst_rw, bits, res); + seq = SEQ2(seq, write); + if (dst_rw.post) { + seq = SEQ2(seq, dst_rw.post); + } + } + return seq; +} + +static RzILOpPure *bitfield_encoded_value(M68KILCtx *ctx, ut8 encoded, bool width) { + if (M68K_BF_IS_REG(encoded)) { + m68k_reg reg = M68K_REG_D0 + M68K_BF_REG_NUM(encoded); + RzILOpPure *value = m68k_read_reg_sized(ctx, reg, 32); + if (!value) { + return NULL; + } + if (width) { + RzILOpPure *low = LOGAND(value, U32(0x1f)); + return ITE(IS_ZERO(DUP(low)), U32(32), low); + } + return value; + } + if (width && encoded == 0) { + return U32(32); + } + return U32(encoded); +} + +static RzILOpPure *bitfield_mask64(void) { + return SUB(SHIFTL0(U64(1), UNSIGNED(8, VARL("width"))), U64(1)); +} + +static RzILOpPure *bitfield_mask32(void) { + return UNSIGNED(32, bitfield_mask64()); +} + +static RzILOpPure *bitfield_shift(void) { + return SUB(U8(64), UNSIGNED(8, ADD(VARL("bit_offset"), VARL("width")))); +} + +static RzILOpPure *bitfield_field_from_container(void) { + return LOGAND(UNSIGNED(32, SHIFTR0(VARL("container"), bitfield_shift())), bitfield_mask32()); +} + +static RzILOpPure *bitfield_container_with_field(RzILOpPure *field) { + RzILOpPure *shift = bitfield_shift(); + RzILOpPure *mask = SHIFTL0(bitfield_mask64(), (RzILOpPure *)DUP(shift)); + RzILOpPure *value = SHIFTL0(LOGAND(UNSIGNED(64, field), bitfield_mask64()), shift); + return LOGOR(LOGAND(VARL("container"), LOGNOT(mask)), value); +} + +static RzILOpPure *bitfield_data_reg_writeback(RzILOpPure *updated) { + RzILOpPure *wrapped_mask = UNSIGNED(32, SHIFTL0(bitfield_mask64(), bitfield_shift())); + RzILOpPure *upper = UNSIGNED(32, SHIFTR0((RzILOpPure *)DUP(updated), U8(32))); + RzILOpPure *lower = UNSIGNED(32, updated); + return LOGOR(LOGAND(upper, LOGNOT((RzILOpPure *)DUP(wrapped_mask))), LOGAND(lower, wrapped_mask)); +} + +static RzILOpPure *bitfield_sign_extend(void) { + RzILOpPure *sign_mask = SHIFTL0(U32(1), UNSIGNED(8, SUB(VARL("width"), U32(1)))); + RzILOpBool *sign = NON_ZERO(LOGAND(VARL("field"), sign_mask)); + return ITE(sign, LOGOR(VARL("field"), LOGNOT(bitfield_mask32())), VARL("field")); +} + +static RzILOpPure *bitfield_left_aligned(void) { + return SHIFTL0(VARL("field"), SUB(U8(32), UNSIGNED(8, VARL("width")))); +} + +static RzILOpPure *bitfield_memory_byte_addr(const char *addr_local, ut32 offset) { + return offset ? ADD(VARL(addr_local), U32(offset)) : VARL(addr_local); +} + +enum { + M68K_BITFIELD_MAX_MEMORY_BYTES = 5, +}; + +static RzILOpEffect *read_bitfield_memory(const char *addr_local) { + RzILOpEffect *seq = SETL("container", U64(0)); + for (ut32 i = 0; i < M68K_BITFIELD_MAX_MEMORY_BYTES; i++) { + RzILOpPure *byte = UNSIGNED(64, LOADW(8, bitfield_memory_byte_addr(addr_local, i))); + byte = SHIFTL0(byte, U8(56 - (i * 8))); + RzILOpEffect *load = SETL("container", LOGOR(VARL("container"), byte)); + if (i > 0) { + load = BRANCH(UGT(VARL("byte_count"), U32(i)), load, EMPTY()); + } + seq = SEQ2(seq, load); + } + return seq; +} + +static RzILOpEffect *write_bitfield_memory(const char *addr_local, RzILOpPure *updated) { + RzILOpEffect *seq = SETL("updated_container", updated); + for (ut32 i = 0; i < M68K_BITFIELD_MAX_MEMORY_BYTES; i++) { + RzILOpPure *byte = UNSIGNED(8, SHIFTR0(VARL("updated_container"), U8(56 - (i * 8)))); + RzILOpEffect *store = STOREW(bitfield_memory_byte_addr(addr_local, i), UNSIGNED(8, byte)); + if (i > 0) { + store = BRANCH(UGT(VARL("byte_count"), U32(i)), store, EMPTY()); + } + seq = SEQ2(seq, store); + } + return seq; +} + +static RzILOpEffect *set_flags_bitfield(RzILOpPure *field) { + RzILOpPure *value = LOGAND(field, bitfield_mask32()); + RzILOpPure *sign_mask = SHIFTL0(U32(1), UNSIGNED(8, SUB(VARL("width"), U32(1)))); + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, NON_ZERO(LOGAND(DUP(value), sign_mask))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, IS_ZERO(value)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, IL_FALSE); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE); + ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X))); + return m68k_set_ccr_from_value(ccr); +} + +static bool bitfield_target_to_local(M68KILCtx *ctx, const cs_m68k_op *op, M68KBitfieldTarget *target, RzILOpEffect **seq) { + rz_return_val_if_fail(ctx && op && target && seq, false); + *target = (M68KBitfieldTarget){ + .op = op, + .memory = rz_m68k_op_is_mem_addr(op), + .addr_local = "bf_addr", + .post = NULL, + }; + RzILOpPure *offset = bitfield_encoded_value(ctx, op->mem.offset, false); + RzILOpPure *width = bitfield_encoded_value(ctx, op->mem.width, true); + if (!offset || !width) { + rz_il_op_pure_free(offset); + rz_il_op_pure_free(width); + return false; + } + *seq = *seq ? SEQ2(*seq, SETL("offset", offset)) : SETL("offset", offset); + *seq = SEQ2(*seq, SETL("width", width)); + if (target->memory) { + M68KEA ea = m68k_effective_addr(ctx, op, 32); + if (!ea.addr) { + m68k_ea_fini(&ea); + return false; + } + *seq = SEQ2(*seq, + m68k_effect_pre_post(ea.pre, SETL("base", UNSIGNED(32, ea.addr)), NULL)); + if (M68K_BF_IS_REG(op->mem.offset)) { + *seq = SEQ3( + *seq, + SETL("bit_offset", LOGAND(VARL("offset"), U32(7))), + SETL("byte_offset", SDIV(SUB(VARL("offset"), VARL("bit_offset")), S32(8)))); + } else { + *seq = SEQ3( + *seq, + SETL("byte_offset", DIV(VARL("offset"), U32(8))), + SETL("bit_offset", MOD(VARL("offset"), U32(8)))); + } + *seq = SEQ4( + *seq, + SETL(target->addr_local, ADD(VARL("base"), VARL("byte_offset"))), + SETL("byte_count", DIV(ADD(ADD(VARL("bit_offset"), VARL("width")), U32(7)), U32(8))), + read_bitfield_memory(target->addr_local)); + target->post = ea.post; + } else if (rz_m68k_op_is_data_reg(op)) { + RzILOpPure *value = m68k_read_reg_sized(ctx, op->reg, 32); + if (!value) { + return false; + } + *seq = SEQ3( + *seq, + SETL("bit_offset", MOD(VARL("offset"), U32(32))), + SETL("container", APPEND(value, m68k_read_reg_sized(ctx, op->reg, 32)))); + } else { + rz_il_op_effect_free(target->post); + target->post = NULL; + return false; + } + *seq = SEQ2(*seq, SETL("field", bitfield_field_from_container())); + return true; +} + +static RzILOpEffect *write_bitfield_target(M68KILCtx *ctx, const M68KBitfieldTarget *target, RzILOpPure *field) { + RzILOpEffect *write = NULL; + RzILOpPure *updated = bitfield_container_with_field(field); + if (target->memory) { + write = write_bitfield_memory(target->addr_local, updated); + } else if (rz_m68k_op_is_data_reg(target->op)) { + write = m68k_write_reg_sized(ctx, target->op->reg, 32, bitfield_data_reg_writeback(updated)); + } else { + rz_il_op_pure_free(updated); + } + if (!write) { + rz_il_op_effect_free(target->post); + return NULL; + } + return m68k_effect_pre_post(NULL, write, target->post); +} + +static RzILOpPure *bitfield_fffo_index(void) { + RzILOpPure *res = VARL("width"); + for (st32 i = 31; i >= 0; i--) { + RzILOpBool *in_range = ULT(U32(i), VARL("width")); + RzILOpBool *bit_set = NON_ZERO(LOGAND(VARL("scan"), U32(1u << (31 - i)))); + res = ITE(AND(in_range, bit_set), U32(i), res); + } + return res; +} + +static RzILOpEffect *lift_bitfield(M68KILCtx *ctx, ut32 insn_id) { + if (ctx->m68k->op_count < 1) { + return NULL; + } + bool insert = insn_id == M68K_INS_BFINS; + const cs_m68k_op *target_op = insert ? &ctx->m68k->operands[1] : &ctx->m68k->operands[0]; + M68KBitfieldTarget target = { 0 }; + RzILOpEffect *seq = NULL; + if (!target_op->mem.bitfield || !bitfield_target_to_local(ctx, target_op, &target, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *write = NULL; + switch (insn_id) { + case M68K_INS_BFTST: + if (target.post) { + seq = SEQ2(seq, target.post); + } + target.post = NULL; + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFEXTU: + case M68K_INS_BFEXTS: + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_data_reg(&ctx->m68k->operands[1])) { + m68k_bitfield_target_fini(&target); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ3( + seq, + SETL("res", insn_id == M68K_INS_BFEXTS ? bitfield_sign_extend() : VARL("field")), + m68k_write_reg_sized(ctx, ctx->m68k->operands[1].reg, 32, VARL("res"))); + if (target.post) { + seq = SEQ2(seq, target.post); + } + target.post = NULL; + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFFFO: + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_data_reg(&ctx->m68k->operands[1])) { + m68k_bitfield_target_fini(&target); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ4( + seq, + SETL("scan", bitfield_left_aligned()), + SETL("first", bitfield_fffo_index()), + m68k_write_reg_sized(ctx, ctx->m68k->operands[1].reg, 32, ADD(VARL("offset"), VARL("first")))); + if (target.post) { + seq = SEQ2(seq, target.post); + } + target.post = NULL; + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFCHG: + write = write_bitfield_target(ctx, &target, LOGXOR(VARL("field"), bitfield_mask32())); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFCLR: + write = write_bitfield_target(ctx, &target, U32(0)); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFSET: + write = write_bitfield_target(ctx, &target, bitfield_mask32()); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return SEQ2(seq, set_flags_bitfield(VARL("field"))); + case M68K_INS_BFINS: + if (ctx->m68k->op_count < 2 || !rz_m68k_op_is_data_reg(&ctx->m68k->operands[0])) { + m68k_bitfield_target_fini(&target); + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, SETL("src", LOGAND(m68k_read_reg_sized(ctx, ctx->m68k->operands[0].reg, 32), bitfield_mask32()))); + write = write_bitfield_target(ctx, &target, VARL("src")); + if (!write) { + rz_il_op_effect_free(seq); + return NULL; + } + seq = SEQ2(seq, write); + return SEQ2(seq, set_flags_bitfield(VARL("src"))); + default: + m68k_bitfield_target_fini(&target); + rz_il_op_effect_free(seq); + return NULL; + } +} + +static RzILOpEffect *lift_mul(M68KILCtx *ctx, bool sign) { + if (ctx->m68k->op_count < 2) { + return NULL; + } + const cs_m68k_op *dst_op = &ctx->m68k->operands[1]; + + if (dst_op->type == M68K_OP_REG_PAIR) { + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 32); + if (bits != 32) { + return NULL; + } + m68k_reg high_reg = dst_op->reg_pair.reg_0; + m68k_reg low_reg = dst_op->reg_pair.reg_1; + if (!rz_m68k_reg_is_dreg(high_reg) || !rz_m68k_reg_is_dreg(low_reg) || high_reg == low_reg) { + return NULL; + } + RzILOpEffect *seq = NULL; + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *dst = m68k_read_reg_sized(ctx, low_reg, bits); + if (!dst) { + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpEffect *write_high = m68k_write_reg_sized(ctx, high_reg, 32, SHIFTR0(VARL("res"), U8(32))); + RzILOpEffect *write_low = m68k_write_reg_sized(ctx, low_reg, 32, VARL("res")); + if (!write_high || !write_low) { + rz_il_op_effect_free(write_high); + rz_il_op_effect_free(write_low); + rz_il_op_effect_free(seq); + return NULL; + } + RzILOpPure *lhs = sign ? SIGNED(64, VARL("dst")) : UNSIGNED(64, VARL("dst")); + RzILOpPure *rhs = sign ? SIGNED(64, VARL("src")) : UNSIGNED(64, VARL("src")); + return SEQ2(seq, SEQ5(SETL("dst", dst), SETL("res", MUL(lhs, rhs)), write_low, write_high, m68k_set_flags_nzvcx(VARL("res"), 64, IL_FALSE, IL_FALSE, NULL))); + } + + if (dst_op->type != M68K_OP_REG) { + return NULL; + } + RzILOpEffect *seq = NULL; + ut32 bits = rz_m68k_detail_op_bits(ctx->m68k, 16); + if (bits != 16 && bits != 32) { + return NULL; + } + if (!m68k_operand_to_local(ctx, "src", &ctx->m68k->operands[0], bits, &seq)) { + rz_il_op_effect_free(seq); + return NULL; + } + m68k_reg reg = dst_op->reg; + RzILOpPure *dst = m68k_read_reg_sized(ctx, reg, bits); + if (!dst) { + rz_il_op_effect_free(seq); + return NULL; + } + ut32 product_bits = bits == 32 ? 64 : 32; + RzILOpPure *lhs = sign ? SIGNED(product_bits, dst) : UNSIGNED(product_bits, dst); + RzILOpPure *rhs = sign ? SIGNED(product_bits, VARL("src")) : UNSIGNED(product_bits, VARL("src")); + if (bits == 32) { + RzILOpBool *overflow = rz_m68k_mode_is_coldfire(ctx->mode) + ? IL_FALSE + : sign + ? m68k_signed_out_of_range(VARL("res_wide"), 32) + : UGT(VARL("res_wide"), U64(UT32_MAX)); + return SEQ2(seq, SEQ4(SETL("res_wide", MUL(lhs, rhs)), SETL("res", UNSIGNED(32, VARL("res_wide"))), m68k_write_reg_sized(ctx, reg, 32, VARL("res")), m68k_set_flags_nzvcx(VARL("res"), 32, overflow, IL_FALSE, NULL))); + } + + RzILOpPure *res = MUL(lhs, rhs); + return SEQ2(seq, SEQ3(SETL("res", DUP(res)), m68k_write_reg_sized(ctx, reg, 32, res), m68k_set_flags_nzvcx(VARL("res"), 32, IL_FALSE, IL_FALSE, NULL))); +} + +static RzILOpEffect *append_trap_arg_metadata(M68KILCtx *ctx, RzILOpEffect *seq) { + if (ctx->m68k->op_count > 0 && ctx->m68k->operands[0].type == M68K_OP_IMM) { + ut32 arg_bits = ctx->insn->size >= 6 ? 32 : 16; + seq = seq ? SEQ2(seq, SETL("trap_arg", U32((ut32)ctx->m68k->operands[0].imm))) : SETL("trap_arg", U32((ut32)ctx->m68k->operands[0].imm)); + seq = SEQ2(seq, SETL("trap_arg_bits", U32(arg_bits))); + } + return seq; +} + +static bool explicit_trap_vector(M68KTrapOp trap_op, M68KExceptionVector *vector) { + switch (trap_op) { + case M68K_TRAP_OP_TRAPCC: + case M68K_TRAP_OP_TRAPV: + *vector = M68K_VECTOR_TRAPV_TRAPCC; + return true; + default: + return false; + } +} + +static RzILOpEffect *explicit_trap_effect(M68KILCtx *ctx, M68KTrapOp trap_op, bool append_arg) { + RzILOpEffect *seq = SETL("trap_op", U32((ut32)trap_op)); + M68KExceptionVector vector; + if (explicit_trap_vector(trap_op, &vector)) { + seq = SEQ2(seq, SETL("trap_vector", U32((ut32)vector))); + } + if (append_arg) { + seq = append_trap_arg_metadata(ctx, seq); + } + return seq ? SEQ2(seq, m68k_label("m68k_trap")) : m68k_label("m68k_trap"); +} + +static RzILOpEffect *lift_trapcc(M68KILCtx *ctx) { + RzILOpBool *cond = cond_code(ctx, ctx->insn->id); + if (!cond) { + return explicit_trap_effect(ctx, M68K_TRAP_OP_TRAPCC, true); + } + return BRANCH(cond, explicit_trap_effect(ctx, M68K_TRAP_OP_TRAPCC, true), EMPTY()); +} + +static RzILOpEffect *lift_trap_vector(M68KILCtx *ctx) { + M68KTrapOp trap_op = ctx->insn->id == M68K_INS_BKPT ? M68K_TRAP_OP_BKPT : M68K_TRAP_OP_TRAP; + RzILOpEffect *seq = SETL("trap_op", U32((ut32)trap_op)); + if (ctx->m68k->op_count > 0 && ctx->m68k->operands[0].type == M68K_OP_IMM) { + ut32 arg = (ut32)ctx->m68k->operands[0].imm; + seq = SEQ2(seq, SETL("trap_arg", U32(arg))); + if (trap_op == M68K_TRAP_OP_TRAP) { + seq = SEQ2(seq, SETL("trap_vector", U32(M68K_VECTOR_TRAP_BASE + (arg & 0xf)))); + } + } + return SEQ2(seq, m68k_label("m68k_trap")); +} + +static RzILOpEffect *lift_trapv(M68KILCtx *ctx) { + return BRANCH(m68k_ccr_bit(M68K_CCR_V), explicit_trap_effect(ctx, M68K_TRAP_OP_TRAPV, false), EMPTY()); +} + +RZ_IPI RzILOpEffect *rz_m68k_cs_get_il_op(csh handle, cs_mode mode, RZ_NONNULL const cs_insn *insn, ut64 addr) { + rz_return_val_if_fail(insn && insn->detail, NULL); + if (insn->id >= M68K_INS_FABS && insn->id <= M68K_INS_FTWOTOX) { + return NULL; + } + M68KILCtx ctx = { + .handle = handle, + .mode = mode, + .insn = insn, + .m68k = &insn->detail->m68k, + .addr = addr, + .next_addr = addr + insn->size, + }; + if (ctx.m68k->op_count > RZ_ARRAY_SIZE(ctx.m68k->operands)) { + return NULL; + } + for (ut8 i = 0; i < ctx.m68k->op_count; i++) { + // Capstone can leave M68K_OP_INVALID on malformed encodings. + if (rz_m68k_op_detail_is_invalid(&ctx.m68k->operands[i])) { + return NULL; + } + } + + switch (insn->id) { + case M68K_INS_INVALID: + return NULL; + case M68K_INS_NOP: + return NOP(); + case M68K_INS_HALT: + return lift_privileged_system(M68K_SYSTEM_OP_HALT); + case M68K_INS_MOVE: +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + if (insn->detail && insn->detail->m68k.op_count >= 2) { + const cs_m68k_op *move_src = &insn->detail->m68k.operands[0]; + const cs_m68k_op *move_dst = &insn->detail->m68k.operands[1]; + if (rz_m68k_op_is_acc_reg(move_src) && rz_m68k_op_is_acc_reg(move_dst)) { + return lift_move_acc_to_acc(&ctx); + } + if (rz_m68k_op_is_acc_reg(move_src) && rz_m68k_op_is_gpr(move_dst)) { + return lift_move_from_acc(&ctx); + } + if (rz_m68k_op_is_acc_reg(move_dst) && + (rz_m68k_op_is_gpr(move_src) || move_src->type == M68K_OP_IMM)) { + return lift_move_to_acc(&ctx); + } + if (mac_op_is_accext(move_src) && rz_m68k_op_is_gpr(move_dst)) { + return lift_move_accext(&ctx); + } + if (mac_op_is_accext(move_dst) && + (rz_m68k_op_is_gpr(move_src) || move_src->type == M68K_OP_IMM)) { + return lift_move_accext(&ctx); + } + if (mac_op_is_mask(move_src) && rz_m68k_op_is_gpr(move_dst)) { + return lift_move_mask(&ctx); + } + if (mac_op_is_mask(move_dst) && + (rz_m68k_op_is_gpr(move_src) || move_src->type == M68K_OP_IMM)) { + return lift_move_mask(&ctx); + } + if (mac_op_is_macsr(move_src) && mac_op_is_ccr(move_dst)) { + return lift_move_macsr_to_ccr(&ctx); + } + if (mac_op_is_macsr(move_src) && rz_m68k_op_is_gpr(move_dst)) { + return lift_move_macsr(&ctx); + } + if (mac_op_is_macsr(move_dst) && + (rz_m68k_op_is_gpr(move_src) || move_src->type == M68K_OP_IMM)) { + return lift_move_macsr(&ctx); + } + } +#endif + return lift_move(&ctx, false); + case M68K_INS_MOVEC: + return lift_movec(&ctx); + case M68K_INS_MOVES: + return lift_moves(&ctx); + case M68K_INS_MOVEP: + return lift_movep(&ctx); + case M68K_INS_MOVEM: + return lift_movem(&ctx); + case M68K_INS_MOVE16: + return lift_move16(&ctx); + case M68K_INS_MOVEA: + return lift_move(&ctx, true); + case M68K_INS_MOVEQ: + return lift_moveq(&ctx); +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + case M68K_INS_MOV3Q: + return lift_mov3q(&ctx); + case M68K_INS_MOVCLR: + return lift_movclr(&ctx); + case M68K_INS_MVS: + return lift_mvs_mvz(&ctx, true); + case M68K_INS_MVZ: + return lift_mvs_mvz(&ctx, false); + case M68K_INS_BITREV: + case M68K_INS_BYTEREV: + case M68K_INS_FF1: + return lift_coldfire_bitop_reg(&ctx); + case M68K_INS_REMS: + return lift_rem(&ctx, true); + case M68K_INS_REMU: + return lift_rem(&ctx, false); + case M68K_INS_SATS: + return lift_sats(&ctx); + case M68K_INS_MAAAC: + return lift_mac_dual_acc(&ctx, false, false); + case M68K_INS_MAC: + return lift_mac_msac(&ctx, false); + case M68K_INS_MASAC: + return lift_mac_dual_acc(&ctx, false, true); + case M68K_INS_MSAAC: + return lift_mac_dual_acc(&ctx, true, false); + case M68K_INS_MSAC: + return lift_mac_msac(&ctx, true); + case M68K_INS_MSSAC: + return lift_mac_dual_acc(&ctx, true, true); +#endif +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + case M68K_INS_BGND: + return explicit_trap_effect(&ctx, M68K_TRAP_OP_BGND, false); +#endif + case M68K_INS_PULSE: + return lift_privileged_system(M68K_SYSTEM_OP_PULSE); +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + case M68K_INS_TPF: + return NOP(); + case M68K_INS_CP0NOP: + case M68K_INS_CP1NOP: + return lift_coprocessor_nop(&ctx); + case M68K_INS_INTOUCH: + return lift_cache_address_effects(&ctx); + case M68K_INS_STRLDSR: + return lift_strldsr(&ctx); + case M68K_INS_WDDATA: + return lift_coldfire_debug_transfer(&ctx, rz_m68k_detail_op_bits(ctx.m68k, 32)); + case M68K_INS_WDEBUG: + return lift_coldfire_debug_transfer(&ctx, 32); + case M68K_INS_CP0BCBUSY: + case M68K_INS_CP1BCBUSY: + return lift_coprocessor_branch(&ctx); + case M68K_INS_CP0LD: + case M68K_INS_CP1LD: + case M68K_INS_CP0ST: + case M68K_INS_CP1ST: + return lift_coprocessor_transfer(&ctx); +#endif + case M68K_INS_LEA: + return lift_lea(&ctx); + case M68K_INS_PEA: + return lift_pea(&ctx); + case M68K_INS_ADD: + case M68K_INS_ADDI: + return lift_binop(&ctx, RZ_IL_OP_ADD, false, false); + case M68K_INS_ADDQ: + return ctx.m68k->op_count >= 2 && rz_m68k_op_is_addr_reg(&ctx.m68k->operands[1]) + ? lift_binop(&ctx, RZ_IL_OP_ADD, true, false) + : lift_binop(&ctx, RZ_IL_OP_ADD, false, false); + case M68K_INS_ADDX: + return lift_addx_subx(&ctx, false); + case M68K_INS_ABCD: + return lift_abcd_sbcd(&ctx, false); + case M68K_INS_PACK: + return lift_pack_unpk(&ctx, false); + case M68K_INS_ADDA: + return lift_binop(&ctx, RZ_IL_OP_ADD, true, false); + case M68K_INS_SUB: + case M68K_INS_SUBI: + return lift_binop(&ctx, RZ_IL_OP_SUB, false, false); + case M68K_INS_SUBQ: + return ctx.m68k->op_count >= 2 && rz_m68k_op_is_addr_reg(&ctx.m68k->operands[1]) + ? lift_binop(&ctx, RZ_IL_OP_SUB, true, false) + : lift_binop(&ctx, RZ_IL_OP_SUB, false, false); + case M68K_INS_SUBX: + return lift_addx_subx(&ctx, true); + case M68K_INS_SBCD: + return lift_abcd_sbcd(&ctx, true); + case M68K_INS_UNPK: + return lift_pack_unpk(&ctx, true); + case M68K_INS_SUBA: + return lift_binop(&ctx, RZ_IL_OP_SUB, true, false); + case M68K_INS_CMP: + case M68K_INS_CMPI: + case M68K_INS_CMPM: + return lift_binop(&ctx, RZ_IL_OP_SUB, false, true); + case M68K_INS_CMPA: + return lift_binop(&ctx, RZ_IL_OP_SUB, true, true); + case M68K_INS_CMP2: + return lift_cmp2_chk2(&ctx, false); + case M68K_INS_AND: + return lift_binop(&ctx, RZ_IL_OP_LOGAND, false, false); + case M68K_INS_ANDI: + return ctx.m68k->op_count >= 2 && rz_m68k_op_is_status_reg(&ctx.m68k->operands[1]) + ? lift_status_binop(&ctx, RZ_IL_OP_LOGAND) + : lift_binop(&ctx, RZ_IL_OP_LOGAND, false, false); + case M68K_INS_OR: + return lift_binop(&ctx, RZ_IL_OP_LOGOR, false, false); + case M68K_INS_ORI: + return ctx.m68k->op_count >= 2 && rz_m68k_op_is_status_reg(&ctx.m68k->operands[1]) + ? lift_status_binop(&ctx, RZ_IL_OP_LOGOR) + : lift_binop(&ctx, RZ_IL_OP_LOGOR, false, false); + case M68K_INS_EOR: + return lift_binop(&ctx, RZ_IL_OP_LOGXOR, false, false); + case M68K_INS_EORI: + return ctx.m68k->op_count >= 2 && rz_m68k_op_is_status_reg(&ctx.m68k->operands[1]) + ? lift_status_binop(&ctx, RZ_IL_OP_LOGXOR) + : lift_binop(&ctx, RZ_IL_OP_LOGXOR, false, false); + case M68K_INS_CLR: + return lift_clr(&ctx); + case M68K_INS_TST: + return lift_tst(&ctx); + case M68K_INS_NOT: + return lift_not(&ctx); + case M68K_INS_NEG: + return lift_neg(&ctx, false); + case M68K_INS_NEGX: + return lift_neg(&ctx, true); + case M68K_INS_NBCD: + return lift_nbcd(&ctx); + case M68K_INS_EXT: + case M68K_INS_EXTB: + return lift_ext(&ctx); + case M68K_INS_TAS: + return lift_tas(&ctx); + case M68K_INS_SWAP: + return lift_swap(&ctx); + case M68K_INS_EXG: + return lift_exg(&ctx); + case M68K_INS_MULS: + return lift_mul(&ctx, true); + case M68K_INS_MULU: + return lift_mul(&ctx, false); + case M68K_INS_DIVS: + case M68K_INS_DIVSL: + return lift_div(&ctx, true); + case M68K_INS_DIVU: + case M68K_INS_DIVUL: + return lift_div(&ctx, false); +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + case M68K_INS_TBLS: + case M68K_INS_TBLU: + case M68K_INS_TBLSN: + case M68K_INS_TBLUN: + return lift_tbl(&ctx); +#endif + case M68K_INS_LSL: + return lift_shift(&ctx, true, false); + case M68K_INS_ASL: + return lift_shift(&ctx, true, true); + case M68K_INS_ASR: + return lift_shift(&ctx, false, true); + case M68K_INS_LSR: + return lift_shift(&ctx, false, false); + case M68K_INS_ROL: + return lift_rotate(&ctx, true, false); + case M68K_INS_ROR: + return lift_rotate(&ctx, false, false); + case M68K_INS_ROXL: + return lift_rotate(&ctx, true, true); + case M68K_INS_ROXR: + return lift_rotate(&ctx, false, true); + case M68K_INS_BRA: + return lift_branch(&ctx, true, false); + case M68K_INS_BSR: + return lift_branch(&ctx, true, true); + case M68K_INS_CALLM: + return lift_callm_address_effects(&ctx); + case M68K_INS_BHI: + case M68K_INS_BLS: + case M68K_INS_BCC: + case M68K_INS_BHS: + case M68K_INS_BCS: + case M68K_INS_BLO: + case M68K_INS_BNE: + case M68K_INS_BEQ: + case M68K_INS_BVC: + case M68K_INS_BVS: + case M68K_INS_BPL: + case M68K_INS_BMI: + case M68K_INS_BGE: + case M68K_INS_BLT: + case M68K_INS_BGT: + case M68K_INS_BLE: + return lift_branch(&ctx, false, false); + case M68K_INS_JMP: + return lift_jmp_jsr(&ctx, false); + case M68K_INS_JSR: + return lift_jmp_jsr(&ctx, true); + case M68K_INS_RTS: + return lift_rts(&ctx); + case M68K_INS_LINK: + return lift_link(&ctx); + case M68K_INS_UNLK: + return lift_unlk(&ctx); + case M68K_INS_CINVA: + case M68K_INS_CINVL: + case M68K_INS_CINVP: + case M68K_INS_CPUSHA: + case M68K_INS_CPUSHL: + case M68K_INS_CPUSHP: + return m68k_guard_supervisor(lift_cache_address_effects(&ctx)); + case M68K_INS_PFLUSHA: + case M68K_INS_PFLUSHAN: + return m68k_guard_supervisor(lift_mmu_flush_all(&ctx)); + case M68K_INS_PFLUSH: + case M68K_INS_PFLUSHN: + case M68K_INS_PLOADR: + case M68K_INS_PLOADW: + case M68K_INS_PLPAR: + case M68K_INS_PLPAW: + return m68k_guard_supervisor(lift_mmu_address_effects(&ctx, 32)); + case M68K_INS_PMOVE: + case M68K_INS_PMOVEFD: + return m68k_guard_supervisor(lift_pmove(&ctx)); + case M68K_INS_PTESTR: + case M68K_INS_PTESTW: + return m68k_guard_supervisor(lift_mmu_address_effects(&ctx, 32)); + case M68K_INS_ST: + case M68K_INS_SF: + case M68K_INS_SHI: + case M68K_INS_SLS: + case M68K_INS_SCC: + case M68K_INS_SHS: + case M68K_INS_SCS: + case M68K_INS_SLO: + case M68K_INS_SNE: + case M68K_INS_SEQ: + case M68K_INS_SVC: + case M68K_INS_SVS: + case M68K_INS_SPL: + case M68K_INS_SMI: + case M68K_INS_SGE: + case M68K_INS_SLT: + case M68K_INS_SGT: + case M68K_INS_SLE: + return lift_scc(&ctx); + case M68K_INS_DBT: + case M68K_INS_DBF: + case M68K_INS_DBRA: + case M68K_INS_DBHI: + case M68K_INS_DBLS: + case M68K_INS_DBCC: + case M68K_INS_DBCS: + case M68K_INS_DBNE: + case M68K_INS_DBEQ: + case M68K_INS_DBVC: + case M68K_INS_DBVS: + case M68K_INS_DBPL: + case M68K_INS_DBMI: + case M68K_INS_DBGE: + case M68K_INS_DBLT: + case M68K_INS_DBGT: + case M68K_INS_DBLE: + return lift_dbcc(&ctx); + case M68K_INS_CHK: + return lift_chk(&ctx); + case M68K_INS_CHK2: + return lift_cmp2_chk2(&ctx, true); + case M68K_INS_CAS: + return lift_cas(&ctx); + case M68K_INS_CAS2: + return lift_cas2(&ctx); + case M68K_INS_BTST: + case M68K_INS_BSET: + case M68K_INS_BCLR: + case M68K_INS_BCHG: + return lift_bitop(&ctx, insn->id); + case M68K_INS_BFCHG: + case M68K_INS_BFCLR: + case M68K_INS_BFEXTS: + case M68K_INS_BFEXTU: + case M68K_INS_BFFFO: + case M68K_INS_BFINS: + case M68K_INS_BFSET: + case M68K_INS_BFTST: + return lift_bitfield(&ctx, insn->id); + case M68K_INS_TRAPT: + case M68K_INS_TRAPF: + case M68K_INS_TRAPHI: + case M68K_INS_TRAPLS: + case M68K_INS_TRAPCC: + case M68K_INS_TRAPHS: + case M68K_INS_TRAPCS: + case M68K_INS_TRAPLO: + case M68K_INS_TRAPNE: + case M68K_INS_TRAPEQ: + case M68K_INS_TRAPVC: + case M68K_INS_TRAPVS: + case M68K_INS_TRAPPL: + case M68K_INS_TRAPMI: + case M68K_INS_TRAPGE: + case M68K_INS_TRAPLT: + case M68K_INS_TRAPGT: + case M68K_INS_TRAPLE: + return lift_trapcc(&ctx); + case M68K_INS_BKPT: + case M68K_INS_TRAP: + return lift_trap_vector(&ctx); + case M68K_INS_TRAPV: + return lift_trapv(&ctx); + case M68K_INS_ILLEGAL: + return m68k_label("m68k_illegal"); + case M68K_INS_RTR: + return lift_rtr(&ctx); + case M68K_INS_RTD: + return lift_rtd(&ctx); + case M68K_INS_RTE: + return lift_rte(&ctx); + case M68K_INS_RTM: + return lift_rtm(&ctx); + case M68K_INS_LPSTOP: + case M68K_INS_STOP: + return lift_stop(&ctx); + case M68K_INS_RESET: + return lift_privileged_system(M68K_SYSTEM_OP_RESET); + default: + return m68k_label("m68k_unimplemented"); + } +} + +static void label_ignore(RzILVM *vm, RzILOpEffect *op) { + (void)vm; + (void)op; +} + +static const char *m68k_il_regs[] = { + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + // PC is synchronized through the VM program counter, not a global variable. + "sr", "sfc", "dfc", "vbr", "cacr", "caar", + "usp", "msp", "isp", "tc", "itt0", "itt1", "dtt0", "dtt1", "mmusr", "urp", "srp", + "tt0", "tt1", "crp", + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "fpcr", "fpsr", "fpiar", + "acc", "acc0", "acc1", "acc2", "acc3", "accext01", "accext23", "macsr", "mask", + "cp_external_data", + NULL +}; + +RZ_IPI RzAnalysisILConfig *rz_m68k_cs_il_config(RZ_NONNULL RzAnalysis *analysis) { + rz_return_val_if_fail(analysis, NULL); + RzAnalysisILConfig *cfg = rz_analysis_il_config_new(32, true, 32); + if (!cfg) { + return NULL; + } + cfg->reg_bindings = m68k_il_regs; + const char *labels[] = { + "m68k_unimplemented", + "m68k_trap", + "m68k_illegal", + "m68k_privilege", + "m68k_chk", + "m68k_mmu", + "m68k_cache", + "m68k_debug", + "m68k_coprocessor", + "m68k_callm", + "m68k_rtm", + "m68k_system", + NULL + }; + for (size_t i = 0; labels[i]; i++) { + RzILEffectLabel *label = rz_il_effect_label_new(labels[i], EFFECT_LABEL_SYSCALL); + if (!label) { + rz_analysis_il_config_free(cfg); + return NULL; + } + label->hook = label_ignore; + rz_analysis_il_config_add_label(cfg, label); + } + cfg->init_state = rz_analysis_il_init_state_new(); + if (!cfg->init_state) { + rz_analysis_il_config_free(cfg); + return NULL; + } + rz_analysis_il_init_state_set_var(cfg->init_state, "sr", rz_il_value_new_bitv(rz_bv_new_from_ut64(16, 0))); + rz_analysis_il_init_state_set_var(cfg->init_state, "mask", rz_il_value_new_bitv(rz_bv_new_from_ut64(32, M68K_MAC_MASK_RESET))); + rz_analysis_il_init_state_set_var(cfg->init_state, "macsr", rz_il_value_new_bitv(rz_bv_new_from_ut64(32, 0))); + rz_analysis_il_init_state_set_var(cfg->init_state, "cp_external_data", rz_il_value_new_bitv(rz_bv_new_from_ut64(32, 0))); + const char *fp_regs[] = { + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", NULL + }; + for (size_t i = 0; fp_regs[i]; i++) { + rz_analysis_il_init_state_set_var(cfg->init_state, fp_regs[i], rz_il_value_new_bitv(rz_bv_new_from_ut64(80, 0))); + } + return cfg; +} + +#include diff --git a/librz/arch/isa/m68k/m68k_il.h b/librz/arch/isa/m68k/m68k_il.h new file mode 100644 index 0000000000..03953335a4 --- /dev/null +++ b/librz/arch/isa/m68k/m68k_il.h @@ -0,0 +1,14 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RZ_M68K_IL_H +#define RZ_M68K_IL_H + +#include +#include +#include + +RZ_IPI RzAnalysisILConfig *rz_m68k_cs_il_config(RZ_NONNULL RzAnalysis *analysis); +RZ_IPI RzILOpEffect *rz_m68k_cs_get_il_op(csh handle, cs_mode mode, RZ_NONNULL const cs_insn *insn, ut64 addr); + +#endif // RZ_M68K_IL_H diff --git a/librz/arch/isa/m68k/m68k_il_helpers.c b/librz/arch/isa/m68k/m68k_il_helpers.c new file mode 100644 index 0000000000..494668e9b2 --- /dev/null +++ b/librz/arch/isa/m68k/m68k_il_helpers.c @@ -0,0 +1,970 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#include "m68k/m68k_il_helpers.h" + +#include +#include + +static inline bool m68k_mode_has_master_stack(cs_mode mode) { + /* MC68060UM 11.1.2: the 68060 retains SR.M for software use, but has + * only one supervisor stack. */ + return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 || + mode == CS_MODE_M68K_040; +} + +static RzILOpBool *sr_bit(ut32 bit) { + return NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16((ut16)(1u << bit)))); +} + +static bool is_supervisor_stack_bank(const M68KILCtx *ctx, m68k_reg reg) { + rz_return_val_if_fail(ctx, false); + return m68k_mode_has_master_stack(ctx->mode) && + (reg == M68K_REG_ISP || reg == M68K_REG_MSP); +} + +static RzILOpBool *supervisor_stack_bank_active(m68k_reg reg) { + /* M68000PRM 1.3.1/1.3.2: ISP and MSP name the physical A7 banks. + * Their globals hold saved values only while the bank is inactive. */ + return AND(sr_bit(M68K_SR_S), reg == M68K_REG_MSP ? sr_bit(M68K_SR_M) : INV(sr_bit(M68K_SR_M))); +} + +RZ_IPI RzILOpPure *m68k_reg_value(M68KILCtx *ctx, m68k_reg reg) { + const char *name = cs_reg_name(ctx->handle, reg); + if (!name) { + rz_warn_if_reached(); + return NULL; + } + if (is_supervisor_stack_bank(ctx, reg)) { + return ITE(supervisor_stack_bank_active(reg), VARG("a7"), VARG(name)); + } + return VARG(name); +} + +RZ_IPI RzILOpPure *m68k_read_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits) { + const char *name = cs_reg_name(ctx->handle, reg); + if (!name) { + rz_warn_if_reached(); + return NULL; + } + switch (reg) { + case M68K_REG_A0: + case M68K_REG_A1: + case M68K_REG_A2: + case M68K_REG_A3: + case M68K_REG_A4: + case M68K_REG_A5: + case M68K_REG_A6: + case M68K_REG_A7: + case M68K_REG_PC: + case M68K_REG_USP: + return bits == 32 ? VARG(name) : UNSIGNED(bits, VARG(name)); + case M68K_REG_MSP: + case M68K_REG_ISP: + return bits == 32 ? m68k_reg_value(ctx, reg) : UNSIGNED(bits, m68k_reg_value(ctx, reg)); + case M68K_REG_CCR: + return bits <= 8 + ? UNSIGNED(bits, VARG("sr")) + : UNSIGNED(bits, UNSIGNED(8, VARG("sr"))); + case M68K_REG_SR: + return bits == 16 ? VARG(name) : UNSIGNED(bits, VARG(name)); + case M68K_REG_FP0: + case M68K_REG_FP1: + case M68K_REG_FP2: + case M68K_REG_FP3: + case M68K_REG_FP4: + case M68K_REG_FP5: + case M68K_REG_FP6: + case M68K_REG_FP7: + return bits == 80 ? VARG(name) : UNSIGNED(bits, VARG(name)); + default: + break; + } + if (rz_m68k_reg_name_is_mmu_root_pointer(name)) { + return bits == 64 ? VARG(name) : UNSIGNED(bits, VARG(name)); + } + return bits == 32 ? VARG(name) : UNSIGNED(bits, VARG(name)); +} + +RZ_IPI RzILOpEffect *m68k_set_ccr_from_value(RzILOpPure *new_ccr) { + RzILOpPure *ccr8 = UNSIGNED(8, new_ccr); + return SETG("sr", LOGOR(LOGAND(VARG("sr"), U16(0xff00)), UNSIGNED(16, ccr8))); +} + +RZ_IPI RzILOpBool *m68k_ccr_bit(ut32 bit) { + rz_return_val_if_fail(bit < 8, NULL); + return NON_ZERO(LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << bit))); +} + +static RzILOpBool *cacr_eusp(RzILOpPure *cacr) { + return NON_ZERO(LOGAND(UNSIGNED(32, cacr), U32(1u << M68K_CACR_EUSP))); +} + +static RzILOpBool *coldfire_supervisor_stack(RzILOpPure *sr) { + /* MCF5208RM 3.2.3 and 5.2.1: the second A7 bank participates only + * while CACR[EUSP] is enabled. */ + return AND( + NON_ZERO(LOGAND(UNSIGNED(16, sr), U16(1u << M68K_SR_S))), + cacr_eusp(VARG("cacr"))); +} + +RZ_IPI RzILOpBool *m68k_supervisor_mode(void) { + return sr_bit(M68K_SR_S); +} + +RZ_IPI RzILOpPure *m68k_ccr_with_flag(RzILOpPure *ccr, ut32 bit, RzILOpBool *value) { + RzILOpPure *cleared = LOGAND(ccr, U8((ut8) ~(1u << bit))); + RzILOpPure *flag = SHIFTL0(BOOL_TO_BV(value, 8), U8(bit)); + return LOGOR(cleared, flag); +} + +RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c, RzILOpBool *x) { + RzILOpPure *val = UNSIGNED(bits, value); + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, MSB(DUP(val))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, IS_ZERO(val)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, v ? v : IL_FALSE); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, c ? c : IL_FALSE); + if (x) { + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, x); + } else { + ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X))); + } + return m68k_set_ccr_from_value(ccr); +} + +RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx_extend(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c) { + RzILOpPure *val = UNSIGNED(bits, value); + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, MSB(DUP(val))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(m68k_ccr_bit(M68K_CCR_Z), IS_ZERO(val))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, v); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, c); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, (RzILOpBool *)DUP(c)); + return m68k_set_ccr_from_value(ccr); +} + +RZ_IPI RzILOpEffect *m68k_set_flags_div(RzILOpPure *quotient, ut32 bits, RzILOpBool *overflow) { + RzILOpPure *quotient_sized = UNSIGNED(bits, quotient); + RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0)); + RzILOpBool *no_overflow = INV((RzILOpBool *)DUP(overflow)); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, AND(no_overflow, MSB(DUP(quotient_sized)))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(INV((RzILOpBool *)DUP(overflow)), IS_ZERO(quotient_sized))); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, overflow); + ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE); + ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X))); + return m68k_set_ccr_from_value(ccr); +} + +RZ_IPI RzILOpBool *m68k_add_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r) { + RzILOpBool *same_sign = EQ(BOOL_TO_BV(MSB(DUP(a)), 1), BOOL_TO_BV(MSB(b), 1)); + RzILOpBool *diff_result = NE(BOOL_TO_BV(MSB(a), 1), BOOL_TO_BV(MSB(r), 1)); + return AND(same_sign, diff_result); +} + +RZ_IPI RzILOpBool *m68k_sub_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r) { + RzILOpBool *diff_sign = NE(BOOL_TO_BV(MSB(DUP(a)), 1), BOOL_TO_BV(MSB(b), 1)); + RzILOpBool *diff_result = NE(BOOL_TO_BV(MSB(a), 1), BOOL_TO_BV(MSB(r), 1)); + return AND(diff_sign, diff_result); +} + +RZ_IPI RzILOpBool *m68k_signed_out_of_range(RzILOpPure *value, ut32 bits) { + st64 min = -(1LL << (bits - 1)); + st64 max = (1LL << (bits - 1)) - 1; + return OR(SLT(DUP(value), S64(min)), SGT(value, S64(max))); +} + +RZ_IPI RzILOpBool *m68k_addx_overflow(ut32 bits) { + RzILOpPure *sum = ADD(ADD(SIGNED(64, VARL("dst")), SIGNED(64, VARL("src"))), UNSIGNED(64, VARL("x"))); + return m68k_signed_out_of_range(sum, bits); +} + +RZ_IPI RzILOpBool *m68k_subx_overflow(ut32 bits) { + RzILOpPure *diff = SUB(SUB(SIGNED(64, VARL("dst")), SIGNED(64, VARL("src"))), UNSIGNED(64, VARL("x"))); + return m68k_signed_out_of_range(diff, bits); +} + +RZ_IPI RzILOpBool *m68k_negx_overflow(ut32 bits) { + RzILOpPure *diff = SUB(SUB(S64(0), SIGNED(64, VARL("dst"))), UNSIGNED(64, VARL("borrow"))); + return m68k_signed_out_of_range(diff, bits); +} + +static RzILOpPure *reg_write_value(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value) { + if (rz_m68k_reg_is_dreg(reg) && bits < 32) { + ut32 mask = bits == 8 ? 0xffffff00u : 0xffff0000u; + return LOGOR(LOGAND(m68k_reg_value(ctx, reg), U32(mask)), UNSIGNED(32, value)); + } + if (rz_m68k_reg_is_areg(reg) && bits == 16) { + return SIGNED(32, value); + } + if (reg == M68K_REG_CCR) { + return UNSIGNED(8, value); + } + if (reg == M68K_REG_SR) { + return UNSIGNED(16, value); + } + if (rz_m68k_reg_is_fpu(reg)) { + return UNSIGNED(80, value); + } + const char *name = cs_reg_name(ctx->handle, reg); + if (rz_m68k_reg_name_is_mmu_root_pointer(name)) { + if (bits == 64) { + return UNSIGNED(64, value); + } + return LOGOR(LOGAND(m68k_reg_value(ctx, reg), U64(0xffffffff00000000ULL)), UNSIGNED(64, value)); + } + return UNSIGNED(32, value); +} + +RZ_IPI RzILOpEffect *m68k_write_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value) { + const char *name = cs_reg_name(ctx->handle, reg); + if (!name) { + rz_warn_if_reached(); + rz_il_op_pure_free(value); + return NULL; + } + if (reg == M68K_REG_PC) { + return JMP(UNSIGNED(32, value)); + } + if (reg == M68K_REG_CCR) { + return m68k_set_ccr_from_value(value); + } + if (is_supervisor_stack_bank(ctx, reg)) { + RzILOpPure *sp = UNSIGNED(32, value); + return BRANCH(supervisor_stack_bank_active(reg), SETG("a7", DUP(sp)), SETG(name, sp)); + } + if (reg == M68K_REG_CACR && rz_m68k_mode_is_coldfire(ctx->mode)) { + /* Changing EUSP in supervisor mode changes which physical A7 is + * active, so preserve the outgoing bank before loading the incoming + * one. */ + RzILOpEffect *enable_eusp = SEQ2( + SETG("usp", UNSIGNED(32, VARG("a7"))), + SETG("a7", UNSIGNED(32, VARG("isp")))); + RzILOpEffect *disable_eusp = SEQ2( + SETG("isp", UNSIGNED(32, VARG("a7"))), + SETG("a7", UNSIGNED(32, VARG("usp")))); + RzILOpEffect *switch_sp = BRANCH( + cacr_eusp(VARG("cacr")), + disable_eusp, + enable_eusp); + return SEQ3( + SETL("cacr_write_value", UNSIGNED(32, value)), + BRANCH( + AND( + m68k_supervisor_mode(), + XOR(cacr_eusp(VARG("cacr")), cacr_eusp(VARL("cacr_write_value")))), + switch_sp, + EMPTY()), + SETG("cacr", VARL("cacr_write_value"))); + } + if (reg == M68K_REG_SR) { + if (rz_m68k_mode_is_coldfire(ctx->mode)) { + RzILOpEffect *save_old_sp = BRANCH( + coldfire_supervisor_stack(VARG("sr")), + SETG("isp", UNSIGNED(32, VARG("a7"))), + SETG("usp", UNSIGNED(32, VARG("a7")))); + RzILOpEffect *load_new_sp = BRANCH( + coldfire_supervisor_stack(VARL("sr_write_value")), + SETG("a7", UNSIGNED(32, VARG("isp"))), + SETG("a7", UNSIGNED(32, VARG("usp")))); + RzILOpPure *old_bank = ITE(coldfire_supervisor_stack(VARG("sr")), U8(1), U8(0)); + RzILOpPure *new_bank = ITE(coldfire_supervisor_stack(VARL("sr_write_value")), U8(1), U8(0)); + return SEQ3( + SETL("sr_write_value", UNSIGNED(16, value)), + BRANCH(NE(old_bank, new_bank), SEQ2(save_old_sp, load_new_sp), EMPTY()), + SETG("sr", VARL("sr_write_value"))); + } + bool has_master_stack = m68k_mode_has_master_stack(ctx->mode); + ut16 master_mask = has_master_stack ? 1u << M68K_SR_M : 0; + RzILOpEffect *save_old_sp = BRANCH( + IS_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(1u << M68K_SR_S))), + SETG("usp", UNSIGNED(32, VARG("a7"))), + BRANCH( + NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(master_mask))), + SETG("msp", UNSIGNED(32, VARG("a7"))), + SETG("isp", UNSIGNED(32, VARG("a7"))))); + RzILOpEffect *load_new_sp = BRANCH( + IS_ZERO(LOGAND(VARL("sr_write_value"), U16(1u << M68K_SR_S))), + SETG("a7", UNSIGNED(32, VARG("usp"))), + BRANCH( + NON_ZERO(LOGAND(VARL("sr_write_value"), U16(master_mask))), + SETG("a7", UNSIGNED(32, VARG("msp"))), + SETG("a7", UNSIGNED(32, VARG("isp"))))); + RzILOpPure *old_bank = ITE( + IS_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(1u << M68K_SR_S))), + U8(0), + ITE(NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(master_mask))), U8(2), U8(1))); + RzILOpPure *new_bank = ITE( + IS_ZERO(LOGAND(VARL("sr_write_value"), U16(1u << M68K_SR_S))), + U8(0), + ITE(NON_ZERO(LOGAND(VARL("sr_write_value"), U16(master_mask))), U8(2), U8(1))); + return SEQ3( + SETL("sr_write_value", UNSIGNED(16, value)), + BRANCH(NE(old_bank, new_bank), SEQ2(save_old_sp, load_new_sp), EMPTY()), + SETG("sr", VARL("sr_write_value"))); + } + return SETG(name, reg_write_value(ctx, reg, bits, value)); +} + +RZ_IPI bool m68k_mode_uses_later_movem_base_value(cs_mode mode) { + if (mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 || + mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060) { + return true; + } +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + return mode == CS_MODE_M68K_CPU32; +#else + return false; +#endif +} + +RZ_IPI bool m68k_mode_has_format_word(cs_mode mode) { + return mode != CS_MODE_M68K_000; +} + +RZ_IPI RzILOpBool *m68k_rte_format_valid(cs_mode mode) { + switch (mode) { + case CS_MODE_M68K_010: + return OR(EQ(VARL("format"), U16(0)), EQ(VARL("format"), U16(8))); + case CS_MODE_M68K_020: + case CS_MODE_M68K_030: + return OR( + ULT(VARL("format"), U16(3)), + AND(UGE(VARL("format"), U16(9)), ULT(VARL("format"), U16(12)))); + case CS_MODE_M68K_040: + return OR(ULT(VARL("format"), U16(5)), EQ(VARL("format"), U16(7))); + case CS_MODE_M68K_060: + return AND(ULT(VARL("format"), U16(5)), NE(VARL("format"), U16(1))); + default: + break; + } +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + if (mode == CS_MODE_M68K_CPU32) { + return OR(ULT(VARL("format"), U16(3)), EQ(VARL("format"), U16(12))); + } +#endif + return AND( + ULT(VARL("format"), U16(12)), + AND(NE(VARL("format"), U16(5)), NE(VARL("format"), U16(6)))); +} + +RZ_IPI RzILOpPure *m68k_rte_frame_size(cs_mode mode) { + RzILOpPure *size = ITE(EQ(VARL("format"), U16(0)), U32(8), + ITE(EQ(VARL("format"), U16(1)), U32(8), + ITE(EQ(VARL("format"), U16(2)), U32(12), + ITE(EQ(VARL("format"), U16(3)), U32(12), + ITE(EQ(VARL("format"), U16(4)), U32(16), + ITE(EQ(VARL("format"), U16(7)), U32(60), + ITE(EQ(VARL("format"), U16(8)), U32(58), + ITE(EQ(VARL("format"), U16(9)), U32(20), + ITE(EQ(VARL("format"), U16(10)), U32(32), U32(92)))))))))); +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 + if (mode == CS_MODE_M68K_CPU32) { + size = ITE(EQ(VARL("format"), U16(12)), U32(24), size); + } +#else + (void)mode; +#endif + return size; +} + +static RzILOpPure *index_value(M68KILCtx *ctx, const cs_m68k_op *op) { + if (op->mem.index_reg == M68K_REG_INVALID) { + return U32(0); + } + RzILOpPure *idx = m68k_read_reg_sized(ctx, op->mem.index_reg, op->mem.index_size ? 32 : 16); + if (!idx) { + return NULL; + } + idx = !op->mem.index_size ? SIGNED(32, idx) : UNSIGNED(32, idx); + ut8 scale = op->mem.scale ? op->mem.scale : 1; + if (scale > 1) { + idx = MUL(idx, U32(scale)); + } + return idx; +} + +#if !defined(RZ_CAPSTONE_HAS_M68K_CPU32) && !defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE) +// Older Capstone releases report raw PC-relative displacements. Recover the +// encoded extension word address so operands after other extension words lift +// to the expected address. +static bool insn_word_at(const M68KILCtx *ctx, ut32 offset, ut16 *ext_word) { + rz_return_val_if_fail(ctx && ctx->insn && ext_word, false); + if (offset + 1 >= ctx->insn->size || offset + 1 >= sizeof(ctx->insn->bytes)) { + return false; + } + *ext_word = ((ut16)ctx->insn->bytes[offset] << 8) | ctx->insn->bytes[offset + 1]; + return true; +} + +static ut32 mem_extension_bytes(const cs_m68k_op *op) { + switch (op->address_mode) { + case M68K_AM_REGI_ADDR_DISP: + case M68K_AM_PCI_DISP: + case M68K_AM_ABSOLUTE_DATA_SHORT: + return 2; + case M68K_AM_AREGI_INDEX_8_BIT_DISP: + case M68K_AM_PCI_INDEX_8_BIT_DISP: + return 2; + case M68K_AM_ABSOLUTE_DATA_LONG: + return 4; + case M68K_AM_AREGI_INDEX_BASE_DISP: + case M68K_AM_MEMI_PRE_INDEX: + case M68K_AM_MEMI_POST_INDEX: + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_PC_MEMI_POST_INDEX: { + ut32 bytes = 2; + if (op->mem.in_disp) { + bytes += 2; + } + if (op->mem.out_disp) { + bytes += 2; + } + return bytes; + } + default: + return 0; + } +} + +static ut32 operand_extension_bytes(const M68KILCtx *ctx, const cs_m68k_op *op) { + switch (op->type) { + case M68K_OP_IMM: + return rz_m68k_detail_op_bits(ctx->m68k, 16) > 16 ? 4 : 2; + case M68K_OP_FP_SINGLE: + return 4; + case M68K_OP_FP_DOUBLE: + return 8; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + case M68K_OP_FP_EXTENDED: + case M68K_OP_FP_PACKED: + return 12; +#endif + case M68K_OP_BR_DISP: + switch (op->br_disp.disp_size) { + case M68K_OP_BR_DISP_SIZE_BYTE: + return 0; + case M68K_OP_BR_DISP_SIZE_WORD: + return 2; + case M68K_OP_BR_DISP_SIZE_LONG: + return 4; + default: + return 0; + } + case M68K_OP_MEM: + return mem_extension_bytes(op); + case M68K_OP_INVALID: + case M68K_OP_REG: + case M68K_OP_REG_BITS: + case M68K_OP_REG_PAIR: +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + case M68K_OP_SHIFT: +#endif + default: + return 0; + } +} + +static ut32 hidden_extension_bytes_before_ea(const M68KILCtx *ctx) { + switch (ctx->insn->id) { + case M68K_INS_MULS: + case M68K_INS_MULU: + case M68K_INS_DIVS: + case M68K_INS_DIVU: + case M68K_INS_DIVSL: + case M68K_INS_DIVUL: + /* M68000PRM long MUL/DIV: the register/size extension precedes EA. */ + return rz_m68k_detail_op_bits(ctx->m68k, 16) == 32 ? 2 : 0; + case M68K_INS_BFCHG: + case M68K_INS_BFCLR: + case M68K_INS_BFEXTS: + case M68K_INS_BFEXTU: + case M68K_INS_BFFFO: + case M68K_INS_BFINS: + case M68K_INS_BFSET: + case M68K_INS_BFTST: + case M68K_INS_CHK2: + case M68K_INS_CMP2: + case M68K_INS_MOVES: + return 2; + default: + break; + } + return ctx->insn->size >= 4 && (ctx->insn->bytes[0] & 0xf0) == 0xf0 ? 2 : 0; +} + +static ut32 expected_pc_relative_extension_offset(const M68KILCtx *ctx, const cs_m68k_op *op) { + ut32 offset = 2 + hidden_extension_bytes_before_ea(ctx); + for (ut8 i = 0; i < ctx->m68k->op_count; i++) { + const cs_m68k_op *cur = &ctx->m68k->operands[i]; + if (cur == op) { + break; + } + offset += operand_extension_bytes(ctx, cur); + } + return offset; +} + +/* 680x0 brief/full index extension word (M68000PRM indexed addressing). */ +enum { + M68K_EXT_WORD_INDEX_ADDR_REG = 0x8000, /* D/A, bit 15 */ + M68K_EXT_WORD_INDEX_LONG = 0x0800, /* W/L, bit 11 */ + M68K_EXT_WORD_FULL_FORMAT = 0x0100, /* 0=brief, 1=full, bit 8 */ + M68K_EXT_WORD_INDEX_SUPPRESS = 0x0040, /* full-format IS, bit 6 */ +}; + +static bool index_extension_word_matches(const cs_m68k_op *op, ut16 ext_word, bool full) { + if (((ext_word & M68K_EXT_WORD_FULL_FORMAT) != 0) != full) { + return false; + } + if (op->mem.index_reg == M68K_REG_INVALID) { + return full && (ext_word & M68K_EXT_WORD_INDEX_SUPPRESS); + } + m68k_reg index_reg = ((ext_word & M68K_EXT_WORD_INDEX_ADDR_REG) ? M68K_REG_A0 : M68K_REG_D0) + + ((ext_word >> 12) & 7); + if (op->mem.index_reg != index_reg) { + return false; + } + if (op->mem.index_size != ((ext_word & M68K_EXT_WORD_INDEX_LONG) ? 1 : 0)) { + return false; + } + ut8 scale = 1 << ((ext_word >> 9) & 3); + return (op->mem.scale ? op->mem.scale : 1) == scale; +} + +static bool pc_relative_extension_word_matches(const cs_m68k_op *op, ut16 ext_word) { + switch (op->address_mode) { + case M68K_AM_PCI_DISP: + return (st16)ext_word == op->mem.disp; + case M68K_AM_PCI_INDEX_8_BIT_DISP: + return index_extension_word_matches(op, ext_word, false) && (st8)(ext_word & 0xff) == op->mem.disp; + case M68K_AM_PCI_INDEX_BASE_DISP: + case M68K_AM_PC_MEMI_PRE_INDEX: + case M68K_AM_PC_MEMI_POST_INDEX: + return index_extension_word_matches(op, ext_word, true); + default: + return false; + } +} + +static ut32 pc_relative_extension_offset(const M68KILCtx *ctx, const cs_m68k_op *op) { + ut32 expected = expected_pc_relative_extension_offset(ctx, op); + ut16 ext_word = 0; + if (insn_word_at(ctx, expected, &ext_word) && pc_relative_extension_word_matches(op, ext_word)) { + return expected; + } + + ut32 fallback = expected; + bool found = false; + for (ut32 offset = 2; offset + 1 < ctx->insn->size; offset += 2) { + if (!insn_word_at(ctx, offset, &ext_word) || !pc_relative_extension_word_matches(op, ext_word)) { + continue; + } + if (offset >= expected) { + return offset; + } + if (!found) { + fallback = offset; + found = true; + } + } + return fallback; +} +#endif + +static ut64 branch_disp_base(const M68KILCtx *ctx) { + /* Capstone br_disp is relative to the opcode-word successor (addr+2). + * FDBcc's encoding displacement is relative to the 16-bit displacement + * word (addr+4 / MC68020 UM 7.2.2.3.2). Capstone already adds that extra + * two bytes into br_disp.disp, so using addr+2 here is correct for both + * DBcc/FBcc and FDBcc. Do not switch FDBcc to addr+4 or the offset is + * applied twice. */ + return ctx->addr + 2; +} + +static ut64 pc_relative_base(M68KILCtx *ctx, const cs_m68k_op *op) { +#if defined(RZ_CAPSTONE_HAS_M68K_CPU32) || defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE) + (void)op; + return branch_disp_base(ctx); +#else + return ctx->addr + pc_relative_extension_offset(ctx, op); +#endif +} + +RZ_IPI RzILOpPure *m68k_branch_disp_target(const M68KILCtx *ctx, const cs_m68k_op *op) { + rz_return_val_if_fail(ctx && op, NULL); + if (op->type != M68K_OP_BR_DISP) { + return NULL; + } + return U32(branch_disp_base(ctx) + op->br_disp.disp); +} + +RZ_IPI RzILOpEffect *m68k_set_addr_reg_delta(M68KILCtx *ctx, m68k_reg reg, st32 delta) { + if (!rz_m68k_reg_is_areg(reg)) { + return NULL; + } + RzILOpPure *base = m68k_reg_value(ctx, reg); + RzILOpPure *res = delta >= 0 ? ADD(base, U32((ut32)delta)) : SUB(base, U32((ut32)-delta)); + return m68k_write_reg_sized(ctx, reg, 32, res); +} + +RZ_IPI M68KEA m68k_effective_addr(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits) { + M68KEA ea = { 0 }; + rz_return_val_if_fail(ctx && op, ea); + RzILOpPure *base = NULL; + RzILOpPure *idx = NULL; + m68k_reg base_reg = rz_m68k_op_base_reg(op); + switch (op->address_mode) { + case M68K_AM_REGI_ADDR: + ea.addr = m68k_reg_value(ctx, base_reg); + break; + case M68K_AM_REGI_ADDR_POST_INC: + ea.addr = m68k_reg_value(ctx, base_reg); + ea.post = m68k_set_addr_reg_delta(ctx, base_reg, rz_m68k_reg_stack_access_bytes(ctx->mode, base_reg, bits)); + break; + case M68K_AM_REGI_ADDR_PRE_DEC: + ea.pre = m68k_set_addr_reg_delta(ctx, base_reg, -(st32)rz_m68k_reg_stack_access_bytes(ctx->mode, base_reg, bits)); + ea.addr = m68k_reg_value(ctx, base_reg); + break; + case M68K_AM_REGI_ADDR_DISP: + ea.addr = ADD(UNSIGNED(32, m68k_reg_value(ctx, base_reg)), UNSIGNED(32, S32((st32)op->mem.disp))); + break; + case M68K_AM_AREGI_INDEX_8_BIT_DISP: + case M68K_AM_AREGI_INDEX_BASE_DISP: { + st64 disp = op->address_mode == M68K_AM_AREGI_INDEX_BASE_DISP ? op->mem.in_disp : op->mem.disp; + base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0); + idx = index_value(ctx, op); + ea.addr = ADD(ADD(UNSIGNED(32, base), UNSIGNED(32, S32((st32)disp))), idx); + break; + } + case M68K_AM_MEMI_PRE_INDEX: + base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0); + idx = index_value(ctx, op); + ea.addr = ADD(LOADW(32, ADD(ADD(base, idx), S32((st32)op->mem.in_disp))), S32((st32)op->mem.out_disp)); + break; + case M68K_AM_MEMI_POST_INDEX: + base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0); + idx = index_value(ctx, op); + ea.addr = ADD(ADD(LOADW(32, ADD(base, S32((st32)op->mem.in_disp))), idx), S32((st32)op->mem.out_disp)); + break; + case M68K_AM_PCI_DISP: + ea.addr = U32(pc_relative_base(ctx, op) + op->mem.disp); + break; + case M68K_AM_PCI_INDEX_8_BIT_DISP: + case M68K_AM_PCI_INDEX_BASE_DISP: { + st64 disp = op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP ? op->mem.in_disp : op->mem.disp; + idx = index_value(ctx, op); + ut64 pc_base = op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP && base_reg == M68K_REG_INVALID + ? 0 + : pc_relative_base(ctx, op); + ea.addr = ADD(U32(pc_base + disp), idx); + break; + } + case M68K_AM_PC_MEMI_PRE_INDEX: + base = base_reg != M68K_REG_INVALID ? U32(pc_relative_base(ctx, op)) : U32(0); + idx = index_value(ctx, op); + ea.addr = ADD(LOADW(32, ADD(ADD(base, idx), S32((st32)op->mem.in_disp))), S32((st32)op->mem.out_disp)); + break; + case M68K_AM_PC_MEMI_POST_INDEX: + base = base_reg != M68K_REG_INVALID ? U32(pc_relative_base(ctx, op)) : U32(0); + idx = index_value(ctx, op); + ea.addr = ADD(ADD(LOADW(32, ADD(base, S32((st32)op->mem.in_disp))), idx), S32((st32)op->mem.out_disp)); + break; + case M68K_AM_ABSOLUTE_DATA_SHORT: + ea.addr = U32(rz_m68k_op_absolute_address(op, true)); + break; + case M68K_AM_ABSOLUTE_DATA_LONG: + ea.addr = U32(rz_m68k_op_absolute_address(op, false)); + break; + default: + if (rz_m68k_op_is_mem_addr(op) && base_reg != M68K_REG_INVALID) { + ea.addr = ADD(m68k_reg_value(ctx, base_reg), S32((st32)op->mem.disp)); + } else if (rz_m68k_op_is_mem_addr(op)) { + ea.addr = U32(rz_m68k_op_absolute_address(op, false)); + } + break; + } + return ea; +} + +RZ_IPI RzILOpPure *m68k_read_operand(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits, RzILOpEffect **pre, RzILOpEffect **post) { + if (pre) { + *pre = NULL; + } + if (post) { + *post = NULL; + } + rz_return_val_if_fail(ctx && op, NULL); + if (rz_m68k_op_is_mem_addr(op)) { + M68KEA ea = m68k_effective_addr(ctx, op, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return NULL; + } + RzILOpPure *addr = ea.addr; + ea.addr = NULL; + if (pre) { + *pre = ea.pre; + ea.pre = NULL; + } + if (post) { + *post = ea.post; + ea.post = NULL; + } + m68k_ea_fini(&ea); + return LOADW(bits, addr); + } + switch (op->type) { + case M68K_OP_REG: + return m68k_read_reg_sized(ctx, op->reg, bits); + case M68K_OP_IMM: + return UN(bits, op->imm); + case M68K_OP_BR_DISP: + return m68k_branch_disp_target(ctx, op); + case M68K_OP_FP_SINGLE: + return F2BV(F32(op->simm)); + case M68K_OP_FP_DOUBLE: + return F2BV(F64(op->dimm)); + case M68K_OP_INVALID: + default: + return NULL; + } +} + +static RzILOpEffect *write_operand_before_store(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits, + RzILOpEffect *before_store, RzILOpPure *value) { + if (!ctx || !op) { + rz_il_op_effect_free(before_store); + rz_il_op_pure_free(value); + } + rz_return_val_if_fail(ctx && op, NULL); + if (rz_m68k_op_is_mem_addr(op)) { + M68KEA ea = m68k_effective_addr(ctx, op, bits); + if (!ea.addr) { + rz_il_op_effect_free(before_store); + rz_il_op_pure_free(value); + m68k_ea_fini(&ea); + return NULL; + } + RzILOpPure *addr = ea.addr; + RzILOpEffect *pre = ea.pre; + RzILOpEffect *post = ea.post; + ea.addr = NULL; + ea.pre = NULL; + ea.post = NULL; + m68k_ea_fini(&ea); + RzILOpEffect *store = STOREW(addr, UNSIGNED(bits, value)); + if (before_store) { + store = SEQ2(before_store, store); + } + return m68k_effect_pre_post(pre, store, post); + } + switch (op->type) { + case M68K_OP_REG: { + RzILOpEffect *write = m68k_write_reg_sized(ctx, op->reg, bits, value); + if (!write) { + rz_il_op_effect_free(before_store); + return NULL; + } + return before_store ? SEQ2(before_store, write) : write; + } + default: + rz_il_op_effect_free(before_store); + rz_il_op_pure_free(value); + return NULL; + } +} + +/** + * \brief Write \p value to \p op, including EA predecrement/postincrement. + * + * \param ctx Lift context + * \param op Destination operand + * \param bits Access width + * \param value Value to store; consumed on all paths + * \return `pre ; store ; post`. EA side effects are part of the returned effect. + * + * Do not sequence a SETL that the store reads *before* this effect: `pre` runs + * first and must not be assumed to commute with caller locals. Bind such a + * local with m68k_write_operand_local() so it is set after `pre`. + */ +RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand(M68KILCtx *ctx, const cs_m68k_op *op, + ut32 bits, RZ_OWN RzILOpPure *value) { + return write_operand_before_store(ctx, op, bits, NULL, value); +} + +/** + * \brief Bind \p value to \p name after EA pre-effects, then store that local. + * + * \return `pre ; SETL(name, value) ; store(VARL(name)) ; post` + */ +RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand_local(M68KILCtx *ctx, const cs_m68k_op *op, + ut32 bits, const char *name, RZ_OWN RzILOpPure *value) { + if (!name) { + rz_il_op_pure_free(value); + } + rz_return_val_if_fail(name, NULL); + return write_operand_before_store(ctx, op, bits, SETL(name, value), VARL(name)); +} + +RZ_IPI RzILOpEffect *m68k_label(const char *label) { + if (RZ_STR_EQ(label, "m68k_illegal")) { + return SEQ3( + SETL("trap_op", U32((ut32)M68K_TRAP_OP_ILLEGAL)), + SETL("trap_vector", U32((ut32)M68K_VECTOR_ILLEGAL)), + GOTO(label)); + } + if (RZ_STR_EQ(label, "m68k_privilege")) { + return SEQ3( + SETL("trap_op", U32((ut32)M68K_TRAP_OP_PRIVILEGE)), + SETL("trap_vector", U32((ut32)M68K_VECTOR_PRIVILEGE)), + GOTO(label)); + } + return GOTO(label); +} + +RZ_IPI RzILOpEffect *m68k_guard_supervisor(RzILOpEffect *effect) { + return effect ? BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")) : NULL; +} + +RZ_IPI RzILOpEffect *m68k_write_status_reg_unchecked(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value) { + ut32 bits = reg == M68K_REG_CCR ? 8 : 16; + return m68k_write_reg_sized(ctx, reg, bits, value); +} + +RZ_IPI RzILOpEffect *m68k_write_status_reg(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value) { + RzILOpEffect *write = m68k_write_status_reg_unchecked(ctx, reg, value); + if (!write) { + return NULL; + } + return reg == M68K_REG_SR ? BRANCH(m68k_supervisor_mode(), write, m68k_label("m68k_privilege")) : write; +} + +RZ_IPI void m68k_ea_fini(M68KEA *ea) { + if (!ea) { + return; + } + rz_il_op_pure_free(ea->addr); + rz_il_op_effect_free(ea->pre); + rz_il_op_effect_free(ea->post); + *ea = (M68KEA){ 0 }; +} + +/** + * \brief Sequence optional bookends around a required effect: pre, then \p eff, then post. + * + * \param pre Side effects before \p eff, or NULL + * \param eff Required effect + * \param post Side effects after \p eff, or NULL + * \return `pre ; eff ; post`. `pre` and `post` are skipped when NULL. + */ +RZ_IPI RZ_OWN RzILOpEffect *m68k_effect_pre_post(RZ_NULLABLE RZ_OWN RzILOpEffect *pre, + RZ_NONNULL RZ_OWN RzILOpEffect *eff, RZ_NULLABLE RZ_OWN RzILOpEffect *post) { + if (!eff) { + rz_il_op_effect_free(pre); + rz_il_op_effect_free(post); + rz_return_val_if_fail(eff, NULL); + return NULL; + } + if (post) { + eff = SEQ2(eff, post); + } + if (pre) { + eff = SEQ2(pre, eff); + } + return eff; +} + +RZ_IPI void m68k_rw_operand_fini(M68KRWOperand *rw) { + if (!rw) { + return; + } + rz_il_op_effect_free(rw->post); + *rw = (M68KRWOperand){ 0 }; +} + +RZ_IPI void m68k_bitfield_target_fini(M68KBitfieldTarget *target) { + if (!target) { + return; + } + rz_il_op_effect_free(target->post); + *target = (M68KBitfieldTarget){ 0 }; +} + +RZ_IPI RzILOpEffect *m68k_exception(M68KTrapOp trap_op, M68KExceptionVector vector, const char *label) { + return SEQ3( + SETL("trap_op", U32((ut32)trap_op)), + SETL("trap_vector", U32((ut32)vector)), + m68k_label(label)); +} + +RZ_IPI bool m68k_operand_to_local(M68KILCtx *ctx, const char *name, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq) { + rz_return_val_if_fail(ctx && name && op && seq, false); + RzILOpEffect *pre = NULL; + RzILOpEffect *post = NULL; + RzILOpPure *value = m68k_read_operand(ctx, op, bits, &pre, &post); + if (!value) { + return false; + } + RzILOpEffect *set = m68k_effect_pre_post(pre, SETL(name, value), post); + *seq = *seq ? SEQ2(*seq, set) : set; + return true; +} + +RZ_IPI bool m68k_rw_operand_to_local(M68KILCtx *ctx, M68KRWOperand *rw, const char *value_local, const char *addr_local, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq) { + rz_return_val_if_fail(ctx && rw && value_local && addr_local && op && seq, false); + *rw = (M68KRWOperand){ + .op = op, + .addr_local = addr_local, + .post = NULL, + }; + if (rz_m68k_op_is_mem_addr(op)) { + M68KEA ea = m68k_effective_addr(ctx, op, bits); + if (!ea.addr) { + m68k_ea_fini(&ea); + return false; + } + RzILOpEffect *pre = ea.pre; + ea.pre = NULL; + RzILOpPure *addr = ea.addr; + ea.addr = NULL; + RzILOpEffect *load = m68k_effect_pre_post(pre, + SEQ2(SETL(addr_local, UNSIGNED(32, addr)), + SETL(value_local, LOADW(bits, VARL(addr_local)))), + NULL); + *seq = *seq ? SEQ2(*seq, load) : load; + rw->post = ea.post; + ea.post = NULL; + m68k_ea_fini(&ea); + return true; + } + switch (op->type) { + case M68K_OP_REG: { + RzILOpPure *value = m68k_read_reg_sized(ctx, op->reg, bits); + if (!value) { + return false; + } + *seq = *seq ? SEQ2(*seq, SETL(value_local, value)) : SETL(value_local, value); + return true; + } + default: + return false; + } +} + +RZ_IPI RzILOpEffect *m68k_write_rw_operand(M68KILCtx *ctx, const M68KRWOperand *rw, ut32 bits, RzILOpPure *value) { + rz_return_val_if_fail(ctx && rw && rw->op, NULL); + if (rz_m68k_op_is_mem_addr(rw->op)) { + return STOREW(VARL(rw->addr_local), UNSIGNED(bits, value)); + } + switch (rw->op->type) { + case M68K_OP_REG: + return m68k_write_reg_sized(ctx, rw->op->reg, bits, value); + default: + rz_il_op_pure_free(value); + return NULL; + } +} + +#include diff --git a/librz/arch/isa/m68k/m68k_il_helpers.h b/librz/arch/isa/m68k/m68k_il_helpers.h new file mode 100644 index 0000000000..e43172a4ee --- /dev/null +++ b/librz/arch/isa/m68k/m68k_il_helpers.h @@ -0,0 +1,177 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RZ_M68K_IL_HELPERS_H +#define RZ_M68K_IL_HELPERS_H + +#include "m68k/m68k_cs.h" + +#include + +#define M68K_ADDR_BITS 32 + +#define M68K_CCR_C 0 +#define M68K_CCR_V 1 +#define M68K_CCR_Z 2 +#define M68K_CCR_N 3 +#define M68K_CCR_X 4 +#define M68K_SR_M 12 +#define M68K_SR_S 13 +#define M68K_CACR_EUSP 4 + +/* ColdFire MACSR. Integer S/U=0 is signed, S/U=1 is unsigned (CFPRM). + * EMAC EV is bit 0. Bit 4 is R/T (mode), not a result flag. */ +#define M68K_MACSR_EV 0 +#define M68K_MACSR_V 1 +#define M68K_MACSR_Z 2 +#define M68K_MACSR_N 3 +#define M68K_MACSR_RT 4 +#define M68K_MACSR_FI 5 +#define M68K_MACSR_SU 6 +#define M68K_MACSR_OMC 7 +#define M68K_MACSR_PAV0 8 +#define M68K_MACSR_NZVE_MASK ((1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V) | (1u << M68K_MACSR_EV)) +#define M68K_MAC_MASK_RESET 0xffffffffu + +// Capstone 4 and 5 do not expose the bitfield register encoding helpers that +// newer releases provide. Keep the encoding local to the M68K lifter. +#ifndef M68K_BF_REG_FLAG +#define M68K_BF_REG_FLAG 0x80 +#define M68K_BF_IS_REG(v) ((v) & M68K_BF_REG_FLAG) +#define M68K_BF_REG_NUM(v) ((v) & 7) +#endif + +/** Capstone decode context and addresses for one lifted instruction. */ +typedef struct { + csh handle; ///< Capstone handle used for register names + cs_mode mode; ///< Capstone M68K CPU mode + const cs_insn *insn; ///< current instruction + const cs_m68k *m68k; ///< Capstone M68K detail for \p insn + ut64 addr; ///< instruction address + ut64 next_addr; ///< fallthrough address +} M68KILCtx; + +/** Effective-address value and optional access side effects. */ +typedef struct { + RzILOpPure *addr; ///< computed effective address, or NULL on failure + RzILOpEffect *pre; ///< side effects before the access, or NULL + RzILOpEffect *post; ///< side effects after the access, or NULL +} M68KEA; + +/** Read/write operand: the Capstone operand plus optional memory state. */ +typedef struct { + const cs_m68k_op *op; ///< Capstone operand + const char *addr_local; ///< IL local holding the memory address, or NULL + RzILOpEffect *post; ///< post-access side effects, or NULL +} M68KRWOperand; + +/** Bitfield destination: register or memory field plus optional side effects. */ +typedef struct { + const cs_m68k_op *op; ///< Capstone operand + bool memory; ///< true when the field is in memory + const char *addr_local; ///< IL local holding the memory address, or NULL + RzILOpEffect *post; ///< post-access side effects, or NULL +} M68KBitfieldTarget; + +typedef enum { + M68K_CACHE_OP_TOUCH, + M68K_CACHE_OP_INVALIDATE, + M68K_CACHE_OP_PUSH +} M68KCacheOp; + +typedef enum { + M68K_DEBUG_OP_DATA, + M68K_DEBUG_OP_DEBUG +} M68KDebugOp; + +typedef enum { + M68K_SYSTEM_OP_RESET, + M68K_SYSTEM_OP_STOP, + M68K_SYSTEM_OP_LPSTOP, + M68K_SYSTEM_OP_HALT, + M68K_SYSTEM_OP_PULSE +} M68KSystemOp; + +typedef enum { + M68K_CP_OP_NOP, + M68K_CP_OP_BRANCH, + M68K_CP_OP_LOAD, + M68K_CP_OP_STORE +} M68KCoprocessorOp; + +typedef enum { + M68K_TRAP_OP_TRAP, + M68K_TRAP_OP_BKPT, + M68K_TRAP_OP_TRAPCC, + M68K_TRAP_OP_FTRAPCC, + M68K_TRAP_OP_TRAPV, + M68K_TRAP_OP_BGND, + M68K_TRAP_OP_DIV_ZERO, + M68K_TRAP_OP_CHK, + M68K_TRAP_OP_ILLEGAL, + M68K_TRAP_OP_PRIVILEGE, + M68K_TRAP_OP_FORMAT +} M68KTrapOp; + +typedef enum { + M68K_VECTOR_ILLEGAL = 4, + M68K_VECTOR_ZERO_DIVIDE = 5, + M68K_VECTOR_CHK = 6, + M68K_VECTOR_TRAPV_TRAPCC = 7, + M68K_VECTOR_PRIVILEGE = 8, + M68K_VECTOR_FORMAT_ERROR = 14 +} M68KExceptionVector; + +#define M68K_VECTOR_TRAP_BASE 32 + +typedef enum { + M68K_MMU_OP_LOAD, + M68K_MMU_OP_FLUSH, + M68K_MMU_OP_TEST, + M68K_MMU_OP_MOVE, + M68K_MMU_OP_LOAD_PHYSICAL +} M68KMMUOp; + +RZ_IPI RzILOpPure *m68k_reg_value(M68KILCtx *ctx, m68k_reg reg); +RZ_IPI RzILOpPure *m68k_read_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits); +RZ_IPI RzILOpEffect *m68k_set_ccr_from_value(RzILOpPure *new_ccr); +RZ_IPI RzILOpBool *m68k_ccr_bit(ut32 bit); +RZ_IPI RzILOpBool *m68k_supervisor_mode(void); +RZ_IPI RzILOpPure *m68k_ccr_with_flag(RzILOpPure *ccr, ut32 bit, RzILOpBool *value); +RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c, RzILOpBool *x); +RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx_extend(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c); +RZ_IPI RzILOpEffect *m68k_set_flags_div(RzILOpPure *quotient, ut32 bits, RzILOpBool *overflow); +RZ_IPI RzILOpBool *m68k_add_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r); +RZ_IPI RzILOpBool *m68k_sub_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r); +RZ_IPI RzILOpBool *m68k_signed_out_of_range(RzILOpPure *value, ut32 bits); +RZ_IPI RzILOpBool *m68k_addx_overflow(ut32 bits); +RZ_IPI RzILOpBool *m68k_subx_overflow(ut32 bits); +RZ_IPI RzILOpBool *m68k_negx_overflow(ut32 bits); +RZ_IPI RzILOpEffect *m68k_write_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value); +RZ_IPI bool m68k_mode_uses_later_movem_base_value(cs_mode mode); +RZ_IPI bool m68k_mode_has_format_word(cs_mode mode); +RZ_IPI RzILOpBool *m68k_rte_format_valid(cs_mode mode); +RZ_IPI RzILOpPure *m68k_rte_frame_size(cs_mode mode); +RZ_IPI RzILOpPure *m68k_branch_disp_target(const M68KILCtx *ctx, const cs_m68k_op *op); +RZ_IPI RzILOpEffect *m68k_set_addr_reg_delta(M68KILCtx *ctx, m68k_reg reg, st32 delta); +RZ_IPI M68KEA m68k_effective_addr(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits); +RZ_IPI RzILOpPure *m68k_read_operand(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits, RzILOpEffect **pre, RzILOpEffect **post); +RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand(M68KILCtx *ctx, const cs_m68k_op *op, + ut32 bits, RZ_OWN RzILOpPure *value); +RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand_local(M68KILCtx *ctx, const cs_m68k_op *op, + ut32 bits, const char *name, RZ_OWN RzILOpPure *value); +RZ_IPI RzILOpEffect *m68k_label(const char *label); +RZ_IPI RzILOpEffect *m68k_guard_supervisor(RzILOpEffect *effect); +RZ_IPI RzILOpEffect *m68k_write_status_reg_unchecked(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value); +RZ_IPI RzILOpEffect *m68k_write_status_reg(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value); +RZ_IPI void m68k_ea_fini(M68KEA *ea); +RZ_IPI RZ_OWN RzILOpEffect *m68k_effect_pre_post(RZ_NULLABLE RZ_OWN RzILOpEffect *pre, + RZ_NONNULL RZ_OWN RzILOpEffect *eff, RZ_NULLABLE RZ_OWN RzILOpEffect *post); +RZ_IPI void m68k_rw_operand_fini(M68KRWOperand *rw); +RZ_IPI void m68k_bitfield_target_fini(M68KBitfieldTarget *target); +RZ_IPI RzILOpEffect *m68k_exception(M68KTrapOp trap_op, M68KExceptionVector vector, const char *label); +RZ_IPI bool m68k_operand_to_local(M68KILCtx *ctx, const char *name, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq); +RZ_IPI bool m68k_rw_operand_to_local(M68KILCtx *ctx, M68KRWOperand *rw, const char *value_local, const char *addr_local, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq); +RZ_IPI RzILOpEffect *m68k_write_rw_operand(M68KILCtx *ctx, const M68KRWOperand *rw, ut32 bits, RzILOpPure *value); + +#endif // RZ_M68K_IL_HELPERS_H diff --git a/librz/arch/meson.build b/librz/arch/meson.build index f0dac12147..32c6644cd7 100644 --- a/librz/arch/meson.build +++ b/librz/arch/meson.build @@ -249,6 +249,9 @@ arch_isa_sources = [ 'isa/luac/luajit/asm_2.1.c', 'isa/luac/luajit/opcode_2.1.c', 'isa/mcore/mcore.c', + 'isa/m68k/m68k_cs.c', + 'isa/m68k/m68k_il.c', + 'isa/m68k/m68k_il_helpers.c', 'isa/milstd1750/milstd1750_disas.c', 'isa/mips/mips_assembler.c', 'isa/mips/mips_esil.c', diff --git a/librz/arch/p/analysis/analysis_m68k_cs.c b/librz/arch/p/analysis/analysis_m68k_cs.c index bfc9488d00..fc6ebc8aae 100644 --- a/librz/arch/p/analysis/analysis_m68k_cs.c +++ b/librz/arch/p/analysis/analysis_m68k_cs.c @@ -19,6 +19,7 @@ #if CAPSTONE_HAS_M68K #include #include "m68k/m68k_cs.h" +#include "m68k/m68k_il.h" // http://www.mrc.uidaho.edu/mrc/people/jff/digital/M68Kir.html #define OPERAND(x) insn->detail->m68k.operands[x] @@ -32,36 +33,6 @@ static inline ut64 make_64bits_address(ut64 address) { return UT32_MAX & address; } -static inline ut64 m68k_mem_operand_absolute_address(const cs_m68k_op *operand) { - if (!operand || operand->type != M68K_OP_MEM) { - return 0; - } -#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE - return operand->mem.address; -#else - if (operand->imm) { - return operand->imm; - } - return (ut64)(st64)(operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp); -#endif -} - -static inline bool m68k_mem_operand_is_absolute(const cs_m68k_op *operand) { - if (!operand || operand->type != M68K_OP_MEM) { - return false; - } - switch (operand->address_mode) { - case M68K_AM_ABSOLUTE_DATA_SHORT: - case M68K_AM_ABSOLUTE_DATA_LONG: - return true; - default: - break; - } - return operand->mem.base_reg == M68K_REG_INVALID && - operand->mem.index_reg == M68K_REG_INVALID && - operand->mem.in_base_reg == M68K_REG_INVALID; -} - static inline void handle_branch_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 type, int index) { if (m68k->operands[index].type == M68K_OP_BR_DISP) { op->type = type; @@ -85,9 +56,9 @@ static inline void handle_jump_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k } else if (operand->type == M68K_OP_IMM) { op->type = type; op->jump = make_64bits_address(operand->imm); - } else if (m68k_mem_operand_is_absolute(operand)) { + } else if (rz_m68k_op_is_absolute_mem(operand)) { op->type = type; - op->jump = make_64bits_address(m68k_mem_operand_absolute_address(operand)); + op->jump = make_64bits_address(rz_m68k_op_absolute_mem_address(operand)); } else { op->type = (type == RZ_ANALYSIS_OP_TYPE_CALL) ? RZ_ANALYSIS_OP_TYPE_ICALL : RZ_ANALYSIS_OP_TYPE_IJMP; } @@ -95,6 +66,11 @@ static inline void handle_jump_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k op->fail = make_64bits_address(addr + op->size); } +static inline void m68k_opex_add_reg(csh handle, RzStructuredData *operand, m68k_reg reg) { + rz_structured_data_map_add_string(operand, "type", "reg"); + rz_structured_data_map_add_string(operand, "value", cs_reg_name(handle, reg)); +} + static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) { if (!insn->detail) { return NULL; @@ -122,9 +98,15 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) { } #endif switch (op->type) { + case M68K_OP_INVALID: + rz_structured_data_map_add_string(operand, "type", "invalid"); + break; case M68K_OP_REG: - rz_structured_data_map_add_string(operand, "type", "reg"); - rz_structured_data_map_add_string(operand, "value", cs_reg_name(handle, op->reg)); + if (op->reg == M68K_REG_INVALID) { + rz_structured_data_map_add_string(operand, "type", "invalid"); + } else { + m68k_opex_add_reg(handle, operand, op->reg); + } break; case M68K_OP_REG_PAIR: rz_structured_data_map_add_string(operand, "type", "reg_pair"); @@ -143,6 +125,19 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) { rz_structured_data_map_add_string(operand, "type", "fp_double"); rz_structured_data_map_add_double(operand, "value", op->dimm); break; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + case M68K_OP_FP_EXTENDED: + rz_structured_data_map_add_string(operand, "type", "fp_extended"); + rz_structured_data_map_add_unsigned(operand, "sign_exp", op->fp_extended.sign_exp, true); + rz_structured_data_map_add_unsigned(operand, "reserved", op->fp_extended.reserved, true); + rz_structured_data_map_add_unsigned(operand, "significand", op->fp_extended.significand, true); + break; + case M68K_OP_FP_PACKED: + rz_structured_data_map_add_string(operand, "type", "fp_packed"); + rz_structured_data_map_add_unsigned(operand, "header", op->fp_packed.header, true); + rz_structured_data_map_add_unsigned(operand, "fraction", op->fp_packed.fraction, true); + break; +#endif case M68K_OP_REG_BITS: rz_structured_data_map_add_string(operand, "type", "reg_bits"); rz_structured_data_map_add_unsigned(operand, "value", op->register_bits, true); @@ -164,8 +159,8 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) { rz_structured_data_map_add_string(operand, "base_reg", cs_reg_name(handle, op->mem.base_reg)); } #ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE - if (m68k_mem_operand_is_absolute(op)) { - rz_structured_data_map_add_unsigned(operand, "address", op->mem.address, false); + if (rz_m68k_op_is_absolute_mem(op)) { + rz_structured_data_map_add_unsigned(operand, "address", rz_m68k_op_absolute_mem_address(op), false); } #endif if (op->mem.index_reg != M68K_REG_INVALID) { @@ -193,6 +188,10 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) { break; } } + if (rz_m68k_fpu_insn_needs_hidden_dst(insn)) { + RzStructuredData *operand = rz_structured_data_array_add_map(operands); + m68k_opex_add_reg(handle, operand, rz_m68k_fpu_insn_extension_dst_reg(insn)); + } return root; } @@ -221,6 +220,10 @@ static inline int m68k_op_memref(const cs_m68k *m68k) { return 8; case M68K_FPU_SIZE_EXTENDED: return 12; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + case M68K_FPU_SIZE_PACKED: + return 12; +#endif default: return 0; } @@ -257,6 +260,9 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const return NULL; } break; + case M68K_OP_INVALID: + rz_analysis_value_free(value); + return NULL; case M68K_OP_IMM: value->type = RZ_ANALYSIS_VAL_IMM; value->imm = (st64)operand->imm; @@ -275,9 +281,9 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const value->regdelta = m68k_reg_get(a, handle, operand->mem.index_reg); value->mul = operand->mem.scale; value->delta = operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp; - if (m68k_mem_operand_is_absolute(operand)) { + if (rz_m68k_op_is_absolute_mem(operand)) { value->absolute = true; - value->base = m68k_mem_operand_absolute_address(operand); + value->base = rz_m68k_op_absolute_mem_address(operand); value->delta = 0; } else if (!value->reg && !value->regdelta && value->delta) { value->absolute = true; @@ -301,6 +307,21 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const return value; } +static RzAnalysisValue *m68k_value_from_reg(RzAnalysis *a, csh handle, m68k_reg reg, RzAnalysisValueAccess access) { + RzAnalysisValue *value = rz_analysis_value_new(); + if (!value) { + return NULL; + } + value->access = access; + value->type = RZ_ANALYSIS_VAL_REG; + value->reg = m68k_reg_get(a, handle, reg); + if (!value->reg) { + rz_analysis_value_free(value); + return NULL; + } + return value; +} + static inline void m68k_note_memref(RzAnalysisOp *op, RzAnalysisValue *value) { if (value && value->type == RZ_ANALYSIS_VAL_MEM && value->memref > 0) { op->refptr = value->memref; @@ -349,12 +370,76 @@ static void m68k_set_dst_operand(RzAnalysis *a, RzAnalysisOp *op, csh handle, co m68k_set_dst_value(op, value); } +static void m68k_fill_fpu_hidden_dst(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_insn *insn) { + rz_return_if_fail(a && op && insn && insn->detail); + if (!rz_m68k_fpu_insn_needs_hidden_dst(insn)) { + return; + } + + const cs_m68k *m68k = &insn->detail->m68k; + for (int i = 0; i < m68k->op_count; i++) { + m68k_add_src_operand(a, op, handle, m68k, i); + } + + m68k_reg dst_reg = rz_m68k_fpu_insn_extension_dst_reg(insn); + if ((op->type & RZ_ANALYSIS_OP_TYPE_MASK) == RZ_ANALYSIS_OP_TYPE_CMP) { + m68k_add_src_value(op, m68k_value_from_reg(a, handle, dst_reg, RZ_ANALYSIS_ACC_R)); + return; + } + + RzAnalysisValueAccess access = RZ_ANALYSIS_ACC_W; + switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) { + case RZ_ANALYSIS_OP_TYPE_ADD: + case RZ_ANALYSIS_OP_TYPE_SUB: + case RZ_ANALYSIS_OP_TYPE_MUL: + case RZ_ANALYSIS_OP_TYPE_DIV: + case RZ_ANALYSIS_OP_TYPE_MOD: + access |= RZ_ANALYSIS_ACC_R; + break; + default: + break; + } + m68k_set_dst_value(op, m68k_value_from_reg(a, handle, dst_reg, access)); +} + +static void m68k_fill_fpu_sincos(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_insn *insn) { + rz_return_if_fail(a && op && insn && insn->detail); + const cs_m68k *m68k = &insn->detail->m68k; + if (m68k->op_count > 0) { + m68k_add_src_operand(a, op, handle, m68k, 0); + } + if (m68k->op_count > 1 && m68k->operands[1].type == M68K_OP_REG_PAIR) { + m68k_set_dst_value(op, m68k_value_from_reg(a, handle, m68k->operands[1].reg_pair.reg_1, RZ_ANALYSIS_ACC_W)); + return; + } + if (m68k->op_count > 2) { + m68k_set_dst_operand(a, op, handle, m68k, 2, RZ_ANALYSIS_ACC_W); + return; + } + + m68k_reg dst_reg = rz_m68k_fpu_insn_extension_dst_reg(insn); + if (dst_reg == M68K_REG_INVALID) { + return; + } + m68k_set_dst_value(op, m68k_value_from_reg(a, handle, dst_reg, RZ_ANALYSIS_ACC_W)); +} + static void m68k_fill_srcs_before_dst(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool dst_is_read) { if (!m68k || m68k->op_count < 1) { return; } int dst_index = m68k->op_count - 1; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + if (m68k->op_count == 3 && m68k->op_size.type == M68K_SIZE_TYPE_FPU && + m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED && m68k->operands[1].type == M68K_OP_MEM) { + dst_index = 1; + m68k_add_src_operand(a, op, handle, m68k, 0); + m68k_add_src_operand(a, op, handle, m68k, 2); + m68k_set_dst_operand(a, op, handle, m68k, dst_index, RZ_ANALYSIS_ACC_W); + return; + } +#endif for (int i = 0; i < dst_index; i++) { m68k_add_src_operand(a, op, handle, m68k, i); } @@ -405,6 +490,60 @@ static void m68k_fill_indirect_target(RzAnalysis *a, RzAnalysisOp *op, csh handl m68k_add_src_operand(a, op, handle, m68k, 0); } +static void m68k_fill_callm(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) { + rz_return_if_fail(a && op && m68k); + if (m68k->op_count < 2) { + return; + } + m68k_add_src_operand(a, op, handle, m68k, 0); + m68k_add_src_operand(a, op, handle, m68k, 1); +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static void m68k_fill_strldsr(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) { + rz_return_if_fail(a && op && m68k); + if (m68k->op_count < 1) { + return; + } + m68k_add_src_operand(a, op, handle, m68k, 0); + m68k_add_src_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_R)); + m68k_set_dst_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_W)); +} + +static void m68k_fill_coprocessor_transfer(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool store) { + rz_return_if_fail(a && op && m68k); + if (m68k->op_count < (store ? 2 : 1)) { + return; + } + if (store) { + m68k_set_dst_operand(a, op, handle, m68k, 1, RZ_ANALYSIS_ACC_W); + } else { + m68k_add_src_operand(a, op, handle, m68k, 0); + } +} +#endif + +static void m68k_fill_fpu_state_transfer(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool restore) { + rz_return_if_fail(a && op && m68k); + if (m68k->op_count < 1) { + return; + } + if (restore) { + m68k_add_src_operand(a, op, handle, m68k, 0); + } else { + m68k_set_dst_operand(a, op, handle, m68k, 0, RZ_ANALYSIS_ACC_W); + } +} + +static void m68k_fill_scc(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) { + rz_return_if_fail(a && op && m68k); + if (m68k->op_count < 1) { + return; + } + m68k_add_src_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_R)); + m68k_set_dst_operand(a, op, handle, m68k, 0, RZ_ANALYSIS_ACC_W); +} + static void m68k_fill_fpu_unknown(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) { if (!m68k || m68k->op_count < 1) { return; @@ -422,7 +561,14 @@ static void m68k_set_move_type(RzAnalysisOp *op, const cs_m68k *m68k) { return; } const cs_m68k_op *src = &m68k->operands[0]; - const cs_m68k_op *dst = &m68k->operands[m68k->op_count - 1]; + int dst_index = m68k->op_count - 1; +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + if (m68k->op_count == 3 && m68k->op_size.type == M68K_SIZE_TYPE_FPU && + m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED) { + dst_index = 1; + } +#endif + const cs_m68k_op *dst = &m68k->operands[dst_index]; if (dst->type == M68K_OP_MEM) { op->type = RZ_ANALYSIS_OP_TYPE_STORE; } else if (src->type == M68K_OP_MEM) { @@ -471,7 +617,7 @@ static void m68k_set_opdir(RzAnalysisOp *op) { } } -static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, unsigned int insn_id) { +static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 insn_id) { op->family = RZ_ANALYSIS_OP_FAMILY_FPU; switch (insn_id) { case M68K_INS_FMOVE: @@ -495,6 +641,7 @@ static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m6 case M68K_INS_FSMUL: case M68K_INS_FDMUL: case M68K_INS_FSGLMUL: + case M68K_INS_FSCALE: op->type = RZ_ANALYSIS_OP_TYPE_MUL; break; case M68K_INS_FDIV: @@ -525,6 +672,32 @@ static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m6 case M68K_INS_FINTRZ: op->type = RZ_ANALYSIS_OP_TYPE_CAST; break; + case M68K_INS_FACOS: + case M68K_INS_FASIN: + case M68K_INS_FATAN: + case M68K_INS_FATANH: + case M68K_INS_FCOS: + case M68K_INS_FCOSH: + case M68K_INS_FETOX: + case M68K_INS_FETOXM1: + case M68K_INS_FGETEXP: + case M68K_INS_FGETMAN: + case M68K_INS_FLOG10: + case M68K_INS_FLOG2: + case M68K_INS_FLOGN: + case M68K_INS_FLOGNP1: + case M68K_INS_FSIN: + case M68K_INS_FSINCOS: + case M68K_INS_FSINH: + case M68K_INS_FSQRT: + case M68K_INS_FSSQRT: + case M68K_INS_FDSQRT: + case M68K_INS_FTAN: + case M68K_INS_FTANH: + case M68K_INS_FTENTOX: + case M68K_INS_FTWOTOX: + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; case M68K_INS_FNOP: op->type = RZ_ANALYSIS_OP_TYPE_NOP; break; @@ -713,11 +886,63 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins case M68K_INS_SATS: m68k_fill_unary_rw(a, op, handle, m68k); return; + case M68K_INS_STRLDSR: + m68k_fill_strldsr(a, op, handle, m68k); + return; + case M68K_INS_CP0LD: + case M68K_INS_CP1LD: + m68k_fill_coprocessor_transfer(a, op, handle, m68k, false); + return; + case M68K_INS_CP0ST: + case M68K_INS_CP1ST: + m68k_fill_coprocessor_transfer(a, op, handle, m68k, true); + return; #endif + case M68K_INS_FSAVE: + m68k_fill_fpu_state_transfer(a, op, handle, m68k, false); + return; + case M68K_INS_FRESTORE: + m68k_fill_fpu_state_transfer(a, op, handle, m68k, true); + return; + case M68K_INS_CALLM: + m68k_fill_callm(a, op, handle, m68k); + return; + case M68K_INS_ST: + case M68K_INS_SF: + case M68K_INS_SHI: + case M68K_INS_SLS: + case M68K_INS_SCC: + case M68K_INS_SHS: + case M68K_INS_SCS: + case M68K_INS_SLO: + case M68K_INS_SNE: + case M68K_INS_SEQ: + case M68K_INS_SVC: + case M68K_INS_SVS: + case M68K_INS_SPL: + case M68K_INS_SMI: + case M68K_INS_SGE: + case M68K_INS_SLT: + case M68K_INS_SGT: + case M68K_INS_SLE: + m68k_fill_scc(a, op, handle, m68k); + return; + case M68K_INS_FSINCOS: + m68k_fill_fpu_sincos(a, op, handle, insn); + return; default: break; } + if (rz_m68k_fpu_insn_needs_hidden_dst(insn)) { + m68k_fill_fpu_hidden_dst(a, op, handle, insn); + return; + } + if (rz_m68k_fpu_insn_has_data_dst(insn->id) && rz_m68k_fpu_insn_single_op_is_complete(insn)) { + m68k_fill_unary_rw(a, op, handle, m68k); + return; + } + switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) { case RZ_ANALYSIS_OP_TYPE_LOAD: case RZ_ANALYSIS_OP_TYPE_MOV: @@ -756,6 +981,9 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins case RZ_ANALYSIS_OP_TYPE_CMP: m68k_fill_all_srcs(a, op, handle, m68k); break; + case RZ_ANALYSIS_OP_TYPE_TRAP: + m68k_fill_all_srcs(a, op, handle, m68k); + break; case RZ_ANALYSIS_OP_TYPE_UJMP: case RZ_ANALYSIS_OP_TYPE_UCALL: m68k_fill_indirect_target(a, op, handle, m68k); @@ -771,8 +999,9 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { M68KContext *ctx = (M68KContext *)a->plugin_data; - int n, ret, opsize = -1; - cs_insn *insn; + int opsize = -1; + size_t n = 0; + cs_insn *insn = NULL; cs_m68k *m68k; cs_detail *detail; @@ -784,26 +1013,20 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 ctx->omode = -1; ctx->obits = a->bits; } - op->size = 4; + if (len < M68K_MIN_OP_SIZE) { + return -1; + } if (ctx->handle == 0) { - ret = cs_open(CS_ARCH_M68K, mode, &ctx->handle); - if (ret != CS_ERR_OK) { + if (cs_open(CS_ARCH_M68K, mode, &ctx->handle) != CS_ERR_OK) { goto fin; } ctx->omode = mode; cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON); } n = cs_disasm(ctx->handle, (ut8 *)buf, len, addr, 1, &insn); - if (n < 1 || insn->size < 1) { + if (n < 1 || !insn || insn->size < 1) { op->type = RZ_ANALYSIS_OP_TYPE_ILL; - op->size = 2; - opsize = -1; - goto beach; - } - if (!memcmp(buf, "\xff\xff", RZ_MIN(len, 2))) { - op->type = RZ_ANALYSIS_OP_TYPE_ILL; - op->size = 2; - opsize = -1; + opsize = op->size = M68K_MIN_OP_SIZE; goto beach; } detail = insn->detail; @@ -813,9 +1036,16 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 if (mask & RZ_ANALYSIS_OP_MASK_OPEX) { op->opex = mk68_opex(ctx->handle, insn); } + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + op->il_op = rz_m68k_cs_get_il_op(ctx->handle, mode, insn, addr); + } switch (insn->id) { case M68K_INS_INVALID: op->type = RZ_ANALYSIS_OP_TYPE_ILL; + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + rz_il_op_effect_free(op->il_op); + op->il_op = NULL; + } break; case M68K_INS_ADD: case M68K_INS_ADDA: @@ -832,9 +1062,13 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 op->type = RZ_ANALYSIS_OP_TYPE_SHL; break; case M68K_INS_ASR: - op->type = RZ_ANALYSIS_OP_TYPE_SHR; + op->type = RZ_ANALYSIS_OP_TYPE_SAR; break; case M68K_INS_ABCD: + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case M68K_INS_BKPT: + op->type = RZ_ANALYSIS_OP_TYPE_TRAP; break; case M68K_INS_BHS: case M68K_INS_BLO: @@ -872,14 +1106,20 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_BFINS: case M68K_INS_BFSET: case M68K_INS_BFTST: - case M68K_INS_BKPT: - case M68K_INS_CALLM: case M68K_INS_CAS: case M68K_INS_CAS2: case M68K_INS_CHK: case M68K_INS_CHK2: // TODO: break; + case M68K_INS_CALLM: + if (m68k->op_count > 1) { + op->type = RZ_ANALYSIS_OP_TYPE_ICALL; + op->fail = make_64bits_address(addr + op->size); + } else { + op->type = RZ_ANALYSIS_OP_TYPE_UCALL; + } + break; case M68K_INS_CLR: op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; @@ -1125,9 +1365,6 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_FTWOTOX: m68k_handle_fpu_instruction(op, addr, m68k, insn->id); break; - case M68K_INS_HALT: - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - break; case M68K_INS_ILLEGAL: op->type = RZ_ANALYSIS_OP_TYPE_ILL; break; @@ -1137,9 +1374,6 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_JSR: handle_jump_instruction(op, addr, m68k, RZ_ANALYSIS_OP_TYPE_CALL); break; - case M68K_INS_LPSTOP: - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - break; case M68K_INS_LSL: op->type = RZ_ANALYSIS_OP_TYPE_SHL; break; @@ -1165,6 +1399,11 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_MOVE16: m68k_set_move_type(op, m68k); break; + case M68K_INS_PMOVE: + case M68K_INS_PMOVEFD: + op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; + m68k_set_move_type(op, m68k); + break; #ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE case M68K_INS_MOV3Q: case M68K_INS_MOVCLR: @@ -1179,7 +1418,11 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 m68k_set_cast_type(op, m68k); break; case M68K_INS_MAC: + case M68K_INS_MAAAC: + case M68K_INS_MASAC: + case M68K_INS_MSAAC: case M68K_INS_MSAC: + case M68K_INS_MSSAC: op->type = RZ_ANALYSIS_OP_TYPE_MUL; break; case M68K_INS_SATS: @@ -1196,10 +1439,16 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 op->type = RZ_ANALYSIS_OP_TYPE_SYNC; break; case M68K_INS_STRLDSR: + op->stackop = RZ_ANALYSIS_STACK_INC; + op->stackptr = -4; + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; case M68K_INS_WDDATA: case M68K_INS_WDEBUG: op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; +#endif +#ifdef RZ_CAPSTONE_HAS_M68K_CPU32 case M68K_INS_TBLS: case M68K_INS_TBLU: case M68K_INS_TBLSN: @@ -1207,6 +1456,10 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 m68k_set_move_type(op, m68k); break; case M68K_INS_BGND: + op->type = RZ_ANALYSIS_OP_TYPE_TRAP; + break; +#endif +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE case M68K_INS_TPF: op->type = RZ_ANALYSIS_OP_TYPE_TRAP; break; @@ -1255,10 +1508,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_PLOADW: case M68K_INS_PLPAR: case M68K_INS_PLPAW: - case M68K_INS_PMOVE: - case M68K_INS_PMOVEFD: case M68K_INS_PTESTR: case M68K_INS_PTESTW: + case M68K_INS_HALT: case M68K_INS_PULSE: case M68K_INS_RESET: break; @@ -1283,6 +1535,8 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 op->type = RZ_ANALYSIS_OP_TYPE_RET; break; case M68K_INS_SBCD: + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + break; case M68K_INS_ST: case M68K_INS_SF: case M68K_INS_SHI: @@ -1301,6 +1555,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case M68K_INS_SLT: case M68K_INS_SGT: case M68K_INS_SLE: + op->type = RZ_ANALYSIS_OP_TYPE_CMOV; + break; + case M68K_INS_LPSTOP: case M68K_INS_STOP: break; case M68K_INS_SUB: @@ -1314,6 +1571,7 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; case M68K_INS_TAS: + op->type = RZ_ANALYSIS_OP_TYPE_OR; break; case M68K_INS_TRAP: case M68K_INS_TRAPV: @@ -1355,7 +1613,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 op_fillval(a, op, ctx->handle, insn); } beach: - cs_free(insn, n); + if (insn) { + cs_free(insn, n); + } // cs_close (&handle); fin: return opsize; @@ -1391,21 +1651,12 @@ static char *m68k_get_reg_profile(RzAnalysis *analysis) { "gpr a7 .32 60 0\n" "gpr pc .32 72 0\n" "gpr ccr .8 71 0\n" // subset of the SR, available from any mode - "gpr fp0 .32 80 0\n" // FPU register 0, 96bits to write and read max - "gpr fp1 .32 84 0\n" // FPU register 1, 96bits to write and read max - "gpr fp2 .32 88 0\n" // FPU register 2, 96bits to write and read max - "gpr fp3 .32 92 0\n" // FPU register 3, 96bits to write and read max - "gpr fp4 .32 96 0\n" // FPU register 4, 96bits to write and read max - "gpr fp5 .32 100 0\n" // FPU register 5, 96bits to write and read max - "gpr fp6 .32 104 0\n" // FPU register 6, 96bits to write and read max - "gpr fp7 .32 108 0\n" // FPU register 7, 96bits to write and read max "gpr fpcr .32 112 0\n" "gpr fpsr .32 116 0\n" "gpr fpiar .32 120 0\n" "gpr sr .16 70 0\n" // only available for read and write access during supervisor mode "gpr sfc .32 124 0\n" // source function code register "gpr dfc .32 128 0\n" // destination function code register - "gpr usp .32 60 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0 "gpr vbr .32 132 0\n" // vector base register, this is a Address pointer "gpr cacr .32 136 0\n" // cache control register, implementation specific "gpr caar .32 140 0\n" // cache address register, 68020, 68EC020, 68030 and 68EC030 only. @@ -1418,19 +1669,29 @@ static char *m68k_get_reg_profile(RzAnalysis *analysis) { "gpr dtt1 .32 168 0\n" // in 68EC040 this is DACR1 "gpr mmusr .32 172 0\n" "gpr urp .32 176 0\n" - "gpr srp .32 180 0\n" - "gpr tt0 .32 184 0\n" - "gpr tt1 .32 188 0\n" - "gpr crp .32 192 0\n" - "gpr acc .32 196 0\n" - "gpr acc0 .32 200 0\n" - "gpr acc1 .32 204 0\n" - "gpr acc2 .32 208 0\n" - "gpr acc3 .32 212 0\n" - "gpr accext01 .32 216 0\n" - "gpr accext23 .32 220 0\n" - "gpr macsr .32 224 0\n" - "gpr mask .32 228 0\n"; + "gpr srp .64 180 0\n" + "gpr tt0 .32 188 0\n" + "gpr tt1 .32 192 0\n" + "gpr crp .64 196 0\n" + "gpr acc .32 204 0\n" + "gpr acc0 .32 208 0\n" + "gpr acc1 .32 212 0\n" + "gpr acc2 .32 216 0\n" + "gpr acc3 .32 220 0\n" + "gpr accext01 .32 224 0\n" + "gpr accext23 .32 228 0\n" + "gpr macsr .32 232 0\n" + "gpr mask .32 236 0\n" + "gpr usp .32 240 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0 + "fpu fp0 .80 244 0\n" // FPU data register 0, 80-bit extended precision + "fpu fp1 .80 254 0\n" // FPU data register 1, 80-bit extended precision + "fpu fp2 .80 264 0\n" // FPU data register 2, 80-bit extended precision + "fpu fp3 .80 274 0\n" // FPU data register 3, 80-bit extended precision + "fpu fp4 .80 284 0\n" // FPU data register 4, 80-bit extended precision + "fpu fp5 .80 294 0\n" // FPU data register 5, 80-bit extended precision + "fpu fp6 .80 304 0\n" // FPU data register 6, 80-bit extended precision + "fpu fp7 .80 314 0\n" // FPU data register 7, 80-bit extended precision + "gpr cp_external_data .32 324 0\n"; return rz_str_dup(p); } @@ -1446,9 +1707,9 @@ static bool m68k_fini(void *user) { static int m68k_archinfo(RzAnalysis *a, RzAnalysisInfoType query) { switch (query) { case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: - return 2; + return M68K_MIN_OP_SIZE; case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: - return M68K_LONGEST_INSTRUCTION; + return M68K_MAX_OP_SIZE; case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2; case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: @@ -1472,6 +1733,7 @@ RzAnalysisPlugin rz_analysis_plugin_m68k_cs = { .init = m68k_init, .fini = m68k_fini, .archinfo = m68k_archinfo, + .il_config = rz_m68k_cs_il_config, }; #else diff --git a/librz/arch/p/asm/asm_m68k_cs.c b/librz/arch/p/asm/asm_m68k_cs.c index 33a88d26c5..dcd9227a7b 100644 --- a/librz/arch/p/asm/asm_m68k_cs.c +++ b/librz/arch/p/asm/asm_m68k_cs.c @@ -11,28 +11,34 @@ CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(m68k_asm); +static int m68k_set_invalid(RzAsmOp *op, int size) { + op->size = size; + rz_asm_op_set_asm(op, "invalid"); + return size; +} + static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { - if (!buf) { + if (!buf || !op) { return -1; } CapstoneContext *ctx = (CapstoneContext *)a->plugin_data; char *buf_asm = NULL; cs_insn *insn = NULL; - int ret = 0, n = 0; + size_t count = 0; + int op_size = -1; cs_mode mode = rz_m68k_cs_mode(a->cpu); - if (op) { - op->size = 4; - } if (mode != ctx->omode) { cs_close(&ctx->handle); ctx->handle = 0; ctx->omode = -1; } + if (len < M68K_MIN_OP_SIZE) { + goto beach; + } + if (!ctx->handle) { - ret = cs_open(CS_ARCH_M68K, mode, &ctx->handle); - if (ret) { - ret = -1; + if (cs_open(CS_ARCH_M68K, mode, &ctx->handle) != CS_ERR_OK) { goto beach; } ctx->omode = mode; @@ -43,44 +49,30 @@ static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_OFF); } - if (len > M68K_LONGEST_INSTRUCTION) { - len = M68K_LONGEST_INSTRUCTION; - } - - n = cs_disasm(ctx->handle, buf, len, a->pc, 1, &insn); - if (n < 1) { - ret = -1; + count = cs_disasm(ctx->handle, buf, len, a->pc, 1, &insn); + if (count < 1 || !insn) { + op_size = m68k_set_invalid(op, M68K_MIN_OP_SIZE); goto beach; } - if (op) { - op->size = 0; - } - if (insn->size < 1) { - ret = -1; + if (insn->id == M68K_INS_INVALID || insn->size < 1) { + op_size = m68k_set_invalid(op, insn->size > 0 ? insn->size : M68K_MIN_OP_SIZE); goto beach; } - if (op && !op->size) { - op->size = insn->size; - buf_asm = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str); - } - if (op && buf_asm) { - buf_asm = rz_str_replace(buf_asm, "$", "0x", true); - if (buf_asm) { - rz_str_replace_char(buf_asm, '#', 0); - rz_asm_op_set_asm(op, buf_asm); - } - } - cs_free(insn, n); -beach: - - if (op && buf_asm) { - if (!strncmp(buf_asm, "dc.w", 4)) { - rz_asm_op_set_asm(op, "invalid"); - } - ret = op->size; + op_size = insn->size; + buf_asm = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str); + if (!buf_asm) { + goto beach; } + buf_asm = rz_str_replace(buf_asm, "$", "0x", true); + rz_str_replace_char(buf_asm, '#', '\0'); + rz_asm_op_set_asm(op, buf_asm); free(buf_asm); - return ret; +beach: + op->size = op_size; + if (insn) { + cs_free(insn, count); + } + return op_size; } static char **m68k_cpu_descriptions() { diff --git a/librz/core/cfile.c b/librz/core/cfile.c index b7d1c9e5bb..ff59089a23 100644 --- a/librz/core/cfile.c +++ b/librz/core/cfile.c @@ -103,6 +103,12 @@ static void loadGP(RzCore *core) { } } +static void sync_m68k_core_usp(RzCore *core, RzReg *reg) { + if (rz_asm_is_arch(core->rasm, "m68k")) { + rz_reg_setv(reg, "usp", rz_reg_getv(reg, "a7")); + } +} + static RZ_OWN RzPVector /**/ *__save_old_sections(RzCore *core) { RzBinObject *obj = rz_bin_cur_object(core->bin); const RzPVector *sections = obj ? rz_bin_object_get_sections_all(obj) : NULL; @@ -1161,12 +1167,15 @@ RZ_API bool rz_core_bin_load(RZ_NONNULL RzCore *r, RZ_NULLABLE const char *filen if (rz_reg_arena_set_bytes(rreg, binfile->o->regstate)) { RZ_LOG_WARN("Setting up coredump: Problem while setting the registers\n"); } else { + sync_m68k_core_usp(r, rreg); RZ_LOG_INFO("Setting up coredump: Registers have been set\n"); } if (!RZ_STR_ISEMPTY(rreg->reg_profile_str)) { rz_reg_set_profile_string(r->dbg->reg, rreg->reg_profile_str); if (binfile->o->regstate && rz_reg_arena_set_bytes(r->dbg->reg, binfile->o->regstate)) { RZ_LOG_WARN("Setting up coredump: Problem while setting debug registers\n"); + } else { + sync_m68k_core_usp(r, r->dbg->reg); } } } diff --git a/meson.build b/meson.build index a7767e45ca..d641e1d893 100644 --- a/meson.build +++ b/meson.build @@ -245,6 +245,26 @@ if has_capstone_m68k_coldfire add_project_arguments(['-DRZ_CAPSTONE_HAS_M68K_COLDFIRE'], language: 'c') endif +has_capstone_m68k_fp_formats = cc.compiles(''' +#include +#include +int main(void) { + m68k_op_fp_extended extended = { 0 }; + m68k_op_fp_packed packed = { 0 }; + m68k_op_type extended_type = M68K_OP_FP_EXTENDED; + m68k_op_type packed_type = M68K_OP_FP_PACKED; + m68k_fpu_size packed_size = M68K_FPU_SIZE_PACKED; + return extended.sign_exp + packed.header + extended_type + packed_type + packed_size; +} +''', + dependencies: capstone_check_deps, + include_directories: capstone_check_includes, + name: 'Capstone has M68K extended and packed FP operand formats' +) +if has_capstone_m68k_fp_formats + add_project_arguments(['-DRZ_CAPSTONE_HAS_M68K_FP_FORMATS'], language: 'c') +endif + # Handle PCRE2 cpu_jit_supported = [ 'aarch64', 'arm', 'mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64', 's390x', 'x86', 'x86_64' ] pcre2_jit_supported = target_machine.cpu_family() in cpu_jit_supported and cc.get_id() != 'tcc' and target_machine.system() not in ['darwin', 'serenity'] diff --git a/test/db/analysis/m68k b/test/db/analysis/m68k index 935680cb54..98ebc1845c 100644 --- a/test/db/analysis/m68k +++ b/test/db/analysis/m68k @@ -115,6 +115,50 @@ goto 0x312 EOF RUN +NAME=M68K FPU analysis has no RzIL +FILE=malloc://16 +CMDS=<> (var src) (bv 8 0x8) false))) (storew 0 (+ (var addr) (bv 32 0x2)) (cast 8 false (var src)))) +d "lea.l 0x4(a0), a0" 41e80004 0x0 (set a0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x4))))) +d "pea.l -0x4(a0)" 4868fffc 0x0 (seq (set push_value (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfffffffc)))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "add.w d1, d0" d041 0x0 (seq (set src (cast 16 false (var d1))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.l d0, (a0)+" d198 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x1, d0" 06400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x1, d0" 5240 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "adda.l d0, a0" d1c0 0x0 (seq (set src (var d0)) (set dst (var a0)) (set res (+ (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "sub.w d1, d0" 9041 0x0 (seq (set src (cast 16 false (var d1))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x1, d0" 04400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x2, d0" 5540 0x0 (seq (set src (bv 16 0x2)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "suba.l d0, a0" 91c0 0x0 (seq (set src (var d0)) (set dst (var a0)) (set res (- (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "cmp.w d1, d0" b041 0x0 (seq (set src (cast 16 false (var d1))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0x1, d0" 0c400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l d0, a0" b1c0 0x0 (seq (set src (var d0)) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpm.w (a0)+, (a0)+" b148 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d1, d0" c041 0x0 (seq (set src (cast 16 false (var d1))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x1, d0" 02400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d1, d0" 8041 0x0 (seq (set src (cast 16 false (var d1))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x1, d0" 00400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, d1" b141 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d1))) (set res (^ (var dst) (var src))) (set d1 (| (& (var d1) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x1, d0" 0a400001 0x0 (seq (set src (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w d0" 4240 0x0 (seq (set res (bv 16 0x0)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l (a0)+" 4298 0x0 (seq (set res (bv 32 0x0)) (storew 0 (var a0) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w d0" 4a40 0x0 (seq (set dst (cast 16 false (var d0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w d0" 4640 0x0 (seq (set dst (cast 16 false (var d0))) (set res (~ (var dst))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l -(a0)" 46a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "neg.w d0" 4440 0x0 (seq (set dst (cast 16 false (var d0))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w d0" 4040 0x0 (seq (set dst (cast 16 false (var d0))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 16 0x1) (bv 16 0x0))) (set res (- (- (bv 16 0x0) (var dst)) (var borrow))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! 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(ule (var count8) (bv 8 0xa))) (== (var count8) (bv 8 0xa))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x5) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xb))) (== (var count8) (bv 8 0xb))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x4) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xc))) (== (var count8) (bv 8 0xc))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x3) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xd))) (== (var count8) (bv 8 0xd))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x2) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xe))) (== (var count8) (bv 8 0xe))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xf))) (== (var count8) (bv 8 0xf))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x0) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite false (bv 1 0x1) (bv 1 0x0)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x1, d0" e348 0x0 (seq (set count (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w 0x1, d0" e240 0x0 (seq (set count (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x1, d0" e248 0x0 (seq (set count (bv 16 0x1)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "bra.b 0x4" 6002 0x0 (jmp (bv 32 0x4)) +d "bsr.b 0x4" 6102 0x0 (seq (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x4))) +d "bhi.b 0x4" 6202 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (jmp (bv 32 0x4)) empty) +d "bls.b 0x4" 6302 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x4)) empty) +d "bcc.b 0x4" 6402 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (jmp (bv 32 0x4)) empty) +d "bcs.b 0x4" 6502 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (jmp (bv 32 0x4)) empty) +d "bne.b 0x4" 6602 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x4)) empty) +d "beq.b 0x4" 6702 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (jmp (bv 32 0x4)) empty) +d "bvc.b 0x4" 6802 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (jmp (bv 32 0x4)) empty) +d "bvs.b 0x4" 6902 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (jmp (bv 32 0x4)) empty) +d "bpl.b 0x4" 6a02 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (jmp (bv 32 0x4)) empty) +d "bmi.b 0x4" 6b02 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (jmp (bv 32 0x4)) empty) +d "bge.b 0x4" 6c02 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (jmp (bv 32 0x4)) empty) +d "blt.b 0x4" 6d02 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x4)) empty) +d "bgt.b 0x4" 6e02 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x4)) empty) +d "ble.b 0x4" 6f02 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (jmp (bv 32 0x4)) empty) +d "jmp (a0)" 4ed0 0x0 (jmp (var a0)) +d "jsr (a0)" 4e90 0x0 (seq (set target (var a0)) (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr (a7)" 4e97 0x0 (seq (set target (var a7)) (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "rts" 4e75 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (jmp (var target))) +d "link.w a6, 0xfffc" 4e56fffc 0x0 (seq (set push_value (var a6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a6 (cast 32 false (var a7))) (set new_sp (- (var a7) (bv 32 0x4))) (set a7 (cast 32 false (var new_sp)))) +d "link.w a7, 0xfffc" 4e57fffc 0x0 (seq (set push_value (var a7)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a7 (cast 32 false (var a7))) (set new_sp (- (var a7) (bv 32 0x4))) (set a7 (cast 32 false (var new_sp)))) +d "unlk a6" 4e5e 0x0 (seq (set a7 (cast 32 false (var a6))) (set old (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (set a6 (cast 32 false (var old)))) +d "st.b d0" 50c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite true (bv 8 0xff) (bv 8 0x0))))) +d "sf.b d0" 51c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite false (bv 8 0xff) (bv 8 0x0))))) +d "shi.b d0" 52c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0))))) +d "sls.b d0" 53c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0))))) +d "scc.b d0" 54c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0))))) +d "scs.b d0" 55c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0))))) +d "sne.b d0" 56c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0))))) +d "seq.b d0" 57c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0))))) +d "svc.b d0" 58c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0))))) +d "svs.b d0" 59c0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0))))) +d "spl.b d0" 5ac0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0))))) +d "smi.b d0" 5bc0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0))))) +d "sge.b d0" 5cc0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0))))) +d "slt.b d0" 5dc0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0))))) +d "sgt.b d0" 5ec0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0))))) +d "sle.b d0" 5fc0 0x0 (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0xff) (bv 8 0x0))))) +d "dbt d0, 0xfffffffe" 50c8fffc 0x0 (branch true empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbra d0, 0xfffffffe" 51c8fffc 0x0 (branch false empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbhi d0, 0xfffffffe" 52c8fffc 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbls d0, 0xfffffffe" 53c8fffc 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbcc d0, 0xfffffffe" 54c8fffc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbcs d0, 0xfffffffe" 55c8fffc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbne d0, 0xfffffffe" 56c8fffc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbeq d0, 0xfffffffe" 57c8fffc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbvc d0, 0xfffffffe" 58c8fffc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbvs d0, 0xfffffffe" 59c8fffc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbpl d0, 0xfffffffe" 5ac8fffc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbmi d0, 0xfffffffe" 5bc8fffc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbge d0, 0xfffffffe" 5cc8fffc 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dblt d0, 0xfffffffe" 5dc8fffc 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dbgt d0, 0xfffffffe" 5ec8fffc 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "dble d0, 0xfffffffe" 5fc8fffc 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0xfffffffe)) empty))) +d "btst.b 0x0, d0" 08000000 0x0 (seq (set bit (bv 32 0x0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "bset.b 0x0, d0" 08c00000 0x0 (seq (set bit (bv 32 0x0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (| (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) +d "bclr.b 0x0, d0" 08800000 0x0 (seq (set bit (bv 32 0x0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (& (var dst) (~ (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false)))))) +d "bchg.b 0x0, d0" 08400000 0x0 (seq (set bit (bv 32 0x0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (^ (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) +d "trap 0x0" 4e40 0x0 (seq (set trap_op (bv 32 0x0)) (set trap_arg (bv 32 0x0)) (set trap_vector (bv 32 0x20)) (goto m68k_trap)) +d "trapv" 4e76 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (seq (set trap_op (bv 32 0x4)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "illegal 0x4afc" 4afc 0x0 (seq (set trap_op (bv 32 0x8)) (set trap_vector (bv 32 0x4)) (goto m68k_illegal)) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set a7 (cast 32 false (+ (var frame) (bv 32 0x6)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (jmp (var target))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "rtr" 4e77 0x0 (seq (set ccr (loadw 0 16 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x2)))) (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var ccr))))) (jmp (var target))) +d "stop 0x0" 4e720000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x1)) (set system_sr (bv 32 0x0)) (set sr_write_value (cast 16 false (bv 16 0x0))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "reset" 4e70 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x0)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ori.b 0x0, d0" 00000000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, (a0)" 00100000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, (a0)+" 00180000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, -(a0)" 00200000 0x0 (seq (set src (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, 0x1(a0)" 002800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, 0x1(a0, d0.w)" 003000000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0xff, (a0, d0.w)" 003000ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, ([0x18001ff, a0], 0x8000fff)" 00300100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, 0x1.w" 003800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, 0x10010.l" 0039000000010010 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.b 0x0, ccr" 003c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var sr))) (set res (| (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var res)))))) +d "ori.w 0x0, (a0)" 00500000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, (a0)+" 00580000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, -(a0)" 00600000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, 0x1(a0)" 006800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, 0x1(a0, d0.w)" 007000000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0xff, (a0, d0.w)" 007000ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x100, ([0x18001ff, a0], 0x8000fff)" 00700100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, 0x1.w" 007800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, 0x10010.l" 0079000000010010 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.w 0x0, sr" 007c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (var sr)) (set res (| (var dst) (var src))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set sr_write_value (cast 16 false (var res))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))) +d "ori.l 0x1, d0" 008000000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, (a0)" 009000000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, (a0)+" 009800000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, -(a0)" 00a000000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, 0x10(a0)" 00a8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, 0x10(a0, d0.w)" 00b0000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x8000ff, (a0, d0.w)" 00b0008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 00b000ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, 0x10.w" 00b8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ori.l 0x1, 0x10007f.l" 00b9000000010010007f 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10007f))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "btst.b d0, d0" 0100 0x0 (seq (set bit (var d0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, (a0)" 0110 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, (a0)+" 0118 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, -(a0)" 0120 0x0 (seq (set bit (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x0(a0)" 01280000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x0(a0, d0.w)" 01300000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, (a0, d0.w)" 01300100 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, ([0x18001ff, a0], 0x8000fff)" 0130017f018001ff08000fff 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x0.w" 01380000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x1.l" 013900000001 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x2(pc)" 013a0000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (bv 32 0x2))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x2(pc, d0.w)" 013b0000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, ([0x1800201, pc], 0x8000fff)" 013b017f018001ff08000fff 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b d0, 0x0" 013c0000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst (bv 8 0x0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "bchg.b d0, d0" 0140 0x0 (seq (set bit (var d0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (^ (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) +d "movep.l 0x0(a0), d0" 01480000 0x0 (seq (set addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (| (| (<< (cast 32 false (loadw 0 8 (var addr))) (bv 8 0x18) false) (<< (cast 32 false (loadw 0 8 (+ (var addr) (bv 32 0x2)))) (bv 8 0x10) false)) (| (<< (cast 32 false (loadw 0 8 (+ (var addr) (bv 32 0x4)))) (bv 8 0x8) false) (cast 32 false (loadw 0 8 (+ (var addr) (bv 32 0x6))))))) (set d0 (cast 32 false (var res)))) +d "bchg.b d0, (a0)" 0150 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, (a0)+" 0158 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bchg.b d0, -(a0)" 0160 0x0 (seq (set bit (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, 0x0(a0)" 01680000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, 0x0(a0, d0.w)" 01700000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, (a0, d0.w)" 01700100 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, ([0x18001ff, a0], 0x8000fff)" 0170017f018001ff08000fff 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, 0x0.w" 01780000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b d0, 0x1.l" 017900000001 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bclr.b d0, d0" 0180 0x0 (seq (set bit (var d0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (& (var dst) (~ (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false)))))) +d "bclr.b d0, (a0)" 0190 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, (a0)+" 0198 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bclr.b d0, -(a0)" 01a0 0x0 (seq (set bit (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, 0x0(a0)" 01a80000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, 0x0(a0, d0.w)" 01b00000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, (a0, d0.w)" 01b00100 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, ([0x18001ff, a0], 0x8000fff)" 01b0017f018001ff08000fff 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, 0x0.w" 01b80000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b d0, 0x1.l" 01b900000001 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bset.b d0, d0" 01c0 0x0 (seq (set bit (var d0)) (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (set d0 (cast 32 false (| (var dst) (<< (bv 32 0x1) (cast 8 false (mod (cast 32 false (var bit)) (bv 32 0x20))) false))))) +d "movep.l d0, 0x0(a0)" 01c80000 0x0 (seq (set addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set src (var d0)) (storew 0 (var addr) (cast 8 false (>> (var src) (bv 8 0x18) false))) (storew 0 (+ (var addr) (bv 32 0x2)) (cast 8 false (>> (var src) (bv 8 0x10) false))) (storew 0 (+ (var addr) (bv 32 0x4)) (cast 8 false (>> (var src) (bv 8 0x8) false))) (storew 0 (+ (var addr) (bv 32 0x6)) (cast 8 false (var src)))) +d "bset.b d0, (a0)" 01d0 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, (a0)+" 01d8 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bset.b d0, -(a0)" 01e0 0x0 (seq (set bit (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, 0x0(a0)" 01e80000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, 0x0(a0, d0.w)" 01f00000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, (a0, d0.w)" 01f00100 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, ([0x18001ff, a0], 0x8000fff)" 01f0017f018001ff08000fff 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, 0x0.w" 01f80000 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b d0, 0x1.l" 01f900000001 0x0 (seq (set bit (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "andi.b 0x0, d0" 02000000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, (a0)" 02100000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, (a0)+" 02180000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, -(a0)" 02200000 0x0 (seq (set src (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, 0x1(a0)" 022800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, 0x1(a0, d0.w)" 023000000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0xff, (a0, d0.w)" 023000ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, ([0x18001ff, a0], 0x8000fff)" 02300100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, 0x1.w" 023800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, 0x10010.l" 0239000000010010 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.b 0x0, ccr" 023c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var sr))) (set res (& (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var res)))))) +d "andi.w 0x0, (a0)" 02500000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, (a0)+" 02580000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, -(a0)" 02600000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, 0x1(a0)" 026800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, 0x1(a0, d0.w)" 027000000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0xff, (a0, d0.w)" 027000ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x100, ([0x18001ff, a0], 0x8000fff)" 02700100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, 0x1.w" 027800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, 0x10010.l" 0279000000010010 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, sr" 027c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (var sr)) (set res (& (var dst) (var src))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set sr_write_value (cast 16 false (var res))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))) +d "andi.l 0x1, d0" 028000000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, (a0)" 029000000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, (a0)+" 029800000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, -(a0)" 02a000000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, 0x10(a0)" 02a8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, 0x10(a0, d0.w)" 02b0000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x8000ff, (a0, d0.w)" 02b0008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 02b000ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, 0x10.w" 02b8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.l 0x1, 0x10007f.l" 02b9000000010010007f 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10007f))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "subi.b 0x0, d0" 04000000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, (a0)" 04100000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, (a0)+" 04180000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, -(a0)" 04200000 0x0 (seq (set src (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, 0x1(a0)" 042800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, 0x1(a0, d0.w)" 043000000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0xff, (a0, d0.w)" 043000ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, ([0x18001ff, a0], 0x8000fff)" 04300100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, 0x1.w" 043800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.b 0x0, 0x10010.l" 0439000000010010 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, (a0)" 04500000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, (a0)+" 04580000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, -(a0)" 04600000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, 0x1(a0)" 046800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, 0x1(a0, d0.w)" 047000000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0xff, (a0, d0.w)" 047000ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x100, ([0x18001ff, a0], 0x8000fff)" 04700100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, 0x1.w" 047800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.w 0x0, 0x10010.l" 0479000000010010 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, d0" 048000000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, (a0)" 049000000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, (a0)+" 049800000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, -(a0)" 04a000000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, 0x10(a0)" 04a8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, 0x10(a0, d0.w)" 04b0000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x8000ff, (a0, d0.w)" 04b0008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 04b000ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subi.l 0x1, 0x10.w" 04b8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, d0" 06000000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, (a0)" 06100000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, (a0)+" 06180000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! 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(== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, 0x1(a0)" 062800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, 0x1(a0, d0.w)" 063000000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0xff, (a0, d0.w)" 063000ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, ([0x18001ff, a0], 0x8000fff)" 06300100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, 0x1.w" 063800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.b 0x0, 0x10010.l" 0639000000010010 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, (a0)" 06500000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, (a0)+" 06580000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, -(a0)" 06600000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, 0x1(a0)" 066800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, 0x1(a0, d0.w)" 067000000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0xff, (a0, d0.w)" 067000ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x100, ([0x18001ff, a0], 0x8000fff)" 06700100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, 0x1.w" 067800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, 0x10010.l" 0679000000010010 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, d0" 068000000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (+ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, (a0)" 069000000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, (a0)+" 069800000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, -(a0)" 06a000000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, 0x10(a0)" 06a8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, 0x10(a0, d0.w)" 06b0000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x8000ff, (a0, d0.w)" 06b0008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 06b000ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, 0x10.w" 06b8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.l 0x1, 0x10007f.l" 06b9000000010010007f 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10007f))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "btst.b 0x0, (a0)" 08100000 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, (a0)+" 08180000 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, -(a0)" 08200000 0x0 (seq (set bit (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, 0x1(a0)" 082800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, 0x1(a0, d0.w)" 083000000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0xff, (a0, d0.w)" 083000ff0100 0x0 (seq (set bit (bv 8 0xff)) (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, ([0x18001ff, a0], 0x8000fff)" 08300100017f018001ff08000fff 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, 0x1.w" 083800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, 0x10010.l" 0839000000010010 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (bv 32 0x10010))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0xff, 0x4(pc, d0.w)" 083b00ff0100 0x0 (seq (set bit (bv 8 0xff)) (set dst (loadw 0 8 (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, ([0x1800203, pc], 0x8000fff)" 083b0100017f018001ff08000fff 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "bchg.b 0x0, (a0)" 08500000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, (a0)+" 08580000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bchg.b 0x0, -(a0)" 08600000 0x0 (seq (set bit (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, 0x1(a0)" 086800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, 0x1(a0, d0.w)" 087000000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0xff, (a0, d0.w)" 087000ff0100 0x0 (seq (set bit (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, ([0x18001ff, a0], 0x8000fff)" 08700100017f018001ff08000fff 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, 0x1.w" 087800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bchg.b 0x0, 0x10010.l" 0879000000010010 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (^ (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bclr.b 0x0, (a0)" 08900000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, (a0)+" 08980000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bclr.b 0x0, -(a0)" 08a00000 0x0 (seq (set bit (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, 0x1(a0)" 08a800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, 0x1(a0, d0.w)" 08b000000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0xff, (a0, d0.w)" 08b000ff0100 0x0 (seq (set bit (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, ([0x18001ff, a0], 0x8000fff)" 08b00100017f018001ff08000fff 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, 0x1.w" 08b800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bclr.b 0x0, 0x10010.l" 08b9000000010010 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (& (var dst) (~ (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))))) +d "bset.b 0x0, (a0)" 08d00000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, (a0)+" 08d80000 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "bset.b 0x0, -(a0)" 08e00000 0x0 (seq (set bit (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, 0x1(a0)" 08e800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, 0x1(a0, d0.w)" 08f000000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0xff, (a0, d0.w)" 08f000ff0100 0x0 (seq (set bit (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, ([0x18001ff, a0], 0x8000fff)" 08f00100017f018001ff08000fff 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, 0x1.w" 08f800000001 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "bset.b 0x0, 0x10010.l" 08f9000000010010 0x0 (seq (set bit (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))) (storew 0 (var dst_addr) (cast 8 false (| (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) +d "eori.b 0x0, d0" 0a000000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, (a0)" 0a100000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, (a0)+" 0a180000 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, -(a0)" 0a200000 0x0 (seq (set src (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, 0x1(a0)" 0a2800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, 0x1(a0, d0.w)" 0a3000000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0xff, (a0, d0.w)" 0a3000ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, ([0x18001ff, a0], 0x8000fff)" 0a300100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, 0x1.w" 0a3800000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, 0x10010.l" 0a39000000010010 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.b 0x0, ccr" 0a3c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var sr))) (set res (^ (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var res)))))) +d "eori.w 0x0, (a0)" 0a500000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, (a0)+" 0a580000 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, -(a0)" 0a600000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, 0x1(a0)" 0a6800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, 0x1(a0, d0.w)" 0a7000000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0xff, (a0, d0.w)" 0a7000ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x100, ([0x18001ff, a0], 0x8000fff)" 0a700100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, 0x1.w" 0a7800000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, 0x10010.l" 0a79000000010010 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.w 0x0, sr" 0a7c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (var sr)) (set res (^ (var dst) (var src))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set sr_write_value (cast 16 false (var res))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))) +d "eori.l 0x1, d0" 0a8000000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (^ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, (a0)" 0a9000000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, (a0)+" 0a9800000001 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, -(a0)" 0aa000000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, 0x10(a0)" 0aa8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, 0x10(a0, d0.w)" 0ab0000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x8000ff, (a0, d0.w)" 0ab0008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 0ab000ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, 0x10.w" 0ab8000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eori.l 0x1, 0x10007f.l" 0ab9000000010010007f 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x10007f))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false 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false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), d0" 1020 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), d0" 10280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), d0" 10300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), d0" 10300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), d0" 1030017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, d0" 10380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, d0" 103900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), d0" 103a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), d0" 103b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), d0" 103b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, d0" 103c0000 0x0 (seq (set src (bv 8 0x0)) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, (a0)" 1080 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), (a0)" 1090 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, (a0)" 1098 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), (a0)" 10a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), (a0)" 10a80000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), (a0)" 10b00000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), (a0)" 10b00100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), (a0)" 10b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, (a0)" 10b80000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, (a0)" 10b900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), (a0)" 10ba0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), (a0)" 10bb0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), (a0)" 10bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, (a0)" 10bc0000 0x0 (seq (set src (bv 8 0x0)) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, (a0)+" 10c0 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), (a0)+" 10d0 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, (a0)+" 10d8 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), (a0)+" 10e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), (a0)+" 10e80000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), (a0)+" 10f00000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), (a0)+" 10f00100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), (a0)+" 10f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, (a0)+" 10f80000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, (a0)+" 10f900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), (a0)+" 10fa0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), (a0)+" 10fb0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), (a0)+" 10fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, (a0)+" 10fc0000 0x0 (seq (set src (bv 8 0x0)) (storew 0 (var a0) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, -(a0)" 1100 0x0 (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), -(a0)" 1110 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, -(a0)" 1118 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), -(a0)" 1120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), -(a0)" 11280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), -(a0)" 11300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), -(a0)" 11300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), -(a0)" 1130017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, -(a0)" 11380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, -(a0)" 113900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), -(a0)" 113a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), -(a0)" 113b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), -(a0)" 113b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, -(a0)" 113c0000 0x0 (seq (set src (bv 8 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, 0x0(a0)" 11400000 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), 0x0(a0)" 11500000 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, 0x0(a0)" 11580000 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), 0x0(a0)" 11600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), 0x1(a0)" 116800000001 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), 0x1(a0)" 117000000001 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), 0x17f(a0)" 11700100017f 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), 0x1000(a0)" 1170017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, 0x1(a0)" 117800000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, 0x10(a0)" 1179000000010010 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), 0x1(a0)" 117a00000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), 0x1(a0)" 117b00000001 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), 0x17f(a0)" 117b0100017f 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), 0x1000(a0)" 117b017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, 0x1(a0)" 117c00000001 0x0 (seq (set src (bv 8 0x0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, 0x0(a0, d0.w)" 11800000 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, (a0, d0.w)" 11800100 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, ([0x18001ff, a0], 0x8000fff)" 1180017f018001ff08000fff 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), 0x0(a0, d0.w)" 11900000 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), (a0, d0.w)" 11900100 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), ([0x18001ff, a0], 0x8000fff)" 1190017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, 0x0(a0, d0.w)" 11980000 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, (a0, d0.w)" 11980100 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, ([0x18001ff, a0], 0x8000fff)" 1198017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), 0x0(a0, d0.w)" 11a00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), (a0, d0.w)" 11a00100 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), ([0x18001ff, a0], 0x8000fff)" 11a0017f018001ff08000fff 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), 0x1(a0, d0.w)" 11a800000001 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0xff(a0), (a0, d0.w)" 11a800ff0100 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xff))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x100(a0), ([0x18001ff, a0], 0x8000fff)" 11a80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x100))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), 0x1(a0, d0.w)" 11b000000001 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -0x1(a0, d0.w), (a0, d0.w)" 11b000ff0100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffffff))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), ([0x18001ff, a0], 0x8000fff)" 11b00100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), 0x0(a0, d1.w)" 11b0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.l), ([0x10001fff], 0x20002fff)" 11b008000fff10001fff20002fff 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x70007fff], -0x7fff7f00), -0x6e005f00(a0)" 11b06fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, a0.w), -0x6e005f00(a0)" 11b08100817091ffa100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([-0x3eff2e01], -0x1eff0e01), ([0x12345678], -0x65440000)" 11b0b1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, 0x1(a0, d0.w)" 11b800000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0xff.w, (a0, d0.w)" 11b800ff0100 0x0 (seq (set src (loadw 0 8 (bv 32 0xff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x100.w, ([0x18001ff, a0], 0x8000fff)" 11b80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (bv 32 0x100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, 0x10(a0, d0.w)" 11b9000000010010 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x8000ff.l, (a0, d0.w)" 11b9008000ff0100 0x0 (seq (set src (loadw 0 8 (bv 32 0x8000ff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0xff0100.l, ([0x18001ff, a0], 0x8000fff)" 11b900ff0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (bv 32 0xff0100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), 0x1(a0, d0.w)" 11ba00000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x101(pc), (a0, d0.w)" 11ba00ff0100 0x0 (seq (set src (loadw 0 8 (bv 32 0x101))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x102(pc), ([0x18001ff, a0], 0x8000fff)" 11ba0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (bv 32 0x102))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), 0x1(a0, d0.w)" 11bb00000001 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1(pc, d0.w), (a0, d0.w)" 11bb00ff0100 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x1) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), ([0x18001ff, a0], 0x8000fff)" 11bb0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), 0x0(a0, d1.w)" 11bb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.l), ([0x10001fff], 0x20002fff)" 11bb08000fff10001fff20002fff 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x70008001], -0x7fff7f00), -0x6e005f00(a0)" 11bb6fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, a0.w), -0x6e005f00(a0)" 11bb8100817091ffa100 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0xc100d201], -0x1eff0e01), ([0x12345678], -0x65440000)" 11bbb1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, 0x1(a0, d0.w)" 11bc00000001 0x0 (seq (set src (bv 8 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0xff, (a0, d0.w)" 11bc00ff0100 0x0 (seq (set src (bv 8 0xff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, ([0x18001ff, a0], 0x8000fff)" 11bc0100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, 0x0.w" 11c00000 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (bv 32 0x0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), 0x0.w" 11d00000 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (bv 32 0x0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, 0x0.w" 11d80000 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (bv 32 0x0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), 0x0.w" 11e00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (bv 32 0x0) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), 0x1.w" 11e800000001 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), 0x1.w" 11f000000001 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), 0x17f.w" 11f00100017f 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), 0x1000.w" 11f0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, 0x1.w" 11f800000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, 0x10.w" 11f9000000010010 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (bv 32 0x10) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), 0x1.w" 11fa00000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), 0x1.w" 11fb00000001 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc, d0.w), 0x17f.w" 11fb0100017f 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), 0x1000.w" 11fb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, 0x1.w" 11fc00000001 0x0 (seq (set src (bv 8 0x0)) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b d0, 0x1.l" 13c000000001 0x0 (seq (set src (cast 8 false (var d0))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0), 0x1.l" 13d000000001 0x0 (seq (set src (loadw 0 8 (var a0))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0)+, 0x1.l" 13d800000001 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b -(a0), 0x1.l" 13e000000001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (storew 0 (bv 32 0x1) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0), 0x10010.l" 13e8000000010010 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x10010) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0(a0, d0.w), 0x10010.l" 13f0000000010010 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x10010) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b (a0, d0.w), 0x17f0180.l" 13f00100017f0180 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f0180) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x18001ff, a0], 0x8000fff), 0x10001fff.l" 13f0017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0.w, 0x10010.l" 13f8000000010010 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (storew 0 (bv 32 0x10010) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x1.l, 0x10007f.l" 13f9000000010010007f 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (storew 0 (bv 32 0x10007f) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x2(pc), 0x10010.l" 13fa000000010010 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (storew 0 (bv 32 0x10010) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 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(| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b ([0x1800201, pc], 0x8000fff), 0x10001fff.l" 13fb017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.b 0x0, 0x10010.l" 13fc000000010010 0x0 (seq (set src (bv 8 0x0)) (storew 0 (bv 32 0x10010) (cast 8 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, d0" 2000 0x0 (seq (set src (var d0)) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, d0" 2008 0x0 (seq (set src (var a0)) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), d0" 2010 0x0 (seq (set src (loadw 0 32 (var a0))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, d0" 2018 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), d0" 2020 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite 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(set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), d0" 20300100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), d0" 2030017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) 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false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), d0" 203b017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false 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(var a0)) (set a0 (cast 32 false (var src)))) +d "movea.l (a0), a0" 2050 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (var src)))) +d "movea.l (a0)+, a0" 2058 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set a0 (cast 32 false (var src)))) +d "movea.l -(a0), a0" 2060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (var src)))) +d "movea.l 0x0(a0), a0" 20680000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set a0 (cast 32 false (var src)))) +d "movea.l 0x0(a0, d0.w), a0" 20700000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (var src)))) +d "movea.l (a0, d0.w), a0" 20700100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 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0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (var src)))) +d "movea.l 0x1, a0" 207c00000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (var src)))) +d "move.l d0, (a0)" 2080 0x0 (seq (set src (var d0)) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, (a0)" 2088 0x0 (seq (set src (var a0)) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), (a0)" 2090 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, (a0)" 2098 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), (a0)" 20a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), (a0)" 20a80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), (a0)" 20b00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), (a0)" 20b00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), (a0)" 20b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, (a0)" 20b80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, (a0)" 20b900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), (a0)" 20ba0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), (a0)" 20bb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), (a0)" 20bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, (a0)" 20bc00000001 0x0 (seq (set src (bv 32 0x1)) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, (a0)+" 20c8 0x0 (seq (set src (var a0)) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), (a0)+" 20d0 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, (a0)+" 20d8 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), (a0)+" 20e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), (a0)+" 20e80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), (a0)+" 20f00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), (a0)+" 20f00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), (a0)+" 20f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, (a0)+" 20f80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, (a0)+" 20f900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), (a0)+" 20fa0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), (a0)+" 20fb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), (a0)+" 20fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, (a0)+" 20fc00000001 0x0 (seq (set src (bv 32 0x1)) (storew 0 (var a0) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, -(a0)" 2100 0x0 (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, -(a0)" 2108 0x0 (seq (set src (var a0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), -(a0)" 2110 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, -(a0)" 2118 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), -(a0)" 2120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), -(a0)" 21280000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), -(a0)" 21300000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), -(a0)" 21300100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), -(a0)" 2130017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, -(a0)" 21380000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, -(a0)" 213900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), -(a0)" 213a0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), -(a0)" 213b0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), -(a0)" 213b017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, -(a0)" 213c00000001 0x0 (seq (set src (bv 32 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (var a0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, 0x0(a0)" 21400000 0x0 (seq (set src (var d0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, 0x0(a0)" 21480000 0x0 (seq (set src (var a0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), 0x0(a0)" 21500000 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, 0x0(a0)" 21580000 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), 0x0(a0)" 21600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), 0x1(a0)" 216800000001 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), 0x1(a0)" 217000000001 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), 0x17f(a0)" 21700100017f 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), 0x1000(a0)" 2170017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, 0x1(a0)" 217800000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, 0x10(a0)" 2179000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), 0x1(a0)" 217a00000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x1(a0)" 217b00000001 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x17f(a0)" 217b0100017f 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), 0x1000(a0)" 217b017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, 0x10(a0)" 217c000000010010 0x0 (seq (set src (bv 32 0x1)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, 0x0(a0, d0.w)" 21800000 0x0 (seq (set src (var d0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, (a0, d0.w)" 21800100 0x0 (seq (set src (var d0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, ([0x18001ff, a0], 0x8000fff)" 2180017f018001ff08000fff 0x0 (seq (set src (var d0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, 0x0(a0, d0.w)" 21880000 0x0 (seq (set src (var a0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, (a0, d0.w)" 21880100 0x0 (seq (set src (var a0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, ([0x18001ff, a0], 0x8000fff)" 2188017f018001ff08000fff 0x0 (seq (set src (var a0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), 0x0(a0, d0.w)" 21900000 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), (a0, d0.w)" 21900100 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), ([0x18001ff, a0], 0x8000fff)" 2190017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, 0x0(a0, d0.w)" 21980000 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, (a0, d0.w)" 21980100 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, ([0x18001ff, a0], 0x8000fff)" 2198017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), 0x0(a0, d0.w)" 21a00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), (a0, d0.w)" 21a00100 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), ([0x18001ff, a0], 0x8000fff)" 21a0017f018001ff08000fff 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), 0x1(a0, d0.w)" 21a800000001 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0xff(a0), (a0, d0.w)" 21a800ff0100 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xff))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x100(a0), ([0x18001ff, a0], 0x8000fff)" 21a80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x100))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), 0x1(a0, d0.w)" 21b000000001 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -0x1(a0, d0.w), (a0, d0.w)" 21b000ff0100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffffff))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), ([0x18001ff, a0], 0x8000fff)" 21b00100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), 0x0(a0, d1.w)" 21b0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.l), ([0x10001fff], 0x20002fff)" 21b008000fff10001fff20002fff 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x70007fff], -0x7fff7f00), -0x6e005f00(a0)" 21b06fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, a0.w), -0x6e005f00(a0)" 21b08100817091ffa100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([-0x3eff2e01], -0x1eff0e01), ([0x12345678], -0x65440000)" 21b0b1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, 0x1(a0, d0.w)" 21b800000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0xff.w, (a0, d0.w)" 21b800ff0100 0x0 (seq (set src (loadw 0 32 (bv 32 0xff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x100.w, ([0x18001ff, a0], 0x8000fff)" 21b80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (bv 32 0x100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, 0x10(a0, d0.w)" 21b9000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x8000ff.l, (a0, d0.w)" 21b9008000ff0100 0x0 (seq (set src (loadw 0 32 (bv 32 0x8000ff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0xff0100.l, ([0x18001ff, a0], 0x8000fff)" 21b900ff0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (bv 32 0xff0100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), 0x1(a0, d0.w)" 21ba00000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x101(pc), (a0, d0.w)" 21ba00ff0100 0x0 (seq (set src (loadw 0 32 (bv 32 0x101))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x102(pc), ([0x18001ff, a0], 0x8000fff)" 21ba0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (bv 32 0x102))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x1(a0, d0.w)" 21bb00000001 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1(pc, d0.w), (a0, d0.w)" 21bb00ff0100 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x1) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), ([0x18001ff, a0], 0x8000fff)" 21bb0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), 0x0(a0, d1.w)" 21bb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.l), ([0x10001fff], 0x20002fff)" 21bb08000fff10001fff20002fff 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x70008001], -0x7fff7f00), -0x6e005f00(a0)" 21bb6fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, a0.w), -0x6e005f00(a0)" 21bb8100817091ffa100 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0xc100d201], -0x1eff0e01), ([0x12345678], -0x65440000)" 21bbb1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, 0x10(a0, d0.w)" 21bc000000010010 0x0 (seq (set src (bv 32 0x1)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x8000ff, (a0, d0.w)" 21bc008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0xff0100, ([0x18001ff, a0], 0x8000fff)" 21bc00ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, 0x0.w" 21c00000 0x0 (seq (set src (var d0)) (storew 0 (bv 32 0x0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, 0x0.w" 21c80000 0x0 (seq (set src (var a0)) (storew 0 (bv 32 0x0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), 0x0.w" 21d00000 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (bv 32 0x0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, 0x0.w" 21d80000 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (bv 32 0x0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), 0x0.w" 21e00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (bv 32 0x0) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), 0x1.w" 21e800000001 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), 0x1.w" 21f000000001 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), 0x17f.w" 21f00100017f 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), 0x1000.w" 21f0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, 0x1.w" 21f800000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, 0x10.w" 21f9000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (bv 32 0x10) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), 0x1.w" 21fa00000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x1.w" 21fb00000001 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x17f.w" 21fb0100017f 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), 0x1000.w" 21fb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, 0x10.w" 21fc000000010010 0x0 (seq (set src (bv 32 0x1)) (storew 0 (bv 32 0x10) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l d0, 0x1.l" 23c000000001 0x0 (seq (set src (var d0)) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l a0, 0x1.l" 23c800000001 0x0 (seq (set src (var a0)) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0), 0x1.l" 23d000000001 0x0 (seq (set src (loadw 0 32 (var a0))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0)+, 0x1.l" 23d800000001 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l -(a0), 0x1.l" 23e000000001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (storew 0 (bv 32 0x1) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0), 0x10010.l" 23e8000000010010 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x10010) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0(a0, d0.w), 0x10010.l" 23f0000000010010 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x10010) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l (a0, d0.w), 0x17f0180.l" 23f00100017f0180 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f0180) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x18001ff, a0], 0x8000fff), 0x10001fff.l" 23f0017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x0.w, 0x10010.l" 23f8000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (storew 0 (bv 32 0x10010) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1.l, 0x10007f.l" 23f9000000010010007f 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (storew 0 (bv 32 0x10007f) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc), 0x10010.l" 23fa000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (storew 0 (bv 32 0x10010) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x10010.l" 23fb000000010010 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x10010) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x2(pc, d0.w), 0x17f0180.l" 23fb0100017f0180 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f0180) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l ([0x1800201, pc], 0x8000fff), 0x10001fff.l" 23fb017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.l 0x1, 0x10007f.l" 23fc000000010010007f 0x0 (seq (set src (bv 32 0x1)) (storew 0 (bv 32 0x10007f) (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, d0" 3000 0x0 (seq (set src (cast 16 false (var d0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, d0" 3008 0x0 (seq (set src (cast 16 false (var a0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), d0" 3010 0x0 (seq (set src (loadw 0 16 (var a0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, d0" 3018 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), d0" 3020 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), d0" 30280000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), d0" 30300000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), d0" 30300100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), d0" 3030017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, d0" 30380000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, d0" 303900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), d0" 303a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), d0" 303b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), d0" 303b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, d0" 303c0000 0x0 (seq (set src (bv 16 0x0)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "movea.w d0, a0" 3040 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w a0, a0" 3048 0x0 (seq (set src (cast 16 false (var a0))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w (a0), a0" 3050 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w (a0)+, a0" 3058 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w -(a0), a0" 3060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x0(a0), a0" 30680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x0(a0, d0.w), a0" 30700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w (a0, d0.w), a0" 30700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w ([0x18001ff, a0], 0x8000fff), a0" 3070017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x0.w, a0" 30780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x1.l, a0" 307900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x2(pc), a0" 307a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x2(pc, d0.w), a0" 307b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w ([0x1800201, pc], 0x8000fff), a0" 307b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 (msb (var src)) (var src)))) +d "movea.w 0x0, a0" 307c0000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 (msb (var src)) (var src)))) +d "move.w d0, (a0)" 3080 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, (a0)" 3088 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), (a0)" 3090 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, (a0)" 3098 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), (a0)" 30a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), (a0)" 30a80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), (a0)" 30b00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), (a0)" 30b00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), (a0)" 30b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, (a0)" 30b80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, (a0)" 30b900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), (a0)" 30ba0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), (a0)" 30bb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), (a0)" 30bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, (a0)" 30bc0000 0x0 (seq (set src (bv 16 0x0)) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, (a0)+" 30c0 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, (a0)+" 30c8 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), (a0)+" 30d0 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, (a0)+" 30d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), (a0)+" 30e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), (a0)+" 30e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), (a0)+" 30f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), (a0)+" 30f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), (a0)+" 30f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, (a0)+" 30f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, (a0)+" 30f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), (a0)+" 30fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), (a0)+" 30fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), (a0)+" 30fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, (a0)+" 30fc0000 0x0 (seq (set src (bv 16 0x0)) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, -(a0)" 3100 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, -(a0)" 3108 0x0 (seq (set src (cast 16 false (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), -(a0)" 3110 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, -(a0)" 3118 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), -(a0)" 3120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), -(a0)" 31280000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), -(a0)" 31300000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), -(a0)" 31300100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), -(a0)" 3130017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, -(a0)" 31380000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, -(a0)" 313900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), -(a0)" 313a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), -(a0)" 313b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), -(a0)" 313b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, -(a0)" 313c0000 0x0 (seq (set src (bv 16 0x0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, 0x0(a0)" 31400000 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, 0x0(a0)" 31480000 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), 0x0(a0)" 31500000 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, 0x0(a0)" 31580000 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), 0x0(a0)" 31600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), 0x1(a0)" 316800000001 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), 0x1(a0)" 317000000001 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), 0x17f(a0)" 31700100017f 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), 0x1000(a0)" 3170017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, 0x1(a0)" 317800000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, 0x10(a0)" 3179000000010010 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), 0x1(a0)" 317a00000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x1(a0)" 317b00000001 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x17f(a0)" 317b0100017f 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), 0x1000(a0)" 317b017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, 0x1(a0)" 317c00000001 0x0 (seq (set src (bv 16 0x0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, 0x0(a0, d0.w)" 31800000 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, (a0, d0.w)" 31800100 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, ([0x18001ff, a0], 0x8000fff)" 3180017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, 0x0(a0, d0.w)" 31880000 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, (a0, d0.w)" 31880100 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, ([0x18001ff, a0], 0x8000fff)" 3188017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), 0x0(a0, d0.w)" 31900000 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), (a0, d0.w)" 31900100 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), ([0x18001ff, a0], 0x8000fff)" 3190017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, 0x0(a0, d0.w)" 31980000 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, (a0, d0.w)" 31980100 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, ([0x18001ff, a0], 0x8000fff)" 3198017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), 0x0(a0, d0.w)" 31a00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), (a0, d0.w)" 31a00100 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), ([0x18001ff, a0], 0x8000fff)" 31a0017f018001ff08000fff 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), 0x1(a0, d0.w)" 31a800000001 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0xff(a0), (a0, d0.w)" 31a800ff0100 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xff))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x100(a0), ([0x18001ff, a0], 0x8000fff)" 31a80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x100))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), 0x1(a0, d0.w)" 31b000000001 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -0x1(a0, d0.w), (a0, d0.w)" 31b000ff0100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffffff))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), ([0x18001ff, a0], 0x8000fff)" 31b00100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), 0x0(a0, d1.w)" 31b0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.l), ([0x10001fff], 0x20002fff)" 31b008000fff10001fff20002fff 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x70007fff], -0x7fff7f00), -0x6e005f00(a0)" 31b06fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, a0.w), -0x6e005f00(a0)" 31b08100817091ffa100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([-0x3eff2e01], -0x1eff0e01), ([0x12345678], -0x65440000)" 31b0b1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, 0x1(a0, d0.w)" 31b800000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0xff.w, (a0, d0.w)" 31b800ff0100 0x0 (seq (set src (loadw 0 16 (bv 32 0xff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x100.w, ([0x18001ff, a0], 0x8000fff)" 31b80100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (bv 32 0x100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, 0x10(a0, d0.w)" 31b9000000010010 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x8000ff.l, (a0, d0.w)" 31b9008000ff0100 0x0 (seq (set src (loadw 0 16 (bv 32 0x8000ff))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0xff0100.l, ([0x18001ff, a0], 0x8000fff)" 31b900ff0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (bv 32 0xff0100))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), 0x1(a0, d0.w)" 31ba00000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x101(pc), (a0, d0.w)" 31ba00ff0100 0x0 (seq (set src (loadw 0 16 (bv 32 0x101))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x102(pc), ([0x18001ff, a0], 0x8000fff)" 31ba0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (bv 32 0x102))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x1(a0, d0.w)" 31bb00000001 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1(pc, d0.w), (a0, d0.w)" 31bb00ff0100 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x1) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), ([0x18001ff, a0], 0x8000fff)" 31bb0100017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), 0x0(a0, d1.w)" 31bb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.l), ([0x10001fff], 0x20002fff)" 31bb08000fff10001fff20002fff 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 false (var d0))))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x70008001], -0x7fff7f00), -0x6e005f00(a0)" 31bb6fff70007fff80008100817091ffa100 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x70007fff))) (bv 32 0x0)) (bv 32 0x80008100)))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, a0.w), -0x6e005f00(a0)" 31bb8100817091ffa100 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x91ffa100))) (bv 32 0x0)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0xc100d201], -0x1eff0e01), ([0x12345678], -0x65440000)" 31bbb1ffc100d1ffe100f1ffffff123456789abc0000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0xc100d1ff))) (bv 32 0x0)) (bv 32 0xe100f1ff)))) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x12345678))) (bv 32 0x0)) (bv 32 0x9abc0000)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, 0x1(a0, d0.w)" 31bc00000001 0x0 (seq (set src (bv 16 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0xff, (a0, d0.w)" 31bc00ff0100 0x0 (seq (set src (bv 16 0xff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x100, ([0x18001ff, a0], 0x8000fff)" 31bc0100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, 0x0.w" 31c00000 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (bv 32 0x0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, 0x0.w" 31c80000 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (bv 32 0x0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), 0x0.w" 31d00000 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (bv 32 0x0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, 0x0.w" 31d80000 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (bv 32 0x0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), 0x0.w" 31e00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (bv 32 0x0) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), 0x1.w" 31e800000001 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), 0x1.w" 31f000000001 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), 0x17f.w" 31f00100017f 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), 0x1000.w" 31f0017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, 0x1.w" 31f800000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, 0x10.w" 31f9000000010010 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (bv 32 0x10) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), 0x1.w" 31fa00000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x1.w" 31fb00000001 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x17f.w" 31fb0100017f 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), 0x1000.w" 31fb017f018001ff08000fff1000 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x1000) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, 0x1.w" 31fc00000001 0x0 (seq (set src (bv 16 0x0)) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w d0, 0x1.l" 33c000000001 0x0 (seq (set src (cast 16 false (var d0))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w a0, 0x1.l" 33c800000001 0x0 (seq (set src (cast 16 false (var a0))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0), 0x1.l" 33d000000001 0x0 (seq (set src (loadw 0 16 (var a0))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0)+, 0x1.l" 33d800000001 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w -(a0), 0x1.l" 33e000000001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (storew 0 (bv 32 0x1) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0), 0x10010.l" 33e8000000010010 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0(a0, d0.w), 0x10010.l" 33f0000000010010 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w (a0, d0.w), 0x17f0180.l" 33f00100017f0180 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f0180) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x18001ff, a0], 0x8000fff), 0x10001fff.l" 33f0017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0.w, 0x10010.l" 33f8000000010010 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x1.l, 0x10007f.l" 33f9000000010010007f 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (storew 0 (bv 32 0x10007f) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc), 0x10010.l" 33fa000000010010 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x10010.l" 33fb000000010010 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x2(pc, d0.w), 0x17f0180.l" 33fb0100017f0180 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (bv 32 0x17f0180) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w ([0x1800201, pc], 0x8000fff), 0x10001fff.l" 33fb017f018001ff08000fff10001fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (bv 32 0x10001fff) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "move.w 0x0, 0x10010.l" 33fc000000010010 0x0 (seq (set src (bv 16 0x0)) (storew 0 (bv 32 0x10010) (cast 16 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "negx.b d0" 4000 0x0 (seq (set dst (cast 8 false (var d0))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 8 0x1) (bv 8 0x0))) (set res (- (- (bv 8 0x0) (var dst)) (var borrow))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffffffffff80)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffffffffff80)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7f)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.b (a0)" 4010 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7f)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.b 0x0.w" 40380000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7f)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.b 0x1.l" 403900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7f)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w (a0)" 4050 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w (a0)+" 4058 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w -(a0)" 4060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w 0x0(a0)" 40680000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w 0x0(a0, d0.w)" 40700000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w (a0, d0.w)" 40700100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w ([0x18001ff, a0], 0x8000fff)" 4070017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w 0x0.w" 40780000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.w 0x1.l" 407900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l d0" 4080 0x0 (seq (set dst (var d0)) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! 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(is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l (a0)+" 4098 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! 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(sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l -(a0)" 40a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l 0x0(a0)" 40a80000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l 0x0(a0, d0.w)" 40b00000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l (a0, d0.w)" 40b00100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l ([0x18001ff, a0], 0x8000fff)" 40b0017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l 0x0.w" 40b80000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "negx.l 0x1.l" 40b900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set borrow (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set res (- (- (bv 32 0x0) (var dst)) (var borrow))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 32 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)) (! (== (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0xffffffff80000000)))) (! (sle (- (- (bv 64 0x0) (cast 64 (msb (var dst)) (var dst))) (cast 64 false (var borrow))) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (! (is_zero (var dst))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "move.w sr, d0" 40c0 0x0 (seq (set src (var sr)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) +d "move.w sr, (a0)" 40d0 0x0 (seq (set src (var sr)) (storew 0 (var a0) (cast 16 false (var src)))) +d "move.w sr, (a0)+" 40d8 0x0 (seq (set src (var sr)) (storew 0 (var a0) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2))))) +d "move.w sr, -(a0)" 40e0 0x0 (seq (set src (var sr)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (var a0) (cast 16 false (var src)))) +d "move.w sr, 0x0(a0)" 40e80000 0x0 (seq (set src (var sr)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var src)))) +d "move.w sr, 0x0(a0, d0.w)" 40f00000 0x0 (seq (set src (var sr)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src)))) +d "move.w sr, (a0, d0.w)" 40f00100 0x0 (seq (set src (var sr)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var src)))) +d "move.w sr, ([0x18001ff, a0], 0x8000fff)" 40f0017f018001ff08000fff 0x0 (seq (set src (var sr)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var src)))) +d "move.w sr, 0x0.w" 40f80000 0x0 (seq (set src (var sr)) (storew 0 (bv 32 0x0) (cast 16 false (var src)))) +d "move.w sr, 0x1.l" 40f900000001 0x0 (seq (set src (var sr)) (storew 0 (bv 32 0x1) (cast 16 false (var src)))) +d "chk.w d0, d0" 4180 0x0 (seq (set bound (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w (a0), d0" 4190 0x0 (seq (set bound (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w (a0)+, d0" 4198 0x0 (seq (set bound (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w -(a0), d0" 41a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set bound (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x0(a0), d0" 41a80000 0x0 (seq (set bound (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x0(a0, d0.w), d0" 41b00000 0x0 (seq (set bound (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w (a0, d0.w), d0" 41b00100 0x0 (seq (set bound (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w ([0x18001ff, a0], 0x8000fff), d0" 41b0017f018001ff08000fff 0x0 (seq (set bound (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x0.w, d0" 41b80000 0x0 (seq (set bound (loadw 0 16 (bv 32 0x0))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x1.l, d0" 41b900000001 0x0 (seq (set bound (loadw 0 16 (bv 32 0x1))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x2(pc), d0" 41ba0000 0x0 (seq (set bound (loadw 0 16 (bv 32 0x2))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x2(pc, d0.w), d0" 41bb0000 0x0 (seq (set bound (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w ([0x1800201, pc], 0x8000fff), d0" 41bb017f018001ff08000fff 0x0 (seq (set bound (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.w 0x0, d0" 41bc0000 0x0 (seq (set bound (bv 16 0x0)) (set dst (cast 16 false (var d0))) (branch (&& (sle (var dst) (bv 16 0x0)) (! (== (var dst) (bv 16 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "lea.l (a0), a0" 41d0 0x0 (set a0 (cast 32 false (var a0))) +d "lea.l 0x0(a0, d0.w), a0" 41f00000 0x0 (set a0 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) +d "lea.l (a0, d0.w), a0" 41f00100 0x0 (set a0 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) +d "lea.l ([0x18001ff, a0], 0x8000fff), a0" 41f0017f018001ff08000fff 0x0 (set a0 (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) +d "lea.l 0x0.w, a0" 41f80000 0x0 (set a0 (cast 32 false (bv 32 0x0))) +d "lea.l 0x1.l, a0" 41f900000001 0x0 (set a0 (cast 32 false (bv 32 0x1))) +d "lea.l 0x2(pc), a0" 41fa0000 0x0 (set a0 (cast 32 false (bv 32 0x2))) +d "lea.l 0x2(pc, d0.w), a0" 41fb0000 0x0 (set a0 (cast 32 false (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) +d "lea.l ([0x1800201, pc], 0x8000fff), a0" 41fb017f018001ff08000fff 0x0 (set a0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) +d "clr.b d0" 4200 0x0 (seq (set res (bv 8 0x0)) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b (a0)" 4210 0x0 (seq (set res (bv 8 0x0)) (storew 0 (var a0) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b (a0)+" 4218 0x0 (seq (set res (bv 8 0x0)) (storew 0 (var a0) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b -(a0)" 4220 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set res (bv 8 0x0)) (storew 0 (var a0) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b 0x0(a0)" 42280000 0x0 (seq (set res (bv 8 0x0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b 0x0(a0, d0.w)" 42300000 0x0 (seq (set res (bv 8 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b (a0, d0.w)" 42300100 0x0 (seq (set res (bv 8 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b ([0x18001ff, a0], 0x8000fff)" 4230017f018001ff08000fff 0x0 (seq (set res (bv 8 0x0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b 0x0.w" 42380000 0x0 (seq (set res (bv 8 0x0)) (storew 0 (bv 32 0x0) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.b 0x1.l" 423900000001 0x0 (seq (set res (bv 8 0x0)) (storew 0 (bv 32 0x1) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w (a0)" 4250 0x0 (seq (set res (bv 16 0x0)) (storew 0 (var a0) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w (a0)+" 4258 0x0 (seq (set res (bv 16 0x0)) (storew 0 (var a0) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w -(a0)" 4260 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set res (bv 16 0x0)) (storew 0 (var a0) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w 0x0(a0)" 42680000 0x0 (seq (set res (bv 16 0x0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w 0x0(a0, d0.w)" 42700000 0x0 (seq (set res (bv 16 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w (a0, d0.w)" 42700100 0x0 (seq (set res (bv 16 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w ([0x18001ff, a0], 0x8000fff)" 4270017f018001ff08000fff 0x0 (seq (set res (bv 16 0x0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w 0x0.w" 42780000 0x0 (seq (set res (bv 16 0x0)) (storew 0 (bv 32 0x0) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.w 0x1.l" 427900000001 0x0 (seq (set res (bv 16 0x0)) (storew 0 (bv 32 0x1) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l d0" 4280 0x0 (seq (set res (bv 32 0x0)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l (a0)" 4290 0x0 (seq (set res (bv 32 0x0)) (storew 0 (var a0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l -(a0)" 42a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set res (bv 32 0x0)) (storew 0 (var a0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l 0x0(a0)" 42a80000 0x0 (seq (set res (bv 32 0x0)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l 0x0(a0, d0.w)" 42b00000 0x0 (seq (set res (bv 32 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l (a0, d0.w)" 42b00100 0x0 (seq (set res (bv 32 0x0)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l ([0x18001ff, a0], 0x8000fff)" 42b0017f018001ff08000fff 0x0 (seq (set res (bv 32 0x0)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l 0x0.w" 42b80000 0x0 (seq (set res (bv 32 0x0)) (storew 0 (bv 32 0x0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "clr.l 0x1.l" 42b900000001 0x0 (seq (set res (bv 32 0x0)) (storew 0 (bv 32 0x1) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "neg.b d0" 4400 0x0 (seq (set dst (cast 8 false (var d0))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b (a0)" 4410 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b (a0)+" 4418 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b -(a0)" 4420 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b 0x0(a0)" 44280000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b 0x0(a0, d0.w)" 44300000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b (a0, d0.w)" 44300100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b ([0x18001ff, a0], 0x8000fff)" 4430017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b 0x0.w" 44380000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.b 0x1.l" 443900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (- (bv 8 0x0) (var dst)) (bv 8 0x0))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 8 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w (a0)" 4450 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w (a0)+" 4458 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w -(a0)" 4460 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w 0x0(a0)" 44680000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w 0x0(a0, d0.w)" 44700000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w (a0, d0.w)" 44700100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w ([0x18001ff, a0], 0x8000fff)" 4470017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w 0x0.w" 44780000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.w 0x1.l" 447900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (- (bv 16 0x0) (var dst)) (bv 16 0x0))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 16 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l d0" 4480 0x0 (seq (set dst (var d0)) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l (a0)" 4490 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l (a0)+" 4498 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l -(a0)" 44a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l 0x0(a0)" 44a80000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l 0x0(a0, d0.w)" 44b00000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l (a0, d0.w)" 44b00100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l ([0x18001ff, a0], 0x8000fff)" 44b0017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l 0x0.w" 44b80000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "neg.l 0x1.l" 44b900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (- (bv 32 0x0) (var dst)) (bv 32 0x0))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (bv 32 0x0)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "move.w d0, ccr" 44c0 0x0 (seq (set src (cast 16 false (var d0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w (a0), ccr" 44d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w (a0)+, ccr" 44d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w -(a0), ccr" 44e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x0(a0), ccr" 44e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x0(a0, d0.w), ccr" 44f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w (a0, d0.w), ccr" 44f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w ([0x18001ff, a0], 0x8000fff), ccr" 44f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x0.w, ccr" 44f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x1.l, ccr" 44f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x2(pc), ccr" 44fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x2(pc, d0.w), ccr" 44fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w ([0x1800201, pc], 0x8000fff), ccr" 44fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "move.w 0x0, ccr" 44fc0000 0x0 (seq (set src (bv 16 0x0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (var src)))))) +d "not.b d0" 4600 0x0 (seq (set dst (cast 8 false (var d0))) (set res (~ (var dst))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b (a0)" 4610 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b (a0)+" 4618 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b -(a0)" 4620 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b 0x0(a0)" 46280000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b 0x0(a0, d0.w)" 46300000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b (a0, d0.w)" 46300100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b ([0x18001ff, a0], 0x8000fff)" 4630017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b 0x0.w" 46380000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.b 0x1.l" 463900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w (a0)" 4650 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w (a0)+" 4658 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w -(a0)" 4660 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w 0x0(a0)" 46680000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w 0x0(a0, d0.w)" 46700000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w (a0, d0.w)" 46700100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w ([0x18001ff, a0], 0x8000fff)" 4670017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w 0x0.w" 46780000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.w 0x1.l" 467900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l d0" 4680 0x0 (seq (set dst (var d0)) (set res (~ (var dst))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l (a0)" 4690 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l (a0)+" 4698 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l 0x0(a0)" 46a80000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l 0x0(a0, d0.w)" 46b00000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l (a0, d0.w)" 46b00100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l ([0x18001ff, a0], 0x8000fff)" 46b0017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l 0x0.w" 46b80000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "not.l 0x1.l" 46b900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (~ (var dst))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "nbcd.b d0" 4800 0x0 (seq (set dst (cast 8 false (var d0))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b (a0)" 4810 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b (a0)+" 4818 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b -(a0)" 4820 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b 0x0(a0)" 48280000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b 0x0(a0, d0.w)" 48300000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b (a0, d0.w)" 48300100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b ([0x18001ff, a0], 0x8000fff)" 4830017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b 0x0.w" 48380000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "nbcd.b 0x1.l" 483900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (bv 32 0x0) (+ (var dst_dec) (var x)))) (set borrow (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 32 0x1) (bv 32 0x0))) (set res_dec (ite (! (is_zero (var borrow))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (is_zero (var borrow))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "pea.l (a0)" 4850 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l (a7)" 4857 0x0 (seq (set push_value (var a7)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l 0x0(a0, d0.w)" 48700000 0x0 (seq (set push_value (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l (a0, d0.w)" 48700100 0x0 (seq (set push_value (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l ([0x18001ff, a0], 0x8000fff)" 4870017f018001ff08000fff 0x0 (seq (set push_value (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l 0x0.w" 48780000 0x0 (seq (set push_value (bv 32 0x0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l 0x1.l" 487900000001 0x0 (seq (set push_value (bv 32 0x1)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l 0x2(pc)" 487a0000 0x0 (seq (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l 0x2(pc, d0.w)" 487b0000 0x0 (seq (set push_value (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "pea.l ([0x1800201, pc], 0x8000fff)" 487b017f018001ff08000fff 0x0 (seq (set push_value (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "movem.w 0x0, (a0)" 48900000 0x0 nop +d "movem.w 0x0, -(a0)" 48a00000 0x0 nop +d "movem.w 0x0, 0x1(a0)" 48a800000001 0x0 nop +d "movem.w 0x0, 0x1(a0, d0.w)" 48b000000001 0x0 nop +d "movem.w d0-d7, (a0, d0.w)" 48b000ff0100 0x0 (seq (set addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var addr) (cast 16 false (cast 16 false (var d0)))) (storew 0 (+ (var addr) (bv 32 0x2)) (cast 16 false (cast 16 false (var d1)))) (storew 0 (+ (var addr) (bv 32 0x4)) (cast 16 false (cast 16 false (var d2)))) (storew 0 (+ (var addr) (bv 32 0x6)) (cast 16 false (cast 16 false (var d3)))) (storew 0 (+ (var addr) (bv 32 0x8)) (cast 16 false (cast 16 false (var d4)))) (storew 0 (+ (var addr) (bv 32 0xa)) (cast 16 false (cast 16 false (var d5)))) (storew 0 (+ (var addr) (bv 32 0xc)) (cast 16 false (cast 16 false (var d6)))) (storew 0 (+ (var addr) (bv 32 0xe)) (cast 16 false (cast 16 false (var d7))))) +d "movem.w a0, ([0x18001ff, a0], 0x8000fff)" 48b00100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var addr) (cast 16 false (cast 16 false (var a0))))) +d "movem.w 0x0, 0x1.w" 48b800000001 0x0 nop +d "movem.w 0x0, 0x10010.l" 48b9000000010010 0x0 nop +d "ext.l d0" 48c0 0x0 (seq (set res (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set d0 (cast 32 false (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "movem.l 0x0, (a0)" 48d00000 0x0 nop +d "movem.l 0x0, -(a0)" 48e00000 0x0 nop +d "movem.l d0-d1, -(a0)" 48e0c000 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (var d1))) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (var d0))) (set a0 (cast 32 false (var addr)))) +d "movem.l 0x0, 0x1(a0)" 48e800000001 0x0 nop +d "movem.l 0x0, 0x1(a0, d0.w)" 48f000000001 0x0 nop +d "movem.l d0-d7, (a0, d0.w)" 48f000ff0100 0x0 (seq (set addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (storew 0 (var addr) (cast 32 false (var d0))) (storew 0 (+ (var addr) (bv 32 0x4)) (cast 32 false (var d1))) (storew 0 (+ (var addr) (bv 32 0x8)) (cast 32 false (var d2))) (storew 0 (+ (var addr) (bv 32 0xc)) (cast 32 false (var d3))) (storew 0 (+ (var addr) (bv 32 0x10)) (cast 32 false (var d4))) (storew 0 (+ (var addr) (bv 32 0x14)) (cast 32 false (var d5))) (storew 0 (+ (var addr) (bv 32 0x18)) (cast 32 false (var d6))) (storew 0 (+ (var addr) (bv 32 0x1c)) (cast 32 false (var d7)))) +d "movem.l a0, ([0x18001ff, a0], 0x8000fff)" 48f00100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (storew 0 (var addr) (cast 32 false (var a0)))) +d "movem.l 0x0, 0x1.w" 48f800000001 0x0 nop +d "movem.l 0x0, 0x10010.l" 48f9000000010010 0x0 nop +d "tst.b d0" 4a00 0x0 (seq (set dst (cast 8 false (var d0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b (a0)" 4a10 0x0 (seq (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b (a0)+" 4a18 0x0 (seq (set dst (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b -(a0)" 4a20 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst (loadw 0 8 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x0(a0)" 4a280000 0x0 (seq (set dst (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x0(a0, d0.w)" 4a300000 0x0 (seq (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b (a0, d0.w)" 4a300100 0x0 (seq (set dst (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b ([0x18001ff, a0], 0x8000fff)" 4a30017f018001ff08000fff 0x0 (seq (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x0.w" 4a380000 0x0 (seq (set dst (loadw 0 8 (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x1.l" 4a3900000001 0x0 (seq (set dst (loadw 0 8 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w (a0)" 4a50 0x0 (seq (set dst (loadw 0 16 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w (a0)+" 4a58 0x0 (seq (set dst (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w -(a0)" 4a60 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst (loadw 0 16 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x0(a0)" 4a680000 0x0 (seq (set dst (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x0(a0, d0.w)" 4a700000 0x0 (seq (set dst (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w (a0, d0.w)" 4a700100 0x0 (seq (set dst (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w ([0x18001ff, a0], 0x8000fff)" 4a70017f018001ff08000fff 0x0 (seq (set dst (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x0.w" 4a780000 0x0 (seq (set dst (loadw 0 16 (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x1.l" 4a7900000001 0x0 (seq (set dst (loadw 0 16 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l d0" 4a80 0x0 (seq (set dst (var d0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l (a0)" 4a90 0x0 (seq (set dst (loadw 0 32 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l (a0)+" 4a98 0x0 (seq (set dst (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l -(a0)" 4aa0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst (loadw 0 32 (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x0(a0)" 4aa80000 0x0 (seq (set dst (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x0(a0, d0.w)" 4ab00000 0x0 (seq (set dst (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l (a0, d0.w)" 4ab00100 0x0 (seq (set dst (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l ([0x18001ff, a0], 0x8000fff)" 4ab0017f018001ff08000fff 0x0 (seq (set dst (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x0.w" 4ab80000 0x0 (seq (set dst (loadw 0 32 (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x1.l" 4ab900000001 0x0 (seq (set dst (loadw 0 32 (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b d0" 4ac0 0x0 (seq (set dst (cast 8 false (var d0))) (set res (| (var dst) (bv 8 0x80))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b (a0)" 4ad0 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b (a0)+" 4ad8 0x0 (seq (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b -(a0)" 4ae0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b 0x0(a0)" 4ae80000 0x0 (seq (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b 0x0(a0, d0.w)" 4af00000 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b (a0, d0.w)" 4af00100 0x0 (seq (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b ([0x18001ff, a0], 0x8000fff)" 4af0017f018001ff08000fff 0x0 (seq (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b 0x0.w" 4af80000 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tas.b 0x1.l" 4af900000001 0x0 (seq (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (bv 8 0x80))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "movem.w (a0), 0x0" 4c900000 0x0 nop +d "movem.w (a0)+, 0x0" 4c980000 0x0 nop +d "movem.w 0x1(a0), 0x0" 4ca800000001 0x0 nop +d "movem.w 0x1(a0, d0.w), 0x0" 4cb000000001 0x0 nop +d "movem.w (a0, d0.w), d0-d7" 4cb000ff0100 0x0 (seq (set addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (cast 32 (msb (loadw 0 16 (var addr))) (loadw 0 16 (var addr))))) (set d1 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x2)))) (loadw 0 16 (+ (var addr) (bv 32 0x2)))))) (set d2 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x4)))) (loadw 0 16 (+ (var addr) (bv 32 0x4)))))) (set d3 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x6)))) (loadw 0 16 (+ (var addr) (bv 32 0x6)))))) (set d4 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x8)))) (loadw 0 16 (+ (var addr) (bv 32 0x8)))))) (set d5 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xa)))) (loadw 0 16 (+ (var addr) (bv 32 0xa)))))) (set d6 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xc)))) (loadw 0 16 (+ (var addr) (bv 32 0xc)))))) (set d7 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xe)))) (loadw 0 16 (+ (var addr) (bv 32 0xe))))))) +d "movem.w ([0x18001ff, a0], 0x8000fff), a0" 4cb00100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (cast 32 (msb (loadw 0 16 (var addr))) (loadw 0 16 (var addr)))))) +d "movem.w 0x1.w, 0x0" 4cb800000001 0x0 nop +d "movem.w 0x10010.l, 0x0" 4cb9000000010010 0x0 nop +d "movem.w 0x5(pc), 0x0" 4cba00000001 0x0 nop +d "movem.w 0x5(pc, d0.w), 0x0" 4cbb00000001 0x0 nop +d "movem.w 0x4(pc, d0.w), d0-d7" 4cbb00ff0100 0x0 (seq (set addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (cast 32 (msb (loadw 0 16 (var addr))) (loadw 0 16 (var addr))))) (set d1 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x2)))) (loadw 0 16 (+ (var addr) (bv 32 0x2)))))) (set d2 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x4)))) (loadw 0 16 (+ (var addr) (bv 32 0x4)))))) (set d3 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x6)))) (loadw 0 16 (+ (var addr) (bv 32 0x6)))))) (set d4 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0x8)))) (loadw 0 16 (+ (var addr) (bv 32 0x8)))))) (set d5 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xa)))) (loadw 0 16 (+ (var addr) (bv 32 0xa)))))) (set d6 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xc)))) (loadw 0 16 (+ (var addr) (bv 32 0xc)))))) (set d7 (cast 32 false (cast 32 (msb (loadw 0 16 (+ (var addr) (bv 32 0xe)))) (loadw 0 16 (+ (var addr) (bv 32 0xe))))))) +d "movem.w ([0x1800203, pc], 0x8000fff), a0" 4cbb0100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (cast 32 (msb (loadw 0 16 (var addr))) (loadw 0 16 (var addr)))))) +d "movem.l (a0), 0x0" 4cd00000 0x0 nop +d "movem.l (a0)+, 0x0" 4cd80000 0x0 nop +d "movem.l 0x1(a0), 0x0" 4ce800000001 0x0 nop +d "movem.l 0x1(a0, d0.w), 0x0" 4cf000000001 0x0 nop +d "movem.l (a0, d0.w), d0-d7" 4cf000ff0100 0x0 (seq (set addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (loadw 0 32 (var addr)))) (set d1 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x4))))) (set d2 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x8))))) (set d3 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0xc))))) (set d4 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x10))))) (set d5 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x14))))) (set d6 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x18))))) (set d7 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x1c)))))) +d "movem.l ([0x18001ff, a0], 0x8000fff), a0" 4cf00100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (loadw 0 32 (var addr))))) +d "movem.l 0x1.w, 0x0" 4cf800000001 0x0 nop +d "movem.l 0x10010.l, 0x0" 4cf9000000010010 0x0 nop +d "movem.l 0x5(pc), 0x0" 4cfa00000001 0x0 nop +d "movem.l 0x5(pc, d0.w), 0x0" 4cfb00000001 0x0 nop +d "movem.l 0x4(pc, d0.w), d0-d7" 4cfb00ff0100 0x0 (seq (set addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set d0 (cast 32 false (loadw 0 32 (var addr)))) (set d1 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x4))))) (set d2 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x8))))) (set d3 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0xc))))) (set d4 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x10))))) (set d5 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x14))))) (set d6 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x18))))) (set d7 (cast 32 false (loadw 0 32 (+ (var addr) (bv 32 0x1c)))))) +d "movem.l ([0x1800203, pc], 0x8000fff), a0" 4cfb0100017f018001ff08000fff 0x0 (seq (set addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set a0 (cast 32 false (loadw 0 32 (var addr))))) +d "move a0, usp" 4e60 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var a0)) (set usp (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "jsr 0x0(a0)" 4ea80000 0x0 (seq (set target (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0)))) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr 0x0(a7)" 4eaf0000 0x0 (seq (set target (+ (cast 32 false (var a7)) (cast 32 false (bv 32 0x0)))) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr 0x0(a0, d0.w)" 4eb00000 0x0 (seq (set target (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr (a0, d0.w)" 4eb00100 0x0 (seq (set target (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr ([0x18001ff, a0], 0x8000fff)" 4eb0017f018001ff08000fff 0x0 (seq (set target (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) (set push_value (bv 32 0xc)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr 0x0.w" 4eb80000 0x0 (seq (set target (bv 32 0x0)) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr 0x2(pc)" 4eba0000 0x0 (seq (set target (bv 32 0x2)) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr 0x2(pc, d0.w)" 4ebb0000 0x0 (seq (set target (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) (set push_value (bv 32 0x4)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jsr ([0x1800201, pc], 0x8000fff)" 4ebb017f018001ff08000fff 0x0 (seq (set target (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) (set push_value (bv 32 0xc)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "jmp 0x0(a0)" 4ee80000 0x0 (jmp (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0)))) +d "jmp 0x0(a0, d0.w)" 4ef00000 0x0 (jmp (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) +d "jmp (a0, d0.w)" 4ef00100 0x0 (jmp (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) +d "jmp ([0x18001ff, a0], 0x8000fff)" 4ef0017f018001ff08000fff 0x0 (jmp (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) +d "jmp 0x0.w" 4ef80000 0x0 (jmp (bv 32 0x0)) +d "jmp 0x1.l" 4ef900000001 0x0 (jmp (bv 32 0x1)) +d "jmp 0x2(pc)" 4efa0000 0x0 (jmp (bv 32 0x2)) +d "jmp 0x2(pc, d0.w)" 4efb0000 0x0 (jmp (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))) +d "jmp ([0x1800201, pc], 0x8000fff)" 4efb017f018001ff08000fff 0x0 (jmp (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff))) +d "addq.b 0x8, d0" 5000 0x0 (seq (set src (bv 8 0x8)) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, (a0)" 5010 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, (a0)+" 5018 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, -(a0)" 5020 0x0 (seq (set src (bv 8 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, 0x0(a0)" 50280000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, 0x0(a0, d0.w)" 50300000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, (a0, d0.w)" 50300100 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, ([0x18001ff, a0], 0x8000fff)" 5030017f018001ff08000fff 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, 0x0.w" 50380000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.b 0x8, 0x1.l" 503900000001 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, a0" 5048 0x0 (seq (set src_raw (bv 16 0x8)) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (+ (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "addq.w 0x8, (a0)" 5050 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, (a0)+" 5058 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, -(a0)" 5060 0x0 (seq (set src (bv 16 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, 0x0(a0)" 50680000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, 0x0(a0, d0.w)" 50700000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, (a0, d0.w)" 50700100 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, ([0x18001ff, a0], 0x8000fff)" 5070017f018001ff08000fff 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, 0x0.w" 50780000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.w 0x8, 0x1.l" 507900000001 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, d0" 5080 0x0 (seq (set src (bv 32 0x8)) (set dst (var d0)) (set res (+ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, a0" 5088 0x0 (seq (set src (bv 32 0x8)) (set dst (var a0)) (set res (+ (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "addq.l 0x8, (a0)" 5090 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, (a0)+" 5098 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, -(a0)" 50a0 0x0 (seq (set src (bv 32 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, 0x0(a0)" 50a80000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, 0x0(a0, d0.w)" 50b00000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, (a0, d0.w)" 50b00100 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, ([0x18001ff, a0], 0x8000fff)" 50b0017f018001ff08000fff 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, 0x0.w" 50b80000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addq.l 0x8, 0x1.l" 50b900000001 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (+ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "st.b (a0)" 50d0 0x0 (storew 0 (var a0) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b (a0)+" 50d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "st.b -(a0)" 50e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0))))) +d "st.b 0x0(a0)" 50e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b 0x0(a0, d0.w)" 50f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b (a0, d0.w)" 50f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b ([0x18001ff, a0], 0x8000fff)" 50f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b 0x0.w" 50f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "st.b 0x1.l" 50f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite true (bv 8 0xff) (bv 8 0x0)))) +d "subq.b 0x8, d0" 5100 0x0 (seq (set src (bv 8 0x8)) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, (a0)" 5110 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, (a0)+" 5118 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, -(a0)" 5120 0x0 (seq (set src (bv 8 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, 0x0(a0)" 51280000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, 0x0(a0, d0.w)" 51300000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, (a0, d0.w)" 51300100 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, ([0x18001ff, a0], 0x8000fff)" 5130017f018001ff08000fff 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, 0x0.w" 51380000 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.b 0x8, 0x1.l" 513900000001 0x0 (seq (set src (bv 8 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, a0" 5148 0x0 (seq (set src_raw (bv 16 0x8)) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "subq.w 0x8, (a0)" 5150 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, (a0)+" 5158 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, -(a0)" 5160 0x0 (seq (set src (bv 16 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, 0x0(a0)" 51680000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, 0x0(a0, d0.w)" 51700000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, (a0, d0.w)" 51700100 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, ([0x18001ff, a0], 0x8000fff)" 5170017f018001ff08000fff 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, 0x0.w" 51780000 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.w 0x8, 0x1.l" 517900000001 0x0 (seq (set src (bv 16 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, d0" 5180 0x0 (seq (set src (bv 32 0x8)) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, a0" 5188 0x0 (seq (set src (bv 32 0x8)) (set dst (var a0)) (set res (- (var dst) (var src))) (set a0 (cast 32 false (var res)))) +d "subq.l 0x8, (a0)" 5190 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, (a0)+" 5198 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, -(a0)" 51a0 0x0 (seq (set src (bv 32 0x8)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, 0x0(a0)" 51a80000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, 0x0(a0, d0.w)" 51b00000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, (a0, d0.w)" 51b00100 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, ([0x18001ff, a0], 0x8000fff)" 51b0017f018001ff08000fff 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, 0x0.w" 51b80000 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x8, 0x1.l" 51b900000001 0x0 (seq (set src (bv 32 0x8)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sf.b (a0)" 51d0 0x0 (storew 0 (var a0) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b (a0)+" 51d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "sf.b -(a0)" 51e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0))))) +d "sf.b 0x0(a0)" 51e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b 0x0(a0, d0.w)" 51f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b (a0, d0.w)" 51f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b ([0x18001ff, a0], 0x8000fff)" 51f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b 0x0.w" 51f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "sf.b 0x1.l" 51f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite false (bv 8 0xff) (bv 8 0x0)))) +d "shi.b (a0)" 52d0 0x0 (storew 0 (var a0) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b (a0)+" 52d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "shi.b -(a0)" 52e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0))))) +d "shi.b 0x0(a0)" 52e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b 0x0(a0, d0.w)" 52f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b (a0, d0.w)" 52f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b ([0x18001ff, a0], 0x8000fff)" 52f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b 0x0.w" 52f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "shi.b 0x1.l" 52f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b (a0)" 53d0 0x0 (storew 0 (var a0) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b (a0)+" 53d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "sls.b -(a0)" 53e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0))))) +d "sls.b 0x0(a0)" 53e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b 0x0(a0, d0.w)" 53f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b (a0, d0.w)" 53f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b ([0x18001ff, a0], 0x8000fff)" 53f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b 0x0.w" 53f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sls.b 0x1.l" 53f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b (a0)" 54d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b (a0)+" 54d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "scc.b -(a0)" 54e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0))))) +d "scc.b 0x0(a0)" 54e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b 0x0(a0, d0.w)" 54f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b (a0, d0.w)" 54f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b ([0x18001ff, a0], 0x8000fff)" 54f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b 0x0.w" 54f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scc.b 0x1.l" 54f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b (a0)" 55d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b (a0)+" 55d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "scs.b -(a0)" 55e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0))))) +d "scs.b 0x0(a0)" 55e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b 0x0(a0, d0.w)" 55f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b (a0, d0.w)" 55f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b ([0x18001ff, a0], 0x8000fff)" 55f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b 0x0.w" 55f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "scs.b 0x1.l" 55f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b (a0)" 56d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b (a0)+" 56d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "sne.b -(a0)" 56e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0))))) +d "sne.b 0x0(a0)" 56e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b 0x0(a0, d0.w)" 56f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b (a0, d0.w)" 56f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b ([0x18001ff, a0], 0x8000fff)" 56f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b 0x0.w" 56f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "sne.b 0x1.l" 56f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b (a0)" 57d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b (a0)+" 57d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "seq.b -(a0)" 57e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0))))) +d "seq.b 0x0(a0)" 57e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b 0x0(a0, d0.w)" 57f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b (a0, d0.w)" 57f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b ([0x18001ff, a0], 0x8000fff)" 57f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b 0x0.w" 57f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "seq.b 0x1.l" 57f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b (a0)" 58d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b (a0)+" 58d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "svc.b -(a0)" 58e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0))))) +d "svc.b 0x0(a0)" 58e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b 0x0(a0, d0.w)" 58f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b (a0, d0.w)" 58f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b ([0x18001ff, a0], 0x8000fff)" 58f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b 0x0.w" 58f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svc.b 0x1.l" 58f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b (a0)" 59d0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b (a0)+" 59d8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "svs.b -(a0)" 59e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0))))) +d "svs.b 0x0(a0)" 59e80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b 0x0(a0, d0.w)" 59f00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b (a0, d0.w)" 59f00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b ([0x18001ff, a0], 0x8000fff)" 59f0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b 0x0.w" 59f80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "svs.b 0x1.l" 59f900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b (a0)" 5ad0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b (a0)+" 5ad8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "spl.b -(a0)" 5ae0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0))))) +d "spl.b 0x0(a0)" 5ae80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b 0x0(a0, d0.w)" 5af00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b (a0, d0.w)" 5af00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b ([0x18001ff, a0], 0x8000fff)" 5af0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b 0x0.w" 5af80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "spl.b 0x1.l" 5af900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b (a0)" 5bd0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b (a0)+" 5bd8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "smi.b -(a0)" 5be0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0))))) +d "smi.b 0x0(a0)" 5be80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b 0x0(a0, d0.w)" 5bf00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b (a0, d0.w)" 5bf00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b ([0x18001ff, a0], 0x8000fff)" 5bf0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b 0x0.w" 5bf80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "smi.b 0x1.l" 5bf900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b (a0)" 5cd0 0x0 (storew 0 (var a0) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b (a0)+" 5cd8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "sge.b -(a0)" 5ce0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0))))) +d "sge.b 0x0(a0)" 5ce80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b 0x0(a0, d0.w)" 5cf00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b (a0, d0.w)" 5cf00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b ([0x18001ff, a0], 0x8000fff)" 5cf0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b 0x0.w" 5cf80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "sge.b 0x1.l" 5cf900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b (a0)" 5dd0 0x0 (storew 0 (var a0) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b (a0)+" 5dd8 0x0 (seq (storew 0 (var a0) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) +d "slt.b -(a0)" 5de0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0))))) +d "slt.b 0x0(a0)" 5de80000 0x0 (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b 0x0(a0, d0.w)" 5df00000 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b (a0, d0.w)" 5df00100 0x0 (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b ([0x18001ff, a0], 0x8000fff)" 5df0017f018001ff08000fff 0x0 (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b 0x0.w" 5df80000 0x0 (storew 0 (bv 32 0x0) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "slt.b 0x1.l" 5df900000001 0x0 (storew 0 (bv 32 0x1) (cast 8 false (ite (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (bv 8 0xff) (bv 8 0x0)))) +d "sgt.b (a0)" 5ed0 0x0 (storew 0 (var a0) (cast 8 false (ite (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! 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(bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b 0x0.w, d0" 80380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b 0x1.l, d0" 803900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b 0x2(pc), d0" 803a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b 0x2(pc, d0.w), d0" 803b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b ([0x1800201, pc], 0x8000fff), d0" 803b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b 0x0, d0" 803c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w (a0), d0" 8050 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w (a0)+, d0" 8058 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w -(a0), d0" 8060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x0(a0), d0" 80680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x0(a0, d0.w), d0" 80700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w (a0, d0.w), d0" 80700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w ([0x18001ff, a0], 0x8000fff), d0" 8070017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x0.w, d0" 80780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x1.l, d0" 807900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x2(pc), d0" 807a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x2(pc, d0.w), d0" 807b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w ([0x1800201, pc], 0x8000fff), d0" 807b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w 0x0, d0" 807c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, d0" 8080 0x0 (seq (set src (var d0)) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l (a0), d0" 8090 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l (a0)+, d0" 8098 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l -(a0), d0" 80a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x0(a0), d0" 80a80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x0(a0, d0.w), d0" 80b00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l (a0, d0.w), d0" 80b00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l ([0x18001ff, a0], 0x8000fff), d0" 80b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x0.w, d0" 80b80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x1.l, d0" 80b900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x2(pc), d0" 80ba0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x2(pc, d0.w), d0" 80bb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l ([0x1800201, pc], 0x8000fff), d0" 80bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l 0x1, d0" 80bc00000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (| (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "divu.w d0, d0" 80c0 0x0 (seq (set src (cast 16 false (var d0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w (a0), d0" 80d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w (a0)+, d0" 80d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w -(a0), d0" 80e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x0(a0), d0" 80e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x0(a0, d0.w), d0" 80f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w (a0, d0.w), d0" 80f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w ([0x18001ff, a0], 0x8000fff), d0" 80f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x0.w, d0" 80f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x1.l, d0" 80f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x2(pc), d0" 80fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x2(pc, d0.w), d0" 80fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w ([0x1800201, pc], 0x8000fff), d0" 80fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.w 0x0, d0" 80fc0000 0x0 (seq (set src (bv 16 0x0)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "sbcd.b d0, d0" 8100 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set src_dec (+ (* (cast 32 false (>> (& (var src) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var src) (bv 8 0xf))))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (- (var dst_dec) (var src_dec)) (var x))) (set res_dec (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sbcd.b -(a0), -(a0)" 8108 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set src_dec (+ (* (cast 32 false (>> (& (var src) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var src) (bv 8 0xf))))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set diff (- (- (var dst_dec) (var src_dec)) (var x))) (set res_dec (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (+ (var diff) (bv 32 0x64)) (var diff))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (sle (var diff) (bv 32 0x0)) (! (== (var diff) (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "or.b d0, (a0)" 8110 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, (a0)+" 8118 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, -(a0)" 8120 0x0 (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, 0x0(a0)" 81280000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, 0x0(a0, d0.w)" 81300000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, (a0, d0.w)" 81300100 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, ([0x18001ff, a0], 0x8000fff)" 8130017f018001ff08000fff 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, 0x0.w" 81380000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.b d0, 0x1.l" 813900000001 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, (a0)" 8150 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, (a0)+" 8158 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, -(a0)" 8160 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, 0x0(a0)" 81680000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, 0x0(a0, d0.w)" 81700000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, (a0, d0.w)" 81700100 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, ([0x18001ff, a0], 0x8000fff)" 8170017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, 0x0.w" 81780000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, 0x1.l" 817900000001 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, (a0)" 8190 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, (a0)+" 8198 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, -(a0)" 81a0 0x0 (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, 0x0(a0)" 81a80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, 0x0(a0, d0.w)" 81b00000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, (a0, d0.w)" 81b00100 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, ([0x18001ff, a0], 0x8000fff)" 81b0017f018001ff08000fff 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, 0x0.w" 81b80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.l d0, 0x1.l" 81b900000001 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (| (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "divs.w d0, d0" 81c0 0x0 (seq (set src (cast 16 false (var d0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w (a0), d0" 81d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w (a0)+, d0" 81d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w -(a0), d0" 81e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x0(a0), d0" 81e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x0(a0, d0.w), d0" 81f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w (a0, d0.w), d0" 81f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w ([0x18001ff, a0], 0x8000fff), d0" 81f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x0.w, d0" 81f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x1.l, d0" 81f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x2(pc), d0" 81fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x2(pc, d0.w), d0" 81fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w ([0x1800201, pc], 0x8000fff), d0" 81fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.w 0x0, d0" 81fc0000 0x0 (seq (set src (bv 16 0x0)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffffffff8000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 16 false (bv 16 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d0 (cast 32 false (| (<< (cast 32 false (var rem)) (bv 8 0x10) false) (cast 32 false (cast 16 false (var quot)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 16 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "sub.b d0, d0" 9000 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b (a0), d0" 9010 0x0 (seq (set src (loadw 0 8 (var a0))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b (a0)+, d0" 9018 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b -(a0), d0" 9020 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b 0x0(a0), d0" 90280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b 0x0(a0, d0.w), d0" 90300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b (a0, d0.w), d0" 90300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b ([0x18001ff, a0], 0x8000fff), d0" 9030017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b 0x0.w, d0" 90380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w 0x2(pc, d0.w), d0" 907b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w ([0x1800201, pc], 0x8000fff), d0" 907b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w 0x0, d0" 907c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l a0, d0" 9088 0x0 (seq (set src (var a0)) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l (a0)+, d0" 9098 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l -(a0), d0" 90a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l 0x0(a0), d0" 90a80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l 0x0(a0, d0.w), d0" 90b00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l (a0, d0.w), d0" 90b00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b d0, (a0, d0.w)" 91300100 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.b d0, 0x0.w" 91380000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subx.w d0, d0" 9140 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 16 0x1) (bv 16 0x0))) (set srcx (+ (var src) (var x))) (set res (- (var dst) (var srcx))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 16 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0xffffffffffff8000)) (! (== (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0xffffffffffff8000)))) (! (sle (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))) (! (== (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))) (! (== (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subx.w -(a0), -(a0)" 9148 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 16 0x1) (bv 16 0x0))) (set srcx (+ (var src) (var x))) (set res (- (var dst) (var srcx))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 16 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0xffffffffffff8000)) (! (== (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0xffffffffffff8000)))) (! (sle (- (- (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (cast 64 false (var x))) (bv 64 0x7fff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))) (! (== (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))) (! (== (cast 64 false (var dst)) (+ (cast 64 false (var src)) (cast 64 false (var x)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, (a0)" 9150 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, (a0)+" 9158 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, -(a0)" 9160 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, 0x0(a0)" 91680000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, 0x0(a0, d0.w)" 91700000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, (a0, d0.w)" 91700100 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, ([0x18001ff, a0], 0x8000fff)" 9170017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.w d0, 0x0.w" 91780000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, -(a0)" 91a0 0x0 (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, 0x0(a0)" 91a80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, 0x0(a0, d0.w)" 91b00000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, (a0, d0.w)" 91b00100 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, ([0x18001ff, a0], 0x8000fff)" 91b0017f018001ff08000fff 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "sub.l d0, 0x0.w" 91b80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.b 0x0, d0" b03c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w a0, d0" b048 0x0 (seq (set src (cast 16 false (var a0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w (a0), d0" b050 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w (a0)+, d0" b058 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w -(a0), d0" b060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x0(a0), d0" b0680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x0(a0, d0.w), d0" b0700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w (a0, d0.w), d0" b0700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w ([0x18001ff, a0], 0x8000fff), d0" b070017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x0.w, d0" b0780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x1.l, d0" b07900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x2(pc), d0" b07a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x2(pc, d0.w), d0" b07b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w ([0x1800201, pc], 0x8000fff), d0" b07b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.w 0x0, d0" b07c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l d0, d0" b080 0x0 (seq (set src (var d0)) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l a0, d0" b088 0x0 (seq (set src (var a0)) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l (a0), d0" b090 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l (a0)+, d0" b098 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l -(a0), d0" b0a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x0(a0), d0" b0a80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x0(a0, d0.w), d0" b0b00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l (a0, d0.w), d0" b0b00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l ([0x18001ff, a0], 0x8000fff), d0" b0b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x0.w, d0" b0b80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x1.l, d0" b0b900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x2(pc), d0" b0ba0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x2(pc, d0.w), d0" b0bb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l ([0x1800201, pc], 0x8000fff), d0" b0bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmp.l 0x1, d0" b0bc00000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w d0, a0" b0c0 0x0 (seq (set src_raw (cast 16 false (var d0))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w a0, a0" b0c8 0x0 (seq (set src_raw (cast 16 false (var a0))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w (a0), a0" b0d0 0x0 (seq (set src_raw (loadw 0 16 (var a0))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w (a0)+, a0" b0d8 0x0 (seq (set src_raw (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w -(a0), a0" b0e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src_raw (loadw 0 16 (var a0))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x0(a0), a0" b0e80000 0x0 (seq (set src_raw (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x0(a0, d0.w), a0" b0f00000 0x0 (seq (set src_raw (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w (a0, d0.w), a0" b0f00100 0x0 (seq (set src_raw (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w ([0x18001ff, a0], 0x8000fff), a0" b0f0017f018001ff08000fff 0x0 (seq (set src_raw (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x0.w, a0" b0f80000 0x0 (seq (set src_raw (loadw 0 16 (bv 32 0x0))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x1.l, a0" b0f900000001 0x0 (seq (set src_raw (loadw 0 16 (bv 32 0x1))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x2(pc), a0" b0fa0000 0x0 (seq (set src_raw (loadw 0 16 (bv 32 0x2))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x2(pc, d0.w), a0" b0fb0000 0x0 (seq (set src_raw (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w ([0x1800201, pc], 0x8000fff), a0" b0fb017f018001ff08000fff 0x0 (seq (set src_raw (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.w 0x0, a0" b0fc0000 0x0 (seq (set src_raw (bv 16 0x0)) (set src (cast 32 (msb (var src_raw)) (var src_raw))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, d0" b100 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpm.b (a0)+, (a0)+" b108 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, (a0)" b110 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, (a0)+" b118 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, -(a0)" b120 0x0 (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, 0x0(a0)" b1280000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, 0x0(a0, d0.w)" b1300000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, (a0, d0.w)" b1300100 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, ([0x18001ff, a0], 0x8000fff)" b130017f018001ff08000fff 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, 0x0.w" b1380000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.b d0, 0x1.l" b13900000001 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, (a0)" b150 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, (a0)+" b158 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, -(a0)" b160 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, 0x0(a0)" b1680000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, 0x0(a0, d0.w)" b1700000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, (a0, d0.w)" b1700100 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, ([0x18001ff, a0], 0x8000fff)" b170017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, 0x0.w" b1780000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, 0x1.l" b17900000001 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, d0" b180 0x0 (seq (set src (var d0)) (set dst (var d0)) (set res (^ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpm.l (a0)+, (a0)+" b188 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, (a0)" b190 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, (a0)+" b198 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, -(a0)" b1a0 0x0 (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, 0x0(a0)" b1a80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, 0x0(a0, d0.w)" b1b00000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, (a0, d0.w)" b1b00100 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, ([0x18001ff, a0], 0x8000fff)" b1b0017f018001ff08000fff 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, 0x0.w" b1b80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.l d0, 0x1.l" b1b900000001 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (^ (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l a0, a0" b1c8 0x0 (seq (set src (var a0)) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l (a0), a0" b1d0 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l (a0)+, a0" b1d8 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l -(a0), a0" b1e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x0(a0), a0" b1e80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x0(a0, d0.w), a0" b1f00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l (a0, d0.w), a0" b1f00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l ([0x18001ff, a0], 0x8000fff), a0" b1f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x0.w, a0" b1f80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x1.l, a0" b1f900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x2(pc), a0" b1fa0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x2(pc, d0.w), a0" b1fb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l ([0x1800201, pc], 0x8000fff), a0" b1fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpa.l 0x1, a0" b1fc00000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var a0)) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, d0" c000 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b (a0), d0" c010 0x0 (seq (set src (loadw 0 8 (var a0))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b (a0)+, d0" c018 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b -(a0), d0" c020 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x0(a0), d0" c0280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x0(a0, d0.w), d0" c0300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b (a0, d0.w), d0" c0300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b ([0x18001ff, a0], 0x8000fff), d0" c030017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x0.w, d0" c0380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x1.l, d0" c03900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x2(pc), d0" c03a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x2(pc, d0.w), d0" c03b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b ([0x1800201, pc], 0x8000fff), d0" c03b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b 0x0, d0" c03c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w (a0), d0" c050 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w (a0)+, d0" c058 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w -(a0), d0" c060 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x0(a0), d0" c0680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x0(a0, d0.w), d0" c0700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w (a0, d0.w), d0" c0700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w ([0x18001ff, a0], 0x8000fff), d0" c070017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x0.w, d0" c0780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x1.l, d0" c07900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x2(pc), d0" c07a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x2(pc, d0.w), d0" c07b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w ([0x1800201, pc], 0x8000fff), d0" c07b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w 0x0, d0" c07c0000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, d0" c080 0x0 (seq (set src (var d0)) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l (a0), d0" c090 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l (a0)+, d0" c098 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l -(a0), d0" c0a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x0(a0), d0" c0a80000 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x0(a0, d0.w), d0" c0b00000 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l (a0, d0.w), d0" c0b00100 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l ([0x18001ff, a0], 0x8000fff), d0" c0b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x0.w, d0" c0b80000 0x0 (seq (set src (loadw 0 32 (bv 32 0x0))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x1.l, d0" c0b900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x2(pc), d0" c0ba0000 0x0 (seq (set src (loadw 0 32 (bv 32 0x2))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x2(pc, d0.w), d0" c0bb0000 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l ([0x1800201, pc], 0x8000fff), d0" c0bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l 0x1, d0" c0bc00000001 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (& (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w (a0), d0" c0d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w (a0)+, d0" c0d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w -(a0), d0" c0e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x0(a0), d0" c0e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x0(a0, d0.w), d0" c0f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w (a0, d0.w), d0" c0f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w ([0x18001ff, a0], 0x8000fff), d0" c0f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x0.w, d0" c0f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x1.l, d0" c0f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x2(pc), d0" c0fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x2(pc, d0.w), d0" c0fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w ([0x1800201, pc], 0x8000fff), d0" c0fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w 0x0, d0" c0fc0000 0x0 (seq (set src (bv 16 0x0)) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "abcd.b d0, d0" c100 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set src_dec (+ (* (cast 32 false (>> (& (var src) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var src) (bv 8 0xf))))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set sum (+ (+ (var dst_dec) (var src_dec)) (var x))) (set res_dec (mod (var sum) (bv 32 0x64))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (ule (var sum) (bv 32 0x63))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (ule (var sum) (bv 32 0x63))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "abcd.b -(a0), -(a0)" c108 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set src_dec (+ (* (cast 32 false (>> (& (var src) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var src) (bv 8 0xf))))) (set dst_dec (+ (* (cast 32 false (>> (& (var dst) (bv 8 0xf0)) (bv 8 0x4) false)) (bv 32 0xa)) (cast 32 false (& (var dst) (bv 8 0xf))))) (set x (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 32 0x1) (bv 32 0x0))) (set sum (+ (+ (var dst_dec) (var src_dec)) (var x))) (set res_dec (mod (var sum) (bv 32 0x64))) (set res (cast 8 false (| (<< (div (cast 32 false (var res_dec)) (bv 32 0xa)) (bv 8 0x4) false) (mod (cast 32 false (var res_dec)) (bv 32 0xa))))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xea)) (bv 8 0xfb)) (<< (ite (&& (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (is_zero (cast 8 false (var res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (ule (var sum) (bv 32 0x63))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (! (ule (var sum) (bv 32 0x63))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "and.b d0, (a0)" c110 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, (a0)+" c118 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, -(a0)" c120 0x0 (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, 0x0(a0)" c1280000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, 0x0(a0, d0.w)" c1300000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, (a0, d0.w)" c1300100 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, ([0x18001ff, a0], 0x8000fff)" c130017f018001ff08000fff 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, 0x0.w" c1380000 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.b d0, 0x1.l" c13900000001 0x0 (seq (set src (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 8 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "exg.l a0, a0" c148 0x0 (seq (set tmp (var a0)) (set a0 (cast 32 false (var a0))) (set a0 (cast 32 false (var tmp)))) +d "and.w d0, (a0)" c150 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, (a0)+" c158 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, -(a0)" c160 0x0 (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, 0x0(a0)" c1680000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, 0x0(a0, d0.w)" c1700000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, (a0, d0.w)" c1700100 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, ([0x18001ff, a0], 0x8000fff)" c170017f018001ff08000fff 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, 0x0.w" c1780000 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, 0x1.l" c17900000001 0x0 (seq (set src (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, (a0)" c190 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, (a0)+" c198 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, -(a0)" c1a0 0x0 (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, 0x0(a0)" c1a80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, 0x0(a0, d0.w)" c1b00000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, (a0, d0.w)" c1b00100 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, ([0x18001ff, a0], 0x8000fff)" c1b0017f018001ff08000fff 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, 0x0.w" c1b80000 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.l d0, 0x1.l" c1b900000001 0x0 (seq (set src (var d0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (& (var dst) (var src))) (storew 0 (var dst_addr) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w (a0), d0" c1d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w (a0)+, d0" c1d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w -(a0), d0" c1e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x0(a0), d0" c1e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x0(a0, d0.w), d0" c1f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w (a0, d0.w), d0" c1f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w ([0x18001ff, a0], 0x8000fff), d0" c1f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x0.w, d0" c1f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x1.l, d0" c1f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x2(pc), d0" c1fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x2(pc, d0.w), d0" c1fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w ([0x1800201, pc], 0x8000fff), d0" c1fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w 0x0, d0" c1fc0000 0x0 (seq (set src (bv 16 0x0)) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "add.b d0, d0" d000 0x0 (seq (set src (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b ([0x18001ff, a0], 0x8000fff), d0" d030017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! 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(== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b 0x0.w, d0" d0380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b 0x1.l, d0" d03900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b 0x2(pc), d0" d03a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b 0x2(pc, d0.w), d0" d03b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b ([0x1800201, pc], 0x8000fff), d0" d03b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.b 0x0, d0" d03c0000 0x0 (seq (set src (bv 8 0x0)) (set dst (cast 8 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w a0, d0" d048 0x0 (seq (set src (cast 16 false (var a0))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w (a0), d0" d050 0x0 (seq (set src (loadw 0 16 (var a0))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! 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(== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! 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(== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w 0x1.l, d0" d07900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! 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(== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w 0x2(pc), d0" d07a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w 0x2(pc, d0.w), d0" d07b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "add.w ([0x1800201, pc], 0x8000fff), d0" d07b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! 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(is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 8 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x9) (var rot_count)) false)))) (set res (cast 8 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.b 0x8, d0" e018 0x0 (seq (set count (bv 8 0x8)) (set dst (cast 8 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x8))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x8) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asr.b d0, d0" e020 0x0 (seq (set count (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x8))) (== (var count8) (bv 8 0x8))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x8)) (! (== (var count8) (bv 8 0x8)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 8 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x8))) (== (var count8) (bv 8 0x8))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x8)) (! (== (var count8) (bv 8 0x8)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 8 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.b d0, d0" e028 0x0 (seq (set count (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 8 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 8 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.b d0, d0" e030 0x0 (seq (set count (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x9))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 8 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x9) (var rot_count)) false)))) (set res (cast 8 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.b d0, d0" e038 0x0 (seq (set count (cast 8 false (var d0))) (set dst (cast 8 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x8))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x8) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "roxr.w 0x8, d0" e050 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.w 0x8, d0" e058 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asr.w d0, d0" e060 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w d0, d0" e068 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w d0, d0" e070 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.w d0, d0" e078 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asr.l 0x8, d0" e080 0x0 (seq (set count (bv 32 0x8)) (set dst (var d0)) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x20))) (== (var count8) (bv 8 0x20))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x20)) (! (== (var count8) (bv 8 0x20)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x20))) (== (var count8) (bv 8 0x20))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x20)) (! (== (var count8) (bv 8 0x20)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.l 0x8, d0" e088 0x0 (seq (set count (bv 32 0x8)) (set dst (var d0)) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.l 0x8, d0" e090 0x0 (seq (set count (bv 32 0x8)) (set dst (var d0)) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x21))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 32 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x21) (var rot_count)) false)))) (set res (cast 32 false (var wide_res))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.l 0x8, d0" e098 0x0 (seq (set count (bv 32 0x8)) (set dst (var d0)) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x20))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x20) (var rot_count)) false)))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asr.l d0, d0" e0a0 0x0 (seq (set count (var d0)) (set dst (var d0)) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x20))) (== (var count8) (bv 8 0x20))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x20)) (! (== (var count8) (bv 8 0x20)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x20))) (== (var count8) (bv 8 0x20))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x20)) (! (== (var count8) (bv 8 0x20)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.l d0, d0" e0a8 0x0 (seq (set count (var d0)) (set dst (var d0)) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 32 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.l d0, d0" e0b0 0x0 (seq (set count (var d0)) (set dst (var d0)) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x21))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 32 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x21) (var rot_count)) false)))) (set res (cast 32 false (var wide_res))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.l d0, d0" e0b8 0x0 (seq (set count (var d0)) (set dst (var d0)) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x20))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x20) (var rot_count)) false)))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asr.w (a0)" e0d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w (a0)+" e0d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w -(a0)" e0e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w 0x0(a0)" e0e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w 0x0(a0, d0.w)" e0f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w (a0, d0.w)" e0f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w ([0x18001ff, a0], 0x8000fff)" e0f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! 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(is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! 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(is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! 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(is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "rol.w 0x8, d0" e158 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asl.w d0, d0" e160 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| false (&& (|| (! (ule (var count8) (bv 8 0x1))) (== (var count8) (bv 8 0x1))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xe) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x2))) (== (var count8) (bv 8 0x2))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xd) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x3))) (== (var count8) (bv 8 0x3))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xc) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x4))) (== (var count8) (bv 8 0x4))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xb) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x5))) (== (var count8) (bv 8 0x5))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xa) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! 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(is_zero (& (>> (var dst) (bv 8 0x5) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xb))) (== (var count8) (bv 8 0xb))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x4) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xc))) (== (var count8) (bv 8 0xc))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x3) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xd))) (== (var count8) (bv 8 0xd))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x2) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xe))) (== (var count8) (bv 8 0xe))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xf))) (== (var count8) (bv 8 0xf))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x0) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite false (bv 1 0x1) (bv 1 0x0)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w d0, d0" e168 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w d0, d0" e170 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "rol.w d0, d0" e178 0x0 (seq (set count (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "asl.l 0x8, d0" e180 0x0 (seq (set count (bv 32 0x8)) (set dst (var d0)) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| false (&& (|| (! (ule (var count8) (bv 8 0x1))) (== (var count8) (bv 8 0x1))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1e) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x2))) (== (var count8) (bv 8 0x2))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1d) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x3))) (== (var count8) (bv 8 0x3))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1c) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x4))) (== (var count8) (bv 8 0x4))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1b) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x5))) (== (var count8) (bv 8 0x5))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1a) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! 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(is_zero (& (>> (var dst) (bv 8 0x15) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xb))) (== (var count8) (bv 8 0xb))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x14) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xc))) (== (var count8) (bv 8 0xc))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x13) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xd))) (== (var count8) (bv 8 0xd))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x12) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xe))) (== (var count8) (bv 8 0xe))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x11) false) (bv 32 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! 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(is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x0(a0)" e2e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x0(a0, d0.w)" e2f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w (a0, d0.w)" e2f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w ([0x18001ff, a0], 0x8000fff)" e2f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x0.w" e2f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x1.l" e2f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w (a0)" e3d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w (a0)+" e3d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w -(a0)" e3e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x0(a0)" e3e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x0(a0, d0.w)" e3f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w (a0, d0.w)" e3f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w ([0x18001ff, a0], 0x8000fff)" e3f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x0.w" e3f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x1.l" e3f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w (a0)" e4d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w (a0)+" e4d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w -(a0)" e4e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w 0x0(a0)" e4e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w 0x0(a0, d0.w)" e4f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w (a0, d0.w)" e4f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w ([0x18001ff, a0], 0x8000fff)" e4f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w 0x0.w" e4f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxr.w 0x1.l" e4f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (>> (var wide) (var rot_count) false) (<< (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w (a0)" e5d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w (a0)+" e5d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w -(a0)" e5e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w 0x0(a0)" e5e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w 0x0(a0, d0.w)" e5f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w (a0, d0.w)" e5f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w ([0x18001ff, a0], 0x8000fff)" e5f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w 0x0.w" e5f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "roxl.w 0x1.l" e5f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x11))) (set wide (append (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10)))) (bv 1 0x1) (bv 1 0x0)) (cast 16 false (var dst)))) (set wide_res (ite (is_zero (var rot_count)) (var wide) (| (<< (var wide) (var rot_count) false) (>> (var wide) (- (bv 8 0x11) (var rot_count)) false)))) (set res (cast 16 false (var wide_res))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (|| (&& (! (! (is_zero (var count_raw)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count_raw)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count_raw))) (msb (var wide_res)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "ror.w (a0)" e6d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w (a0)+" e6d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w -(a0)" e6e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w 0x0(a0)" e6e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w 0x0(a0, d0.w)" e6f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w (a0, d0.w)" e6f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w ([0x18001ff, a0], 0x8000fff)" e6f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w 0x0.w" e6f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "ror.w 0x1.l" e6f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (>> (var dst) (var rot_count) false) (<< (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (msb (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w (a0)" e7d0 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w (a0)+" e7d8 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w -(a0)" e7e0 0x0 (seq (set count (bv 8 0x1)) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w 0x0(a0)" e7e80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w 0x0(a0, d0.w)" e7f00000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w (a0, d0.w)" e7f00100 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w ([0x18001ff, a0], 0x8000fff)" e7f0017f018001ff08000fff 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w 0x0.w" e7f80000 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x0))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rol.w 0x1.l" e7f900000001 0x0 (seq (set count (bv 8 0x1)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set count_raw (& (cast 8 false (var count)) (bv 8 0x3f))) (set rot_count (mod (var count_raw) (bv 8 0x10))) (set res (ite (is_zero (var rot_count)) (var dst) (| (<< (var dst) (var rot_count) false) (>> (var dst) (- (bv 8 0x10) (var rot_count)) false)))) (storew 0 (var dst_addr) (cast 16 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count_raw))) (! (is_zero (& (var res) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (var a0))) (set a0 (cast 32 false (var addr)))) +d "link.w a0, 0x4" 4e500004 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x4))) (set a7 (cast 32 false (var new_sp)))) +d "unlk a0" 4e58 0x0 (seq (set a7 (cast 32 false (var a0))) (set old (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (set a0 (cast 32 false (var old)))) +d "move.w 0x100, 0xa10000.l" 33fc010000a10000 +d "invalid" ff diff --git a/test/db/asm/m68k_68010_32 b/test/db/asm/m68k_68010_32 new file mode 100644 index 0000000000..3a18c92a81 --- /dev/null +++ b/test/db/asm/m68k_68010_32 @@ -0,0 +1,127 @@ +d "ori.w 0x0, d0" 00400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "andi.w 0x0, d0" 02400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "subi.w 0x0, d0" 04400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "addi.w 0x0, d0" 06400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "btst.b 0x0, 0x5(pc)" 083a00000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (bv 32 0x5))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "btst.b 0x0, 0x5(pc, d0.w)" 083b00000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false))))))) +d "eori.w 0x0, d0" 0a400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.b 0x0, 0x5(pc)" 0c3a00000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x5))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.b 0x0, 0x5(pc, d0.w)" 0c3b00000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.b 0xff, 0x4(pc, d0.w)" 0c3b00ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.b 0x0, ([0x1800203, pc], 0x8000fff)" 0c3b0100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0x0, d0" 0c400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0x0, 0x5(pc)" 0c7a00000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x5))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0x0, 0x5(pc, d0.w)" 0c7b00000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0xff, 0x4(pc, d0.w)" 0c7b00ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.w 0x100, ([0x1800203, pc], 0x8000fff)" 0c7b0100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.l 0x1, 0x16(pc)" 0cba000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x16))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.l 0x1, 0x16(pc, d0.w)" 0cbb000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (bv 32 0x16) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.l 0x8000ff, 0x6(pc, d0.w)" 0cbb008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (bv 32 0x6) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cmpi.l 0xff0100, ([0x1800205, pc], 0x8000fff)" 0cbb00ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800203))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "moves.b (a0), d0" 0e100000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, (a0)" 0e100800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b (a0)+, d0" 0e180000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, (a0)+" 0e180800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b -(a0), d0" 0e200000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, -(a0)" 0e200800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b 0x1(a0), d0" 0e2800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, 0xfff(a0)" 0e2808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b 0x1(a0, d0.w), d0" 0e3000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, ([0x10001fff], 0x20002fff)" 0e3008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b ([0x20002fff], 0x30003fff), d1" 0e3010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (| (& (var d1) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b (a0, a0.w), a0" 0e3080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (cast 32 (msb (var src)) (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b 0x1.w, d0" 0e3800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, 0xfff.w" 0e3808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b 0x10010.l, d0" 0e39000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (bv 32 0x10010)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.b d0, 0xfff1000.l" 0e3908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w (a0), d0" 0e500000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, (a0)" 0e500800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w (a0)+, d0" 0e580000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, (a0)+" 0e580800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w -(a0), d0" 0e600000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, -(a0)" 0e600800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w 0x1(a0), d0" 0e6800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, 0xfff(a0)" 0e6808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w 0x1(a0, d0.w), d0" 0e7000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, ([0x10001fff], 0x20002fff)" 0e7008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w ([0x20002fff], 0x30003fff), d1" 0e7010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (| (& (var d1) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w (a0, a0.w), a0" 0e7080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (cast 32 (msb (var src)) (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w 0x1.w, d0" 0e7800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, 0xfff.w" 0e7808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w 0x10010.l, d0" 0e79000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (bv 32 0x10010)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.w d0, 0xfff1000.l" 0e7908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l (a0), d0" 0e900000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (var a0)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, (a0)" 0e900800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l (a0)+, d0" 0e980000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, (a0)+" 0e980800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l -(a0), d0" 0ea00000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (cast 32 false (var a0)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, -(a0)" 0ea00800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l 0x1(a0), d0" 0ea800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, 0xfff(a0)" 0ea808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l 0x1(a0, d0.w), d0" 0eb000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, ([0x10001fff], 0x20002fff)" 0eb008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l ([0x20002fff], 0x30003fff), d1" 0eb010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l (a0, a0.w), a0" 0eb080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l 0x1.w, d0" 0eb800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (bv 32 0x1)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, 0xfff.w" 0eb808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l 0x10010.l, d0" 0eb9000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (bv 32 0x10010)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "moves.l d0, 0xfff1000.l" 0eb908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "move.l 0x1.l, d0" 203900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "lea.l 0x0(a0), a0" 41e80000 0x0 (set a0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) +d "bkpt 0x0" 4848 0x0 (seq (set trap_op (bv 32 0x1)) (set trap_arg (bv 32 0x0)) (goto m68k_trap)) +d "pea.l 0x0(a0)" 48680000 0x0 (seq (set push_value (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0)))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value)))) +d "link.w a0, 0x0" 4e500000 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x0))) (set a7 (cast 32 false (var new_sp)))) +d "unlk a0" 4e58 0x0 (seq (set a7 (cast 32 false (var a0))) (set old (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (set a0 (cast 32 false (var old)))) +d "rtd 0x0" 4e740000 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (jmp (var target))) +d "movec sfc, d0" 4e7a0000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set d0 (cast 32 false (var sfc))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "jsr 0x1.l" 4eb900000001 0x0 (seq (set target (bv 32 0x1)) (set push_value (bv 32 0x6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target))) +d "addq.w 0x8, d0" 5040 0x0 (seq (set src (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "dbt d0, 0x2" 50c80000 0x0 (branch true empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "subq.w 0x8, d0" 5140 0x0 (seq (set src (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "dbra d0, 0x2" 51c80000 0x0 (branch false empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbhi d0, 0x2" 52c80000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbls d0, 0x2" 53c80000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbcc d0, 0x2" 54c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbcs d0, 0x2" 55c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbne d0, 0x2" 56c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbeq d0, 0x2" 57c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbvc d0, 0x2" 58c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbvs d0, 0x2" 59c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbpl d0, 0x2" 5ac80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbmi d0, 0x2" 5bc80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbge d0, 0x2" 5cc80000 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dblt d0, 0x2" 5dc80000 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dbgt d0, 0x2" 5ec80000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "dble d0, 0x2" 5fc80000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty))) +d "bra.b 0x3" 6001 0x0 (jmp (bv 32 0x3)) +d "bsr.b 0x3" 6101 0x0 (seq (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x3))) +d "bhi.b 0x3" 6201 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (jmp (bv 32 0x3)) empty) +d "bls.b 0x3" 6301 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty) +d "bcc.b 0x3" 6401 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (jmp (bv 32 0x3)) empty) +d "bcs.b 0x3" 6501 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (jmp (bv 32 0x3)) empty) +d "bne.b 0x3" 6601 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty) +d "beq.b 0x3" 6701 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (jmp (bv 32 0x3)) empty) +d "bvc.b 0x3" 6801 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (jmp (bv 32 0x3)) empty) +d "bvs.b 0x3" 6901 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (jmp (bv 32 0x3)) empty) +d "bpl.b 0x3" 6a01 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (jmp (bv 32 0x3)) empty) +d "bmi.b 0x3" 6b01 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (jmp (bv 32 0x3)) empty) +d "bge.b 0x3" 6c01 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (jmp (bv 32 0x3)) empty) +d "blt.b 0x3" 6d01 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty) +d "bgt.b 0x3" 6e01 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty) +d "ble.b 0x3" 6f01 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (jmp (bv 32 0x3)) empty) +d "moveq 0x0, d0" 7000 0x0 (seq (set res (bv 32 0x0)) (set d0 (cast 32 false (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "or.w d0, d0" 8040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "sub.w d0, d0" 9040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "cmp.w d0, d0" b040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "eor.w d0, d0" b140 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "and.w d0, d0" c040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.w d0, d0" c0c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.w d0, d0" c1c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "add.w d0, d0" d040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asr.w 0x8, d0" e040 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsr.w 0x8, d0" e048 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "asl.w 0x8, d0" e140 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| false (&& (|| (! (ule (var count8) (bv 8 0x1))) (== (var count8) (bv 8 0x1))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xe) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x2))) (== (var count8) (bv 8 0x2))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xd) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x3))) (== (var count8) (bv 8 0x3))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xc) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x4))) (== (var count8) (bv 8 0x4))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xb) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x5))) (== (var count8) (bv 8 0x5))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xa) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x6))) (== (var count8) (bv 8 0x6))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x9) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x7))) (== (var count8) (bv 8 0x7))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x8) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x8))) (== (var count8) (bv 8 0x8))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x7) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x9))) (== (var count8) (bv 8 0x9))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x6) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xa))) (== (var count8) (bv 8 0xa))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x5) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xb))) (== (var count8) (bv 8 0xb))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x4) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xc))) (== (var count8) (bv 8 0xc))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x3) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xd))) (== (var count8) (bv 8 0xd))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x2) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xe))) (== (var count8) (bv 8 0xe))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xf))) (== (var count8) (bv 8 0xf))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x0) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite false (bv 1 0x1) (bv 1 0x0)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "lsl.w 0x8, d0" e148 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (== (var format) (bv 16 0x0)) (== (var format) (bv 16 0x8))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (var a0))) (set a0 (cast 32 false (var addr)))) +d "rtd 0x4" 4e740004 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x8)))) (jmp (var target))) diff --git a/test/db/asm/m68k_68020_32 b/test/db/asm/m68k_68020_32 index fdb77ed7f7..964ead1ec1 100644 --- a/test/db/asm/m68k_68020_32 +++ b/test/db/asm/m68k_68020_32 @@ -1,3 +1,653 @@ -d "bftst 0x9c.w{d0:32}" e8f80800009c -d "bftst 0x9c.w{20:5}" e8f80505009c -d "bftst 0x9c.w{d1:d0}" e8f80860009c +d "cmp2.b (a0), d0" 00d00000 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b (a0), d0" 00d00800 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b 0x1(a0), d0" 00e800000001 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b 0xfff(a0), d0" 00e808000fff 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b 0x1(a0, d0.w), d0" 00f000000001 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b ([0x10001fff], 0x20002fff), d0" 00f008000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b ([0x20002fff], 0x30003fff), d1" 00f010001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d1))) (cast 8 false (var d1)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.b (a0, a0.w), a0" 00f080008100 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.b 0x1.w, d0" 00f800000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b 0xfff.w, d0" 00f808000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b 0x10010.l, d0" 00f9000000010010 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x10010))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b 0xfff1000.l, d0" 00f908000fff1000 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff1000))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b 0x5(pc), d0" 00fa00000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x5))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b 0x1003(pc), d0" 00fa08000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1003))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b 0x5(pc, d0.w), d0" 00fb00000001 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.b ([0x10002003], 0x20002fff), d0" 00fb08000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.b ([0x20003003], 0x30003fff), d1" 00fb10001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (cast 32 (msb (cast 8 false (var d1))) (cast 8 false (var d1)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.b 0x4(pc, a0.w), a0" 00fb80008100 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (cast 32 (msb (loadw 0 8 (var bounds_addr))) (loadw 0 8 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1)))) (loadw 0 8 (+ (var bounds_addr) (bv 32 0x1))))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.w (a0), d0" 02d00000 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w (a0), d0" 02d00800 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w 0x1(a0), d0" 02e800000001 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w 0xfff(a0), d0" 02e808000fff 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w 0x1(a0, d0.w), d0" 02f000000001 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w ([0x10001fff], 0x20002fff), d0" 02f008000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w ([0x20002fff], 0x30003fff), d1" 02f010001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.w (a0, a0.w), a0" 02f080008100 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.w 0x1.w, d0" 02f800000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w 0xfff.w, d0" 02f808000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! 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(== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w 0xfff1000.l, d0" 02f908000fff1000 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff1000))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w 0x5(pc), d0" 02fa00000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x5))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w 0x1003(pc), d0" 02fa08000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1003))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w 0x5(pc, d0.w), d0" 02fb00000001 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.w ([0x10002003], 0x20002fff), d0" 02fb08000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.w ([0x20003003], 0x30003fff), d1" 02fb10001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1)))) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.w 0x4(pc, a0.w), a0" 02fb80008100 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (cast 32 (msb (loadw 0 16 (var bounds_addr))) (loadw 0 16 (var bounds_addr)))) (set upper (cast 32 (msb (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var bounds_addr) (bv 32 0x2))))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.l (a0), d0" 04d00000 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l (a0), d0" 04d00800 0x0 (seq (set bounds_addr (cast 32 false (var a0))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l 0x1(a0), d0" 04e800000001 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l 0xfff(a0), d0" 04e808000fff 0x0 (seq (set bounds_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l 0x1(a0, d0.w), d0" 04f000000001 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l ([0x10001fff], 0x20002fff), d0" 04f008000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l ([0x20002fff], 0x30003fff), d1" 04f010001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d1)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.l (a0, a0.w), a0" 04f080008100 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.l 0x1.w, d0" 04f800000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l 0xfff.w, d0" 04f808000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l 0x10010.l, d0" 04f9000000010010 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x10010))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l 0xfff1000.l, d0" 04f908000fff1000 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0xfff1000))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l 0x5(pc), d0" 04fa00000001 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x5))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l 0x1003(pc), d0" 04fa08000fff 0x0 (seq (set bounds_addr (cast 32 false (bv 32 0x1003))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l 0x5(pc, d0.w), d0" 04fb00000001 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "chk2.l ([0x10002003], 0x20002fff), d0" 04fb08000fff10001fff20002fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)))))) (branch (! (is_zero (var outside))) (seq (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty)) +d "cmp2.l ([0x20003003], 0x30003fff), d1" 04fb10001fff20002fff30003fff 0x0 (seq (set bounds_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var d1)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "cmp2.l 0x4(pc, a0.w), a0" 04fb80008100 0x0 (seq (set bounds_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set lower (loadw 0 32 (var bounds_addr))) (set upper (loadw 0 32 (+ (var bounds_addr) (bv 32 0x4)))) (set rn (var a0)) (set outside (ite (|| (&& (sle (var lower) (var upper)) (|| (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower)))) (! (sle (var rn) (var upper))))) (&& (! (sle (var lower) (var upper))) (&& (! (sle (var rn) (var upper))) (&& (sle (var rn) (var lower)) (! (== (var rn) (var lower))))))) (bv 1 0x1) (bv 1 0x0))) (set equal (ite (|| (== (var rn) (var lower)) (== (var rn) (var upper))) (bv 1 0x1) (bv 1 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xfa)) (bv 8 0xfb)) (<< (ite (! (is_zero (var equal))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (var outside))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false))))))) +d "rtm d0" 06c0 0x0 (seq (set frame (var a7)) (set frame_info (loadw 0 16 (var frame))) (set ccr_arg (loadw 0 16 (+ (var frame) (bv 32 0x2)))) (set arg_count (cast 32 false (cast 8 false (var ccr_arg)))) (set target (loadw 0 32 (+ (var frame) (bv 32 0xc)))) (set module_data (loadw 0 32 (+ (var frame) (bv 32 0x10)))) (branch (is_zero (& (var frame_info) (bv 16 0xff00))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (>> (var ccr_arg) (bv 8 0x8) false))))) (set d0 (cast 32 false (var module_data))) (set a7 (cast 32 false (+ (+ (var frame) (bv 32 0x18)) (var arg_count)))) (jmp (var target))) (goto m68k_rtm))) +d "callm 0x0, (a0)" 06d00000 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (var a0))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x1(a0)" 06e800000001 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x1(a0, d0.w)" 06f000000001 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0xff, (a0, d0.w)" 06f000ff0100 0x0 (seq (set callm_count (bv 32 0xff)) (set callm_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x1.w" 06f800000001 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (bv 32 0x1))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x10010.l" 06f9000000010010 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (bv 32 0x10010))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x5(pc)" 06fa00000001 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (bv 32 0x5))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0x0, 0x5(pc, d0.w)" 06fb00000001 0x0 (seq (set callm_count (bv 32 0x0)) (set callm_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "callm 0xff, 0x4(pc, d0.w)" 06fb00ff0100 0x0 (seq (set callm_count (bv 32 0xff)) (set callm_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set callm_frame_info (loadw 0 16 (var callm_addr))) (set callm_entry (loadw 0 32 (+ (var callm_addr) (bv 32 0x4)))) (set callm_data (loadw 0 32 (+ (var callm_addr) (bv 32 0x8)))) (set callm_entry_word (loadw 0 16 (var callm_entry))) (set callm_reg_code (cast 32 false (>> (var callm_entry_word) (bv 8 0xc) false))) (set callm_frame (- (var a7) (bv 32 0x18))) (branch (is_zero (& (var callm_frame_info) (bv 16 0xff00))) (seq (branch (== (var callm_reg_code) (bv 32 0x0)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d0)) (branch (== (var callm_reg_code) (bv 32 0x1)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d1)) (branch (== (var callm_reg_code) (bv 32 0x2)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d2)) (branch (== (var callm_reg_code) (bv 32 0x3)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d3)) (branch (== (var callm_reg_code) (bv 32 0x4)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d4)) (branch (== (var callm_reg_code) (bv 32 0x5)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d5)) (branch (== (var callm_reg_code) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d6)) (branch (== (var callm_reg_code) (bv 32 0x7)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var d7)) (branch (== (var callm_reg_code) (bv 32 0x8)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a0)) (branch (== (var callm_reg_code) (bv 32 0x9)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a1)) (branch (== (var callm_reg_code) (bv 32 0xa)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a2)) (branch (== (var callm_reg_code) (bv 32 0xb)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a3)) (branch (== (var callm_reg_code) (bv 32 0xc)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a4)) (branch (== (var callm_reg_code) (bv 32 0xd)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a5)) (branch (== (var callm_reg_code) (bv 32 0xe)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a6)) (branch (== (var callm_reg_code) (bv 32 0xf)) (storew 0 (+ (var callm_frame) (bv 32 0x10)) (var a7)) empty)))))))))))))))) (storew 0 (var callm_frame) (cast 16 false (var callm_frame_info))) (set callm_ccr_arg (| (<< (cast 16 false (cast 8 false (var sr))) (bv 8 0x8) false) (cast 16 false (var callm_count)))) (storew 0 (+ (var callm_frame) (bv 32 0x2)) (cast 16 false (var callm_ccr_arg))) (storew 0 (+ (var callm_frame) (bv 32 0x4)) (cast 32 false (var callm_addr))) (storew 0 (+ (var callm_frame) (bv 32 0x8)) (var a7)) (storew 0 (+ (var callm_frame) (bv 32 0xc)) (bv 32 0x6)) (storew 0 (+ (var callm_frame) (bv 32 0x14)) (bv 32 0x0)) (set a7 (cast 32 false (var callm_frame))) (branch (== (var callm_reg_code) (bv 32 0x0)) (set d0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x1)) (set d1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x2)) (set d2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x3)) (set d3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x4)) (set d4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x5)) (set d5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x6)) (set d6 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x7)) (set d7 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x8)) (set a0 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0x9)) (set a1 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xa)) (set a2 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xb)) (set a3 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xc)) (set a4 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xd)) (set a5 (cast 32 false (var callm_data))) (branch (== (var callm_reg_code) (bv 32 0xe)) (set a6 (cast 32 false (var callm_data))) empty))))))))))))))) (jmp (+ (var callm_entry) (bv 32 0x2)))) (goto m68k_callm))) +d "cas.b d0, d0, (a0)" 0ad00000 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, (a0)+" 0ad80000 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, -(a0)" 0ae00000 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, 0x1(a0)" 0ae800000001 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, 0x1(a0, d0.w)" 0af000000001 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d4, ([0x18001ff, a0], 0x8000fff)" 0af00100017f018001ff08000fff 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d4))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, 0x1.w" 0af800000001 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.b d0, d0, 0x10010.l" 0af9000000010010 0x0 (seq (set cmp (cast 8 false (var d0))) (set upd (cast 8 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 8 false (var cmp)) (cast 8 false (var dst))) (storew 0 (var dst_addr) (cast 8 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, (a0)" 0cd00000 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, (a0)+" 0cd80000 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, -(a0)" 0ce00000 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, 0x1(a0)" 0ce800000001 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, 0x1(a0, d0.w)" 0cf000000001 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d4, ([0x18001ff, a0], 0x8000fff)" 0cf00100017f018001ff08000fff 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d4))) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, 0x1.w" 0cf800000001 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.w d0, d0, 0x10010.l" 0cf9000000010010 0x0 (seq (set cmp (cast 16 false (var d0))) (set upd (cast 16 false (var d0))) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 16 false (var cmp)) (cast 16 false (var dst))) (storew 0 (var dst_addr) (cast 16 false (var upd))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas2.w d0:d1,d0:d0,(d0):(d0)" 0cfc00000001 0x0 (seq (set addr0 (var d0)) (set addr1 (var d0)) (set cmp0 (cast 16 false (var d0))) (set cmp1 (cast 16 false (var d1))) (set upd0 (cast 16 false (var d0))) (set upd1 (cast 16 false (var d0))) (set dst0 (loadw 0 16 (var addr0))) (set dst1 (loadw 0 16 (var addr1))) (set first_eq (ite (== (var cmp0) (var dst0)) (bv 1 0x1) (bv 1 0x0))) (set second_eq (ite (== (var cmp1) (var dst1)) (bv 1 0x1) (bv 1 0x0))) (set res0 (- (var dst0) (var cmp0))) (set res1 (- (var dst1) (var cmp1))) (set flag_cmp (ite (! (is_zero (var first_eq))) (var cmp1) (var cmp0))) (set flag_dst (ite (! (is_zero (var first_eq))) (var dst1) (var dst0))) (set res (ite (! (is_zero (var first_eq))) (var res1) (var res0))) (branch (&& (! (is_zero (var first_eq))) (! (is_zero (var second_eq)))) (seq (storew 0 (var addr0) (cast 16 false (var upd0))) (storew 0 (var addr1) (cast 16 false (var upd1)))) (seq (set d1 (| (& (var d1) (bv 32 0xffff0000)) (cast 32 false (var dst1)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dst0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var flag_dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var flag_cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var flag_dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var flag_dst) (var flag_cmp)) (! (== (var flag_dst) (var flag_cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, (a0)" 0ed00000 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, (a0)+" 0ed80000 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, -(a0)" 0ee00000 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set dst_addr (cast 32 false (var a0))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, 0x1(a0)" 0ee800000001 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, 0x1(a0, d0.w)" 0ef000000001 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d4, ([0x18001ff, a0], 0x8000fff)" 0ef00100017f018001ff08000fff 0x0 (seq (set cmp (var d0)) (set upd (var d4)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, 0x1.w" 0ef800000001 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas.l d0, d0, 0x10010.l" 0ef9000000010010 0x0 (seq (set cmp (var d0)) (set upd (var d0)) (set dst_addr (cast 32 false (bv 32 0x10010))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var cmp))) (branch (== (cast 32 false (var cmp)) (cast 32 false (var dst))) (storew 0 (var dst_addr) (cast 32 false (var upd))) (set d0 (cast 32 false (var dst)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var cmp)) (! (== (var dst) (var cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "cas2.l d0:d1,d0:d0,(d0):(d0)" 0efc00000001 0x0 (seq (set addr0 (var d0)) (set addr1 (var d0)) (set cmp0 (var d0)) (set cmp1 (var d1)) (set upd0 (var d0)) (set upd1 (var d0)) (set dst0 (loadw 0 32 (var addr0))) (set dst1 (loadw 0 32 (var addr1))) (set first_eq (ite (== (var cmp0) (var dst0)) (bv 1 0x1) (bv 1 0x0))) (set second_eq (ite (== (var cmp1) (var dst1)) (bv 1 0x1) (bv 1 0x0))) (set res0 (- (var dst0) (var cmp0))) (set res1 (- (var dst1) (var cmp1))) (set flag_cmp (ite (! (is_zero (var first_eq))) (var cmp1) (var cmp0))) (set flag_dst (ite (! (is_zero (var first_eq))) (var dst1) (var dst0))) (set res (ite (! (is_zero (var first_eq))) (var res1) (var res0))) (branch (&& (! (is_zero (var first_eq))) (! (is_zero (var second_eq)))) (seq (storew 0 (var addr0) (cast 32 false (var upd0))) (storew 0 (var addr1) (cast 32 false (var upd1)))) (seq (set d1 (cast 32 false (var dst1))) (set d0 (cast 32 false (var dst0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var flag_dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var flag_cmp)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var flag_dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var flag_dst) (var flag_cmp)) (! (== (var flag_dst) (var flag_cmp)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "chk.l d0, d0" 4100 0x0 (seq (set bound (var d0)) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l (a0), d0" 4110 0x0 (seq (set bound (loadw 0 32 (var a0))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l (a0)+, d0" 4118 0x0 (seq (set bound (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l -(a0), d0" 4120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set bound (loadw 0 32 (var a0))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x0(a0), d0" 41280000 0x0 (seq (set bound (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x0(a0, d0.w), d0" 41300000 0x0 (seq (set bound (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l (a0, d0.w), d0" 41300100 0x0 (seq (set bound (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l ([0x18001ff, a0], 0x8000fff), d0" 4130017f018001ff08000fff 0x0 (seq (set bound (loadw 0 32 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x0.w, d0" 41380000 0x0 (seq (set bound (loadw 0 32 (bv 32 0x0))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x1.l, d0" 413900000001 0x0 (seq (set bound (loadw 0 32 (bv 32 0x1))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x2(pc), d0" 413a0000 0x0 (seq (set bound (loadw 0 32 (bv 32 0x2))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x2(pc, d0.w), d0" 413b0000 0x0 (seq (set bound (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l ([0x1800201, pc], 0x8000fff), d0" 413b017f018001ff08000fff 0x0 (seq (set bound (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "chk.l 0x1, d0" 413c00000001 0x0 (seq (set bound (bv 32 0x1)) (set dst (var d0)) (branch (&& (sle (var dst) (bv 32 0x0)) (! (== (var dst) (bv 32 0x0)))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) (branch (! (sle (var dst) (var bound))) (seq (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (cast 8 false (var sr)) (bv 8 0xf7)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)))))) (set trap_op (bv 32 0x7)) (set trap_vector (bv 32 0x6)) (goto m68k_chk)) empty))) +d "link.l a0, 0x1" 480800000001 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x1))) (set a7 (cast 32 false (var new_sp)))) +d "extb.l d0" 49c0 0x0 (seq (set res (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0)))) (set d0 (cast 32 false (cast 32 (msb (cast 8 false (var d0))) (cast 8 false (var d0))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x2(pc)" 4a3a0000 0x0 (seq (set dst (loadw 0 8 (bv 32 0x2))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x2(pc, d0.w)" 4a3b0000 0x0 (seq (set dst (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b ([0x1800201, pc], 0x8000fff)" 4a3b017f018001ff08000fff 0x0 (seq (set dst (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.b 0x0" 4a3c0000 0x0 (seq (set dst (bv 8 0x0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w a0" 4a48 0x0 (seq (set dst (cast 16 false (var a0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x2(pc)" 4a7a0000 0x0 (seq (set dst (loadw 0 16 (bv 32 0x2))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x2(pc, d0.w)" 4a7b0000 0x0 (seq (set dst (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w ([0x1800201, pc], 0x8000fff)" 4a7b017f018001ff08000fff 0x0 (seq (set dst (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.w 0x0" 4a7c0000 0x0 (seq (set dst (bv 16 0x0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l a0" 4a88 0x0 (seq (set dst (var a0)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x2(pc)" 4aba0000 0x0 (seq (set dst (loadw 0 32 (bv 32 0x2))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x2(pc, d0.w)" 4abb0000 0x0 (seq (set dst (loadw 0 32 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l ([0x1800201, pc], 0x8000fff)" 4abb017f018001ff08000fff 0x0 (seq (set dst (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tst.l 0x1" 4abc00000001 0x0 (seq (set dst (bv 32 0x1)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var dst))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.l d0, d0" 4c000000 0x0 (seq (set src (var d0)) (set res_wide (* (cast 64 false (var d0)) (cast 64 false (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (ule (var res_wide) (bv 64 0xffffffff))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.l d0, d0" 4c000800 0x0 (seq (set src (var d0)) (set res_wide (* (cast 64 (msb (var d0)) (var d0)) (cast 64 (msb (var src)) (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (var res_wide) (bv 64 0xffffffff80000000)) (! (== (var res_wide) (bv 64 0xffffffff80000000)))) (! (sle (var res_wide) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.l (a0), d0" 4c100000 0x0 (seq (set src (loadw 0 32 (var a0))) (set res_wide (* (cast 64 false (var d0)) (cast 64 false (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (ule (var res_wide) (bv 64 0xffffffff))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.l (a0), d0" 4c100800 0x0 (seq (set src (loadw 0 32 (var a0))) (set res_wide (* (cast 64 (msb (var d0)) (var d0)) (cast 64 (msb (var src)) (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (var res_wide) (bv 64 0xffffffff80000000)) (! (== (var res_wide) (bv 64 0xffffffff80000000)))) (! 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(== (var res_wide) (bv 64 0xffffffff80000000)))) (! (sle (var res_wide) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.l ([0x20003003], 0x30003fff), d1" 4c3b10001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set res_wide (* (cast 64 false (var d1)) (cast 64 false (var src)))) (set res (cast 32 false (var res_wide))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (ule (var res_wide) (bv 64 0xffffffff))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mulu.l 0x10010, d0" 4c3c000000010010 0x0 (seq (set src (bv 32 0x10010)) (set res_wide (* (cast 64 false (var d0)) (cast 64 false (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (ule (var res_wide) (bv 64 0xffffffff))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.l 0xfff1000, d0" 4c3c08000fff1000 0x0 (seq (set src (bv 32 0xfff1000)) (set res_wide (* (cast 64 (msb (var d0)) (var d0)) (cast 64 (msb (var src)) (var src)))) (set res (cast 32 false (var res_wide))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (&& (sle (var res_wide) (bv 64 0xffffffff80000000)) (! (== (var res_wide) (bv 64 0xffffffff80000000)))) (! (sle (var res_wide) (bv 64 0x7fffffff)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "divu.l d0, d0" 4c400000 0x0 (seq (set src (var d0)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l d0, d0" 4c400800 0x0 (seq (set src (var d0)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l d0, d1:d2" 4c402401 0x0 (seq (set src (var d0)) (set dst (append (var d1) (var d2))) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d2 (cast 32 false (cast 32 false (var quot)))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l d0, d1:d2" 4c402c01 0x0 (seq (set src (var d0)) (set dst (append (var d1) (var d2))) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d2 (cast 32 false (cast 32 false (var quot)))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l (a0), d0" 4c500000 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l (a0), d0" 4c500800 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l (a0)+, d0" 4c580000 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l (a0)+, d0" 4c580800 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l -(a0), d0" 4c600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l -(a0), d0" 4c600800 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x1(a0), d0" 4c6800000001 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l 0xfff(a0), d0" 4c6808000fff 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x1(a0, d0.w), d0" 4c7000000001 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l ([0x10001fff], 0x20002fff), d0" 4c7008000fff10001fff20002fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l ([0x20002fff], 0x30003fff), d1" 4c7010001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var quot)))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x1.w, d0" 4c7800000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l 0xfff.w, d0" 4c7808000fff 0x0 (seq (set src (loadw 0 32 (bv 32 0xfff))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x10010.l, d0" 4c79000000010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x10010))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l 0xfff1000.l, d0" 4c7908000fff1000 0x0 (seq (set src (loadw 0 32 (bv 32 0xfff1000))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x5(pc), d0" 4c7a00000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x5))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l 0x1003(pc), d0" 4c7a08000fff 0x0 (seq (set src (loadw 0 32 (bv 32 0x1003))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x5(pc, d0.w), d0" 4c7b00000001 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l ([0x10002003], 0x20002fff), d0" 4c7b08000fff10001fff20002fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l ([0x20003003], 0x30003fff), d1" 4c7b10001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var quot)))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divu.l 0x10010, d0" 4c7c000000010010 0x0 (seq (set src (bv 32 0x10010)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "divs.l 0xfff1000, d0" 4c7c08000fff1000 0x0 (seq (set src (bv 32 0xfff1000)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (|| (&& (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)) (! (== (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0xffffffff80000000)))) (! (sle (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src))) (bv 64 0x7fffffff)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d0 (cast 32 false (cast 32 false (var quot)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "rtd 0x4" 4e740004 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x8)))) (jmp (var target))) +d "movec dfc, d0" 4e7a0001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set d0 (cast 32 false (var dfc))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movec d0, dfc" 4e7b0001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set dfc (cast 32 false (& (var d0) (bv 32 0x7)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "trapt.w 0x0" 50fa0000 0x0 (branch true (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapt.l 0x1" 50fb00000001 0x0 (branch true (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapt" 50fc 0x0 (branch true (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapf.w 0x0" 51fa0000 0x0 (branch false (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapf.l 0x1" 51fb00000001 0x0 (branch false (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapf" 51fc 0x0 (branch false (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "traphi.w 0x0" 52fa0000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "traphi.l 0x1" 52fb00000001 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "traphi" 52fc 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapls.w 0x0" 53fa0000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapls.l 0x1" 53fb00000001 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapls" 53fc 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapcc.w 0x0" 54fa0000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapcc.l 0x1" 54fb00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapcc" 54fc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapcs.w 0x0" 55fa0000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapcs.l 0x1" 55fb00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapcs" 55fc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapne.w 0x0" 56fa0000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapne.l 0x1" 56fb00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapne" 56fc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapeq.w 0x0" 57fa0000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapeq.l 0x1" 57fb00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapeq" 57fc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapvc.w 0x0" 58fa0000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapvc.l 0x1" 58fb00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapvc" 58fc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapvs.w 0x0" 59fa0000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapvs.l 0x1" 59fb00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapvs" 59fc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trappl.w 0x0" 5afa0000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trappl.l 0x1" 5afb00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trappl" 5afc 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapmi.w 0x0" 5bfa0000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapmi.l 0x1" 5bfb00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapmi" 5bfc 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapge.w 0x0" 5cfa0000 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapge.l 0x1" 5cfb00000001 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapge" 5cfc 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "traplt.w 0x0" 5dfa0000 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "traplt.l 0x1" 5dfb00000001 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "traplt" 5dfc 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "trapgt.w 0x0" 5efa0000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "trapgt.l 0x1" 5efb00000001 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "trapgt" 5efc 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "traple.w 0x0" 5ffa0000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x0)) (set trap_arg_bits (bv 32 0x10)) (goto m68k_trap)) empty) +d "traple.l 0x1" 5ffb00000001 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (set trap_arg (bv 32 0x1)) (set trap_arg_bits (bv 32 0x20)) (goto m68k_trap)) empty) +d "traple" 5ffc 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (seq (set trap_op (bv 32 0x2)) (set trap_vector (bv 32 0x7)) (goto m68k_trap)) empty) +d "bra.l 0x3" 60ff00000001 0x0 (jmp (bv 32 0x3)) +d "bsr.l 0x3" 61ff00000001 0x0 (seq (set push_value (bv 32 0x6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x3))) +d "bhi.l 0x3" 62ff00000001 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (jmp (bv 32 0x3)) empty) +d "bls.l 0x3" 63ff00000001 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty) +d "bcc.l 0x3" 64ff00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (jmp (bv 32 0x3)) empty) +d "bcs.l 0x3" 65ff00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (jmp (bv 32 0x3)) empty) +d "bne.l 0x3" 66ff00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty) +d "beq.l 0x3" 67ff00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (jmp (bv 32 0x3)) empty) +d "bvc.l 0x3" 68ff00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (jmp (bv 32 0x3)) empty) +d "bvs.l 0x3" 69ff00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (jmp (bv 32 0x3)) empty) +d "bpl.l 0x3" 6aff00000001 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (jmp (bv 32 0x3)) empty) +d "bmi.l 0x3" 6bff00000001 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (jmp (bv 32 0x3)) empty) +d "bge.l 0x3" 6cff00000001 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (jmp (bv 32 0x3)) empty) +d "blt.l 0x3" 6dff00000001 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty) +d "bgt.l 0x3" 6eff00000001 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty) +d "ble.l 0x3" 6fff00000001 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (jmp (bv 32 0x3)) empty) +d "pack d0, d0" 81400000 0x0 (seq (set src (cast 16 false (var d0))) (set adjustment (bv 16 0x0)) (set adjusted (+ (cast 16 false (var src)) (var adjustment))) (set res (cast 8 false (| (>> (& (var adjusted) (bv 16 0xf00)) (bv 8 0x4) false) (& (var adjusted) (bv 16 0xf))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res))))) +d "pack d0, d0, 0x1" 81400001 0x0 (seq (set src (cast 16 false (var d0))) (set adjustment (bv 16 0x1)) (set adjusted (+ (cast 16 false (var src)) (var adjustment))) (set res (cast 8 false (| (>> (& (var adjusted) (bv 16 0xf00)) (bv 8 0x4) false) (& (var adjusted) (bv 16 0xf))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res))))) +d "pack -(a0), -(a0)" 81480000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src_low (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src_high (loadw 0 8 (var a0))) (set src (append (var src_high) (var src_low))) (set adjustment (bv 16 0x0)) (set adjusted (+ (cast 16 false (var src)) (var adjustment))) (set res (cast 8 false (| (>> (& (var adjusted) (bv 16 0xf00)) (bv 8 0x4) false) (& (var adjusted) (bv 16 0xf))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var res)))) +d "pack -(a0), -(a0), 0x1" 81480001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src_low (loadw 0 8 (var a0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src_high (loadw 0 8 (var a0))) (set src (append (var src_high) (var src_low))) (set adjustment (bv 16 0x1)) (set adjusted (+ (cast 16 false (var src)) (var adjustment))) (set res (cast 8 false (| (>> (& (var adjusted) (bv 16 0xf00)) (bv 8 0x4) false) (& (var adjusted) (bv 16 0xf))))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (var res)))) +d "unpk d0, d0" 81800000 0x0 (seq (set src (cast 8 false (var d0))) (set adjustment (bv 16 0x0)) (set expanded (| (<< (cast 16 false (& (var src) (bv 8 0xf0))) (bv 8 0x4) false) (cast 16 false (& (var src) (bv 8 0xf))))) (set res (+ (var expanded) (var adjustment))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res))))) +d "unpk d0, d0, 0x1" 81800001 0x0 (seq (set src (cast 8 false (var d0))) (set adjustment (bv 16 0x1)) (set expanded (| (<< (cast 16 false (& (var src) (bv 8 0xf0))) (bv 8 0x4) false) (cast 16 false (& (var src) (bv 8 0xf))))) (set res (+ (var expanded) (var adjustment))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res))))) +d "unpk -(a0), -(a0)" 81880000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set adjustment (bv 16 0x0)) (set expanded (| (<< (cast 16 false (& (var src) (bv 8 0xf0))) (bv 8 0x4) false) (cast 16 false (& (var src) (bv 8 0xf))))) (set res (+ (var expanded) (var adjustment))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (cast 8 false (var res)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (cast 8 false (>> (var res) (bv 8 0x8) false))))) +d "unpk -(a0), -(a0), 0x1" 81880001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set adjustment (bv 16 0x1)) (set expanded (| (<< (cast 16 false (& (var src) (bv 8 0xf0))) (bv 8 0x4) false) (cast 16 false (& (var src) (bv 8 0xf))))) (set res (+ (var expanded) (var adjustment))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (cast 8 false (var res)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (var a0) (cast 8 false (cast 8 false (>> (var res) (bv 8 0x8) false))))) +d "bftst d0{0:32}" e8c00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst (a0){0:32}" e8d00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x1(a0){0:32}" e8e800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x1(a0, d0.w){0:32}" e8f000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst (a0, d0.w){3:d7}" e8f000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst ([0x18001ff, a0], 0x8000fff){4:32}" e8f00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x9c.w{20:5}" e8f80505009c 0x0 (seq (set offset (bv 32 0x14)) (set width (bv 32 0x5)) (set base (cast 32 false (bv 32 0x9c))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x9c.w{d0:32}" e8f80800009c 0x0 (seq (set offset (var d0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x9c))) (set bit_offset (& (var offset) (bv 32 0x7))) (set byte_offset (sdiv (- (var offset) (var bit_offset)) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x9c.w{d1:d0}" e8f80860009c 0x0 (seq (set offset (var d1)) (set width (ite (is_zero (& (var d0) (bv 32 0x1f))) (bv 32 0x20) (& (var d0) (bv 32 0x1f)))) (set base (cast 32 false (bv 32 0x9c))) (set bit_offset (& (var offset) (bv 32 0x7))) (set byte_offset (sdiv (- (var offset) (var bit_offset)) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x10010.l{0:32}" e8f9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x5(pc){0:32}" e8fa00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x5))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x5(pc, d0.w){0:32}" e8fb00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst 0x4(pc, d0.w){3:d7}" e8fb00ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bftst ([0x1800203, pc], 0x8000fff){4:32}" e8fb0100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu d0{0:32}, d0" e9c00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu (a0){0:32}, d0" e9d00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x1(a0){0:32}, d0" e9e800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x1(a0, d0.w){0:32}, d0" e9f000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu (a0, d0.w){3:d7}, d0" e9f000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu ([0x18001ff, a0], 0x8000fff){4:32}, d0" e9f00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x1.w{0:32}, d0" e9f800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x10010.l{0:32}, d0" e9f9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x5(pc){0:32}, d0" e9fa00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x5))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x5(pc, d0.w){0:32}, d0" e9fb00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu 0x4(pc, d0.w){3:d7}, d0" e9fb00ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfextu ([0x1800203, pc], 0x8000fff){4:32}, d0" e9fb0100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (var field)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg d0{0:32}" eac00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set d0 (cast 32 false (| (& (cast 32 false (>> (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (bv 8 0x20) false)) (~ (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))) (& (cast 32 false (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg (a0){0:32}" ead00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg 0x1(a0){0:32}" eae800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg 0x1(a0, d0.w){0:32}" eaf000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg (a0, d0.w){3:d7}" eaf000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg ([0x18001ff, a0], 0x8000fff){4:32}" eaf00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg 0x1.w{0:32}" eaf800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfchg 0x10010.l{0:32}" eaf9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (^ (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts d0{0:32}, d0" ebc00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts (a0){0:32}, d0" ebd00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x1(a0){0:32}, d0" ebe800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x1(a0, d0.w){0:32}, d0" ebf000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts (a0, d0.w){3:d7}, d0" ebf000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts ([0x18001ff, a0], 0x8000fff){4:32}, d0" ebf00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x1.w{0:32}, d0" ebf800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x10010.l{0:32}, d0" ebf9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x5(pc){0:32}, d0" ebfa00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x5))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x5(pc, d0.w){0:32}, d0" ebfb00000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts 0x4(pc, d0.w){3:d7}, d0" ebfb00ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfexts ([0x1800203, pc], 0x8000fff){4:32}, d0" ebfb0100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set res (ite (! (is_zero (& (var field) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (| (var field) (~ (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (var field))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr d0{0:32}" ecc00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set d0 (cast 32 false (| (& (cast 32 false (>> (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (bv 8 0x20) false)) (~ (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))) (& (cast 32 false (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr (a0){0:32}" ecd00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr 0x1(a0){0:32}" ece800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr 0x1(a0, d0.w){0:32}" ecf000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr (a0, d0.w){3:d7}" ecf000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr ([0x18001ff, a0], 0x8000fff){4:32}" ecf00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr 0x1.w{0:32}" ecf800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfclr 0x10010.l{0:32}" ecf9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (bv 32 0x0)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! 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(is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfffo d0{0:32}, d0" edc00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set scan (<< (var field) (- (bv 8 0x20) (cast 8 false (var width))) false)) (set first (ite (&& (&& (ule (bv 32 0x0) (var width)) (! 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(is_zero (& (var scan) (bv 32 0x1000000))))) (bv 32 0x7) (ite (&& (&& (ule (bv 32 0x8) (var width)) (! (== (bv 32 0x8) (var width)))) (! (is_zero (& (var scan) (bv 32 0x800000))))) (bv 32 0x8) (ite (&& (&& (ule (bv 32 0x9) (var width)) (! (== (bv 32 0x9) (var width)))) (! (is_zero (& (var scan) (bv 32 0x400000))))) (bv 32 0x9) (ite (&& (&& (ule (bv 32 0xa) (var width)) (! (== (bv 32 0xa) (var width)))) (! (is_zero (& (var scan) (bv 32 0x200000))))) (bv 32 0xa) (ite (&& (&& (ule (bv 32 0xb) (var width)) (! (== (bv 32 0xb) (var width)))) (! (is_zero (& (var scan) (bv 32 0x100000))))) (bv 32 0xb) (ite (&& (&& (ule (bv 32 0xc) (var width)) (! (== (bv 32 0xc) (var width)))) (! (is_zero (& (var scan) (bv 32 0x80000))))) (bv 32 0xc) (ite (&& (&& (ule (bv 32 0xd) (var width)) (! (== (bv 32 0xd) (var width)))) (! (is_zero (& (var scan) (bv 32 0x40000))))) (bv 32 0xd) (ite (&& (&& (ule (bv 32 0xe) (var width)) (! (== (bv 32 0xe) (var width)))) (! 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(is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfffo (a0){0:32}, d0" edd00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! 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(ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set scan (<< (var field) (- (bv 8 0x20) (cast 8 false (var width))) false)) (set first (ite (&& (&& (ule (bv 32 0x0) (var width)) (! (== (bv 32 0x0) (var width)))) (! (is_zero (& (var scan) (bv 32 0x80000000))))) (bv 32 0x0) (ite (&& (&& (ule (bv 32 0x1) (var width)) (! (== (bv 32 0x1) (var width)))) (! (is_zero (& (var scan) (bv 32 0x40000000))))) (bv 32 0x1) (ite (&& (&& (ule (bv 32 0x2) (var width)) (! (== (bv 32 0x2) (var width)))) (! (is_zero (& (var scan) (bv 32 0x20000000))))) (bv 32 0x2) (ite (&& (&& (ule (bv 32 0x3) (var width)) (! (== (bv 32 0x3) (var width)))) (! (is_zero (& (var scan) (bv 32 0x10000000))))) (bv 32 0x3) (ite (&& (&& (ule (bv 32 0x4) (var width)) (! (== (bv 32 0x4) (var width)))) (! (is_zero (& (var scan) (bv 32 0x8000000))))) (bv 32 0x4) (ite (&& (&& (ule (bv 32 0x5) (var width)) (! (== (bv 32 0x5) (var width)))) (! (is_zero (& (var scan) (bv 32 0x4000000))))) (bv 32 0x5) (ite (&& (&& (ule (bv 32 0x6) (var width)) (! (== (bv 32 0x6) (var width)))) (! (is_zero (& (var scan) (bv 32 0x2000000))))) (bv 32 0x6) (ite (&& (&& (ule (bv 32 0x7) (var width)) (! (== (bv 32 0x7) (var width)))) (! (is_zero (& (var scan) (bv 32 0x1000000))))) (bv 32 0x7) (ite (&& (&& (ule (bv 32 0x8) (var width)) (! (== (bv 32 0x8) (var width)))) (! (is_zero (& (var scan) (bv 32 0x800000))))) (bv 32 0x8) (ite (&& (&& (ule (bv 32 0x9) (var width)) (! (== (bv 32 0x9) (var width)))) (! (is_zero (& (var scan) (bv 32 0x400000))))) (bv 32 0x9) (ite (&& (&& (ule (bv 32 0xa) (var width)) (! (== (bv 32 0xa) (var width)))) (! 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(ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset (a0){0:1}" eed00001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x1)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset 0x1(a0){0:32}" eee800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset 0x1(a0, d0.w){0:32}" eef000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset (a0, d0.w){3:d7}" eef000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset ([0x18001ff, a0], 0x8000fff){4:32}" eef00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset 0x1.w{0:32}" eef800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfset 0x10010.l{0:32}" eef9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, d0{0:32}" efc00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set bit_offset (mod (var offset) (bv 32 0x20))) (set container (append (var d0) (var d0))) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set d0 (cast 32 false (| (& (cast 32 false (>> (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (bv 8 0x20) false)) (~ (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))) (& (cast 32 false (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (cast 32 false (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, (a0){0:32}" efd00000 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (var a0))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, 0x1(a0){0:32}" efe800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, 0x1(a0, d0.w){0:32}" eff000000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, (a0, d0.w){3:d7}" eff000ff0100 0x0 (seq (set offset (bv 32 0x3)) (set width (ite (is_zero (& (var d7) (bv 32 0x1f))) (bv 32 0x20) (& (var d7) (bv 32 0x1f)))) (set base (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, ([0x18001ff, a0], 0x8000fff){4:32}" eff00100017f018001ff08000fff 0x0 (seq (set offset (bv 32 0x4)) (set width (bv 32 0x20)) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, 0x1.w{0:32}" eff800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "bfins d0, 0x10010.l{0:32}" eff9000000010010 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x10010))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set src (& (var d0) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set updated_container (| (& (var container) (~ (<< (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (<< (& (cast 64 false (var src)) (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false))) (storew 0 (var bf_addr) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x38) false)))) (branch (! (ule (var byte_count) (bv 32 0x1))) (storew 0 (+ (var bf_addr) (bv 32 0x1)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x30) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (storew 0 (+ (var bf_addr) (bv 32 0x2)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x28) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (storew 0 (+ (var bf_addr) (bv 32 0x3)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x20) false)))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (storew 0 (+ (var bf_addr) (bv 32 0x4)) (cast 8 false (cast 8 false (>> (var updated_container) (bv 8 0x18) false)))) empty) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var src) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "fbf.w 0x2" f0800000 +d "fbeq.w 0x2" f0810000 +d "fbogt.w 0x2" f0820000 +d "fboge.w 0x2" f0830000 +d "fbolt.w 0x2" f0840000 +d "fbole.w 0x2" f0850000 +d "fbogl.w 0x2" f0860000 +d "fbor.w 0x2" f0870000 +d "fbun.w 0x2" f0880000 +d "fbueq.w 0x2" f0890000 +d "fbugt.w 0x2" f08a0000 +d "fbuge.w 0x2" f08b0000 +d "fbult.w 0x2" f08c0000 +d "fbule.w 0x2" f08d0000 +d "fbne.w 0x2" f08e0000 +d "fbt.w 0x2" f08f0000 +d "fbsf.w 0x2" f2900000 +d "fbseq.w 0x2" f2910000 +d "fbgt.w 0x2" f2920000 +d "fbge.w 0x2" f2930000 +d "fblt.w 0x2" f2940000 +d "fble.w 0x2" f2950000 +d "fbgl.w 0x2" f2960000 +d "fbgle.w 0x2" f2970000 +d "fbngle.w 0x2" f2980000 +d "fbngl.w 0x2" f2990000 +d "fbnle.w 0x2" f29a0000 +d "fbnlt.w 0x2" f29b0000 +d "fbnge.w 0x2" f29c0000 +d "fbngt.w 0x2" f29d0000 +d "fbsne.w 0x2" f29e0000 +d "fbst.w 0x2" f29f0000 +d "fbf.l 0x3" f0c000000001 +d "fbeq.l 0x3" f0c100000001 +d "fbogt.l 0x3" f0c200000001 +d "fboge.l 0x3" f0c300000001 +d "fbolt.l 0x3" f0c400000001 +d "fbole.l 0x3" f0c500000001 +d "fbogl.l 0x3" f0c600000001 +d "fbor.l 0x3" f0c700000001 +d "fbun.l 0x3" f0c800000001 +d "fbueq.l 0x3" f0c900000001 +d "fbugt.l 0x3" f0ca00000001 +d "fbuge.l 0x3" f0cb00000001 +d "fbult.l 0x3" f0cc00000001 +d "fbule.l 0x3" f0cd00000001 +d "fbne.l 0x3" f0ce00000001 +d "fbt.l 0x3" f0cf00000001 +d "fmove fp0, fp0" f2000000 +d "fint fp0" f2000001 +d "fint fp1, fp2" f2000501 +d "fintrz fp1, fp2" f2000503 +d "fsqrt fp1, fp2" f2000504 +d "flognp1 fp1, fp2" f2000506 +d "fatanh fp1, fp2" f2000509 +d "fatan fp1, fp2" f200050a +d "fasin fp1, fp2" f200050c +d "fsin fp1, fp2" f200050e +d "ftan fp1, fp2" f200050f +d "flogn fp1, fp2" f2000514 +d "flog10 fp1, fp2" f2000515 +d "flog2 fp1, fp2" f2000516 +d "fabs fp1, fp2" f2000518 +d "fneg fp1, fp2" f200051a +d "facos fp1, fp2" f200051c +d "fcos fp1, fp2" f200051d +d "fetox fp0" f2000010 +d "fsinh fp1, fp2" f2000502 +d "fetoxm1 fp1, fp2" f2000508 +d "fetox fp1, fp2" f2000510 +d "ftwotox fp1, fp2" f2000511 +d "ftentox fp1, fp2" f2000512 +d "fcosh fp1, fp2" f2000519 +d "fgetexp fp1, fp2" f200051e +d "fgetman fp1, fp2" f200051f +d "fdiv fp1, fp2" f2000520 +d "fmod fp1, fp2" f2000521 +d "fadd fp1, fp2" f2000522 +d "fmul fp1, fp2" f2000523 +d "frem fp1, fp2" f2000525 +d "fscale fp1, fp2" f2000526 +d "fscale.l 0x3, fp0" f23c402600000003 +d "fsgldiv fp1, fp2" f2000524 +d "fsglmul fp1, fp2" f2000527 +d "fsub fp2, fp4" f2000a28 +d "fmove.l d0, fp0" f2004000 +d "add.x d0, fp7" f2004fff +d "fmove.w d0, fp0" f2005000 +d "fcos.d d0, fp4" f2005678 +d "fmovecr 0x3f, fp7" f2005fff +d "fmovecr 0xf, fp6" f2005f0f +d "fcmp fp1, fp2" f2000538 +d "ftst fp1, fp2" f200053a +d "fmove.s fp0, (a0)" f2106400 +d "fmovem (a0), fp6-fp7" f210d003 +d "fmovem fp6-fp7, (a0)" f210f003 +d "fmovem (a0)+, fp6-fp7" f218d003 +d "fmovem fp0-fp1, -(a0)" f220e003 +d "fmove.s 1.000000, fp1" f23c44803f800000 +d "fmove.d 3.141593, fp1" f23c5480400921fb54442d18 +d "fmove.l d0, fpsr" f2008800 +d "fmove.l d0, fpcr" f2009000 +d "fmove.l fpiar, d0" f200a400 +d "fmove.l fpcr, d0" f200b000 +d "fmove.l fp0, d0" f2006000 +d "fmove.w fp0, d0" f2007000 +d "fmove.p fp7, d0{d7}" f2007fff +d "fmove.l a0, fp0" f2084000 +d "add.x a0, fp7" f2084fff +d "fmove.w a0, fp0" f2085000 +d "fcos.d a0, fp4" f2085678 +d "fmove.l fp0, a0" f2086000 +d "fmove.w fp0, a0" f2087000 +d "fmove.l (a0), fp0" f2104000 +d "fmove.x (a0), fp0" f2104800 +d "fadd.x (a0), fp0" f2104c22 +d "add.x (a0), fp7" f2104fff +d "fmove.w (a0), fp0" f2105000 +d "fcos.d (a0), fp4" f2105678 +d "fmove.l fp0, (a0)" f2106000 +d "fmove.x fp0, (a0)" f2106800 +d "fmove.w fp0, (a0)" f2107000 +d "fmove.l (a0)+, fp0" f2184000 +d "fmove.x (a0)+, fp0" f2184800 +d "add.x (a0)+, fp7" f2184fff +d "fmove.w (a0)+, fp0" f2185000 +d "fcos.d (a0)+, fp4" f2185678 +d "fmove.l fp0, (a0)+" f2186000 +d "fmove.x fp0, (a0)+" f2186800 +d "fmove.w fp0, (a0)+" f2187000 +d "fmove.l -(a0), fp0" f2204000 +d "fmove.x -(a0), fp0" f2204800 +d "add.x -(a0), fp7" f2204fff +d "fmove.w -(a0), fp0" f2205000 +d "fcos.d -(a0), fp4" f2205678 +d "fmove.l fp0, -(a0)" f2206000 +d "fmove.x fp0, -(a0)" f2206800 +d "fmove.w fp0, -(a0)" f2207000 +d "fmove.l 0x4fff(a0), fp0" f22840004fff +d "add.x 0x5000(a0), fp7" f2284fff5000 +d "fmove.w 0x5fff(a0), fp0" f22850005fff +d "fcos.d -0x6544(a0), fp4" f22856789abc +d "fmove.l fp0, 0x6fff(a0)" f22860006fff +d "fmove.w fp0, 0x7fff(a0)" f22870007fff +d "fmove.l ([0x50005fff], 0x60006fff), fp0" f23040004fff50005fff60006fff +d "add.x 0x0(a0, d5.w), fp7" f2304fff5000 +d "fmove.w ([0x60006fff], 0x70007fff), fp0" f23050005fff60006fff70007fff +d "fcos.d -0x44(a0, a1.l * 2), fp4" f23056789abc +d "fmove.l fp0, ([0x70007fff], -0x7fff7f00)" f23060006fff70007fff80008100 +d "fmove.w fp0, ([-0x7fff7f00], -0x7e8f6e01)" f23070007fff80008100817091ff +d "fmove.l (a0, a0.w), invalid" f23080008100 +d "fmove.l 0x0(a0, d0.w), fpcr" f2309abc0000 +d "fmove.l fpcr, (a0, a4.w)" f230b1ffc100 +d "fmove.l 0x4fff.w, fp0" f23840004fff +d "add.x 0x5000.w, fp7" f2384fff5000 +d "fmove.w 0x5fff.w, fp0" f23850005fff +d "fcos.d 0x9abc.w, fp4" f23856789abc +d "fmove.l fp0, 0x6fff.w" f23860006fff +d "fmove.w fp0, 0x7fff.w" f23870007fff +d "fmove.l 0x4fff5000.l, fp0" f23940004fff5000 +d "add.x 0x50005fff.l, fp7" f2394fff50005fff +d "fmove.w 0x5fff6000.l, fp0" f23950005fff6000 +d "fcos.d 0x9abc0000.l, fp4" f23956789abc0000 +d "fmove.l fp0, 0x6fff7000.l" f23960006fff7000 +d "fmove.w fp0, 0x7fff8000.l" f23970007fff8000 +d "fmove.l 0x5003(pc), fp0" f23a40004fff +d "add.x 0x5004(pc), fp7" f23a4fff5000 +d "fmove.w 0x6003(pc), fp0" f23a50005fff +d "fcos.d 0xffff9ac0(pc), fp4" f23a56789abc +d "fmove.l fp0, 0x7003(pc)" f23a60006fff +d "fmove.w fp0, 0xffff8003(pc)" f23a70007fff +d "fmove.l ([0x50006003], 0x60006fff), fp0" f23b40004fff50005fff60006fff +d "add.x 0x4(pc, d5.w), fp7" f23b4fff5000 +d "fmove.w ([0x60007003], 0x70007fff), fp0" f23b50005fff60006fff70007fff +d "fcos.d 0xffffffc0(pc, a1.l * 2), fp4" f23b56789abc +d "fmove.l fp0, ([0x70008003], -0x7fff7f00)" f23b60006fff70007fff80008100 +d "fmove.w fp0, ([0x80008104], -0x7e8f6e01)" f23b70007fff80008100817091ff +d "fmove.l 0x4(pc, a0.w), invalid" f23b80008100 +d "fmove.l 0x4(pc, d0.w), fpcr" f23b9abc0000 +d "fmove.l fpcr, 0x4(pc, a4.w)" f23bb1ffc100 +d "fmovem 0x4(pc, a6.w), fp0-fp7" f23bd0ffe100 +d "fmove.l 0x4fff5000, fp0" f23c40004fff5000 +d "add.x , fp7" f23c4fff50005fff60006fff +d "fmove.w 0x5fff, fp0" f23c50005fff +d "fcos.d -0.000000, fp4" f23c56789abc000000010010 +d "fmove.l fp0, 0x6fff7000" f23c60006fff7000 +d "fmove.w fp0, 0x7fff" f23c70007fff +d "fsf.b d0" f2400000 +d "fseq.b d0" f2400001 +d "fsst.b d0" f240007f +d "fslt.b d0" f2401234 +d "fsngle.b d0" f2405678 +d "fssf.b d0" f2408170 +d "fsnge.b d0" f2409abc +d "fdbf d0, 0x5" f24800000001 +d "fdbf d0, 0x14" f24800000010 +d "fsf.b (a0)" f2500000 +d "fseq.b (a0)" f2500001 +d "fsst.b (a0)" f250007f +d "fslt.b (a0)" f2501234 +d "fsngle.b (a0)" f2505678 +d "fssf.b (a0)" f2508170 +d "fsnge.b (a0)" f2509abc +d "fsf.b (a0)+" f2580000 +d "fseq.b (a0)+" f2580001 +d "fsst.b (a0)+" f258007f +d "fslt.b (a0)+" f2581234 +d "fsngle.b (a0)+" f2585678 +d "fssf.b (a0)+" f2588170 +d "fsnge.b (a0)+" f2589abc +d "fsf.b -(a0)" f2600000 +d "fseq.b -(a0)" f2600001 +d "fsst.b -(a0)" f260007f +d "fslt.b -(a0)" f2601234 +d "fsngle.b -(a0)" f2605678 +d "fssf.b -(a0)" f2608170 +d "fsnge.b -(a0)" f2609abc +d "fsf.b 0x1(a0)" f26800000001 +d "fseq.b 0x10(a0)" f26800010010 +d "fsst.b 0x80(a0)" f268007f0080 +d "fslt.b 0x5678(a0)" f26812345678 +d "fsngle.b -0x6544(a0)" f26856789abc +d "fssf.b -0x6e01(a0)" f268817091ff +d "fsnge.b 0x0(a0)" f2689abc0000 +d "fsf.b 0x1(a0, d0.w)" f27000000001 +d "fseq.b 0x10(a0, d0.w)" f27000010010 +d "fsst.b -0x80(a0, d0.w)" f270007f0080 +d "fsst.b (a0, d0.w)" f27000ff0100 +d "fsf.b ([0x18001ff, a0], 0x8000fff)" f2700100017f018001ff08000fff +d "fslt.b 0x78(a0, d5.w * 8)" f27012345678 +d "fsngle.b -0x44(a0, a1.l * 2)" f27056789abc +d "fsf.b (a0, a0.w)" f27080008100 +d "fssf.b ([-0x5eff4e01], -0x3eff2e01)" f270817091ffa100b1ffc100d1ff +d "fsnge.b 0x0(a0, d0.w)" f2709abc0000 +d "fsst.b ([0x12345678], -0x65440000)" f270f1ffffff123456789abc0000 +d "fsf.b 0x1.w" f27800000001 +d "fseq.b 0x10.w" f27800010010 +d "fsst.b 0x80.w" f278007f0080 +d "fslt.b 0x5678.w" f27812345678 +d "fsngle.b 0x9abc.w" f27856789abc +d "fssf.b 0x91ff.w" f278817091ff +d "fsnge.b 0x0.w" f2789abc0000 +d "fsf.b 0x10010.l" f279000000010010 +d "fseq.b 0x10007f.l" f27900010010007f +d "fsst.b 0x8000ff.l" f279007f008000ff +d "fslt.b 0x56789abc.l" f279123456789abc +d "fsngle.b 0x9abc0000.l" f27956789abc0000 +d "fssf.b 0x91ffa100.l" f279817091ffa100 +d "fsnge.b 0x1.l" f2799abc00000001 +d "fbsf.w 0x2" f2b00000 +d "fbsf.l 0x3" f2f000000001 +d "fdbseq d0, 0x5" f24800310001 +d "ftrapge.l 0x12345678" f27b003312345678 +d "ftrapf.w 0x1" f27a00000001 +d "ftrapeq.w 0x10" f27a00010010 +d "ftrapf.w 0x1234" f27a00001234 +d "ftrapf.l 0x12345678" f27b000012345678 +d "ftrapst.w 0x80" f27a007f0080 +d "ftraplt.w 0x5678" f27a12345678 +d "ftrapngle.w 0x9abc" f27a56789abc +d "ftrapsf.w 0x91ff" f27a817091ff +d "ftrapnge.w 0x0" f27a9abc0000 +d "ftrapf" f27c0000 +d "ftrapeq" f27c0001 +d "ftrapst" f27c007f +d "ftraplt" f27c1234 +d "ftrapngle" f27c5678 +d "ftrapsf" f27c8170 +d "ftrapnge" f27c9abc +d "fnop" f2800000 +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x3)) (! (== (var format) (bv 16 0x3)))) (&& (|| (! (ule (var format) (bv 16 0x9))) (== (var format) (bv 16 0x9))) (&& (ule (var format) (bv 16 0xc)) (! (== (var format) (bv 16 0xc)))))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr)))) +d "fmovem 0x10(a0), fp6-fp7" f228d0030010 +d "fmovem 0x0(a0, d0.w), fp6-fp7" f230d0030000 +d "fmovem 0x1234.w, fp6-fp7" f238d0031234 +d "fmovem 0x12345678.l, fp6-fp7" f239d00312345678 +d "fmovem 0x4(pc), fp6-fp7" f23ad0030000 +d "fmovem fp6-fp7, 0x10(a0)" f228f0030010 +d "fmovem fp6-fp7, 0x0(a0, d0.w)" f230f0030000 +d "fmovem fp6-fp7, 0x1234.w" f238f0031234 +d "fmovem fp6-fp7, 0x12345678.l" f239f00312345678 +d "fmovem 0x10(a0), d1" f228d8100010 +d "fmovem 0x0(a0, d0.w), d1" f230d8100000 +d "fmovem 0x1234.w, d1" f238d8101234 +d "fmovem 0x12345678.l, d1" f239d81012345678 +d "fmovem 0x4(pc), d1" f23ad8100000 +d "fmovem 0x4(pc, d0.w), d1" f23bd8100000 +d "fmovem d1, 0x10(a0)" f228f8100010 +d "fmovem d1, 0x0(a0, d0.w)" f230f8100000 +d "fmovem d1, 0x1234.w" f238f8101234 +d "fmovem d1, 0x12345678.l" f239f81012345678 +d "fmovem (a0)+, d1" f218d810 +d "fmovem (a0), d1" f210d810 +d "fmovem d1, (a0)" f210f810 +d "fmove.s (a0), fp0" f2104400 +d "fmovem d1, -(a0)" f220e810 +d "fsave ([0x10, a0, d0.w], 0x20)" f33001330000001000000020 +d "frestore ([0x12, pc, d0.w], 0x20)" f37b01330000001000000020 +d "fsave (a0)" f310 +d "fsave -(a0)" f320 +d "fsave 0x0(a0)" f3280000 +d "fsave 0x0(a0, d0.w)" f3300000 +d "fsave (a0, d0.w)" f3300100 +d "fsave ([0x18001ff, a0], 0x8000fff)" f330017f018001ff08000fff +d "fsave 0x0.w" f3380000 +d "fsave 0x1.l" f33900000001 +d "frestore (a0)" f350 +d "frestore (a0)+" f358 +d "frestore 0x0(a0)" f3680000 +d "frestore 0x0(a0, d0.w)" f3700000 +d "frestore (a0, d0.w)" f3700100 +d "frestore ([0x18001ff, a0], 0x8000fff)" f370017f018001ff08000fff +d "frestore 0x0.w" f3780000 +d "frestore 0x1.l" f37900000001 +d "frestore 0x2(pc)" f37a0000 +d "frestore 0x2(pc, d0.w)" f37b0000 +d "frestore ([0x1800201, pc], 0x8000fff)" f37b017f018001ff08000fff +d "frestore 0x0" f37c0000 +d "mulu.l d0, d4:d5" 4c005404 0x0 (seq (set src (var d0)) (set dst (var d5)) (set res (* (cast 64 false (var dst)) (cast 64 false (var src)))) (set d5 (cast 32 false (var res))) (set d4 (cast 32 false (>> (var res) (bv 8 0x20) false))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 64 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 64 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "muls.l d0, d4:d5" 4c005c04 0x0 (seq (set src (var d0)) (set dst (var d5)) (set res (* (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set d5 (cast 32 false (var res))) (set d4 (cast 32 false (>> (var res) (bv 8 0x20) false))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 64 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 64 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "lea.l -0x2a(a1, d2.w), a3" 47f12120ffd6 0x0 (set a3 (cast 32 false (+ (+ (cast 32 false (var a1)) (cast 32 false (bv 32 0xffffffd6))) (cast 32 (msb (cast 16 false (var d2))) (cast 16 false (var d2)))))) +d "fmove.d (a0), fp0" f2105400 +d "fmove.b (a0), fp0" f2105800 +d "fbf.w 0x12" f2800010 diff --git a/test/db/asm/m68k_68030_32 b/test/db/asm/m68k_68030_32 index fdf4d66a58..20aa0a5b3a 100644 --- a/test/db/asm/m68k_68030_32 +++ b/test/db/asm/m68k_68030_32 @@ -1,13 +1,77 @@ -d "pmove (a0), tc" f0104000 -d "pmove tc, (a0)" f0104200 -d "pmove (a1), srp" f0114800 -d "pmove (a2), crp" f0124c00 -d "pmove (a0), mmusr" f0106000 -d "pmove (a0), tt0" f0100800 -d "pmove (a0), tt1" f0100c00 -d "pflush sfc, 0x0, (a0)" f0103800 -d "pflusha" f0002400 -d "ploadw sfc, (a0)" f0102000 -d "ploadr sfc, (a0)" f0102200 -d "ptestw sfc, (a0), 0x7" f0109c00 -d "ptestr sfc, (a0), 0x7" f0109e00 +d "bftst 0x1.w{0:32}" e8f800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "pmove d0, tt0" f0000800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, d0" f0002000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflusha" f0002400 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, d0" f0003000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, d0" f0003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove a0, tt0" f0080800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var a0)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, a0" f0082000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, a0" f0083000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, a0" f0083fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, a0, 0x0" f0088000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a0), tt0" f0100800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a0), tt1" f0100c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt1 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, (a0)" f0102000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadr sfc, (a0)" f0102200 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x0)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, (a0)" f0103800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, (a0)" f0103fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a0), tc" f0104000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tc (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd (a0), tc" f0104100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tc (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove tc, (a0)" f0104200 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var tc)) (storew 0 (var mmu_addr) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd tc, (a0)" f0104300 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var tc)) (storew 0 (var mmu_addr) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd (a0), srp" f0104900 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 64 (var mmu_addr))) (set srp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd srp, (a0)" f0104b00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var srp)) (storew 0 (var mmu_addr) (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd (a0), crp" f0104d00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 64 (var mmu_addr))) (set crp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmovefd crp, (a0)" f0104f00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var crp)) (storew 0 (var mmu_addr) (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a0), mmusr" f0106000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 16 (var mmu_addr))) (set mmusr (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, (a0), 0x7" f0109c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestr sfc, (a0), 0x7" f0109e00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a1), srp" f0114800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a1))) (set src (loadw 0 64 (var mmu_addr))) (set srp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a2), crp" f0124c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a2))) (set src (loadw 0 64 (var mmu_addr))) (set crp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove (a0)+, tt0" f0180800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, (a0)+" f0182000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, (a0)+" f0183000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, (a0)+" f0183fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, (a0)+, 0x0" f0188000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove -(a0), tt0" f0200800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, -(a0)" f0202000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, -(a0)" f0203000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, -(a0)" f0203fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, -(a0), 0x0" f0208000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove 0xfff(a0), tt0" f02808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, 0x2fff(a0)" f02820002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x2fff))))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, 0x3fff(a0)" f02830003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x3fff))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x4000(a0)" f0283fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x4000))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, -0x7f00(a0), 0x0" f02880008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove ([0x10001fff], 0x20002fff), tt0" f03008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, ([0x30003fff], 0x40004fff)" f03020002fff30003fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x30003fff))) (bv 32 0x0)) (bv 32 0x40004fff)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, ([0x40004fff], 0x50005fff)" f03030003fff40004fff50005fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x40004fff))) (bv 32 0x0)) (bv 32 0x50005fff)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x0(a0, d4.w)" f0303fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4)))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, (a0, a0.w), 0x0" f03080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove 0xfff.w, tt0" f03808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xfff))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, 0x2fff.w" f03820002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x2fff))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, 0x3fff.w" f03830003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3fff))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x4000.w" f0383fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4000))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, 0x8100.w, 0x0" f03880008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xffff8100))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove 0xfff1000.l, tt0" f03908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xfff1000))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, 0x2fff3000.l" f03920002fff3000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x2fff3000))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, 0x3fff4000.l" f03930003fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3fff4000))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x40004fff.l" f0393fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x40004fff))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, 0x81008170.l, 0x0" f039800081008170 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x81008170))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove 0x1003(pc), tt0" f03a08000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x1003))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, 0x3003(pc)" f03a20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3003))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, 0x4003(pc)" f03a30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4003))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x4004(pc)" f03a3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4004))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, 0xffff8104(pc), 0x0" f03a80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xffff8104))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove ([0x10002003], 0x20002fff), tt0" f03b08000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, ([0x30004003], 0x40004fff)" f03b20002fff30003fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x30004001))) (bv 32 0x0)) (bv 32 0x40004fff)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, ([0x40005003], 0x50005fff)" f03b30003fff40004fff50005fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x40005001))) (bv 32 0x0)) (bv 32 0x50005fff)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x4(pc, d4.w)" f03b3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4)))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, 0x4(pc, a0.w), 0x0" f03b80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pmove 0xfff1000, tt0" f03c08000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (bv 32 0xfff1000)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ploadw sfc, 0xff" f03c20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0xff)) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush sfc, 0x0, 0xff" f03c30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0xff)) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush 0xf, 0x7, 0x0" f03c3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0x0)) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw sfc, 0x0, 0x0" f03c80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0x0)) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x3)) (! (== (var format) (bv 16 0x3)))) (&& (|| (! (ule (var format) (bv 16 0x9))) (== (var format) (bv 16 0x9))) (&& (ule (var format) (bv 16 0xc)) (! (== (var format) (bv 16 0xc)))))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr)))) diff --git a/test/db/asm/m68k_68040_32 b/test/db/asm/m68k_68040_32 new file mode 100644 index 0000000000..9f81b1ea7e --- /dev/null +++ b/test/db/asm/m68k_68040_32 @@ -0,0 +1,44 @@ +d "add fp0" f200007f +d "add fp0, fp1" f20000ff +d "fsmove fp1, fp2" f2000540 +d "fssqrt fp1, fp2" f2000541 +d "fdmove fp1, fp2" f2000544 +d "fdsqrt fp1, fp2" f2000545 +d "fsabs fp1, fp2" f2000558 +d "fsneg fp1, fp2" f200055a +d "fdabs fp1, fp2" f200055c +d "fdneg fp1, fp2" f200055e +d "fsdiv fp1, fp2" f2000560 +d "fsadd fp1, fp2" f2000562 +d "fsmul fp1, fp2" f2000563 +d "fddiv fp1, fp2" f2000564 +d "fdadd fp1, fp2" f2000566 +d "fdmul fp1, fp2" f2000567 +d "fssub fp1, fp2" f2000568 +d "fdsub fp1, fp2" f200056c +d "cinvl nc, (a0)" f408 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "cinvp nc, (a0)" f410 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "cinva nc" f418 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (set cache_all (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "cpushp nc, (a0)" f430 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "cpusha nc" f438 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x0)) (set cache_all (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "cpushl dc, (a0)" f468 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflushn (a0)" f500 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflush (a0)" f508 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflushan" f510 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x1)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pflusha" f518 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestw (a0)" f548 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "ptestr (a0)" f568 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "move16 (a0)+, 0x1.l" f60000000001 0x0 (seq (set src_addr (var a0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10))))) +d "move16 0x1.l, (a0)+" f60800000001 0x0 (seq (set src_addr (cast 32 false (bv 32 0x1))) (set dst_addr (var a0)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var dst_addr) (bv 32 0x10))))) +d "move16 (a0), 0x1.l" f61000000001 0x0 (seq (set src_addr (cast 32 false (var a0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3)))) +d "move16 0x1.l, (a0)" f61800000001 0x0 (seq (set src_addr (cast 32 false (bv 32 0x1))) (set dst_addr (cast 32 false (var a0))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3)))) +d "move16 (a0)+, (a0)+" f6208000 0x0 (seq (set src_addr (var a0)) (set dst_addr (var a0)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10))))) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x5)) (! (== (var format) (bv 16 0x5)))) (== (var format) (bv 16 0x7))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr)))) +d "fmove.x 0e1, fp0" f23c48003fff00008000000000000000 +d "fmove.p 0e1.2345678901234567e+025, fp0" f23c4c00002500012345678901234567 +d "fmove.p (a0), fp0" f2104c00 +d "fmove.p fp0, (a1){-5}" f2116c7b +d "fmove.p fp2, (a2){d3}" f2127d30 +d "fmove.p (a0)+, fp0" f2184c00 +d "fmove.p fp0, -(a0){17}" f2206c11 diff --git a/test/db/asm/m68k_68060_32 b/test/db/asm/m68k_68060_32 index 903cb507f2..492c2ea2b8 100644 --- a/test/db/asm/m68k_68060_32 +++ b/test/db/asm/m68k_68060_32 @@ -1,8 +1,8 @@ -d "move16 (a0)+, (a1)+" f6209000 -d "halt" 4ac8 -d "pflushn (a0)" f500 -d "pflush (a0)" f508 -d "pflushan" f510 -d "pflusha" f518 -d "plpaw (a0)" f588 -d "plpar (a0)" f5c8 +d "halt" 4ac8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x3)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "pulse" 4acc 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x4)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "plpaw (a0)" f588 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "plpar (a0)" f5c8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "move16 (a0)+, (a1)+" f6209000 0x0 (seq (set src_addr (var a0)) (set dst_addr (var a1)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10)))) (set a1 (cast 32 false (+ (var dst_addr) (bv 32 0x10))))) +d "lpstop 0x0" f80001c00000 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (&& (&& (ule (var format) (bv 16 0x5)) (! (== (var format) (bv 16 0x5)))) (! (== (var format) (bv 16 0x1)))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr)))) diff --git a/test/db/asm/m68k_cfv1_32 b/test/db/asm/m68k_cfv1_32 index bf36ec818f..17b63f075a 100644 --- a/test/db/asm/m68k_cfv1_32 +++ b/test/db/asm/m68k_cfv1_32 @@ -1,105 +1,276 @@ -d "mov3q.l 0x2, (a4)" a554 -d "mvs.b d0, d0" 7100 -d "mvs.w d0, d0" 7140 -d "mvz.b d0, d0" 7180 -d "mvz.w d0, d0" 71c0 -d "mvs.b d0, d1" 7300 -d "mov3q.l 0xffffffff, d0" a140 -d "mvs.b (a0), d1" 7310 -d "mvz.w (a0), d1" 73d0 -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "bra.l 0x12" 60ff00000010 -d "bsr.l 0x12" 61ff00000010 -d "bne.l 0x12" 66ff00000010 -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "sats.l d0" 4c80 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bitrev d0" 00c0 -d "byterev d1" 02c1 -d "ff1 d2" 04c2 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "halt" 4ac8 -d "strldsr.w 0x4d2" 40e746fc04d2 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "move usp, a0" 4e68 -d "move a0, usp" 4e60 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "intouch (a0)" f428 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "bitrev d0" 00c0 0x0 (seq (set src (var d0)) (set res (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var src) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1f) false)) (<< (& (>> (var src) (bv 32 0x1) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1e) false)) (<< (& (>> (var src) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1d) false)) (<< (& (>> (var src) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1c) false)) (<< (& (>> (var src) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1b) false)) (<< (& (>> (var src) (bv 32 0x5) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1a) false)) (<< (& (>> (var src) (bv 32 0x6) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x19) false)) (<< (& (>> (var src) (bv 32 0x7) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x18) false)) (<< (& (>> (var src) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x17) false)) (<< (& (>> (var src) (bv 32 0x9) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x16) false)) (<< (& (>> (var src) (bv 32 0xa) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x15) false)) (<< (& (>> (var src) (bv 32 0xb) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x14) false)) (<< (& (>> (var src) (bv 32 0xc) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x13) false)) (<< (& (>> (var src) (bv 32 0xd) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x12) false)) (<< (& (>> (var src) (bv 32 0xe) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x11) false)) (<< (& (>> (var src) (bv 32 0xf) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x10) false)) (<< (& (>> (var src) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xf) false)) (<< (& (>> (var src) (bv 32 0x11) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xe) false)) (<< (& (>> (var src) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xd) false)) (<< (& (>> (var src) (bv 32 0x13) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xc) false)) (<< (& (>> (var src) (bv 32 0x14) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xb) false)) (<< (& (>> (var src) (bv 32 0x15) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xa) false)) (<< (& (>> (var src) (bv 32 0x16) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x9) false)) (<< (& (>> (var src) (bv 32 0x17) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x8) false)) (<< (& (>> (var src) (bv 32 0x18) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x7) false)) (<< (& (>> (var src) (bv 32 0x19) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x6) false)) (<< (& (>> (var src) (bv 32 0x1a) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x5) false)) (<< (& (>> (var src) (bv 32 0x1b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x4) false)) (<< (& (>> (var src) (bv 32 0x1c) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x3) false)) (<< (& (>> (var src) (bv 32 0x1d) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x2) false)) (<< (& (>> (var src) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1) false)) (& (>> (var src) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set d0 (cast 32 false (var res)))) +d "byterev d1" 02c1 0x0 (seq (set src (var d1)) (set res (| (| (<< (& (var src) (bv 32 0xff)) (bv 8 0x18) false) (<< (& (var src) (bv 32 0xff00)) (bv 8 0x8) false)) (| (& (>> (var src) (bv 8 0x8) false) (bv 32 0xff00)) (>> (var src) (bv 8 0x18) false)))) (set d1 (cast 32 false (var res)))) +d "ff1 d2" 04c2 0x0 (seq (set src (var d2)) (set res (ite (! (is_zero (& (>> (var src) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (ite (! (is_zero (& (>> (var src) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1) (ite (! (is_zero (& (>> (var src) (bv 32 0x1d) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x2) (ite (! (is_zero (& (>> (var src) (bv 32 0x1c) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x3) (ite (! (is_zero (& (>> (var src) (bv 32 0x1b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x4) (ite (! (is_zero (& (>> (var src) (bv 32 0x1a) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x5) (ite (! (is_zero (& (>> (var src) (bv 32 0x19) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x6) (ite (! (is_zero (& (>> (var src) (bv 32 0x18) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x7) (ite (! (is_zero (& (>> (var src) (bv 32 0x17) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x8) (ite (! (is_zero (& (>> (var src) (bv 32 0x16) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x9) (ite (! (is_zero (& (>> (var src) (bv 32 0x15) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xa) (ite (! (is_zero (& (>> (var src) (bv 32 0x14) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xb) (ite (! (is_zero (& (>> (var src) (bv 32 0x13) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xc) (ite (! (is_zero (& (>> (var src) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xd) (ite (! (is_zero (& (>> (var src) (bv 32 0x11) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xe) (ite (! (is_zero (& (>> (var src) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xf) (ite (! (is_zero (& (>> (var src) (bv 32 0xf) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x10) (ite (! (is_zero (& (>> (var src) (bv 32 0xe) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x11) (ite (! (is_zero (& (>> (var src) (bv 32 0xd) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x12) (ite (! (is_zero (& (>> (var src) (bv 32 0xc) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x13) (ite (! (is_zero (& (>> (var src) (bv 32 0xb) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x14) (ite (! (is_zero (& (>> (var src) (bv 32 0xa) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x15) (ite (! (is_zero (& (>> (var src) (bv 32 0x9) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x16) (ite (! (is_zero (& (>> (var src) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x17) (ite (! (is_zero (& (>> (var src) (bv 32 0x7) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x18) (ite (! (is_zero (& (>> (var src) (bv 32 0x6) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x19) (ite (! (is_zero (& (>> (var src) (bv 32 0x5) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1a) (ite (! (is_zero (& (>> (var src) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1b) (ite (! (is_zero (& (>> (var src) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1c) (ite (! (is_zero (& (>> (var src) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1d) (ite (! (is_zero (& (>> (var src) (bv 32 0x1) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1e) (ite (! (is_zero (& (>> (var src) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1f) (bv 32 0x20)))))))))))))))))))))))))))))))))) (set d2 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (var src)) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (var src)) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "strldsr.w 0x4d2" 40e746fc04d2 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)) +d "strldsr.w 0x24d2" 40e746fc24d2 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set push_value (cast 32 false (var sr))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set sr_write_value (cast 16 false (bv 16 0x24d2))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "move.w ccr, d3" 42c3 0x0 (seq (set src (cast 16 false (cast 8 false (var sr)))) (set d3 (| (& (var d3) (bv 32 0xffff0000)) (cast 32 false (var src))))) +d "move.w d0, sr" 46c0 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (set sr_write_value (cast 16 false (var src))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l d0-d1, (a0)" 48d00003 0x0 (seq (set addr (cast 32 false (var a0))) (storew 0 (var addr) (cast 32 false (var d0))) (storew 0 (+ (var addr) (bv 32 0x4)) (cast 32 false (var d1)))) +d "sats.l d0" 4c80 0x0 (seq (set src (var d0)) (set res (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (ite (msb (var src)) (bv 32 0x7fffffff) (bv 32 0x80000000)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "link.w a0, 0x4" 4e500004 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x4))) (set a7 (cast 32 false (var new_sp)))) +d "move usp, a0" 4e68 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var usp)) (set a0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "stop 0x2700" 4e722700 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x1)) (set system_sr (bv 32 0x2700)) (set sr_write_value (cast 16 false (bv 16 0x2700))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movec cacr, d1" 4e7a1002 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set d1 (cast 32 false (var cacr))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movec d0, cacr" 4e7b0002 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cacr_write_value (cast 32 false (var d0))) (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (^^ (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10)))) (! (is_zero (& (cast 32 false (var cacr_write_value)) (bv 32 0x10)))))) (branch (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10)))) (seq (set isp (cast 32 false (var a7))) (set a7 (cast 32 false (var usp)))) (seq (set usp (cast 32 false (var a7))) (set a7 (cast 32 false (var isp))))) empty) (set cacr (var cacr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "tpf.w 0x1234" 51fa1234 0x0 nop +d "tpf.l 0x12345678" 51fb12345678 0x0 nop +d "tpf" 51fc 0x0 nop +d "addq.l 0x1, d0" 5280 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (+ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "subq.l 0x1, d0" 5380 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "bra.l 0x12" 60ff00000010 0x0 (jmp (bv 32 0x12)) +d "bsr.l 0x12" 61ff00000010 0x0 (seq (set push_value (bv 32 0x6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x12))) +d "bne.l 0x12" 66ff00000010 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x12)) empty) +d "mvs.b d0, d0" 7100 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b (a0)+, d0" 7118 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b -(a0), d0" 7120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x0(a0), d0" 71280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x0(a0, d0.w), d0" 71300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b (a0, d0.w), d0" 71300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b ([0x18001ff, a0], 0x8000fff), d0" 7130017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x0.w, d0" 71380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x1.l, d0" 713900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x2(pc), d0" 713a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x2(pc, d0.w), d0" 713b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b ([0x1800201, pc], 0x8000fff), d0" 713b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b 0x0, d0" 713c0000 0x0 (seq (set src (bv 8 0x0)) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w d0, d0" 7140 0x0 (seq (set src (cast 16 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w a0, d0" 7148 0x0 (seq (set src (cast 16 false (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w (a0), d0" 7150 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w (a0)+, d0" 7158 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w -(a0), d0" 7160 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x0(a0), d0" 71680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x0(a0, d0.w), d0" 71700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w (a0, d0.w), d0" 71700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w ([0x18001ff, a0], 0x8000fff), d0" 7170017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x0.w, d0" 71780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x1.l, d0" 717900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x2(pc), d0" 717a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x2(pc, d0.w), d0" 717b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w ([0x1800201, pc], 0x8000fff), d0" 717b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.w 0x0, d0" 717c0000 0x0 (seq (set src (bv 16 0x0)) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b d0, d0" 7180 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b (a0), d0" 7190 0x0 (seq (set src (loadw 0 8 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b (a0)+, d0" 7198 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b -(a0), d0" 71a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x0(a0), d0" 71a80000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x0(a0, d0.w), d0" 71b00000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b (a0, d0.w), d0" 71b00100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b ([0x18001ff, a0], 0x8000fff), d0" 71b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x0.w, d0" 71b80000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x1.l, d0" 71b900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x2(pc), d0" 71ba0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x2(pc, d0.w), d0" 71bb0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b ([0x1800201, pc], 0x8000fff), d0" 71bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.b 0x0, d0" 71bc0000 0x0 (seq (set src (bv 8 0x0)) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w d0, d0" 71c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w a0, d0" 71c8 0x0 (seq (set src (cast 16 false (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w (a0)+, d0" 71d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w -(a0), d0" 71e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x0(a0), d0" 71e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x0(a0, d0.w), d0" 71f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w (a0, d0.w), d0" 71f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w ([0x18001ff, a0], 0x8000fff), d0" 71f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x0.w, d0" 71f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x1.l, d0" 71f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x2(pc), d0" 71fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x2(pc, d0.w), d0" 71fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w ([0x1800201, pc], 0x8000fff), d0" 71fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w 0x0, d0" 71fc0000 0x0 (seq (set src (bv 16 0x0)) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b d0, d1" 7300 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvs.b (a0), d1" 7310 0x0 (seq (set src (loadw 0 8 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mvz.w (a0), d1" 73d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (cast 32 false (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, d0" a140 0x0 (seq (set res (bv 32 0xffffffff)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, a0" a148 0x0 (seq (set res (bv 32 0xffffffff)) (set a0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, (a0)+" a158 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (var a0) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, -(a0)" a160 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set res (bv 32 0xffffffff)) (storew 0 (var a0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x0(a0)" a1680000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x0(a0, d0.w)" a1700000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, (a0, d0.w)" a1700100 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, ([0x18001ff, a0], 0x8000fff)" a170017f018001ff08000fff 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x0.w" a1780000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x1.l" a17900000001 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x1) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x2(pc)" a17a0000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x2) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x2(pc, d0.w)" a17b0000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, ([0x1800201, pc], 0x8000fff)" a17b017f018001ff08000fff 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0xffffffff, 0x1" a17c00000001 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x1) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "mov3q.l 0x2, (a4)" a554 0x0 (seq (set res (bv 32 0x2)) (storew 0 (var a4) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "intouch (a0)" f428 0x0 (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x0)) (goto m68k_cache)) +d "cpushl bc, (a0)" f4e8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x3)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "wddata.b (a0)" fb10 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b (a0)+" fb18 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b -(a0)" fb20 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b 0x0(a0)" fb280000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b 0x0(a0, d0.w)" fb300000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b (a0, d0.w)" fb300100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b ([0x18001ff, a0], 0x8000fff)" fb30017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b 0x0.w" fb380000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.b 0x1.l" fb3900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug)) +d "wddata.w (a0)" fb50 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w (a0)+" fb58 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w -(a0)" fb60 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w 0x0(a0)" fb680000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w 0x0(a0, d0.w)" fb700000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w (a0, d0.w)" fb700100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w ([0x18001ff, a0], 0x8000fff)" fb70017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w 0x0.w" fb780000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.w 0x1.l" fb7900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug)) +d "wddata.l (a0)" fb90 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l (a0)+" fb98 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l -(a0)" fba0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l 0x0(a0)" fba80000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l 0x0(a0, d0.w)" fbb00000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l (a0, d0.w)" fbb00100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l ([0x18001ff, a0], 0x8000fff)" fbb0017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l 0x0.w" fbb80000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wddata.l 0x1.l" fbb900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "wdebug.l (a0)" fbd00003 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x1)) (set debug_bits (bv 32 0x20)) (goto m68k_debug)) +d "cp0ld.b d0, d0, 0x1, 0x1" fc000001 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0nop 0x8" fc000e00 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x8)) (goto m68k_coprocessor)) +d "cp0ld.b d0, a0, 0x1, 0x0" fc008000 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b a0, d0, 0x1, 0x0" fc080000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b a0, a0, 0x1, 0x0" fc088000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b (a0), d0, 0x1, 0x0" fc100000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b (a0), a0, 0x1, 0x0" fc108000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b (a0)+, d0, 0x1, 0x0" fc180000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x6)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0ld.b -(a0), d0, 0x1, 0x0" fc200000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b -(a0), a0, 0x1, 0x0" fc208000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b 0x1(a0), d0, 0x1, 0x0" fc2800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.b -0x7f00(a0), a0, 0x1, 0x0" fc2880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w d0, d0, 0x1, 0x1" fc400001 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0ld.w d0, a0, 0x1, 0x0" fc408000 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w a0, d0, 0x1, 0x0" fc480000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w a0, a0, 0x1, 0x0" fc488000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w (a0), d0, 0x1, 0x0" fc500000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0ld.w (a0)+, d0, 0x1, 0x0" fc580000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w (a0)+, a0, 0x1, 0x0" fc588000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w -(a0), d0, 0x1, 0x0" fc600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w -(a0), a0, 0x1, 0x0" fc608000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w 0x1(a0), d0, 0x1, 0x0" fc6800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.w -0x7f00(a0), a0, 0x1, 0x0" fc6880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0nop 0x3" fc800400 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x3)) (goto m68k_coprocessor)) +d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor)) +d "cp0ld.l d0, a0, 0x1, 0x0" fc808000 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l a0, d0, 0x1, 0x0" fc880000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l a0, a0, 0x1, 0x0" fc888000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l (a0), d0, 0x1, 0x0" fc900000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l (a0), a0, 0x1, 0x0" fc908000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l (a0)+, d0, 0x1, 0x0" fc980000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l (a0)+, a0, 0x1, 0x0" fc988000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l -(a0), d0, 0x1, 0x0" fca00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l -(a0), a0, 0x1, 0x0" fca08000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l 0x1(a0), d0, 0x1, 0x0" fca800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x8)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0bcbusy 0x52" fcc00050 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x1)) (set cp_branch (bv 32 0x52)) (goto m68k_coprocessor)) +d "cp0st.b d0, d0, 0x1, 0x0" fd000000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, d0, 0x1, 0x0" fd008000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b d0, a0, 0x1, 0x0" fd080000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, a0, 0x1, 0x0" fd088000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b d0, (a0), 0x1, 0x0" fd100000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, (a0), 0x1, 0x0" fd108000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b d0, (a0)+, 0x1, 0x0" fd180000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, (a0)+, 0x1, 0x0" fd188000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b d0, -(a0), 0x1, 0x0" fd200000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, -(a0), 0x1, 0x0" fd208000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b d0, 0x1(a0), 0x1, 0x0" fd2800000001 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.b a0, -0x7f00(a0), 0x1, 0x0" fd2880008100 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w d0, d0, 0x1, 0x0" fd400000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a0, d0, 0x1, 0x0" fd408000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w d0, a0, 0x1, 0x0" fd480000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a0, a0, 0x1, 0x0" fd488000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w d0, (a0), 0x1, 0x0" fd500000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp0st.w d0, (a0)+, 0x1, 0x0" fd580000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a0, (a0)+, 0x1, 0x0" fd588000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w d0, -(a0), 0x1, 0x0" fd600000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a0, -(a0), 0x1, 0x0" fd608000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w d0, 0x1(a0), 0x1, 0x0" fd6800000001 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.w a0, -0x7f00(a0), 0x1, 0x0" fd6880008100 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d2, d0, 0x1, 0x123" fd802123 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor)) +d "cp0st.l a0, d0, 0x1, 0x0" fd808000 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d0, a0, 0x1, 0x0" fd880000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l a0, a0, 0x1, 0x0" fd888000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d0, (a0), 0x1, 0x0" fd900000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l a0, (a0), 0x1, 0x0" fd908000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d0, (a0)+, 0x1, 0x0" fd980000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l a0, (a0)+, 0x1, 0x0" fd988000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d0, -(a0), 0x1, 0x0" fda00000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l a0, -(a0), 0x1, 0x0" fda08000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l d0, 0x1(a0), 0x1, 0x0" fda800000001 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp0st.l a0, -0x7f00(a0), 0x1, 0x0" fda880008100 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b d0, d0, 0x1, 0x1" fe000001 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp1nop 0x8" fe000e00 0x0 (seq (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x8)) (goto m68k_coprocessor)) +d "cp1ld.b d0, a0, 0x1, 0x0" fe008000 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b a0, d0, 0x1, 0x0" fe080000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b a0, a0, 0x1, 0x0" fe088000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b (a0), d0, 0x1, 0x0" fe100000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b (a0), a0, 0x1, 0x0" fe108000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b (a0)+, d0, 0x1, 0x0" fe180000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b (a0)+, a0, 0x1, 0x0" fe188000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b -(a0), d0, 0x1, 0x0" fe200000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b -(a0), a0, 0x1, 0x0" fe208000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b 0x1(a0), d0, 0x1, 0x0" fe2800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.b -0x7f00(a0), a0, 0x1, 0x0" fe2880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w d0, d0, 0x1, 0x1" fe400001 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor)) +d "cp1ld.w d0, a0, 0x1, 0x0" fe408000 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w a0, d0, 0x1, 0x0" fe480000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w a0, a0, 0x1, 0x0" fe488000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w (a0), d0, 0x1, 0x0" fe500000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w (a0), a0, 0x1, 0x0" fe508000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w (a0)+, d0, 0x1, 0x0" fe580000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w (a0)+, a0, 0x1, 0x0" fe588000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w -(a0), d0, 0x1, 0x0" fe600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w -(a0), a0, 0x1, 0x0" fe608000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w 0x1(a0), d0, 0x1, 0x0" fe6800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.w -0x7f00(a0), a0, 0x1, 0x0" fe6880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor)) +d "cp1ld.l d0, a0, 0x1, 0x0" fe808000 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l a0, d0, 0x1, 0x0" fe880000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l a0, a0, 0x1, 0x0" fe888000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l (a0), d0, 0x1, 0x0" fe900000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l (a0), a0, 0x1, 0x0" fe908000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l (a0)+, d0, 0x1, 0x0" fe980000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l (a0)+, a0, 0x1, 0x0" fe988000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l -(a0), d0, 0x1, 0x0" fea00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l -(a0), a0, 0x1, 0x0" fea08000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l 0x1(a0), d0, 0x1, 0x0" fea800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1ld.l -0x7f00(a0), a0, 0x1, 0x0" fea880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1bcbusy 0x52" fec00050 0x0 (seq (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x1)) (set cp_branch (bv 32 0x52)) (goto m68k_coprocessor)) +d "cp1st.b d0, d0, 0x1, 0x0" ff000000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, d0, 0x1, 0x0" ff008000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b d0, a0, 0x1, 0x0" ff080000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, a0, 0x1, 0x0" ff088000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b d0, (a0), 0x1, 0x0" ff100000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, (a0), 0x1, 0x0" ff108000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b d0, (a0)+, 0x1, 0x0" ff180000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, (a0)+, 0x1, 0x0" ff188000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b d0, -(a0), 0x1, 0x0" ff200000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, -(a0), 0x1, 0x0" ff208000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b d0, 0x1(a0), 0x1, 0x0" ff2800000001 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.b a0, -0x7f00(a0), 0x1, 0x0" ff2880008100 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, d0, 0x1, 0x0" ff400000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, d0, 0x1, 0x0" ff408000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, a0, 0x1, 0x0" ff480000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, a0, 0x1, 0x0" ff488000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, (a0), 0x1, 0x0" ff500000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, (a0), 0x1, 0x0" ff508000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, (a0)+, 0x1, 0x0" ff580000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, (a0)+, 0x1, 0x0" ff588000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, -(a0), 0x1, 0x0" ff600000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, -(a0), 0x1, 0x0" ff608000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w d0, 0x1(a0), 0x1, 0x0" ff6800000001 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.w a0, -0x7f00(a0), 0x1, 0x0" ff6880008100 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d2, d0, 0x1, 0x123" ff802123 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor)) +d "cp1st.l a0, d0, 0x1, 0x0" ff808000 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d0, a0, 0x1, 0x0" ff880000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l a0, a0, 0x1, 0x0" ff888000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d0, (a0), 0x1, 0x0" ff900000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l a0, (a0), 0x1, 0x0" ff908000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d0, (a0)+, 0x1, 0x0" ff980000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l a0, (a0)+, 0x1, 0x0" ff988000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d0, -(a0), 0x1, 0x0" ffa00000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l a0, -(a0), 0x1, 0x0" ffa08000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l d0, 0x1(a0), 0x1, 0x0" ffa800000001 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) +d "cp1st.l a0, -0x7f00(a0), 0x1, 0x0" ffa880008100 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor)) diff --git a/test/db/asm/m68k_cfv2_32 b/test/db/asm/m68k_cfv2_32 index 9aba77891a..c30dc76aa7 100644 --- a/test/db/asm/m68k_cfv2_32 +++ b/test/db/asm/m68k_cfv2_32 @@ -1,90 +1,14 @@ -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "divs.l d0, d2" 4c402802 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "halt" 4ac8 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "remu.l d0, d1:d2" 4c402001 0x0 (seq (set src (var d0)) (set dst (var d2)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "rems.l d0, d1:d2" 4c402801 0x0 (seq (set src (var d0)) (set dst (var d2)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (&& (== (var dst) (bv 32 0x80000000)) (== (var src) (bv 32 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l (a0), d1:d0" 4c500001 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l (a0)+, d1:d0" 4c580001 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l -(a0), d1:d0" 4c600001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x10(a0), d1:d0" 4c6800010010 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x10(a0, d0.w), d1:d0" 4c7000010010 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l ([0x20002fff], 0x30003fff), d0:d1" 4c7010001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x10.w, d1:d0" 4c7800010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x10))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x10007f.l, d1:d0" 4c7900010010007f 0x0 (seq (set src (loadw 0 32 (bv 32 0x10007f))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x14(pc), d1:d0" 4c7a00010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x14))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x14(pc, d0.w), d1:d0" 4c7b00010010 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x14) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l ([0x20003003], 0x30003fff), d0:d1" 4c7b10001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) +d "remu.l 0x10007f, d1:d0" 4c7c00010010007f 0x0 (seq (set src (bv 32 0x10007f)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))))) diff --git a/test/db/asm/m68k_cfv3_32 b/test/db/asm/m68k_cfv3_32 index 9aba77891a..f0552467ba 100644 --- a/test/db/asm/m68k_cfv3_32 +++ b/test/db/asm/m68k_cfv3_32 @@ -1,90 +1 @@ -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "divs.l d0, d2" 4c402802 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "halt" 4ac8 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "moveq 0x1, d0" 7001 0x0 (seq (set res (bv 32 0x1)) (set d0 (cast 32 false (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) diff --git a/test/db/asm/m68k_cfv4_32 b/test/db/asm/m68k_cfv4_32 index 105849a333..76341050a9 100644 --- a/test/db/asm/m68k_cfv4_32 +++ b/test/db/asm/m68k_cfv4_32 @@ -1,108 +1 @@ -d "mov3q.l 0x2, (a4)" a554 -d "mvs.b d0, d0" 7100 -d "mvs.w d0, d0" 7140 -d "mvz.b d0, d0" 7180 -d "mvz.w d0, d0" 71c0 -d "mvs.b d0, d1" 7300 -d "mov3q.l 0xffffffff, d0" a140 -d "mvs.b (a0), d1" 7310 -d "mvz.w (a0), d1" 73d0 -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "bra.l 0x12" 60ff00000010 -d "bsr.l 0x12" 61ff00000010 -d "bne.l 0x12" 66ff00000010 -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "sats.l d0" 4c80 -d "divs.l d0, d2" 4c402802 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bitrev d0" 00c0 -d "byterev d1" 02c1 -d "ff1 d2" 04c2 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "halt" 4ac8 -d "strldsr.w 0x4d2" 40e746fc04d2 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "intouch (a0)" f428 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "sats.l d0" 4c80 0x0 (seq (set src (var d0)) (set res (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (ite (msb (var src)) (bv 32 0x7fffffff) (bv 32 0x80000000)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) diff --git a/test/db/asm/m68k_cfv4e_32 b/test/db/asm/m68k_cfv4e_32 index 4720ba2461..2880f3c31b 100644 --- a/test/db/asm/m68k_cfv4e_32 +++ b/test/db/asm/m68k_cfv4e_32 @@ -1,211 +1,150 @@ -d "mov3q.l 0x2, (a4)" a554 -d "mvs.b d0, d0" 7100 -d "mvs.w d0, d0" 7140 -d "mvz.b d0, d0" 7180 -d "mvz.w d0, d0" 71c0 -d "mvs.b d0, d1" 7300 -d "fsmove fp1, fp2" f2000540 -d "fdmove fp1, fp2" f2000544 -d "mov3q.l 0xffffffff, d0" a140 -d "mvs.b (a0), d1" 7310 -d "mvz.w (a0), d1" 73d0 -d "move.l d0, acc0" a100 -d "move.l acc0, d0" a180 -d "move.l 0x12345678, acc0" a13c12345678 -d "move.l d0, macsr" a900 -d "move.l macsr, d0" a980 -d "move.l 0x7, macsr" a93c00000007 -d "move.l d0, mask" ad00 -d "move.l mask, d0" ad80 -d "move.l 0x7, mask" ad3c00000007 -d "movclr.l acc0, d0" a1c0 -d "move.l d0, accext01" ab00 -d "move.l accext01, d0" ab80 -d "move.l 0x7, accext01" ab3c00000007 -d "move.l d0, accext23" af00 -d "fmove.l d0, fp0" f2004000 -d "fmove.l fp0, d0" f2006000 -d "fmove.s 1.000000, fp1" f23c44803f800000 -d "fmove.d 3.141593, fp1" f23c5480400921fb54442d18 -d "fmove.w (a0), fp0" f2105000 -d "fmove.s fp0, (a0)" f2106400 -d "fmovecr 0xf, fp6" f2005f0f -d "fmove.l d0, fpcr" f2009000 -d "fmove.l fpcr, d0" f200b000 -d "fmove.l d0, fpsr" f2008800 -d "fmove.l fpiar, d0" f200a400 -d "fmovem (a0)+, fp6-fp7" f218d003 -d "fmovem fp0-fp1, -(a0)" f220e003 -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "bra.l 0x12" 60ff00000010 -d "bsr.l 0x12" 61ff00000010 -d "bne.l 0x12" 66ff00000010 -d "fnop" f2800000 +d "msac.l d0, d0, >>, acc2" a0000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0))))) +d "mac.w d1l, d0l, acc0" a0010000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.w d1l, d0l, acc0" a0010100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.w d1l, d0u, <<, acc0" a0010280 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var d0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var d0) (bv 8 0x10) false))) (cast 16 false (>> (var d0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var d0) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.w d2l, d0l, >>, acc0" a0020600 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d2) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d2))) (cast 16 false (var d2))) (cast 32 false (cast 16 false (var d2)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.w a0l, d0l, acc0" a0080000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.w a0l, d0l, acc0" a0080100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.l a0, d0, acc0" a0080800 0x0 (seq (set src0 (var a0)) (set src1 (var d0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.l a0, d0, >>, acc2" a0080fff 0x0 (seq (set src0 (var a0)) (set src1 (var d0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0))))) +d "mac.w d0l, d0l, (a0), d0, acc1" a0100000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, (a0)&, d0, acc3" a010007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, (a0), d0, acc1" a0100100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, (a0)&, d0, acc3" a010017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, (a0), d0, acc1" a0100800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, (a0)&, d0, acc3" a0100fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, (a0)&, d0, acc3" a0101234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, (a0)&, d0, acc3" a0105678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, (a0), d0, acc1" a0108000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, (a0), d0, acc1" a0108100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, (a0)&, d0, acc3" a01091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, (a0)&, d0, acc3" a0109abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, (a0)&, d0, acc3" a010ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, d0l, (a0)+, d0, acc1" a0180000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w a7u, d0l, (a0)+&, d0, acc3" a018007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w d0l, d0l, (a0)+, d0, acc1" a0180100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w a7u, d0l, (a0)+&, d0, acc3" a018017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.l d0, d0, (a0)+, d0, acc1" a0180800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.l a7, d0, >>, (a0)+&, d0, acc3" a0180fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d4l, d1l, <<, (a0)+&, d0, acc3" a0181234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w a0u, d5l, >>, (a0)+&, d0, acc3" a0185678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d0l, a0l, (a0)+, d0, acc1" a0188000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w d0l, a0l, (a0)+, d0, acc1" a0188100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w a7u, a1u, (a0)+&, d0, acc3" a01891ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.l a4, a1, <<, (a0)+&, d0, acc3" a0189abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.l a7, a7, >>, (a0)+&, d0, acc3" a018ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d0l, d0l, -(a0), d0, acc1" a0200000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, -(a0)&, d0, acc3" a020007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, -(a0), d0, acc1" a0200100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, -(a0)&, d0, acc3" a020017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, -(a0), d0, acc1" a0200800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, -(a0)&, d0, acc3" a0200fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, -(a0)&, d0, acc3" a0201234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, -(a0)&, d0, acc3" a0205678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, -(a0), d0, acc1" a0208000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, -(a0), d0, acc1" a0208100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, -(a0)&, d0, acc3" a02091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, -(a0)&, d0, acc3" a0209abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, -(a0)&, d0, acc3" a020ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, d0l, 0x1(a0), d0, acc1" a02800000001 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, 0x80(a0)&, d0, acc3" a028007f0080 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x80))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, 0x17f(a0), d0, acc1" a0280100017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, 0x180(a0)&, d0, acc3" a028017f0180 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, 0xfff(a0), d0, acc1" a02808000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, 0x1000(a0)&, d0, acc3" a0280fff1000 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, 0x5678(a0)&, d0, acc3" a02812345678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x5678))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, -0x6544(a0)&, d0, acc3" a02856789abc 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff9abc))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, -0x7f00(a0), d0, acc1" a02880008100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, -0x7e90(a0), d0, acc1" a02881008170 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8170))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, -0x5f00(a0)&, d0, acc3" a02891ffa100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffa100))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, 0x0(a0)&, d0, acc3" a0289abc0000 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, 0x1234(a0)&, d0, acc3" a028ffff1234 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1234))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, acc0" a0400000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.w d0l, a0l, acc0" a0400100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.l d0, a0, acc0" a0400800 0x0 (seq (set src0 (var d0)) (set src1 (var a0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.l d0, a0, >>, acc2" a0400fff 0x0 (seq (set src0 (var d0)) (set src1 (var a0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0))))) +d "mac.w a0l, a0l, acc0" a0480000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.w a0l, a0l, acc0" a0480100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.l a0, a0, acc0" a0480800 0x0 (seq (set src0 (var a0)) (set src1 (var a0)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.l a0, a0, >>, acc2" a0480fff 0x0 (seq (set src0 (var a0)) (set src1 (var a0)) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x400))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x400) (bv 32 0x0))))) +d "mac.w d0l, d0l, (a0), a0, acc1" a0500000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, (a0)&, a0, acc3" a050007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, (a0), a0, acc1" a0500100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, (a0)&, a0, acc3" a050017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, (a0), a0, acc1" a0500800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, (a0)&, a0, acc3" a0500fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, (a0)&, a0, acc3" a0501234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, (a0)&, a0, acc3" a0505678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, (a0), a0, acc1" a0508000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, (a0), a0, acc1" a0508100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, (a0)&, a0, acc3" a05091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, (a0)&, a0, acc3" a0509abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, (a0)&, a0, acc3" a050ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d0l, d0l, (a0)+, a0, acc1" a0580000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w a7u, d0l, (a0)+&, a0, acc3" a058007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w d0l, d0l, (a0)+, a0, acc1" a0580100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w a7u, d0l, (a0)+&, a0, acc3" a058017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.l d0, d0, (a0)+, a0, acc1" a0580800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.l a7, d0, >>, (a0)+&, a0, acc3" a0580fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d4l, d1l, <<, (a0)+&, a0, acc3" a0581234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w a0u, d5l, >>, (a0)+&, a0, acc3" a0585678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d0l, a0l, (a0)+, a0, acc1" a0588000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w d0l, a0l, (a0)+, a0, acc1" a0588100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.w a7u, a1u, (a0)+&, a0, acc3" a05891ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.l a4, a1, <<, (a0)+&, a0, acc3" a0589abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "msac.l a7, a7, >>, (a0)+&, a0, acc3" a058ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load))) (set a0 (cast 32 false (+ (var mac_ea) (bv 32 0x4))))) +d "mac.w d0l, d0l, -(a0), a0, acc1" a0600000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, -(a0)&, a0, acc3" a060007f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, -(a0), a0, acc1" a0600100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, -(a0)&, a0, acc3" a060017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, -(a0), a0, acc1" a0600800 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, -(a0)&, a0, acc3" a0600fff 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, -(a0)&, a0, acc3" a0601234 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, -(a0)&, a0, acc3" a0605678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, -(a0), a0, acc1" a0608000 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, -(a0), a0, acc1" a0608100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, -(a0)&, a0, acc3" a06091ff 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, -(a0)&, a0, acc3" a0609abc 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, -(a0)&, a0, acc3" a060ffff 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mac_ea (cast 32 false (var a0))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d0l, d0l, 0x1(a0), a0, acc1" a06800000001 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a7u, d0l, 0x80(a0)&, a0, acc3" a068007f0080 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x80))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, d0l, 0x17f(a0), a0, acc1" a0680100017f 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, d0l, 0x180(a0)&, a0, acc3" a068017f0180 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l d0, d0, 0xfff(a0), a0, acc1" a06808000fff 0x0 (seq (set src0 (var d0)) (set src1 (var d0)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, d0, >>, 0x1000(a0)&, a0, acc3" a0680fff1000 0x0 (seq (set src0 (var a7)) (set src1 (var d0)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1000))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d4l, d1l, <<, 0x5678(a0)&, a0, acc3" a06812345678 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d4) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4))) (cast 32 false (cast 16 false (var d4)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x5678))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w a0u, d5l, >>, -0x6544(a0)&, a0, acc3" a06856789abc 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a0) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 16 false (>> (var a0) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a0) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d5) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d5))) (cast 16 false (var d5))) (cast 32 false (cast 16 false (var d5)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff9abc))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.w d0l, a0l, -0x7f00(a0), a0, acc1" a06880008100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w d0l, a0l, -0x7e90(a0), a0, acc1" a06881008170 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))) (cast 32 false (cast 16 false (var a0)))))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8170))))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.w a7u, a1u, -0x5f00(a0)&, a0, acc3" a06891ffa100 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a7) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 16 false (>> (var a7) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a7) (bv 8 0x10) false)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a1) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 16 false (>> (var a1) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a1) (bv 8 0x10) false)))))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffffa100))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "mac.l a4, a1, <<, 0x0(a0)&, a0, acc3" a0689abc0000 0x0 (seq (set src0 (var a4)) (set src1 (var a1)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "msac.l a7, a7, >>, 0x1234(a0)&, a0, acc3" a068ffff1234 0x0 (seq (set src0 (var a7)) (set src1 (var a7)) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x800) (bv 32 0x0)))) (set mac_ea (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1234))))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set a0 (cast 32 false (var mem_load)))) +d "move.l d0, acc0" a100 0x0 (seq (set src (var d0)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0))))) +d "move.l a0, acc0" a108 0x0 (seq (set src (var a0)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0))))) +d "move.l 0x12345678, acc0" a13c12345678 0x0 (seq (set src (bv 32 0x12345678)) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (msb (var src)) (bv 32 0xff00) (bv 32 0x0)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (msb (var src)) (bv 32 0xffff) (bv 32 0x0)) (bv 32 0x0)))) (set acc0 (cast 32 false (var src))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (& (var macsr) (bv 32 0xfffffef0)) (ite (! (is_zero (& (var ext16) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0))))) +d "move.l acc0, d0" a180 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set d0 (cast 32 false (var stored)))) +d "move.l acc0, a0" a188 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set a0 (cast 32 false (var stored)))) +d "move.l acc0, acc1" a310 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set acc1 (cast 32 false (var src))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (& (var macsr) (bv 32 0xfffffdf0)) (ite (! (is_zero (& (cast 32 false (var ext16)) (bv 32 0x8000)))) (bv 32 0x8) (bv 32 0x0))) (ite (&& (is_zero (var src)) (is_zero (var ext16))) (bv 32 0x4) (bv 32 0x0))) (ite (! (is_zero (& (var macsr) (bv 32 0x100)))) (bv 32 0x202) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (! (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (! (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff)))) (! (is_zero (var ext16))))) (bv 32 0x1) (bv 32 0x0))))) +d "movclr.l acc0, d0" a1c0 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set d0 (cast 32 false (var stored))) (set acc0 (cast 32 false (bv 32 0x0))) (set accext01 (cast 32 false (& (var accext01) (bv 32 0xffff0000)))) (set macsr (& (var macsr) (bv 32 0xfffffeff)))) +d "movclr.l acc0, a0" a1c8 0x0 (seq (set src (var acc0)) (set ext16 (cast 16 false (var accext01))) (set ext_hi (>> (cast 32 false (var ext16)) (bv 8 0x8) false)) (set ext_lo (& (cast 32 false (var ext16)) (bv 32 0xff))) (set hi16 (>> (var src) (bv 8 0x10) false)) (set frac24 (| (<< (& (var src) (bv 32 0xffff)) (bv 8 0x8) false) (var ext_lo))) (set bits_47_31 (| (<< (cast 32 false (var ext16)) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set bits_47_39 (| (<< (var ext_hi) (bv 8 0x1) false) (ite (msb (var src)) (bv 32 0x1) (bv 32 0x0)))) (set field40 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x20) false) (cast 64 false (var src)))) (set field24 (| (<< (cast 64 false (var ext_hi)) (bv 8 0x10) false) (cast 64 false (var hi16)))) (set rnd32 (ite (&& (ule (var ext_lo) (bv 32 0x80)) (! (== (var ext_lo) (bv 32 0x80)))) (var src) (ite (! (ule (var ext_lo) (bv 32 0x80))) (+ (var src) (bv 32 0x1)) (ite (! (is_zero (& (var src) (bv 32 0x1)))) (+ (var src) (bv 32 0x1)) (var src))))) (set rnd16 (ite (&& (ule (var frac24) (bv 32 0x800000)) (! (== (var frac24) (bv 32 0x800000)))) (var hi16) (ite (! (ule (var frac24) (bv 32 0x800000))) (+ (var hi16) (bv 32 0x1)) (ite (! (is_zero (& (var hi16) (bv 32 0x1)))) (+ (var hi16) (bv 32 0x1)) (var hi16))))) (set rnd40 (ite (&& (ule (cast 64 false (var ext_lo)) (bv 64 0x80)) (! (== (cast 64 false (var ext_lo)) (bv 64 0x80)))) (var field40) (ite (! (ule (cast 64 false (var ext_lo)) (bv 64 0x80))) (+ (var field40) (bv 64 0x1)) (ite (! (is_zero (& (var field40) (bv 64 0x1)))) (+ (var field40) (bv 64 0x1)) (var field40))))) (set rnd24 (ite (&& (ule (cast 64 false (var frac24)) (bv 64 0x800000)) (! (== (cast 64 false (var frac24)) (bv 64 0x800000)))) (var field24) (ite (! (ule (cast 64 false (var frac24)) (bv 64 0x800000))) (+ (var field24) (bv 64 0x1)) (ite (! (is_zero (& (var field24) (bv 64 0x1)))) (+ (var field24) (bv 64 0x1)) (var field24))))) (set rnd32_bits_47_39 (cast 32 false (& (>> (var rnd40) (bv 8 0x1f) false) (bv 64 0x1ff)))) (set rnd16_bits_47_39 (cast 32 false (& (>> (var rnd24) (bv 8 0xf) false) (bv 64 0x1ff)))) (set stored (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (! (is_zero (& (var macsr) (bv 32 0x40)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (|| (is_zero (var rnd16_bits_47_39)) (== (var rnd16_bits_47_39) (bv 32 0x1ff))) (& (var rnd16) (bv 32 0xffff)) (ite (! (is_zero (& (var rnd24) (bv 64 0x800000)))) (bv 32 0x8000) (bv 32 0x7fff))) (& (var rnd16) (bv 32 0xffff))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (ite (|| (is_zero (var rnd32_bits_47_39)) (== (var rnd32_bits_47_39) (bv 32 0x1ff))) (var rnd32) (ite (! (is_zero (& (var rnd40) (bv 64 0x8000000000)))) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (|| (is_zero (var bits_47_39)) (== (var bits_47_39) (bv 32 0x1ff))) (var src) (ite (! (is_zero (& (var ext_hi) (bv 32 0x80)))) (bv 32 0x80000000) (bv 32 0x7fffffff)))) (ite (! (is_zero (& (var macsr) (bv 32 0x10)))) (var rnd32) (var src)))) (ite (! (is_zero (& (var macsr) (bv 32 0x80)))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (ite (|| (is_zero (var bits_47_31)) (== (var bits_47_31) (bv 32 0x1ffff))) (var src) (ite (msb (var ext16)) (bv 32 0x80000000) (bv 32 0x7fffffff))) (ite (is_zero (var ext16)) (var src) (bv 32 0xffffffff))) (var src)))) (set a0 (cast 32 false (var stored))) (set acc0 (cast 32 false (bv 32 0x0))) (set accext01 (cast 32 false (& (var accext01) (bv 32 0xffff0000)))) (set macsr (& (var macsr) (bv 32 0xfffffeff)))) +d "mac.w a1l, a2u, (a3), d1, acc0" a293a089 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load)))) +d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (& (var mac_ea) (var mask))) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load)))) +d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load)))) +d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load)))) +d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var a1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var a1))) (cast 16 false (var a1))) (cast 32 false (cast 16 false (var a1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (& (var a2) (bv 32 0xffff0000)) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 16 false (>> (var a2) (bv 8 0x10) false))) (cast 32 false (cast 16 false (>> (var a2) (bv 8 0x10) false)))))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0)))) (set mac_ea (cast 32 false (var a3))) (set mem_addr (var mac_ea)) (set mem_load (loadw 0 32 (var mem_addr))) (set d1 (cast 32 false (var mem_load)))) +d "mac.l d2, d3, acc0" a6020800 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "msac.l d2, d3, acc0" a6020900 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x100))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x100) (bv 32 0x0))))) +d "mac.l d2, d3, acc1" a6820800 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set macsr (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x200) (bv 32 0x0))))) +d "move.l d0, macsr" a900 0x0 (seq (set src (var d0)) (set vis (& (var src) (bv 32 0xfff))) (set macsr (cast 32 false (var vis)))) +d "move.l 0x7, macsr" a93c00000007 0x0 (seq (set src (bv 32 0x7)) (set vis (& (var src) (bv 32 0xfff))) (set macsr (cast 32 false (var vis)))) +d "move.l macsr, d0" a980 0x0 (seq (set src (var macsr)) (set vis (& (var src) (bv 32 0xfff))) (set d0 (cast 32 false (var vis)))) +d "move.l macsr, ccr" a9c0 0x0 (seq (set macsr_src (var macsr)) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (bv 8 0x0) (bv 8 0xf7)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x8)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x4)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x2)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (! (is_zero (& (var macsr_src) (bv 32 0x1)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false))))))) +d "move.l d0, accext01" ab00 0x0 (seq (set src (var d0)) (set accext01 (cast 32 false (var src)))) +d "move.l 0x7, accext01" ab3c00000007 0x0 (seq (set src (bv 32 0x7)) (set accext01 (cast 32 false (var src)))) +d "move.l accext01, d0" ab80 0x0 (seq (set src (var accext01)) (set d0 (cast 32 false (var src)))) +d "move.l d0, mask" ad00 0x0 (seq (set src (var d0)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set mask (cast 32 false (var masked)))) +d "move.l 0x7, mask" ad3c00000007 0x0 (seq (set src (bv 32 0x7)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set mask (cast 32 false (var masked)))) +d "move.l mask, d0" ad80 0x0 (seq (set src (var mask)) (set masked (| (& (var src) (bv 32 0xffff)) (bv 32 0xffff0000))) (set d0 (cast 32 false (var masked)))) +d "move.l d0, accext23" af00 0x0 (seq (set src (var d0)) (set accext23 (cast 32 false (var src)))) d "fbf.w 0x12" f2800010 d "fbf.l 0x12" f2c000000010 -d "fdbf d0, 0x14" f24800000010 -d "fsf.b (a0)" f2500000 -d "ftrapf" f27c0000 -d "ftrapf.w 0x1234" f27a00001234 -d "ftrapf.l 0x12345678" f27b000012345678 -d "ftst fp1, fp2" f200053a -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "sats.l d0" 4c80 -d "mac.w d1l, d0l, acc0" a0010000 -d "mac.w d1l, d0u, <<, acc0" a0010280 -d "mac.l d2, d3, acc0" a6020800 -d "mac.w a1l, a2u, (a3), d1, acc0" a293a089 -d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9 -d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289 -d "divs.l d0, d2" 4c402802 -d "mac.l d2, d3, acc1" a6820800 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "msac.w d1l, d0l, acc0" a0010100 -d "msac.l d2, d3, acc0" a6020900 -d "mac.w d2l, d0l, >>, acc0" a0020600 -d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389 -d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "fsub fp2, fp4" f2000a28 -d "fsadd fp1, fp2" f2000562 -d "fdadd fp1, fp2" f2000566 -d "fssub fp1, fp2" f2000568 -d "fdsub fp1, fp2" f200056c -d "fsmul fp1, fp2" f2000563 -d "fdmul fp1, fp2" f2000567 -d "fsdiv fp1, fp2" f2000560 -d "fddiv fp1, fp2" f2000564 -d "fsneg fp1, fp2" f200055a -d "fdneg fp1, fp2" f200055e -d "fsabs fp1, fp2" f2000558 -d "fdabs fp1, fp2" f200055c -d "fssqrt fp1, fp2" f2000541 -d "fdsqrt fp1, fp2" f2000545 -d "fint fp1, fp2" f2000501 -d "fsinh fp1, fp2" f2000502 -d "fintrz fp1, fp2" f2000503 -d "fsqrt fp1, fp2" f2000504 -d "flognp1 fp1, fp2" f2000506 -d "fetoxm1 fp1, fp2" f2000508 -d "fatanh fp1, fp2" f2000509 -d "fatan fp1, fp2" f200050a -d "fasin fp1, fp2" f200050c -d "fsin fp1, fp2" f200050e -d "ftan fp1, fp2" f200050f -d "fetox fp1, fp2" f2000510 -d "ftwotox fp1, fp2" f2000511 -d "ftentox fp1, fp2" f2000512 -d "flogn fp1, fp2" f2000514 -d "flog10 fp1, fp2" f2000515 -d "flog2 fp1, fp2" f2000516 -d "fcosh fp1, fp2" f2000519 -d "facos fp1, fp2" f200051c -d "fcos fp1, fp2" f200051d -d "fgetexp fp1, fp2" f200051e -d "fgetman fp1, fp2" f200051f -d "fdiv fp1, fp2" f2000520 -d "fmod fp1, fp2" f2000521 -d "fadd fp1, fp2" f2000522 -d "fmul fp1, fp2" f2000523 -d "fsgldiv fp1, fp2" f2000524 -d "frem fp1, fp2" f2000525 -d "fscale fp1, fp2" f2000526 -d "fsglmul fp1, fp2" f2000527 -d "fcmp fp1, fp2" f2000538 -d "fabs fp1, fp2" f2000518 -d "fneg fp1, fp2" f200051a -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bitrev d0" 00c0 -d "byterev d1" 02c1 -d "ff1 d2" 04c2 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "move.l macsr, ccr" a9c0 -d "halt" 4ac8 -d "strldsr.w 0x4d2" 40e746fc04d2 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "move usp, a0" 4e68 -d "move a0, usp" 4e60 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "fsave (a0)" f310 -d "frestore (a0)" f350 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "intouch (a0)" f428 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 diff --git a/test/db/asm/m68k_cfv5_32 b/test/db/asm/m68k_cfv5_32 index 05b9ef08fd..dd1828ee2a 100644 --- a/test/db/asm/m68k_cfv5_32 +++ b/test/db/asm/m68k_cfv5_32 @@ -1,137 +1,9 @@ -d "mov3q.l 0x2, (a4)" a554 -d "mvs.b d0, d0" 7100 -d "mvs.w d0, d0" 7140 -d "mvz.b d0, d0" 7180 -d "mvz.w d0, d0" 71c0 -d "mvs.b d0, d1" 7300 -d "mov3q.l 0xffffffff, d0" a140 -d "mvs.b (a0), d1" 7310 -d "mvz.w (a0), d1" 73d0 -d "move.l d0, acc0" a100 -d "move.l acc0, d0" a180 -d "move.l 0x12345678, acc0" a13c12345678 -d "move.l d0, macsr" a900 -d "move.l macsr, d0" a980 -d "move.l 0x7, macsr" a93c00000007 -d "move.l d0, mask" ad00 -d "move.l mask, d0" ad80 -d "move.l 0x7, mask" ad3c00000007 -d "movclr.l acc0, d0" a1c0 -d "move.l d0, accext01" ab00 -d "move.l accext01, d0" ab80 -d "move.l 0x7, accext01" ab3c00000007 -d "move.l d0, accext23" af00 -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "bra.l 0x12" 60ff00000010 -d "bsr.l 0x12" 61ff00000010 -d "bne.l 0x12" 66ff00000010 -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "sats.l d0" 4c80 -d "mac.w d1l, d0l, acc0" a0010000 -d "mac.w d1l, d0u, <<, acc0" a0010280 -d "mac.l d2, d3, acc0" a6020800 -d "mac.w a1l, a2u, (a3), d1, acc0" a293a089 -d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9 -d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289 -d "divs.l d0, d2" 4c402802 -d "mac.l d2, d3, acc1" a6820800 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "msac.w d1l, d0l, acc0" a0010100 -d "msac.l d2, d3, acc0" a6020900 -d "mac.w d2l, d0l, >>, acc0" a0020600 -d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389 -d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bitrev d0" 00c0 -d "byterev d1" 02c1 -d "ff1 d2" 04c2 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "move.l macsr, ccr" a9c0 -d "halt" 4ac8 -d "strldsr.w 0x4d2" 40e746fc04d2 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "move usp, a0" 4e68 -d "move a0, usp" 4e60 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "intouch (a0)" f428 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "move.l accext01, d0" ab80 0x0 (seq (set src (var accext01)) (set d0 (cast 32 false (var src)))) +d "maaac.w d1l, d0l, acc0, acc1" a0010005 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "masac.w d2l, d0l, acc0, acc1" a0020007 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d2) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d2))) (cast 16 false (var d2))) (cast 32 false (cast 16 false (var d2)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "msaac.l d2, d3, acc0, acc1" a6020905 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "mssac.l d2, d3, acc2, acc3" a602091f 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (var prod_wide)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x400) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x800) (bv 32 0x0))))) +d "maaac.w d1l, d0l, <<, acc0, acc1" a0010205 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d1) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d1))) (cast 16 false (var d1))) (cast 32 false (cast 16 false (var d1)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "masac.w d2l, d0l, >>, acc0, acc1" a0020407 0x0 (seq (set src0 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d2) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d2))) (cast 16 false (var d2))) (cast 32 false (cast 16 false (var d2)))))) (set src1 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (<< (var d0) (bv 8 0x10) false) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 false (cast 16 false (var d0)))))) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "msaac.l d2, d3, <<, acc0, acc1" a6020b05 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (<< (var prod_wide) (bv 8 0x1) false)) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc0)) (set acc_ext (cast 16 false (var accext01))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc0 (cast 32 false (var res))) (set accext01 (cast 32 false (| (& (var accext01) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc1)) (set acc_ext (cast 16 false (>> (var accext01) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (+ (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (+ (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc1 (cast 32 false (var res))) (set accext01 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext01) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x200))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x100) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x200) (bv 32 0x0))))) +d "mssac.l d2, d3, >>, acc2, acc3" a6020d1f 0x0 (seq (set src0 (var d2)) (set src1 (var d3)) (set prod_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (* (cast 80 (msb (var src0)) (var src0)) (cast 80 (msb (var src1)) (var src1))) (* (cast 80 false (var src0)) (cast 80 false (var src1))))) (set prod_scaled (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (>> (var prod_wide) (bv 8 0x1) (msb (var prod_wide))) (>> (var prod_wide) (bv 8 0x1) false))) (set prod (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 64 (msb (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (cast 40 false (+ (>> (var prod_wide) (bv 8 0x18) false) (ite (&& (! (is_zero (& (var macsr) (bv 32 0x10)))) (|| (! (ule (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000))) (&& (== (& (var prod_wide) (bv 80 0xffffff)) (bv 80 0x800000)) (! (is_zero (& (>> (var prod_wide) (bv 8 0x18) false) (bv 80 0x1))))))) (bv 80 0x1) (bv 80 0x0))))) (ite (is_zero (& (var macsr) (bv 32 0x40))) (cast 64 (msb (cast 40 false (var prod_scaled))) (cast 40 false (var prod_scaled))) (cast 64 false (cast 40 false (var prod_scaled)))))) (set prod_overflow (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (bv 32 0x0) (ite (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (cast 40 (msb (var prod_scaled)) (var prod_scaled))) (var prod_scaled))) (! (is_zero (>> (var prod_scaled) (bv 8 0x28) false)))) (bv 32 0x1) (bv 32 0x0)))) (set acc_word (var acc2)) (set acc_ext (cast 16 false (var accext23))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc2 (cast 32 false (var res))) (set accext23 (cast 32 false (| (& (var accext23) (bv 32 0xffff0000)) (cast 32 false (var ext16))))) (set ov_first (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_first (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set acc_word (var acc3)) (set acc_ext (cast 16 false (>> (var accext23) (bv 8 0x10) false))) (set acc_full (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 48 false (>> (var acc_ext) (bv 8 0x8) false)) (bv 8 0x28) false) (| (<< (cast 48 false (var acc_word)) (bv 8 0x8) false) (cast 48 false (& (var acc_ext) (bv 16 0xff))))) (| (<< (cast 48 false (var acc_ext)) (bv 8 0x20) false) (cast 48 false (var acc_word))))) (set acc (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (cast 64 (msb (var acc_full)) (var acc_full)) (cast 64 false (var acc_full)))) (set res_wide (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (- (cast 80 (msb (var acc)) (var acc)) (cast 80 (msb (var prod)) (var prod))) (- (cast 80 false (var acc)) (cast 80 false (var prod))))) (set res_full (cast 48 false (var res_wide))) (set res (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (cast 32 false (>> (var res_full) (bv 8 0x8) false)) (cast 32 false (var res_full)))) (set ext16 (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (| (<< (cast 16 false (>> (var res_full) (bv 8 0x28) false)) (bv 8 0x8) false) (cast 16 false (& (var res_full) (bv 48 0xff)))) (cast 16 false (>> (var res_full) (bv 8 0x20) false)))) (set acc3 (cast 32 false (var res))) (set accext23 (cast 32 false (| (<< (cast 32 false (var ext16)) (bv 8 0x10) false) (& (var accext23) (bv 32 0xffff))))) (set ov_second (ite (|| (! (is_zero (var prod_overflow))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 48 (msb (var res_wide)) (var res_wide))) (cast 48 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x30) false))))) (bv 32 0x1) (bv 32 0x0))) (set ev_second (ite (ite (! (is_zero (& (var macsr) (bv 32 0x20)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 40 (msb (var res_wide)) (var res_wide))) (cast 40 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x28) false)))) (ite (|| (! (is_zero (& (var macsr) (bv 32 0x20)))) (is_zero (& (var macsr) (bv 32 0x40)))) (! (== (cast 80 (msb (cast 32 (msb (var res_wide)) (var res_wide))) (cast 32 (msb (var res_wide)) (var res_wide))) (var res_wide))) (! (is_zero (>> (var res_wide) (bv 8 0x20) false))))) (bv 32 0x1) (bv 32 0x0))) (set macsr (| (| (| (| (| (| (& (var macsr) (bv 32 0xfffffff0)) (ite (msb (var res_full)) (bv 32 0x8) (bv 32 0x0))) (ite (is_zero (var res_full)) (bv 32 0x4) (bv 32 0x0))) (ite (|| (! (is_zero (var ov_second))) (! (is_zero (& (var macsr) (bv 32 0x800))))) (bv 32 0x2) (bv 32 0x0))) (ite (! (is_zero (var ev_second))) (bv 32 0x1) (bv 32 0x0))) (ite (! (is_zero (var ov_first))) (bv 32 0x400) (bv 32 0x0))) (ite (! (is_zero (var ov_second))) (bv 32 0x800) (bv 32 0x0))))) diff --git a/test/db/asm/m68k_coldfire_32 b/test/db/asm/m68k_coldfire_32 index 4720ba2461..3dc61decc8 100644 --- a/test/db/asm/m68k_coldfire_32 +++ b/test/db/asm/m68k_coldfire_32 @@ -1,211 +1 @@ -d "mov3q.l 0x2, (a4)" a554 -d "mvs.b d0, d0" 7100 -d "mvs.w d0, d0" 7140 -d "mvz.b d0, d0" 7180 -d "mvz.w d0, d0" 71c0 -d "mvs.b d0, d1" 7300 -d "fsmove fp1, fp2" f2000540 -d "fdmove fp1, fp2" f2000544 -d "mov3q.l 0xffffffff, d0" a140 -d "mvs.b (a0), d1" 7310 -d "mvz.w (a0), d1" 73d0 -d "move.l d0, acc0" a100 -d "move.l acc0, d0" a180 -d "move.l 0x12345678, acc0" a13c12345678 -d "move.l d0, macsr" a900 -d "move.l macsr, d0" a980 -d "move.l 0x7, macsr" a93c00000007 -d "move.l d0, mask" ad00 -d "move.l mask, d0" ad80 -d "move.l 0x7, mask" ad3c00000007 -d "movclr.l acc0, d0" a1c0 -d "move.l d0, accext01" ab00 -d "move.l accext01, d0" ab80 -d "move.l 0x7, accext01" ab3c00000007 -d "move.l d0, accext23" af00 -d "fmove.l d0, fp0" f2004000 -d "fmove.l fp0, d0" f2006000 -d "fmove.s 1.000000, fp1" f23c44803f800000 -d "fmove.d 3.141593, fp1" f23c5480400921fb54442d18 -d "fmove.w (a0), fp0" f2105000 -d "fmove.s fp0, (a0)" f2106400 -d "fmovecr 0xf, fp6" f2005f0f -d "fmove.l d0, fpcr" f2009000 -d "fmove.l fpcr, d0" f200b000 -d "fmove.l d0, fpsr" f2008800 -d "fmove.l fpiar, d0" f200a400 -d "fmovem (a0)+, fp6-fp7" f218d003 -d "fmovem fp0-fp1, -(a0)" f220e003 -d "move.l d0, d0" 2000 -d "movea.l d0, a0" 2040 -d "moveq 0x1, d0" 7001 -d "movem.l d0-d1, (a0)" 48d00003 -d "lea.l (a0), a0" 41d0 -d "link.w a0, 0x4" 4e500004 -d "pea.l (a0)" 4850 -d "unlk a0" 4e58 -d "tpf" 51fc -d "tpf.w 0x1234" 51fa1234 -d "tpf.l 0x12345678" 51fb12345678 -d "bra.l 0x12" 60ff00000010 -d "bsr.l 0x12" 61ff00000010 -d "bne.l 0x12" 66ff00000010 -d "fnop" f2800000 -d "fbf.w 0x12" f2800010 -d "fbf.l 0x12" f2c000000010 -d "fdbf d0, 0x14" f24800000010 -d "fsf.b (a0)" f2500000 -d "ftrapf" f27c0000 -d "ftrapf.w 0x1234" f27a00001234 -d "ftrapf.l 0x12345678" f27b000012345678 -d "ftst fp1, fp2" f200053a -d "st.b d0" 50c0 -d "jmp (a0)" 4ed0 -d "jsr (a0)" 4e90 -d "nop" 4e71 -d "rts" 4e75 -d "tas.b d0" 4ac0 -d "tst.l d0" 4a80 -d "sats.l d0" 4c80 -d "mac.w d1l, d0l, acc0" a0010000 -d "mac.w d1l, d0u, <<, acc0" a0010280 -d "mac.l d2, d3, acc0" a6020800 -d "mac.w a1l, a2u, (a3), d1, acc0" a293a089 -d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9 -d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289 -d "divs.l d0, d2" 4c402802 -d "mac.l d2, d3, acc1" a6820800 -d "divu.l d0, d1:d2" 4c402401 -d "divs.l d0, d1:d2" 4c402c01 -d "msac.w d1l, d0l, acc0" a0010100 -d "msac.l d2, d3, acc0" a6020900 -d "mac.w d2l, d0l, >>, acc0" a0020600 -d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389 -d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489 -d "add.l d0, d0" d080 -d "adda.l d0, a0" d1c0 -d "addi.l 0x1, d0" 068000000001 -d "addq.l 0x1, d0" 5280 -d "addx.l d0, d0" d180 -d "clr.l d0" 4280 -d "cmp.l d0, d0" b080 -d "cmpa.l d0, a0" b1c0 -d "cmpi.l 0x1, d0" 0c8000000001 -d "ext.l d0" 48c0 -d "extb.l d0" 49c0 -d "muls.w d0, d0" c1c0 -d "mulu.w d0, d0" c0c0 -d "neg.l d0" 4480 -d "negx.l d0" 4080 -d "remu.l d0, d1:d2" 4c402001 -d "rems.l d0, d1:d2" 4c402801 -d "sub.l d0, d0" 9080 -d "suba.l d0, a0" 91c0 -d "subi.l 0x1, d0" 048000000001 -d "subq.l 0x1, d0" 5380 -d "subx.l d0, d0" 9180 -d "fsub fp2, fp4" f2000a28 -d "fsadd fp1, fp2" f2000562 -d "fdadd fp1, fp2" f2000566 -d "fssub fp1, fp2" f2000568 -d "fdsub fp1, fp2" f200056c -d "fsmul fp1, fp2" f2000563 -d "fdmul fp1, fp2" f2000567 -d "fsdiv fp1, fp2" f2000560 -d "fddiv fp1, fp2" f2000564 -d "fsneg fp1, fp2" f200055a -d "fdneg fp1, fp2" f200055e -d "fsabs fp1, fp2" f2000558 -d "fdabs fp1, fp2" f200055c -d "fssqrt fp1, fp2" f2000541 -d "fdsqrt fp1, fp2" f2000545 -d "fint fp1, fp2" f2000501 -d "fsinh fp1, fp2" f2000502 -d "fintrz fp1, fp2" f2000503 -d "fsqrt fp1, fp2" f2000504 -d "flognp1 fp1, fp2" f2000506 -d "fetoxm1 fp1, fp2" f2000508 -d "fatanh fp1, fp2" f2000509 -d "fatan fp1, fp2" f200050a -d "fasin fp1, fp2" f200050c -d "fsin fp1, fp2" f200050e -d "ftan fp1, fp2" f200050f -d "fetox fp1, fp2" f2000510 -d "ftwotox fp1, fp2" f2000511 -d "ftentox fp1, fp2" f2000512 -d "flogn fp1, fp2" f2000514 -d "flog10 fp1, fp2" f2000515 -d "flog2 fp1, fp2" f2000516 -d "fcosh fp1, fp2" f2000519 -d "facos fp1, fp2" f200051c -d "fcos fp1, fp2" f200051d -d "fgetexp fp1, fp2" f200051e -d "fgetman fp1, fp2" f200051f -d "fdiv fp1, fp2" f2000520 -d "fmod fp1, fp2" f2000521 -d "fadd fp1, fp2" f2000522 -d "fmul fp1, fp2" f2000523 -d "fsgldiv fp1, fp2" f2000524 -d "frem fp1, fp2" f2000525 -d "fscale fp1, fp2" f2000526 -d "fsglmul fp1, fp2" f2000527 -d "fcmp fp1, fp2" f2000538 -d "fabs fp1, fp2" f2000518 -d "fneg fp1, fp2" f200051a -d "and.l d0, d0" c080 -d "andi.l 0x1, d0" 028000000001 -d "eor.l d0, d0" b180 -d "eori.l 0x1, d0" 0a8000000001 -d "not.l d0" 4680 -d "or.l d0, d0" 8080 -d "ori.l 0x1, d0" 008000000001 -d "asl.l 0x8, d0" e180 -d "asr.l 0x8, d0" e080 -d "lsl.l 0x8, d0" e188 -d "lsr.l 0x8, d0" e088 -d "swap d0" 4840 -d "bitrev d0" 00c0 -d "byterev d1" 02c1 -d "ff1 d2" 04c2 -d "bchg.b d0, d0" 0140 -d "bclr.b d0, d0" 0180 -d "bset.b d0, d0" 01c0 -d "btst.b d0, d0" 0100 -d "move.l macsr, ccr" a9c0 -d "halt" 4ac8 -d "strldsr.w 0x4d2" 40e746fc04d2 -d "wddata.b (a0)" fb10 -d "wdebug.l (a0)" fbd00003 -d "move.w ccr, d3" 42c3 -d "move usp, a0" 4e68 -d "move a0, usp" 4e60 -d "pulse" 4acc -d "movec d0, cacr" 4e7b0002 -d "movec cacr, d1" 4e7a1002 -d "wddata.w (a0)" fb50 -d "wddata.l (a0)" fb90 -d "fsave (a0)" f310 -d "frestore (a0)" f350 -d "move.w d0, ccr" 44c0 -d "move.w sr, d0" 40c0 -d "move.w d0, sr" 46c0 -d "illegal 0x4afc" 4afc -d "rte" 4e73 -d "stop 0x2700" 4e722700 -d "trap 0x0" 4e40 -d "intouch (a0)" f428 -d "cpushl bc, (a0)" f4e8 -d "cp0bcbusy 0x52" fcc00050 -d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 -d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 -d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 -d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 -d "cp0st.l d2, d0, 0x1, 0x123" fd802123 -d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 -d "cp0nop 0x8" fc000e00 -d "cp0nop 0x3" fc800400 -d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 -d "cp1bcbusy 0x52" fec00050 -d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 -d "cp1st.l d2, d0, 0x1, 0x123" ff802123 -d "cp1nop 0x8" fe000e00 +d "move.l accext01, d0" ab80 0x0 (seq (set src (var accext01)) (set d0 (cast 32 false (var src)))) diff --git a/test/db/asm/m68k_cpu32_32 b/test/db/asm/m68k_cpu32_32 index adde4a9010..7635fc524f 100644 --- a/test/db/asm/m68k_cpu32_32 +++ b/test/db/asm/m68k_cpu32_32 @@ -1,7 +1,73 @@ -d "bgnd" 4afa -d "tblu.w (a0), d0" f8100140 -d "tbls.l (a2), d3" f8123980 -d "tblun.b (a1), d2" f8112500 -d "tblsn.w (a4), d5" f8145d40 -d "tblu.w d1:d2, d3" f8013042 -d "tbls.b d4:d5, d6" f8046805 +d "bgnd" 4afa 0x0 (seq (set trap_op (bv 32 0x5)) (goto m68k_trap)) +d "lpstop 0x0" f80001c00000 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)) +d "fbf.w 0x3" f2800001 +d "fbeq.w 0x2" f2810000 +d "fbogt.w 0x2" f2820000 +d "fboge.w 0x2" f2830000 +d "fbolt.w 0x2" f2840000 +d "fbole.w 0x2" f2850000 +d "fbogl.w 0x2" f2860000 +d "fbor.w 0x2" f2870000 +d "fbun.w 0x2" f2880000 +d "fbueq.w 0x2" f2890000 +d "fbugt.w 0x2" f28a0000 +d "fbuge.w 0x2" f28b0000 +d "fbult.w 0x2" f28c0000 +d "fbule.w 0x2" f28d0000 +d "fbne.w 0x2" f28e0000 +d "fbt.w 0x2" f28f0000 +d "fbf.l 0x3" f2c000000001 +d "fbeq.l 0x3" f2c100000001 +d "fbogt.l 0x3" f2c200000001 +d "fboge.l 0x3" f2c300000001 +d "fbolt.l 0x3" f2c400000001 +d "fbole.l 0x3" f2c500000001 +d "fbogl.l 0x3" f2c600000001 +d "fbor.l 0x3" f2c700000001 +d "fbun.l 0x3" f2c800000001 +d "fbueq.l 0x3" f2c900000001 +d "fbugt.l 0x3" f2ca00000001 +d "fbuge.l 0x3" f2cb00000001 +d "fbult.l 0x3" f2cc00000001 +d "fbule.l 0x3" f2cd00000001 +d "fbne.l 0x3" f2ce00000001 +d "fbt.l 0x3" f2cf00000001 +d "tblu.b d0:d0, d0" f8000000 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (cast 8 false (var d0)))) (set entry1 (cast 64 false (cast 8 false (var d0)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l d0:d0, d0" f8000080 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (var d0))) (set entry1 (cast 64 false (var d0))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w d1:d2, d3" f8013042 0x0 (seq (set x (cast 16 false (var d3))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (cast 16 false (var d1)))) (set entry1 (cast 64 false (cast 16 false (var d2)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d3 (| (& (var d3) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tbls.b d4:d5, d6" f8046805 0x0 (seq (set x (cast 16 false (var d6))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 (msb (cast 8 false (var d4))) (cast 8 false (var d4)))) (set entry1 (cast 64 (msb (cast 8 false (var d5))) (cast 8 false (var d5)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d6 (| (& (var d6) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b (a0), d0" f8100100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w (a0), d0" f8100140 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l (a0), d0" f8100180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblun.b (a1), d2" f8112500 0x0 (seq (set x (cast 16 false (var d2))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a1))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set fixed (+ (<< (var entry0) (bv 8 0x8) false) (var prod))) (set res (cast 32 false (cast 16 false (var fixed)))) (set d2 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tbls.l (a2), d3" f8123980 0x0 (seq (set x (cast 16 false (var d3))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a2))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 (msb (loadw 0 32 (var entry_addr))) (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 (msb (loadw 0 32 (+ (var entry_addr) (bv 32 0x4)))) (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d3 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblsn.w (a4), d5" f8145d40 0x0 (seq (set x (cast 16 false (var d5))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a4))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 (msb (loadw 0 16 (var entry_addr))) (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 (msb (loadw 0 16 (+ (var entry_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set fixed (+ (<< (var entry0) (bv 8 0x8) false) (var prod))) (set res (cast 32 (msb (cast 24 false (var fixed))) (cast 24 false (var fixed)))) (set d5 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b (a0)+, d0" f8180100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w (a0)+, d0" f818017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l (a0)+, d0" f8180180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b -(a0), d0" f8200100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w -(a0), d0" f820017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l -(a0), d0" f8200180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b 0x17f(a0), d0" f8280100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x180(a0), d0" f828017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l 0x1ff(a0), d0" f828018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1ff))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b ([0x18001ff, a0], 0x8000fff), d0" f8300100017f018001ff08000fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w (d0.w), d0" f830017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (cast 32 false (bv 32 0x0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l ([0x8000fff], 0x10001fff), d0" f830018001ff08000fff10001fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x8000fff))) (bv 32 0x0)) (bv 32 0x10001fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b 0x17f.w, d0" f8380100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x17f))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x180.w, d0" f838017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x180))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l 0x1ff.w, d0" f838018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x1ff))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b 0x17f0180.l, d0" f8390100017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x17f0180))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x18001ff.l, d0" f839017f018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x18001ff))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l 0x1ff0800.l, d0" f839018001ff0800 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x1ff0800))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b 0x183(pc), d0" f83a0100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x183))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x184(pc), d0" f83a017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x184))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l 0x203(pc), d0" f83a018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x203))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b ([0x1800203, pc], 0x8000fff), d0" f83b0100017f018001ff08000fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x4(pc, d0.w), d0" f83b017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l ([0x8001003], 0x10001fff), d0" f83b018001ff08000fff10001fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x8001001))) (bv 32 0x0)) (bv 32 0x10001fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.b 0x7f, d0" f83c0100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x5)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.w 0x180, d0" f83c017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x4)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "tblu.l 0x1ff0800, d0" f83c018001ff0800 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x4)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))) +d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0xc)) (bv 32 0x18) (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c)))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x3)) (! (== (var format) (bv 16 0x3)))) (== (var format) (bv 16 0xc))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))) +d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr)))) diff --git a/test/db/cmd/cmd_aL b/test/db/cmd/cmd_aL index 2a96db1fd1..46371b8060 100644 --- a/test/db/cmd/cmd_aL +++ b/test/db/cmd/cmd_aL @@ -35,7 +35,7 @@ _d___ 32 lm32 BSD Lattice Micro 32 ISA disassembler (by Felix _dA__ 32 64 loongarch LGPL3 Loongson LoongArch disassembler adA__ 32 luac LGPL3 Lua bytecode (LUAC) disassembler _dA__ 8 32 m680x BSD Motorola 680X Capstone-based disassembler -_dA__ 32 m68k BSD Motorola 68K Capstone-based disassembler +_dA_I 32 m68k BSD Motorola 68K Capstone-based disassembler _dA__ 32 malbolge LGPL3 Malbolge Ternary VM bytecode disassembler (by condret) _dA__ 32 mcore LGPL3 Motorola MCORE disassembler _dA__ 16 mcs96 LGPL3 Intel MCS-96 disassembler (by condret) diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list index 0c0b4177b1..33e5fbf0f4 100644 --- a/test/db/cmd/cmd_list +++ b/test/db/cmd/cmd_list @@ -774,7 +774,7 @@ _d___ 32 lm32 BSD Lattice Micro 32 ISA disassembler (by Felix _dA__ 32 64 loongarch LGPL3 Loongson LoongArch disassembler adA__ 32 luac LGPL3 Lua bytecode (LUAC) disassembler _dA__ 8 32 m680x BSD Motorola 680X Capstone-based disassembler -_dA__ 32 m68k BSD Motorola 68K Capstone-based disassembler +_dA_I 32 m68k BSD Motorola 68K Capstone-based disassembler _dA__ 32 malbolge LGPL3 Malbolge Ternary VM bytecode disassembler (by condret) _dA__ 32 mcore LGPL3 Motorola MCORE disassembler _dA__ 16 mcs96 LGPL3 Intel MCS-96 disassembler (by condret) @@ -811,7 +811,7 @@ _dA__ 16 xap PD Cambridge Consultants XAP4 RISC (CSR) disas _dA__ 32 xcore BSD XCore Capstone-based disassembler (by pancake) _dAeI 32 xtensa LGPL3 Tensilica Xtensa Capstone-based disassembler (by billow) adA__ 8 z80 GPL3 Zilog Z80 disassembler (by condret) -["6502":{"bits":"8 16 ","license":"LGPL3","description":"6502/NES/C64/Tamagotchi/T-1000 CPU","features":"_dAeI"},"8051":{"bits":"8 ","license":"PD","description":"Intel 8051 disassembler","features":"adAeI"},"alpha":{"bits":"32 64","license":"LGPL3","description":"DEC Alpha Capstone-based disassembler","features":"_dA__"},"amd29k":{"bits":"32 ","license":"LGPL3","description":"AMD 29k RISC disassembler","features":"_dA__","author":"deroad"},"arc":{"bits":"16 32 ","license":"GPL3","description":"Argonaut RISC Core","features":"_dA__"},"arm":{"bits":"16 32 64","license":"BSD","description":"ARM Capstone-based disassembler","features":"adAeI"},"arm.as":{"bits":"16 32 64","license":"LGPL3","description":"as ARM Assembler (use RZ_ARM32_AS and RZ_ARM64_AS environment)","features":"a____","author":"pancake"},"avr":{"bits":"8 16 ","license":"LGPL3","description":"Atmel AVR disassembler","features":"adAeI"},"bf":{"bits":"16 32 64","license":"LGPL3","description":"Brainfuck","features":"adA_I","author":"pancake, nibble","version":"4.0.0"},"bpf":{"bits":"64","license":"LGPL3","description":"eBPF disassembler","features":"_dA__","author":"Jagath-P"},"c166":{"bits":"16 ","license":"LGPL3","description":"Siemens/Infineon C166 microcontroller disassembler","features":"_dA__"},"cbpf":{"bits":"32 ","license":"LGPL3","description":"cBPF disassembler","features":"_dA__","author":"Jagath-P"},"chip8":{"bits":"32 ","license":"LGPL3","description":"Chip8 disassembler","features":"_dA__"},"cil":{"bits":"16 32 64","license":"LGPL3","description":".NET CIL/MSIL (Common Intermediate Language) bytecode disassembler","features":"_dA__"},"cr16":{"bits":"16 ","license":"LGPL3","description":"CompactRISC CR16 disassembler","features":"_dA__"},"cris":{"bits":"32 ","license":"GPL3","description":"Axis Communications 32-bit embedded processor disassembler","features":"_dA__","author":"pancake"},"dalvik":{"bits":"32 64","license":"LGPL3","description":"Dalvik (Android VM) bytecode disassembler","features":"adA__"},"dcpu16":{"bits":"16 ","license":"PD","description":"Mojang's DCPU-16 disassembler","features":"ad___"},"ebc":{"bits":"32 64","license":"LGPL3","description":"EFI bytecode disassembler","features":"_dA__","author":"Fedor Sakharov"},"gb":{"bits":"16 ","license":"LGPL3","description":"GameBoy(TM) (z80-like)","features":"adAeI","author":"condret"},"h8300":{"bits":"16 ","license":"LGPL3","description":"Hitachi/Renesas H8/300 disassembly plugin","features":"_dAeI"},"h8500":{"bits":"16 ","license":"LGPL3","description":"Hitachi/Renesas H8/500 disassembler","features":"_dA__","author":"billow"},"hexagon":{"bits":"32 ","license":"LGPL3","description":"Qualcomm Hexagon (QDSP6) V6","features":"_dA_I","author":"Rot127"},"hppa":{"bits":"32 64","license":"LGPL3","description":"HP PA-RISC Capstone-based disassembler","features":"_dA__","author":"xvilka"},"i4004":{"bits":"4 ","license":"LGPL3","description":"Intel 4004 disassembler","features":"_dA__"},"i8080":{"bits":"8 ","license":"BSD","description":"Intel 8080 disassembler","features":"_dA__"},"java":{"bits":"32 ","license":"LGPL-3","description":"Java bytecode disassembler","features":"adA__","author":"deroad"},"lanai":{"bits":"32 ","license":"GPL3","description":"Google LANAI disassembler","features":"_d___"},"lh5801":{"bits":"8 ","license":"LGPL3","description":"SHARP LH5801 disassembler","features":"_d___"},"lm32":{"bits":"32 ","license":"BSD","description":"Lattice Micro 32 ISA disassembler","features":"_d___","author":"Felix Held"},"loongarch":{"bits":"32 64","license":"LGPL3","description":"Loongson LoongArch disassembler","features":"_dA__"},"luac":{"bits":"32 ","license":"LGPL3","description":"Lua bytecode (LUAC) disassembler","features":"adA__"},"m680x":{"bits":"8 32 ","license":"BSD","description":"Motorola 680X Capstone-based disassembler","features":"_dA__"},"m68k":{"bits":"32 ","license":"BSD","description":"Motorola 68K Capstone-based disassembler","features":"_dA__"},"malbolge":{"bits":"32 ","license":"LGPL3","description":"Malbolge Ternary VM bytecode disassembler","features":"_dA__","author":"condret"},"mcore":{"bits":"32 ","license":"LGPL3","description":"Motorola MCORE disassembler","features":"_dA__"},"mcs96":{"bits":"16 ","license":"LGPL3","description":"Intel MCS-96 disassembler","features":"_dA__","author":"condret"},"milstd1750":{"bits":"8 ","license":"MIT","description":"MIL-STD 1750 ISA disassembler","features":"_dA__"},"mips":{"bits":"16 32 64","license":"BSD","description":"MIPS Capstone-based disassembler","features":"adAeI"},"msp430":{"bits":"16 ","license":"LGPL3","description":"Texas Instruments MSP430 disassembler","features":"_dA_I"},"null":{"bits":"16 32 64","license":"MIT","description":"NULL (empty) disassembler","features":"adA__","author":"pancake","version":"1.0.0"},"or1k":{"bits":"32 ","license":"LGPL3","description":"OpenRISC 1000 disassembler","features":"_dA__"},"pic":{"bits":"16 32 ","license":"LGPL3","description":"Microchip PIC disassembler","features":"_dAeI"},"ppc":{"bits":"32 64","license":"BSD","description":"PowerPC Capstone-based disassembler","features":"_dAeI","author":"pancake"},"ppc.as":{"bits":"32 64","license":"LGPL3","description":"as PPC Assembler (use RZ_PPC_AS environment)","features":"a____","author":"eagleoflqj"},"propeller":{"bits":"32 ","license":"LGPL3","description":"Parallax Propeller disassembler","features":"_dA__"},"pyc":{"bits":"8 16 ","license":"LGPL3","description":"Python bytecode (PYC) disassembler","features":"_dA__"},"riscv":{"bits":"32 64","license":"BSD","description":"RISC-V Capstone-based disassembler","features":"_dA__"},"rl78":{"bits":"32 ","license":"LGPL3","description":"Renesas RL78 disassembler","features":"adA__","author":"Bastian Engel"},"rsp":{"bits":"32 ","license":"LGPL3","description":"Nintendo N64 Reality Signal Processor disassembler","features":"_dA__"},"rx":{"bits":"32 ","license":"LGPL3","description":"Renesas RX Family disassembler","features":"_dA__","author":"Heersin"},"sh":{"bits":"32 ","license":"LGPL3","description":"Hitachi/Renesas SuperH-4/SuperH-3 disassembler","features":"adAeI","author":"DMaroo"},"snes":{"bits":"8 16 ","license":"LGPL3","description":"SuperNES CPU disassembler","features":"_dA__"},"sparc":{"bits":"32 64","license":"BSD","description":"Sun SPARC Capstone-based disassembler","features":"_dA_I"},"spc700":{"bits":"16 ","license":"LGPL3","description":"Sony SPC700 (Nintendo SuperNES sound-chip) disassembler","features":"_dA__"},"sysz":{"bits":"32 64","license":"BSD","description":"IBM SystemZ (S/390) Capstone-based disassembler","features":"_dA__"},"tms320":{"bits":"16 32 ","license":"LGPL3","description":"Texas Instruments TMS320 DSP family (c54x,c55x,c55x+,c2x,c5x,c28x,c6x) disassembler","features":"_dA_I"},"tricore":{"bits":"32 ","license":"BSD","description":"Siemens TriCore Capstone-based disassembler","features":"_dA_I","author":"billow"},"v810":{"bits":"32 ","license":"LGPL3","description":"NEC V810 disassembler","features":"_dAeI","author":"pancake"},"v850":{"bits":"32 ","license":"LGPL3","description":"NEC/Renesas V850 disassembler","features":"_dAeI"},"vax":{"bits":"32 ","license":"LGPL3","description":"DEC VAX-11 disassembler","features":"_dA__","author":"xvilka"},"wasm":{"bits":"32 ","license":"MIT","description":"WebAssembly disassembler","features":"adA__","author":"cgvwzq","version":"0.1.0"},"x86":{"bits":"16 32 64","license":"MIT","description":"X86/X86_64 Zydis-based disassembler","features":"_dAeI"},"x86.as":{"bits":"16 32 64","license":"LGPL3","description":"Intel X86 GNU Assembler (Use RZ_X86_AS env)","features":"a____"},"x86.nasm":{"bits":"16 32 64","license":"LGPL3","description":"X86 nasm assembler","features":"a____"},"x86.nz":{"bits":"16 32 64","license":"LGPL3","description":"x86 handmade assembler","features":"a____"},"xap":{"bits":"16 ","license":"PD","description":"Cambridge Consultants XAP4 RISC (CSR) disassembler","features":"_dA__"},"xcore":{"bits":"32 ","license":"BSD","description":"XCore Capstone-based disassembler","features":"_dA__","author":"pancake"},"xtensa":{"bits":"32 ","license":"LGPL3","description":"Tensilica Xtensa Capstone-based disassembler","features":"_dAeI","author":"billow"},"z80":{"bits":"8 ","license":"GPL3","description":"Zilog Z80 disassembler","features":"adA__","author":"condret"}] +["6502":{"bits":"8 16 ","license":"LGPL3","description":"6502/NES/C64/Tamagotchi/T-1000 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assembler","features":"a____"},"xap":{"bits":"16 ","license":"PD","description":"Cambridge Consultants XAP4 RISC (CSR) disassembler","features":"_dA__"},"xcore":{"bits":"32 ","license":"BSD","description":"XCore Capstone-based disassembler","features":"_dA__","author":"pancake"},"xtensa":{"bits":"32 ","license":"LGPL3","description":"Tensilica Xtensa Capstone-based disassembler","features":"_dAeI","author":"billow"},"z80":{"bits":"8 ","license":"GPL3","description":"Zilog Z80 disassembler","features":"adA__","author":"condret"}] name bits features license version author description ---------------------------------------------------------------------------------------------------------------------------------------------- _dAeI 8 16 6502 LGPL3 6502/NES/C64/Tamagotchi/T-1000 CPU @@ -847,7 +847,7 @@ _d___ 32 lm32 BSD Felix Held Lattice Micro 32 ISA d _dA__ 32 64 loongarch LGPL3 Loongson LoongArch disassembler adA__ 32 luac LGPL3 Lua bytecode (LUAC) disassembler _dA__ 8 32 m680x BSD Motorola 680X Capstone-based disassembler -_dA__ 32 m68k BSD Motorola 68K Capstone-based disassembler +_dA_I 32 m68k BSD Motorola 68K Capstone-based disassembler _dA__ 32 malbolge LGPL3 condret Malbolge Ternary VM bytecode disassembler _dA__ 32 mcore LGPL3 Motorola MCORE disassembler _dA__ 16 mcs96 LGPL3 condret Intel MCS-96 disassembler @@ -993,6 +993,7 @@ adA_I 16 32 64 bf LGPL3 Brainfuck (by pancake, nibble) v4.0.0 adAeI 16 gb LGPL3 GameBoy(TM) (z80-like) (by condret) _dAeI 16 h8300 LGPL3 Hitachi/Renesas H8/300 disassembly plugin _dA_I 32 hexagon LGPL3 Qualcomm Hexagon (QDSP6) V6 (by Rot127) +_dA_I 32 m68k BSD Motorola 68K Capstone-based disassembler adAeI 16 32 64 mips BSD MIPS Capstone-based disassembler _dA_I 16 msp430 LGPL3 Texas Instruments MSP430 disassembler _dAeI 16 32 pic LGPL3 Microchip PIC disassembler @@ -1128,7 +1129,7 @@ a____ 16 32 64 x86.as LGPL3 Intel X86 GNU Assembler (Use RZ_X86_AS env) a____ 16 32 64 x86.nasm LGPL3 X86 nasm assembler a____ 16 32 64 x86.nz LGPL3 x86 handmade assembler adA__ 8 z80 GPL3 Zilog Z80 disassembler (by condret) -["6502":{"bits":"8 16 ","license":"LGPL3","description":"6502/NES/C64/Tamagotchi/T-1000 CPU","features":"_dAeI"},"8051":{"bits":"8 ","license":"PD","description":"Intel 8051 disassembler","features":"adAeI"},"arm":{"bits":"16 32 64","license":"BSD","description":"ARM Capstone-based disassembler","features":"adAeI"},"avr":{"bits":"8 16 ","license":"LGPL3","description":"Atmel AVR disassembler","features":"adAeI"},"bf":{"bits":"16 32 64","license":"LGPL3","description":"Brainfuck","features":"adA_I","author":"pancake, nibble","version":"4.0.0"},"gb":{"bits":"16 ","license":"LGPL3","description":"GameBoy(TM) (z80-like)","features":"adAeI","author":"condret"},"h8300":{"bits":"16 ","license":"LGPL3","description":"Hitachi/Renesas H8/300 disassembly plugin","features":"_dAeI"},"hexagon":{"bits":"32 ","license":"LGPL3","description":"Qualcomm Hexagon (QDSP6) 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","license":"LGPL3","description":"Tensilica Xtensa Capstone-based disassembler","features":"_dAeI","author":"billow"}] name bits features license version author description ----------------------------------------------------------------------------------------------- _dAeI 8 16 6502 LGPL3 6502/NES/C64/Tamagotchi/T-1000 CPU @@ -1166,7 +1167,7 @@ NAME=Print the asm/analysis plugins in JSON FILE== CMDS=Laj EXPECT=< /dev/null +EOF +EXPECT= +EXPECT_ERR= +RUN + +NAME=m68k aez 68060 M changes preserve the supervisor stack +FILE=malloc://256 +ARGS=-a m68k -b 32 -E big +CMDS=< +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include "minunit.h" + +/* Expected states follow M68000PRM, sections 4 and 5, and CFPRM, sections 3 + * and 4. Test real encodings through the plugin, including its VAL and OPEX + * interfaces; IL snapshots alone do not check these values or execution. */ + +static RzCore *m68k_core_new(const char *cpu) { + rz_return_val_if_fail(cpu, NULL); + RzCore *core = rz_core_new(); + if (!core) { + return NULL; + } + if (!rz_core_arch_configure(core, "m68k", 32, cpu, NULL, NULL) || + !rz_io_open_at(core->io, "malloc://0x1000", RZ_PERM_RWX, 0, 0, NULL)) { + rz_core_free(core); + return NULL; + } + rz_config_set_b(core->config, "cfg.bigendian", true); + return core; +} + +static bool m68k_decode(RzCore *core, RzAnalysisOp *op, const char *hex) { + rz_return_val_if_fail(core && op && hex, false); + ut8 bytes[32]; + int size = rz_hex_str2bin(hex, bytes); + rz_analysis_op_init(op); + return size > 0 && rz_analysis_op(core->analysis, op, 0x100, bytes, size, RZ_ANALYSIS_OP_MASK_VAL | RZ_ANALYSIS_OP_MASK_OPEX) == size; +} + +static bool m68k_value_reg(const RzAnalysisValue *value, const char *name, RzAnalysisValueAccess access) { + rz_return_val_if_fail(name, false); + mu_assert_notnull(value, "register value exists"); + mu_assert_eq(value->type, RZ_ANALYSIS_VAL_REG, "register value type"); + mu_assert_notnull(value->reg, "register exists"); + mu_assert_streq(value->reg->name, name, "register name"); + mu_assert_eq(value->access, access, "register access"); + return true; +} + +#if defined(RZ_CAPSTONE_HAS_M68K_FP_FORMATS) || defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE) +static bool m68k_value_mem(const RzAnalysisValue *value, const char *base, int size, RzAnalysisValueAccess access) { + rz_return_val_if_fail(base, false); + mu_assert_notnull(value, "memory value exists"); + mu_assert_eq(value->type, RZ_ANALYSIS_VAL_MEM, "memory value type"); + mu_assert_notnull(value->reg, "base register exists"); + mu_assert_streq(value->reg->name, base, "base register"); + mu_assert_eq(value->memref, size, "memory access size"); + mu_assert_eq(value->access, access, "memory access direction"); + return true; +} + +#endif + +static bool m68k_opex_is(const RzAnalysisOp *op, const char *expected) { + rz_return_val_if_fail(op && expected, false); + mu_assert_notnull(op->opex, "operand metadata exists"); + char *json = rz_structured_data_to_json(op->opex); + mu_assert_notnull(json, "operand metadata JSON"); + bool equal = rz_json_string_eq(json, expected); + if (!equal) { + fprintf(stderr, "OPEX: %s\nExpected: %s\n", json, expected); + } + free(json); + return equal; +} + +static bool test_m68k_hidden_fpu_destination(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + const char *encodings[] = { + "f2000025", "f2001fa5", /* frem fp0 / fp7 */ + "f2000026", "f2001fa6", /* fscale fp0 / fp7 */ + "f2000027", "f2001fa7", /* fsglmul fp0 / fp7 */ + }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(encodings); i++) { + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, encodings[i]), "decode collapsed FPU instruction"); + const char *reg = i % 2 ? "fp7" : "fp0"; + mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "FPU family"); + mu_assert_true(m68k_value_reg(op.src[0], reg, RZ_ANALYSIS_ACC_R), "collapsed source"); + mu_assert_null(op.src[1], "one source"); + mu_assert_true(m68k_value_reg(op.dst, reg, RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "hidden destination is read/write"); + char *expected = rz_str_newf("{\"opex\":{\"operands\":[{\"type\":\"reg\",\"value\":\"%s\"},{\"type\":\"reg\",\"value\":\"%s\"}]}}", reg, reg); + mu_assert_notnull(expected, "expected operand metadata"); + bool matches = m68k_opex_is(&op, expected); + free(expected); + mu_assert_true(matches, "materialized destination in OPEX"); + rz_analysis_op_fini(&op); + } + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, "f2000522"), "fadd fp1, fp2"); + mu_assert_true(m68k_value_reg(op.src[0], "fp1", RZ_ANALYSIS_ACC_R), "explicit source"); + mu_assert_null(op.src[1], "no invented source"); + mu_assert_true(m68k_value_reg(op.dst, "fp2", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "explicit destination"); + rz_analysis_op_fini(&op); + + mu_assert_true(m68k_decode(core, &op, "f2000538"), "fcmp fp1, fp2"); + mu_assert_true(m68k_value_reg(op.src[0], "fp1", RZ_ANALYSIS_ACC_R), "comparison first source"); + mu_assert_true(m68k_value_reg(op.src[1], "fp2", RZ_ANALYSIS_ACC_R), "comparison second source"); + mu_assert_null(op.src[2], "two comparison sources"); + mu_assert_null(op.dst, "comparison does not write a data register"); + rz_analysis_op_fini(&op); + + const char *unary[] = { "f2000018", "f200003a" }; /* fabs fp0, ftst fp0 */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(unary); i++) { + mu_assert_true(m68k_decode(core, &op, unary[i]), "complete unary FPU instruction"); + mu_assert_true(m68k_value_reg(op.src[0], "fp0", RZ_ANALYSIS_ACC_R), "unary source"); + mu_assert_null(op.src[1], "no synthetic unary source"); + if (i == 0) { + mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "unary destination"); + } else { + mu_assert_null(op.dst, "ftst has no destination"); + } + mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "complete unary operand is not duplicated"); + rz_analysis_op_fini(&op); + } + rz_core_free(core); + mu_end; +} + +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS +static bool test_m68k_fp_formats(void) { + RzCore *core = m68k_core_new("68040"); + mu_assert_notnull(core, "M68K core"); + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, "f23c48003fff00008000000000000000"), "extended immediate"); + mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "extended FPU family"); + mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "extended destination"); + mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"fp_extended\",\"sign_exp\":16383,\"reserved\":0,\"significand\":9223372036854775808},{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "extended bits are retained"); + rz_analysis_op_fini(&op); + mu_assert_true(m68k_decode(core, &op, "f23c4c00002500012345678901234567"), "packed immediate"); + mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "packed FPU family"); + mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "packed destination"); + mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"fp_packed\",\"header\":2424833,\"fraction\":2541551402847782247},{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "packed bits are retained"); + rz_analysis_op_fini(&op); + + const char *loads[] = { "f2104800", "f2104c00" }; /* fmove.x/p (a0), fp0 */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(loads); i++) { + mu_assert_true(m68k_decode(core, &op, loads[i]), "extended/packed load"); + mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_LOAD, "FP load type"); + mu_assert_eq(op.direction, RZ_ANALYSIS_OP_DIR_READ, "FP load direction"); + mu_assert_eq(op.refptr, 12, "FP memory representation occupies 12 bytes"); + mu_assert_true(m68k_value_mem(op.src[0], "a0", 12, RZ_ANALYSIS_ACC_R), "FP load source"); + mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "FP load destination"); + rz_analysis_op_fini(&op); + } + const char *stores[] = { "f2116c7b", "f2127d30" }; /* static -5 / dynamic d3 k-factor */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(stores); i++) { + mu_assert_true(m68k_decode(core, &op, stores[i]), "packed store"); + mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_STORE, "k-factor is not the destination"); + mu_assert_eq(op.direction, RZ_ANALYSIS_OP_DIR_WRITE, "packed store direction"); + mu_assert_eq(op.refptr, 12, "packed store width"); + mu_assert_true(m68k_value_reg(op.src[0], i ? "fp2" : "fp0", RZ_ANALYSIS_ACC_R), "packed source"); + if (i) { + mu_assert_true(m68k_value_reg(op.src[1], "d3", RZ_ANALYSIS_ACC_R), "dynamic k-factor"); + } else { + mu_assert_notnull(op.src[1], "static k-factor"); + mu_assert_eq(op.src[1]->type, RZ_ANALYSIS_VAL_IMM, "static k-factor type"); + mu_assert_eq(op.src[1]->imm, -5, "signed static k-factor"); + mu_assert_eq(op.src[1]->access, RZ_ANALYSIS_ACC_R, "static k-factor access"); + } + mu_assert_null(op.src[2], "only FP value and k-factor are sources"); + mu_assert_true(m68k_value_mem(op.dst, i ? "a2" : "a1", 12, RZ_ANALYSIS_ACC_W), "packed memory destination"); + rz_analysis_op_fini(&op); + } + rz_core_free(core); + mu_end; +} +#endif + +static void m68k_reset(RzCore *core, ut32 d0, ut32 d1, ut16 sr) { + rz_return_if_fail(core); + RzReg *reg = rz_analysis_get_reg(core->analysis); + rz_reg_setv(reg, "pc", 0x100); + rz_reg_setv(reg, "d0", d0); + rz_reg_setv(reg, "d1", d1); + rz_reg_setv(reg, "a0", 0x400); + rz_reg_setv(reg, "a1", 0x500); + rz_reg_setv(reg, "a7", 0x800); + rz_reg_setv(reg, "sr", sr); +} + +static bool m68k_step(RzCore *core, const char *hex) { + rz_return_val_if_fail(core && hex, false); + ut8 bytes[32]; + int size = rz_hex_str2bin(hex, bytes); + ut64 pc = rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"); + if (size <= 0 || !rz_io_write_at(core->io, pc, bytes, size)) { + return false; + } + RzAnalysisILVM *vm = rz_analysis_il_vm_new(core->analysis, rz_analysis_get_reg(core->analysis)); + if (!vm) { + return false; + } + RzAnalysisILStepResult result = rz_analysis_il_vm_step(core->analysis, vm, rz_analysis_get_reg(core->analysis)); + rz_analysis_il_vm_free(vm); + if (result != RZ_ANALYSIS_IL_STEP_RESULT_SUCCESS) { + fprintf(stderr, "M68K step %s at 0x%" PFMT64x ": result %d\n", hex, pc, result); + return false; + } + return true; +} + +/* Bit n gives the condition's value for NZVC == n (M68000PRM table 3-19). + * This truth table is independent of the lifter's Boolean expressions. */ +static const ut16 condition_truth[] = { + 0xffff, 0x0000, 0x0505, 0xfafa, 0x5555, 0xaaaa, 0x0f0f, 0xf0f0, + 0x3333, 0xcccc, 0x00ff, 0xff00, 0xcc33, 0x33cc, 0x0c03, 0xf3fc +}; + +static bool test_m68k_bcc_conditions(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + for (ut8 condition = 2; condition < 16; condition++) { + char hex[5]; + snprintf(hex, sizeof(hex), "%02x10", 0x60 | condition); + for (ut8 flags = 0; flags < 16; flags++) { + m68k_reset(core, 0x12345678, 0, 0x2010 | flags); + mu_assert_true(m68k_step(core, hex), "Bcc executes"); + bool taken = (condition_truth[condition] >> flags) & 1; + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), taken ? 0x112 : 0x102, "Bcc target or fallthrough"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "Bcc preserves SR"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), 0x12345678, "Bcc preserves data register"); + } + } + rz_core_free(core); + mu_end; +} + +static bool test_m68k_scc_conditions(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + for (ut8 condition = 0; condition < 16; condition++) { + for (ut8 flags = 0; flags < 16; flags++) { + ut8 expected = (condition_truth[condition] >> flags) & 1 ? 0xff : 0; + for (int memory = 0; memory < 2; memory++) { + char hex[5]; + snprintf(hex, sizeof(hex), "%02x%02x", 0x50 | condition, memory ? 0xd0 : 0xc0); + m68k_reset(core, 0x12345678, 0, 0x2010 | flags); + ut8 bytes[] = { 0xaa, 0x55 }; + mu_assert_true(rz_io_write_at(core->io, 0x400, bytes, sizeof(bytes)), "initialize Scc memory"); + mu_assert_true(m68k_step(core, hex), "Scc executes"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0x102, "Scc advances PC"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "Scc preserves SR"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), memory ? 0x12345678 : 0x12345600 | expected, "Scc only changes destination byte"); + mu_assert_eq(rz_io_nread_at(core->io, 0x400, bytes, sizeof(bytes)), sizeof(bytes), "read Scc memory"); + mu_assert_eq(bytes[0], memory ? expected : 0xaa, "Scc memory byte"); + mu_assert_eq(bytes[1], 0x55, "Scc preserves adjacent memory"); + } + } + } + rz_core_free(core); + mu_end; +} + +static bool test_m68k_dbcc_conditions(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + for (ut8 condition = 0; condition < 16; condition++) { + char hex[9]; + snprintf(hex, sizeof(hex), "%02xc8fffc", 0x50 | condition); + for (ut8 flags = 0; flags < 16; flags++) { + for (ut32 counter = 0; counter <= 2; counter += 2) { + m68k_reset(core, 0x12340000 | counter, 0, 0x2010 | flags); + mu_assert_true(m68k_step(core, hex), "DBcc executes"); + bool satisfied = (condition_truth[condition] >> flags) & 1; + ut32 expected = satisfied ? counter : (ut16)(counter - 1); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), 0x12340000 | expected, "DBcc decrements only the low word when false"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), !satisfied && counter ? 0xfe : 0x104, "DBcc branch, expiry, or condition-true fallthrough"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "DBcc preserves SR"); + } + } + } + rz_core_free(core); + mu_end; +} + +static bool test_m68k_branch_widths_and_calls(void) { + const struct { + const char *cpu; + const char *hex; + ut32 target; + bool call; + } cases[] = { + { "68000", "6010", 0x112, false }, + { "68000", "60f0", 0xf2, false }, + { "68000", "60000020", 0x122, false }, + { "68000", "6000ffe0", 0xe2, false }, + { "68020", "60ff00000040", 0x142, false }, + { "68020", "60ffffffffc0", 0xc2, false }, + { "68000", "6110", 0x112, true }, + { "68000", "61f0", 0xf2, true }, + { "68000", "61000020", 0x122, true }, + { "68000", "6100ffe0", 0xe2, true }, + { "68020", "61ff00000040", 0x142, true }, + { "68020", "61ffffffffc0", 0xc2, true }, + { "68000", "4ed0", 0x400, false }, /* jmp (a0) */ + { "68000", "4ef900000420", 0x420, false }, + { "68000", "4e90", 0x400, true }, /* jsr (a0) */ + { "68000", "4eb900000420", 0x420, true }, + { "68000", "4ebafffc", 0xfe, true }, /* PC-relative jsr */ + { "68000", "4eaf0004", 0x804, true }, /* target must use A7 before pushing */ +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + { "cfv4e", "6010", 0x112, false }, + { "cfv4e", "61ff00000040", 0x142, true }, + { "cfv1", "4e90", 0x400, true }, +#endif + }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(cases); i++) { + RzCore *core = m68k_core_new(cases[i].cpu); + mu_assert_notnull(core, "M68K core"); + m68k_reset(core, 0, 0, 0x201f); + mu_assert_true(m68k_step(core, cases[i].hex), "branch/call executes"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), cases[i].target, "branch/call target"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x201f, "branch/call preserves SR"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), cases[i].call ? 0x7fc : 0x800, "call pushes one longword"); + if (cases[i].call) { + ut8 bytes[4]; + ut32 next = 0x100 + strlen(cases[i].hex) / 2; + mu_assert_eq(rz_io_nread_at(core->io, 0x7fc, bytes, sizeof(bytes)), sizeof(bytes), "read return address"); + mu_assert_eq(rz_read_be32(bytes), next, "big-endian return address follows the full instruction"); + mu_assert_true(m68k_step(core, "4e75"), "RTS executes at call target"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), next, "RTS returns to caller"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x800, "RTS restores stack pointer"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x201f, "RTS preserves SR"); + } + rz_core_free(core); + } + mu_end; +} + +static bool test_m68k_integer_results_and_flags(void) { + const struct { + const char *instruction; + const char *hex; + ut32 d0, d1; + ut16 sr; + ut32 result; + ut16 flags; + ut16 mask; /* Zero checks all SR bits; omit architecturally undefined flags. */ + } cases[] = { + { "move.b d1,d0", "1001", 0x12345678, 0x80, 0x201f, 0x12345680, 0x2018, 0 }, + { "move.w d1,d0", "3001", 0x12345678, 0, 0x201f, 0x12340000, 0x2014, 0 }, + { "move.l d1,d0", "2001", 0, 0x87654321, 0x201f, 0x87654321, 0x2018, 0 }, + { "moveq -1,d0", "70ff", 0, 0, 0x201f, 0xffffffff, 0x2018, 0 }, + { "add.b d1,d0 carry", "d001", 0x123400ff, 1, 0x2000, 0x12340000, 0x2015, 0 }, + { "add.w d1,d0 overflow", "d041", 0x12347fff, 1, 0x2010, 0x12348000, 0x200a, 0 }, + { "add.l d1,d0 carry", "d081", 0xffffffff, 1, 0x2000, 0, 0x2015, 0 }, + { "addi.w 1,d0", "06400001", 0x1234ffff, 0, 0x2000, 0x12340000, 0x2015, 0 }, + { "addq.l 1,d0", "5280", 0x7fffffff, 0, 0x2010, 0x80000000, 0x200a, 0 }, + { "sub.b d1,d0 borrow", "9001", 0x12340000, 1, 0x2000, 0x123400ff, 0x2019, 0 }, + { "sub.w d1,d0 overflow", "9041", 0x12348000, 1, 0x2010, 0x12347fff, 0x2002, 0 }, + { "sub.l d1,d0 zero", "9081", 1, 1, 0x201f, 0, 0x2004, 0 }, + { "subi.w 1,d0", "04400001", 0x12340000, 0, 0x2000, 0x1234ffff, 0x2019, 0 }, + { "subq.l 1,d0", "5380", 0, 0, 0x2000, 0xffffffff, 0x2019, 0 }, + { "cmp.w d1,d0 borrow", "b041", 1, 2, 0x2010, 1, 0x2019, 0 }, + { "cmp.w d1,d0 equal", "b041", 2, 2, 0x2010, 2, 0x2014, 0 }, + { "tst.b d0", "4a00", 0x12340000, 0, 0x201f, 0x12340000, 0x2014, 0 }, + { "and.l d1,d0", "c081", 0xf000000f, 0x0ffffff0, 0x201f, 0, 0x2014, 0 }, + { "or.l d1,d0", "8081", 0x80000000, 1, 0x201f, 0x80000001, 0x2018, 0 }, + { "eor.l d1,d0", "b380", 0x80000001, 0x80000000, 0x201f, 1, 0x2010, 0 }, + { "clr.b d0", "4200", 0x123456ff, 0, 0x201f, 0x12345600, 0x2014, 0 }, + { "neg.b d0 overflow", "4400", 0x12345680, 0, 0x2000, 0x12345680, 0x201b, 0 }, + { "neg.l d0 zero", "4480", 0, 0, 0x201f, 0, 0x2004, 0 }, + { "not.b d0", "4600", 0x123456ff, 0, 0x201f, 0x12345600, 0x2014, 0 }, + { "ext.w d0", "4880", 0x12340080, 0, 0x201f, 0x1234ff80, 0x2018, 0 }, + { "swap d0", "4840", 0x12345678, 0, 0x201f, 0x56781234, 0x2010, 0 }, + { "asl.w 1,d0 overflow", "e340", 0x12344000, 0, 0x2010, 0x12348000, 0x200a, 0 }, + { "lsl.w 1,d0 carry", "e348", 0x12348000, 0, 0x2000, 0x12340000, 0x2015, 0 }, + { "asr.w 1,d0", "e240", 0x12348001, 0, 0x2000, 0x1234c000, 0x2019, 0 }, + { "lsr.w 1,d0", "e248", 0x12348001, 0, 0x2000, 0x12344000, 0x2011, 0 }, + { "rol.w 1,d0", "e358", 0x12348000, 0, 0x2010, 0x12340001, 0x2011, 0 }, + { "ror.w 1,d0", "e258", 0x12340001, 0, 0x2010, 0x12348000, 0x2019, 0 }, + { "roxl.w 1,d0", "e350", 0x12340000, 0, 0x2010, 0x12340001, 0x2000, 0 }, + { "roxr.w 1,d0", "e250", 0x12340001, 0, 0x2000, 0x12340000, 0x2015, 0 }, + { "muls.w d1,d0", "c1c1", 0x1234fffe, 3, 0x201f, 0xfffffffa, 0x2018, 0 }, + { "mulu.w d1,d0", "c0c1", 0xffff, 2, 0x201f, 0x1fffe, 0x2010, 0 }, + { "divs.w d1,d0", "81c1", 0xfffffff9, 2, 0x201f, 0xfffffffd, 0x2018, 0 }, + { "divu.w d1,d0", "80c1", 7, 2, 0x201f, 0x00010003, 0x2010, 0 }, + { "divu.w quotient overflow", "80c1", 0x10000, 1, 0x2010, 0x10000, 0x2012, 0xfff3 }, + }; + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + for (size_t i = 0; i < RZ_ARRAY_SIZE(cases); i++) { + m68k_reset(core, cases[i].d0, cases[i].d1, cases[i].sr); + mu_assert_true(m68k_step(core, cases[i].hex), cases[i].instruction); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), cases[i].result, cases[i].instruction); + ut16 mask = cases[i].mask ? cases[i].mask : UT16_MAX; + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr") & mask, cases[i].flags & mask, cases[i].instruction); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d1"), cases[i].d1, "source register is preserved"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0x100 + strlen(cases[i].hex) / 2, "integer instruction advances PC"); + } + rz_core_free(core); + mu_end; +} + +static bool test_m68k_data_transfers(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + RzReg *reg = rz_analysis_get_reg(core->analysis); + m68k_reset(core, 0x8000, 0, 0x201f); + mu_assert_true(m68k_step(core, "3040"), "movea.w d0,a0"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0xffff8000, "MOVEA sign extends a word"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "MOVEA preserves SR"); + m68k_reset(core, 0, 0, 0x201f); + mu_assert_true(m68k_step(core, "41e8fffc"), "lea -4(a0),a0"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0x3fc, "LEA computes address without loading memory"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "LEA preserves SR"); + m68k_reset(core, 0x12345678, 0, 0x201f); + mu_assert_true(m68k_step(core, "20c0"), "move.l d0,(a0)+"); + ut8 bytes[4]; + mu_assert_eq(rz_io_nread_at(core->io, 0x400, bytes, sizeof(bytes)), sizeof(bytes), "read stored longword"); + mu_assert_eq(rz_read_be32(bytes), 0x12345678, "MOVE stores big endian"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0x404, "MOVE postincrement"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x2010, "MOVE store flags"); + mu_assert_true(m68k_step(core, "2220"), "move.l -(a0),d1"); + mu_assert_eq(rz_reg_getv(reg, "d1"), 0x12345678, "MOVE loads big endian"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0x400, "MOVE predecrement"); + m68k_reset(core, 0, 0, 0x201f); + mu_assert_true(m68k_step(core, "4850"), "pea (a0)"); + mu_assert_eq(rz_reg_getv(reg, "a7"), 0x7fc, "PEA stack delta"); + mu_assert_eq(rz_io_nread_at(core->io, 0x7fc, bytes, sizeof(bytes)), sizeof(bytes), "read pushed effective address"); + mu_assert_eq(rz_read_be32(bytes), 0x400, "PEA pushes address"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "PEA preserves SR"); + m68k_reset(core, 0, 0, 0x201f); + mu_assert_true(m68k_step(core, "4e50fff8"), "link a0,-8"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0x7fc, "LINK frame pointer"); + mu_assert_eq(rz_reg_getv(reg, "a7"), 0x7f4, "LINK reserves stack space"); + mu_assert_true(m68k_step(core, "4e58"), "unlk a0"); + mu_assert_eq(rz_reg_getv(reg, "a0"), 0x400, "UNLK restores frame pointer"); + mu_assert_eq(rz_reg_getv(reg, "a7"), 0x800, "UNLK restores stack"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "LINK/UNLK preserve SR"); + rz_core_free(core); + mu_end; +} + +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE +static bool m68k_opex_field(const RzAnalysisOp *op, size_t index, const char *key, const char *expected) { + rz_return_val_if_fail(op && key && expected, false); + mu_assert_notnull(op->opex, "operand metadata exists"); + char *text = rz_structured_data_to_json(op->opex); + char *expected_text = rz_str_dup(expected); + mu_assert_notnull(text, "operand JSON"); + mu_assert_notnull(expected_text, "expected JSON"); + RzJson *json = rz_json_parse(text); + RzJson *expected_json = rz_json_parse(expected_text); + const RzJson *opex = json ? rz_json_get(json, "opex") : NULL; + const RzJson *operands = opex ? rz_json_get(opex, "operands") : NULL; + const RzJson *operand = operands ? rz_json_item(operands, index) : NULL; + const RzJson *field = operand ? operand->children.first : NULL; + while (field && (!field->key || strcmp(field->key, key))) { + field = field->next; + } + bool matches = field && expected_json && rz_json_eq(field, expected_json); + if (!matches) { + fprintf(stderr, "operand %zu %s: expected %s\n", index, key, expected); + } + rz_json_free(expected_json); + rz_json_free(json); + free(expected_text); + free(text); + return matches; +} + +static bool test_m68k_coldfire_profiles(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + const RzAsmPlugin *plugin = rz_asm_plugin_current(core->rasm); + mu_assert_notnull(plugin, "M68K assembler plugin"); + mu_assert_notnull(plugin->get_cpu_desc, "CPU descriptions callback"); + char **descriptions = plugin->get_cpu_desc(); + const char *cpus[] = { "cfv1", "cfv2", "cfv3", "cfv4", "cfv4e", "cfv5", "coldfire" }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(cpus); i++) { + bool listed = false; + for (size_t j = 0; descriptions[j]; j += 2) { + if (!strcmp(descriptions[j], cpus[i])) { + listed = descriptions[j + 1] && *descriptions[j + 1]; + break; + } + } + mu_assert_true(listed, "ColdFire profile has a description"); + mu_assert_true(rz_core_arch_configure(core, "m68k", 32, cpus[i], NULL, NULL), "select ColdFire profile"); + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, "101f"), "MOVE.B (A7)+,D0 on ColdFire"); + mu_assert_true(m68k_value_mem(op.src[0], "a7", 1, RZ_ANALYSIS_ACC_R), "byte load source"); + rz_analysis_op_fini(&op); + m68k_reset(core, 0, 0, 0x2010); + mu_assert_true(m68k_step(core, "101f"), "byte load executes on selected CPU"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x801, "ColdFire A7 byte increment"); + mu_assert_true(rz_core_arch_configure(core, "m68k", 32, "68020", NULL, NULL), "switch back to classic M68K"); + m68k_reset(core, 0, 0, 0x2010); + mu_assert_true(m68k_step(core, "101f"), "byte load executes on classic CPU"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x802, "ColdFire mode does not leak into classic execution"); + } + rz_core_free(core); + mu_end; +} + +static bool test_m68k_coldfire_acc_copy(void) { + const char *cpus[] = { "coldfire", "cfv4e", "cfv5" }; + /* Signed integer, unsigned integer, and fractional MACSR modes. */ + const ut32 modes[] = { 0, 0x40, 0x20 }; + for (size_t cpu = 0; cpu < RZ_ARRAY_SIZE(cpus); cpu++) { + RzCore *core = m68k_core_new(cpus[cpu]); + mu_assert_notnull(core, "ColdFire core"); + RzReg *reg = rz_analysis_get_reg(core->analysis); + for (size_t mode = 0; mode < RZ_ARRAY_SIZE(modes); mode++) { + for (ut32 ev = 0; ev <= 1; ev++) { + m68k_reset(core, 0, 0, 0x201f); + rz_reg_setv(reg, "acc0", 0x12345678); + rz_reg_setv(reg, "acc1", 0); + rz_reg_setv(reg, "accext01", 1); + rz_reg_setv(reg, "macsr", 0x100 | modes[mode] | ev); + mu_assert_true(m68k_step(core, "a310"), "MOVE ACC0,ACC1 executes and releases its IL tree"); + mu_assert_eq(rz_reg_getv(reg, "acc0"), 0x12345678, "source accumulator is preserved"); + mu_assert_eq(rz_reg_getv(reg, "acc1"), 0x12345678, "destination accumulator is copied"); + mu_assert_eq(rz_reg_getv(reg, "accext01"), 0x00010001, "accumulator extension is copied"); + /* The value overflows 32-bit integer storage but fits fractional + * storage. EMAC recomputes EV; original MAC preserves it. PAV0 + * remains set and is copied to PAV1 and V; N and Z are clear. */ + ut32 expected_ev = cpu == 0 ? ev : (mode == 2 ? 0 : 1); + mu_assert_eq(rz_reg_getv(reg, "macsr"), 0x302 | modes[mode] | expected_ev, "MACSR after accumulator copy"); + mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "accumulator copy preserves SR"); + mu_assert_eq(rz_reg_getv(reg, "pc"), 0x102, "accumulator copy advances PC"); + } + } + rz_core_free(core); + } + mu_end; +} + +static bool test_m68k_coldfire_values(void) { + RzCore *core = m68k_core_new("cfv1"); + mu_assert_notnull(core, "ColdFire core"); + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, "a140"), "MOV3Q on CFv1"); + mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_MOV, "MOV3Q type"); + mu_assert_notnull(op.src[0], "MOV3Q immediate"); + mu_assert_eq(op.src[0]->imm, UT32_MAX, "MOV3Q encodes minus one"); + mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "MOV3Q destination"); + rz_analysis_op_fini(&op); + const char *unary[] = { "00c0", "02c0", "04c0", "4c80" }; /* BITREV, BYTEREV, FF1, SATS */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(unary); i++) { + mu_assert_true(m68k_decode(core, &op, unary[i]), "ColdFire unary operation"); + mu_assert_true(m68k_value_reg(op.src[0], "d0", RZ_ANALYSIS_ACC_R), "unary source"); + mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "unary destination"); + rz_analysis_op_fini(&op); + } + const char *casts[] = { "7100", "7180", "7110", "7190" }; /* MVS/MVZ from D0/(A0) */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(casts); i++) { + mu_assert_true(m68k_decode(core, &op, casts[i]), "ColdFire sign/zero extension"); + mu_assert_eq(op.type, i < 2 ? RZ_ANALYSIS_OP_TYPE_CAST : RZ_ANALYSIS_OP_TYPE_LOAD, "cast or load type"); + mu_assert_eq(op.sign, !(i % 2), "MVS is signed; MVZ is unsigned"); + if (i < 2) { + mu_assert_true(m68k_value_reg(op.src[0], "d0", RZ_ANALYSIS_ACC_R), "cast source"); + } else { + mu_assert_true(m68k_value_mem(op.src[0], "a0", 1, RZ_ANALYSIS_ACC_R), "cast memory source"); + } + mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "cast destination"); + rz_analysis_op_fini(&op); + } + mu_assert_true(m68k_decode(core, &op, "40e746fc24d2"), "STRLDSR"); + mu_assert_eq(op.stackptr, -4, "STRLDSR stack delta"); + mu_assert_notnull(op.src[0], "STRLDSR immediate"); + mu_assert_eq(op.src[0]->imm, 0x24d2, "STRLDSR new SR"); + mu_assert_true(m68k_value_reg(op.src[1], "sr", RZ_ANALYSIS_ACC_R), "STRLDSR reads old SR"); + mu_assert_true(m68k_value_reg(op.dst, "sr", RZ_ANALYSIS_ACC_W), "STRLDSR writes SR"); + rz_analysis_op_fini(&op); + const char *transfers[] = { "fc900000", "fd900000", "fe900000", "ff900000" }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(transfers); i++) { + mu_assert_true(m68k_decode(core, &op, transfers[i]), "coprocessor memory transfer"); + if (i % 2) { + mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_STORE, "coprocessor store"); + mu_assert_true(m68k_value_mem(op.dst, "a0", 4, RZ_ANALYSIS_ACC_W), "coprocessor store destination"); + mu_assert_null(op.src[0], "coprocessor store has no CPU source"); + } else { + mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_LOAD, "coprocessor load"); + mu_assert_true(m68k_value_mem(op.src[0], "a0", 4, RZ_ANALYSIS_ACC_R), "coprocessor load source"); + mu_assert_null(op.dst, "coprocessor load has no CPU destination"); + } + rz_analysis_op_fini(&op); + } + mu_assert_true(rz_core_arch_configure(core, "m68k", 32, "cfv4e", NULL, NULL), "select EMAC"); + mu_assert_true(m68k_decode(core, &op, "a1c0"), "MOVCLR"); + mu_assert_true(m68k_value_reg(op.src[0], "acc0", RZ_ANALYSIS_ACC_R), "MOVCLR accumulator source"); + mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "MOVCLR destination"); + rz_analysis_op_fini(&op); + + /* The flags are part of OPEX's numeric interface: lower=1, upper=2, + * left=4, right=8, masked memory=16. */ + const char *macs[] = { "a293a2a9", "a293a4a9" }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(macs); i++) { + mu_assert_true(m68k_decode(core, &op, macs[i]), "MAC with register halves, shift, and masked load"); + mu_assert_true(m68k_opex_field(&op, 0, "value", "\"a1\""), "MAC first register"); + mu_assert_true(m68k_opex_field(&op, 0, "flags", "1"), "MAC lower half"); + mu_assert_true(m68k_opex_field(&op, 1, "flags", "2"), "MAC upper half"); + mu_assert_true(m68k_opex_field(&op, 2, "type", "\"shift\""), "MAC shift operand"); + mu_assert_true(m68k_opex_field(&op, 2, "flags", i ? "8" : "4"), "MAC shift direction"); + mu_assert_true(m68k_opex_field(&op, 3, "flags", "16"), "MAC masked memory"); + mu_assert_true(m68k_value_reg(op.dst, "acc0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "MAC accumulator destination"); + rz_analysis_op_fini(&op); + } + rz_core_free(core); + mu_end; +} + +#endif + +static bool test_m68k_address_metadata(void) { + RzCore *core = m68k_core_new("68020"); + mu_assert_notnull(core, "M68K core"); + const char *hex[] = { "20380000", "20387fff", "20388000", "2038fffc", "203912345678" }; + const ut32 address[] = { 0, 0x7fff, 0xffff8000, 0xfffffffc, 0x12345678 }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(hex); i++) { + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, hex[i]), "absolute MOVE"); + mu_assert_notnull(op.src[0], "absolute memory source"); + mu_assert_true(op.src[0]->absolute, "absolute address"); + mu_assert_eq(op.src[0]->base, address[i], "absolute address value"); + mu_assert_eq(op.src[0]->delta, 0, "absolute address is not counted twice"); + mu_assert_eq(op.src[0]->memref, 4, "absolute memory width"); +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + char expected[16]; + snprintf(expected, sizeof(expected), "%" PFMT32u, address[i]); + mu_assert_true(m68k_opex_field(&op, 0, "address", expected), "absolute address in OPEX"); +#endif + rz_analysis_op_fini(&op); + } + const char *jumps[] = { "4ef8fffc", "4eb8fffc" }; /* JMP/JSR absolute short */ + for (size_t i = 0; i < RZ_ARRAY_SIZE(jumps); i++) { + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, jumps[i]), "absolute-short jump/call"); + mu_assert_eq(op.jump, 0xfffffffc, "analysis jump target is sign-extended"); + rz_analysis_op_fini(&op); + m68k_reset(core, 0, 0, 0x2010); + mu_assert_true(m68k_step(core, jumps[i]), "absolute-short jump/call executes"); + mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0xfffffffc, "analysis agrees with execution"); + } +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + const char *indexed[] = { "20300122fff0ffe0", "20300133fffffff0ffffffe0" }; + for (size_t i = 0; i < RZ_ARRAY_SIZE(indexed); i++) { + RzAnalysisOp op; + mu_assert_true(m68k_decode(core, &op, indexed[i]), "full-format preindexed MOVE"); + mu_assert_true(m68k_value_mem(op.src[0], "a0", 4, RZ_ANALYSIS_ACC_R), "indexed memory source"); + mu_assert_true(m68k_opex_field(&op, 0, "in_disp", "-16"), "signed base displacement"); + mu_assert_true(m68k_opex_field(&op, 0, "out_disp", "-32"), "signed outer displacement"); + /* Capstone's displacement-size metadata uses 0 for word, 1 for long. */ + mu_assert_true(m68k_opex_field(&op, 0, "in_disp_size", i ? "1" : "0"), "base displacement size"); + mu_assert_true(m68k_opex_field(&op, 0, "out_disp_size", i ? "1" : "0"), "outer displacement size"); + rz_analysis_op_fini(&op); + } +#endif + rz_core_free(core); + mu_end; +} + +int all_tests(void) { + mu_run_test(test_m68k_hidden_fpu_destination); +#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS + mu_run_test(test_m68k_fp_formats); +#endif + mu_run_test(test_m68k_bcc_conditions); + mu_run_test(test_m68k_scc_conditions); + mu_run_test(test_m68k_dbcc_conditions); + mu_run_test(test_m68k_branch_widths_and_calls); + mu_run_test(test_m68k_integer_results_and_flags); + mu_run_test(test_m68k_data_transfers); +#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE + mu_run_test(test_m68k_coldfire_profiles); + mu_run_test(test_m68k_coldfire_acc_copy); + mu_run_test(test_m68k_coldfire_values); +#endif + mu_run_test(test_m68k_address_metadata); + return tests_passed != tests_run; +} + +mu_main(all_tests)