diff --git a/librz/arch/isa/tms320/README.md b/librz/arch/isa/tms320/README.md index 833670f4f5..4a7d692520 100644 --- a/librz/arch/isa/tms320/README.md +++ b/librz/arch/isa/tms320/README.md @@ -89,6 +89,24 @@ RzIL, except with a register operand such as `@AL` in place of memory. The other arithmetic, `VPACK4`, `VSHLMB`, and the complex, Viterbi, FFT and Galois-field instructions are not lifted. +The FPU32 and FPU64 instructions of the floating-point parts decode too, with +the TMU's trigonometric and math instructions and the fast integer division. +All are documented in **SPRUHS1**, and FPU32 also in **SPRUEO2**. They work on +`R0H`-`R7H`, their low halves `R0L`-`R7L` and the 64-bit `R0`-`R7`, `STF` and +`RB`. They include the parallel forms written with `||`, such as +`MPYF32 ... || MOV32 ...`. The rows were derived from `dis2000` and checked +against it on random encodings of every row. Most are lifted to RzIL. These are +not: + +- the TMU's transcendental functions and the reciprocal estimates, whose exact + results TI does not define +- `PREDIVF64`, `SUBC3F64` and `POSTDIVF64`, and `MOV32` between the halves of + two registers, which SPRUHS1C does not document +- `MOVDD32 RaL,mem32`, whose description contradicts itself +- `MACF32 RaH,RbH,mem32,*XAR7++` with registers other than `R7H,R3H` +- a register operand such as `@ACC` in place of `mem32`, except in an + unconditional `MOV32` to or from `RaH` or `RaL` + ## c55x Variable-length (1-7 byte) instructions, little-endian, 16-bit word. @@ -159,7 +177,7 @@ as `c28x`, from COFF and from ELF with `e_machine` set to `EM_TI_C2000`. - TI [SPRAC71C][sprac71c] -- C28x Embedded Application Binary Interface (DWARF register numbers and ELF relocations) - TI [SPRUHS1C][spruhs1c] -- TMS320C28x Extended Instruction Sets Technical - Reference Manual (the VCU) + Reference Manual (the VCU, FPU, TMU and FINTDIV) - TI SWPU086 -- TMS320C55x 'C55x+' CPU Reference Guide, Preliminary, May 2005 - TI SWPU104 -- TMS320C55x+ DSP Algebraic Instruction Set Reference diff --git a/librz/arch/isa/tms320/c28x/c28x.h b/librz/arch/isa/tms320/c28x/c28x.h index 6f52d237f2..2cb0be1fdc 100644 --- a/librz/arch/isa/tms320/c28x/c28x.h +++ b/librz/arch/isa/tms320/c28x/c28x.h @@ -97,6 +97,39 @@ typedef enum { C28X_REG_XF, C28X_REG_NMI, C28X_REG_EMUINT, + // FPU32: result registers R0H-R7H, the status register and the repeat-block + // register. R0H-R7H stay consecutive for a 3-bit field. + C28X_REG_R0H, + C28X_REG_R1H, + C28X_REG_R2H, + C28X_REG_R3H, + C28X_REG_R4H, + C28X_REG_R5H, + C28X_REG_R6H, + C28X_REG_R7H, + C28X_REG_STF, + C28X_REG_RB, + // FPU64 splits each result register into RaH:RaL and names the 64-bit whole + // Ra. The fast integer division works on fixed pairs of result registers. + C28X_REG_R0L, + C28X_REG_R1L, + C28X_REG_R2L, + C28X_REG_R3L, + C28X_REG_R4L, + C28X_REG_R5L, + C28X_REG_R6L, + C28X_REG_R7L, + C28X_REG_R0, + C28X_REG_R1, + C28X_REG_R2, + C28X_REG_R3, + C28X_REG_R4, + C28X_REG_R5, + C28X_REG_R6, + C28X_REG_R7, + C28X_REG_R1H_R0H, + C28X_REG_R2H_R4H, + C28X_REG_R3H_R5H, // VCU registers that only moves and CRC set-up name C28X_REG_VCRC, C28X_REG_VSTATUS, @@ -151,6 +184,10 @@ typedef enum { C28X_OP_PORT, ///< I/O space port address, rendered as "*(PA)" C28X_OP_MODE, ///< ST0/ST1 mode bit mask for SETC/CLRC C28X_OP_INTR, ///< interrupt selector for INTR, rendered by name + C28X_OP_FCOND, ///< FPU condition code in \ref C28xOperand::imm + C28X_OP_FFLAGS, ///< MOVST0 flag mask in \ref C28xOperand::imm + C28X_OP_FSETFLG, ///< SETFLG/SAVE flag values, for the flags in \ref C28xOperand::mask + C28X_OP_FZERO, ///< the constant #0.0 C28X_OP_PAR, ///< start of the parallel half; its \ref C28xInsnId in \ref C28xOperand::imm C28X_OP_REG_HIGH, ///< high half of a VCU register, spelled VRnH C28X_OP_VSMPAIR, ///< state-metric pair VSM(2n+1):VSM(2n), n in \ref C28xOperand::imm @@ -172,6 +209,7 @@ typedef struct { ut8 arn; ///< XARn / ARPn selected by the mode ut8 off; ///< 6-bit DP or SP offset, or the 3-bit XARn index bool wide; ///< loc32 (32-bit) rather than loc16 (16-bit) access + ut16 mask; ///< SETFLG/SAVE: the flags whose values \ref imm holds } C28xOperand; /** @@ -191,11 +229,21 @@ typedef struct { X(A_VCLROVFR, "a_vclrovfr") \ X(ABORTI, "aborti") \ X(ABS, "abs") \ + X(ABSF32, "absf32") \ + X(ABSF64, "absf64") \ + X(ABSI32DIV32, "absi32div32") \ + X(ABSI32DIV32U, "absi32div32u") \ + X(ABSI64DIV32, "absi64div32") \ + X(ABSI64DIV32U, "absi64div32u") \ + X(ABSI64DIV64, "absi64div64") \ + X(ABSI64DIV64U, "absi64div64u") \ X(ABSTC, "abstc") \ X(ADD, "add") \ X(ADDB, "addb") \ X(ADDCL, "addcl") \ X(ADDCU, "addcu") \ + X(ADDF32, "addf32") \ + X(ADDF64, "addf64") \ X(ADDL, "addl") \ X(ADDU, "addu") \ X(ADDUL, "addul") \ @@ -206,6 +254,7 @@ typedef struct { X(ASR, "asr") \ X(ASR64, "asr64") \ X(ASRL, "asrl") \ + X(ATANPUF32, "atanpuf32") \ X(B, "b") \ X(BANZ, "banz") \ X(BAR, "bar") \ @@ -214,22 +263,54 @@ typedef struct { X(CMP, "cmp") \ X(CMP64, "cmp64") \ X(CMPB, "cmpb") \ + X(CMPF32, "cmpf32") \ + X(CMPF64, "cmpf64") \ X(CMPL, "cmpl") \ X(CMPR, "cmpr") \ + X(COSPUF32, "cospuf32") \ X(CSB, "csb") \ X(DEC, "dec") \ X(DINT, "dint") \ + X(DIV2PIF32, "div2pif32") \ + X(DIVF32, "divf32") \ X(DMAC, "dmac") \ X(DMOV, "dmov") \ X(EALLOW, "eallow") \ X(EDIS, "edis") \ X(EINT, "eint") \ + X(EINVF32, "einvf32") \ + X(EINVF64, "einvf64") \ + X(EISQRTF32, "eisqrtf32") \ + X(EISQRTF64, "eisqrtf64") \ + X(ENEGI32DIV32, "enegi32div32") \ + X(ENEGI64DIV32, "enegi64div32") \ + X(ENEGI64DIV64, "enegi64div64") \ X(ESTOP0, "estop0") \ X(ESTOP1, "estop1") \ + X(F32DTOF64, "f32dtof64") \ + X(F32TOF64, "f32tof64") \ + X(F32TOI16, "f32toi16") \ + X(F32TOI16R, "f32toi16r") \ + X(F32TOI32, "f32toi32") \ + X(F32TOUI16, "f32toui16") \ + X(F32TOUI16R, "f32toui16r") \ + X(F32TOUI32, "f32toui32") \ + X(F64TOF32, "f64tof32") \ + X(F64TOI32, "f64toi32") \ + X(F64TOI64, "f64toi64") \ + X(F64TOUI32, "f64toui32") \ + X(F64TOUI64, "f64toui64") \ X(FFC, "ffc") \ X(FLIP, "flip") \ + X(FRACF32, "fracf32") \ + X(FRACF64, "fracf64") \ + X(I16TOF32, "i16tof32") \ + X(I32TOF32, "i32tof32") \ + X(I32TOF64, "i32tof64") \ + X(I64TOF64, "i64tof64") \ X(IACK, "iack") \ X(IDLE, "idle") \ + X(IEXP2F32, "iexp2f32") \ X(IMACL, "imacl") \ X(IMPYAL, "impyal") \ X(IMPYL, "impyl") \ @@ -242,6 +323,7 @@ typedef struct { X(LB, "lb") \ X(LC, "lc") \ X(LCR, "lcr") \ + X(LOG2F32, "log2f32") \ X(LOOPNZ, "loopnz") \ X(LOOPZ, "loopz") \ X(LPADDR, "lpaddr") \ @@ -255,34 +337,60 @@ typedef struct { X(LSR64, "lsr64") \ X(LSRL, "lsrl") \ X(MAC, "mac") \ + X(MACF32, "macf32") \ + X(MACF64, "macf64") \ X(MAX, "max") \ X(MAXCUL, "maxcul") \ + X(MAXF32, "maxf32") \ + X(MAXF64, "maxf64") \ X(MAXL, "maxl") \ X(MIN, "min") \ X(MINCUL, "mincul") \ + X(MINF32, "minf32") \ + X(MINF64, "minf64") \ X(MINL, "minl") \ + X(MNEGI32DIV32, "mnegi32div32") \ + X(MNEGI64DIV32, "mnegi64div32") \ + X(MNEGI64DIV64, "mnegi64div64") \ X(MOV, "mov") \ + X(MOV16, "mov16") \ + X(MOV32, "mov32") \ + X(MOV64, "mov64") \ X(MOVA, "mova") \ X(MOVAD, "movad") \ X(MOVB, "movb") \ + X(MOVD32, "movd32") \ + X(MOVDD32, "movdd32") \ X(MOVDL, "movdl") \ X(MOVH, "movh") \ + X(MOVIX, "movix") \ + X(MOVIZ, "moviz") \ X(MOVL, "movl") \ X(MOVP, "movp") \ X(MOVS, "movs") \ + X(MOVST0, "movst0") \ X(MOVU, "movu") \ X(MOVW, "movw") \ X(MOVX, "movx") \ + X(MOVXI, "movxi") \ X(MOVZ, "movz") \ X(MPY, "mpy") \ + X(MPY2PIF32, "mpy2pif32") \ X(MPYA, "mpya") \ X(MPYB, "mpyb") \ + X(MPYF32, "mpyf32") \ + X(MPYF64, "mpyf64") \ X(MPYS, "mpys") \ X(MPYU, "mpyu") \ X(MPYXU, "mpyxu") \ X(NASP, "nasp") \ X(NEG, "neg") \ X(NEG64, "neg64") \ + X(NEGF32, "negf32") \ + X(NEGF64, "negf64") \ + X(NEGI32DIV32, "negi32div32") \ + X(NEGI64DIV32, "negi64div32") \ + X(NEGI64DIV64, "negi64div64") \ X(NEGTC, "negtc") \ X(NOP, "nop") \ X(NORM, "norm") \ @@ -291,7 +399,9 @@ typedef struct { X(ORB, "orb") \ X(OUT, "out") \ X(POP, "pop") \ + X(POSTDIVF64, "postdivf64") \ X(PREAD, "pread") \ + X(PREDIVF64, "predivf64") \ X(PUSH, "push") \ X(PWRITE, "pwrite") \ X(QMACL, "qmacl") \ @@ -300,37 +410,54 @@ typedef struct { X(QMPYSL, "qmpysl") \ X(QMPYUL, "qmpyul") \ X(QMPYXUL, "qmpyxul") \ + X(QUADF32, "quadf32") \ + X(RESTORE, "restore") \ X(ROL, "rol") \ X(ROR, "ror") \ X(RPT, "rpt") \ X(RPTB, "rptb") \ X(SAT, "sat") \ X(SAT64, "sat64") \ + X(SAVE, "save") \ X(SB, "sb") \ X(SBBU, "sbbu") \ X(SBF, "sbf") \ X(SBRK, "sbrk") \ X(SETC, "setc") \ + X(SETFLG, "setflg") \ X(SFR, "sfr") \ + X(SINPUF32, "sinpuf32") \ X(SPM, "spm") \ X(SQRA, "sqra") \ X(SQRS, "sqrs") \ + X(SQRTF32, "sqrtf32") \ X(SUB, "sub") \ X(SUBB, "subb") \ X(SUBBL, "subbl") \ + X(SUBC2UI64, "subc2ui64") \ + X(SUBC3F64, "subc3f64") \ + X(SUBC4UI32, "subc4ui32") \ X(SUBCU, "subcu") \ X(SUBCUL, "subcul") \ + X(SUBF32, "subf32") \ + X(SUBF64, "subf64") \ X(SUBL, "subl") \ X(SUBR, "subr") \ X(SUBRL, "subrl") \ X(SUBU, "subu") \ X(SUBUL, "subul") \ + X(SWAPF, "swapf") \ X(SXTB, "sxtb") \ X(TBIT, "tbit") \ X(TCLR, "tclr") \ X(TEST, "test") \ + X(TESTTF, "testtf") \ X(TRAP, "trap") \ X(TSET, "tset") \ + X(UI16TOF32, "ui16tof32") \ + X(UI32TOF32, "ui32tof32") \ + X(UI32TOF64, "ui32tof64") \ + X(UI64TOF64, "ui64tof64") \ X(UOUT, "uout") \ X(VASHL32, "vashl32") \ X(VASHR32, "vashr32") \ @@ -440,7 +567,9 @@ typedef struct { X(XRETC, "xretc") \ X(ZALR, "zalr") \ X(ZAP, "zap") \ - X(ZAPA, "zapa") + X(ZAPA, "zapa") \ + X(ZERO, "zero") \ + X(ZEROA, "zeroa") /** * \brief Instruction identifier, one per mnemonic. @@ -518,6 +647,7 @@ RZ_IPI RZ_OWN RzStructuredData *c28x_opex(RZ_NONNULL const C28xInsn *insn); RZ_IPI RZ_BORROW const char *c28x_reg_name(C28xReg reg); RZ_IPI RZ_BORROW const char *c28x_cond_name(ut8 cond); +RZ_IPI RZ_BORROW const char *c28x_fcond_name(ut8 cond); RZ_IPI RZ_BORROW const char *c28x_insn_name(C28xInsnId id); RZ_IPI RZ_OWN RzPVector /**/ *c28x_mnemonics(void); diff --git a/librz/arch/isa/tms320/c28x/c28x_analysis.c b/librz/arch/isa/tms320/c28x/c28x_analysis.c index a90eaa4c5c..249c97c585 100644 --- a/librz/arch/isa/tms320/c28x/c28x_analysis.c +++ b/librz/arch/isa/tms320/c28x/c28x_analysis.c @@ -104,6 +104,10 @@ static const char *const c28x_opkind_names[] = { [C28X_OP_PORT] = "port", [C28X_OP_MODE] = "mode", [C28X_OP_INTR] = "intr", + [C28X_OP_FCOND] = "fcond", + [C28X_OP_FFLAGS] = "fflags", + [C28X_OP_FSETFLG] = "fsetflg", + [C28X_OP_FZERO] = "fzero", [C28X_OP_PAR] = "par", [C28X_OP_REG_HIGH] = "reg_high", [C28X_OP_VSMPAIR] = "vsm_pair", @@ -216,10 +220,18 @@ RZ_IPI RZ_OWN RzStructuredData *c28x_opex(RZ_NONNULL const C28xInsn *insn) { rz_structured_data_map_add_string(ent, "part", o->kind == C28X_OP_REG_LOW ? "low" : "high"); break; + case C28X_OP_FCOND: + rz_structured_data_map_add_string(ent, "value", + c28x_fcond_name((ut8)o->imm)); + break; case C28X_OP_PAR: rz_structured_data_map_add_string(ent, "value", c28x_insn_name((C28xInsnId)o->imm)); break; + case C28X_OP_FSETFLG: + rz_structured_data_map_add_unsigned(ent, "mask", o->mask, true); + rz_structured_data_map_add_unsigned(ent, "value", (ut64)o->imm, true); + break; case C28X_OP_PCREL: case C28X_OP_PMA: case C28X_OP_DMA: diff --git a/librz/arch/isa/tms320/c28x/c28x_decode.c b/librz/arch/isa/tms320/c28x/c28x_decode.c index fd69aebb89..38b5fa3b75 100644 --- a/librz/arch/isa/tms320/c28x/c28x_decode.c +++ b/librz/arch/isa/tms320/c28x/c28x_decode.c @@ -47,6 +47,10 @@ typedef enum { C28X_OD_BITNUM, ///< bit number for TBIT/TSET/TCLR C28X_OD_INTR, ///< interrupt selector for INTR C28X_OD_IND, ///< fixed indirect operand, mode in param and register in lo + C28X_OD_FCOND, ///< 4-bit FPU condition code; the reserved ones name nothing + C28X_OD_FFLAGS, ///< MOVST0 flag mask + C28X_OD_FSETFLG, ///< SETFLG/SAVE: values at lo, the mask at param, width bits each + C28X_OD_FZERO, ///< the constant #0.0 C28X_OD_PAR, ///< parallel half begins; param is its C28xInsnId C28X_OD_REGSEL_HIGH, ///< as REGSEL, but naming the register's high half C28X_OD_REGSEL_SPLIT, ///< VR0-VR7, low bits at lo and the rest at param @@ -60,7 +64,7 @@ typedef struct { ut8 kind; ///< C28xOpndKind ut8 lo; ///< low bit of the field inside the packed opcode ut8 width; ///< field width in bits - ut8 param; ///< kind-specific selector (see \ref C28xOpndKind) + ut16 param; ///< kind-specific selector, wide enough for a C28xInsnId (\ref C28xOpndKind) } C28xOpndDef; typedef struct { @@ -77,6 +81,7 @@ typedef struct { static const C28xInsnDef c28x_table[] = { #include "c28x_rows.inc" #include "c28x_rows_vcu.inc" +#include "c28x_rows_fpu.inc" }; #include "c28x_rowundefs.h" @@ -207,6 +212,11 @@ static st64 c28x_sext(ut32 v, ut8 width) { */ static const ut8 c28x_regsel_counts[] = { [C28X_REG_VR0] = 9, + [C28X_REG_R0H] = 8, + [C28X_REG_R4H] = 4, + [C28X_REG_R0L] = 8, + [C28X_REG_R4L] = 4, + [C28X_REG_R0] = 8, [C28X_REG_VT0] = 2, }; @@ -355,6 +365,23 @@ static void c28x_decode_operand(const C28xOpndDef *def, ut32 packed, ut64 pc, out->kind = C28X_OP_INTR; out->imm = f; break; + case C28X_OD_FCOND: + // codes 6-9 are reserved; dis2000 prints nothing for them + out->kind = f >= 6 && f <= 9 ? C28X_OP_NONE : C28X_OP_FCOND; + out->imm = f; + break; + case C28X_OD_FFLAGS: + out->kind = C28X_OP_FFLAGS; + out->imm = f; + break; + case C28X_OD_FSETFLG: + out->kind = C28X_OP_FSETFLG; + out->imm = f; + out->mask = BITS(packed, def->param, def->width); + break; + case C28X_OD_FZERO: + out->kind = C28X_OP_FZERO; + break; case C28X_OD_PAR: out->kind = C28X_OP_PAR; out->imm = def->param; diff --git a/librz/arch/isa/tms320/c28x/c28x_format.c b/librz/arch/isa/tms320/c28x/c28x_format.c index ba5261cc38..e3d0350851 100644 --- a/librz/arch/isa/tms320/c28x/c28x_format.c +++ b/librz/arch/isa/tms320/c28x/c28x_format.c @@ -51,6 +51,35 @@ static const char *const c28x_reg_names[] = { [C28X_REG_VR7] = "vr7", [C28X_REG_VR8] = "vr8", [C28X_REG_VT0] = "vt0", + [C28X_REG_R0H] = "r0h", + [C28X_REG_R1H] = "r1h", + [C28X_REG_R2H] = "r2h", + [C28X_REG_R3H] = "r3h", + [C28X_REG_R4H] = "r4h", + [C28X_REG_R5H] = "r5h", + [C28X_REG_R6H] = "r6h", + [C28X_REG_R7H] = "r7h", + [C28X_REG_STF] = "stf", + [C28X_REG_RB] = "rb", + [C28X_REG_R0L] = "r0l", + [C28X_REG_R1L] = "r1l", + [C28X_REG_R2L] = "r2l", + [C28X_REG_R3L] = "r3l", + [C28X_REG_R4L] = "r4l", + [C28X_REG_R5L] = "r5l", + [C28X_REG_R6L] = "r6l", + [C28X_REG_R7L] = "r7l", + [C28X_REG_R0] = "r0", + [C28X_REG_R1] = "r1", + [C28X_REG_R2] = "r2", + [C28X_REG_R3] = "r3", + [C28X_REG_R4] = "r4", + [C28X_REG_R5] = "r5", + [C28X_REG_R6] = "r6", + [C28X_REG_R7] = "r7", + [C28X_REG_R1H_R0H] = "r1h:r0h", + [C28X_REG_R2H_R4H] = "r2h:r4h", + [C28X_REG_R3H_R5H] = "r3h:r5h", [C28X_REG_VCRC] = "vcrc", [C28X_REG_VSTATUS] = "vstatus", [C28X_REG_VCRCPOLY] = "vcrcpoly", @@ -106,6 +135,37 @@ RZ_IPI RZ_BORROW const char *c28x_reg_name(C28xReg reg) { return c28x_reg_names[reg]; } +/** + * \brief FPU condition names by code. + * + * The FPU tests STF rather than ST0, so its conditions differ from the core's + * from code 6 on. The reserved codes 6-9 print as nothing. + */ +static const char *const c28x_fcond_names[16] = { + "neq", "eq", "gt", "geq", "lt", "leq", "", "", + "", "", "tf", "ntf", "lu", "lv", "unc", "uncf" +}; + +/** + * \brief STF flag names in MOVST0 order. + * + * MOVST0 and SETFLG/SAVE number the same STF flags in different orders. + */ +static const char *const c28x_movst0_names[8] = { + "lvf", "luf", "nf", "ni", "zf", "zi", "ci", "tf" +}; + +static const char *const c28x_setflg_names[11] = { + "lvf", "luf", "nf", "zf", "ni", "zi", "tf", "rndq16", "rndq32", "rndf32", "rndf64" +}; + +/** + * \brief Printable name of FPU condition code \p cond. + */ +RZ_IPI RZ_BORROW const char *c28x_fcond_name(ut8 cond) { + return c28x_fcond_names[cond & 0xf]; +} + /** * \brief Printable name of condition code \p cond. */ @@ -251,6 +311,37 @@ static void c28x_format_operand(RzStrBuf *sb, const C28xInsn *insn, const C28xOp case C28X_OP_COND: rz_strbuf_append(sb, c28x_cond_name((ut8)op->imm)); break; + case C28X_OP_FCOND: + rz_strbuf_append(sb, c28x_fcond_name((ut8)op->imm)); + break; + case C28X_OP_FFLAGS: { + bool any = false; + for (ut32 b = 0; b < RZ_ARRAY_SIZE(c28x_movst0_names); b++) { + if (op->imm & (1u << b)) { + rz_strbuf_appendf(sb, "%s%s", any ? "," : "", c28x_movst0_names[b]); + any = true; + } + } + if (!any) { + rz_strbuf_append(sb, "#0"); + } + break; + } + case C28X_OP_FSETFLG: { + const ut32 mask = op->mask; + bool any = false; + for (ut32 b = 0; b < RZ_ARRAY_SIZE(c28x_setflg_names); b++) { + if (mask & (1u << b)) { + rz_strbuf_appendf(sb, "%s%s=%u", any ? "," : "", + c28x_setflg_names[b], (ut32)(op->imm >> b) & 1); + any = true; + } + } + break; + } + case C28X_OP_FZERO: + rz_strbuf_append(sb, "#0.0"); + break; case C28X_OP_PCREL: case C28X_OP_PMA: rz_strbuf_appendf(sb, "0x%" PFMT64x, (ut64)op->imm); diff --git a/librz/arch/isa/tms320/c28x/c28x_il.c b/librz/arch/isa/tms320/c28x/c28x_il.c index 2d2152437e..301027816a 100644 --- a/librz/arch/isa/tms320/c28x/c28x_il.c +++ b/librz/arch/isa/tms320/c28x/c28x_il.c @@ -3243,8 +3243,11 @@ RZ_IPI RZ_OWN RzILOpEffect *c28x_lift(RZ_NONNULL const C28xInsn *insn, ut64 pc) if ((size_t)insn->id < RZ_ARRAY_SIZE(c28x_lifters) && c28x_lifters[insn->id]) { eff = c28x_lifters[insn->id](insn, pc); } - // the VCU lifts its own instructions - return eff ? eff : c28x_lift_vcu(insn, pc); + // the extensions lift their own instructions and their forms of core ones, such as PUSH RB + if (!eff) { + eff = c28x_lift_vcu(insn, pc); + } + return eff ? eff : c28x_lift_fpu(insn, pc); } /** diff --git a/librz/arch/isa/tms320/c28x/c28x_il.h b/librz/arch/isa/tms320/c28x/c28x_il.h index 1ae1c18613..6bb8a7256b 100644 --- a/librz/arch/isa/tms320/c28x/c28x_il.h +++ b/librz/arch/isa/tms320/c28x/c28x_il.h @@ -37,5 +37,6 @@ static inline RzILOpEffect *c28x_with_mem(const C28xOperand *m, bool wide, RzILO } RZ_IPI RzILOpEffect *c28x_lift_vcu(const C28xInsn *insn, ut64 pc); +RZ_IPI RzILOpEffect *c28x_lift_fpu(const C28xInsn *insn, ut64 pc); #endif // C28X_IL_H diff --git a/librz/arch/isa/tms320/c28x/c28x_il_fpu.c b/librz/arch/isa/tms320/c28x/c28x_il_fpu.c new file mode 100644 index 0000000000..28115c84da --- /dev/null +++ b/librz/arch/isa/tms320/c28x/c28x_il_fpu.c @@ -0,0 +1,1533 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +/* + * RzIL for the C28x FPU (SPRUHS1C chapters 1 and 2). + * + * The FPU computes the way TI's FPU primer (SPRAAN9A) describes: a denormal + * operand counts as zero and a NaN as infinity, results never come out + * denormal or NaN, and ADDF32, SUBF32 and MPYF32 round to zero or to nearest + * even as STF.RND32 selects (SPRUHS1C table 1-2). + */ + +#include "c28x_il.h" + +#include + +typedef RzILOpEffect *(*C28xFpuLifter)(const C28xInsn *insn); + +static const char *c28x_fpu_regs[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }; +static const char *c28x_fpu_shadows[] = { "r0s", "r1s", "r2s", "r3s", "r4s", "r5s", "r6s", "r7s" }; + +/** + * \brief STF flags by bit (SPRUHS1C figures 1-3 and 2-3); SHDWS, bit 31, is + * left to SAVE and RESTORE. + */ +static const char *c28x_stf_bits[] = { + [0] = "lvf", + [1] = "luf", + [2] = "nf", + [3] = "zf", + [4] = "ni", + [5] = "zi", + [6] = "tf", + [9] = "rnd32", + [10] = "rnd64", +}; + +/** + * \brief The 64-bit IL global behind FPU register operand \p o, and in + * \p high whether \p o names its RnH half (else its RnL half). + */ +static const char *c28x_fpu_name(const C28xOperand *o, bool *high) { + if (o->kind != C28X_OP_REG) { + return NULL; + } + if (o->reg >= C28X_REG_R0H && o->reg <= C28X_REG_R7H) { + *high = true; + return c28x_fpu_regs[o->reg - C28X_REG_R0H]; + } + if (o->reg >= C28X_REG_R0L && o->reg <= C28X_REG_R7L) { + *high = false; + return c28x_fpu_regs[o->reg - C28X_REG_R0L]; + } + return NULL; +} + +/** + * \brief The 64-bit IL global of operand \p o when it names all of Ra (R0-R7). + */ +static const char *c28x_fpu_name64(const C28xOperand *o) { + if (o->kind != C28X_OP_REG || o->reg < C28X_REG_R0 || o->reg > C28X_REG_R7) { + return NULL; + } + return c28x_fpu_regs[o->reg - C28X_REG_R0]; +} + +static RzILOpPure *c28x_fpu_read(const C28xOperand *o) { + bool high; + const char *n = c28x_fpu_name(o, &high); + if (!n) { + return NULL; + } + RzILOpPure *v = VARG(n); + return UNSIGNED(32, high ? SHIFTR0(v, UN(8, 32)) : v); +} + +/** + * \brief RnH and RnL are one register on FPU64 parts, so a write keeps the + * other half. + */ +static RzILOpEffect *c28x_fpu_write(const C28xOperand *o, RzILOpPure *val) { + bool high; + const char *n = c28x_fpu_name(o, &high); + if (!n) { + rz_il_op_pure_free(val); + return NULL; + } + RzILOpPure *v = UNSIGNED(64, val); + if (high) { + RzILOpPure *low = LOGAND(VARG(n), UN(64, 0xffffffffULL)); + return SETG(n, LOGOR(low, SHIFTL0(v, UN(8, 32)))); + } + return SETG(n, LOGOR(LOGAND(VARG(n), UN(64, 0xffffffff00000000ULL)), v)); +} + +/** + * \brief A binary format the FPU computes in: binary32 in RnH or RnL for FPU32 + * and binary64 in Rn for FPU64. + */ +typedef struct { + RzFloatFormat format; + ut32 bits; + ut32 man; ///< mantissa width, where the exponent starts + ut64 emax; ///< the exponent field of infinity and NaN + const char *rnd; ///< the STF flag that rounds to nearest rather than truncating +} C28xFloat; + +static const C28xFloat c28x_bin32 = { RZ_FLOAT_IEEE754_BIN_32, 32, 23, 0xff, "rnd32" }; +static const C28xFloat c28x_bin64 = { RZ_FLOAT_IEEE754_BIN_64, 64, 52, 0x7ff, "rnd64" }; + +static ut64 c28x_fp_mask(const C28xFloat *f) { + return f->bits == 64 ? UT64_MAX : UT32_MAX; +} + +static ut64 c28x_fp_mant(const C28xFloat *f) { + return (1ULL << f->man) - 1; +} + +/** + * \brief The sign and exponent fields: a value's infinity of the same sign, as + * a mask. + */ +static ut64 c28x_fp_top(const C28xFloat *f) { + return ~c28x_fp_mant(f) & c28x_fp_mask(f); +} + +static RzILOpPure *c28x_fp_read(const C28xFloat *f, const C28xOperand *o) { + if (f->bits == 32) { + return c28x_fpu_read(o); + } + const char *n = c28x_fpu_name64(o); + return n ? VARG(n) : NULL; +} + +static RzILOpEffect *c28x_fp_write(const C28xFloat *f, const C28xOperand *o, RzILOpPure *v) { + if (f->bits == 32) { + return c28x_fpu_write(o, v); + } + const char *n = c28x_fpu_name64(o); + if (!n) { + rz_il_op_pure_free(v); + return NULL; + } + return SETG(n, v); +} + +/** + * \brief The bits of operand \p o: an FPU register, a #16FHi immediate (the + * value's top 16 bits) or #0.0. + */ +static RzILOpPure *c28x_fp_operand(const C28xFloat *f, const C28xOperand *o) { + if (o->kind == C28X_OP_IMM) { + return UN(f->bits, (ut64)(o->imm & 0xffff) << (f->bits - 16)); + } + if (o->kind == C28X_OP_FZERO) { + return UN(f->bits, 0); + } + return c28x_fp_read(f, o); +} + +static RzILOpPure *c28x_fp_exp(const C28xFloat *f, const char *local) { + return LOGAND(SHIFTR0(VARL(local), UN(8, f->man)), UN(f->bits, f->emax)); +} + +/** + * \brief The value in \p local as the FPU computes with it: zeros and + * denormals as +0, NaN as the infinity of its sign. + */ +static RzILOpFloat *c28x_fp_in(const C28xFloat *f, const char *local) { + RzILOpPure *inf = LOGAND(VARL(local), UN(f->bits, c28x_fp_top(f))); + RzILOpPure *big = ITE(EQ(c28x_fp_exp(f, local), UN(f->bits, f->emax)), inf, VARL(local)); + return BV2F(f->format, ITE(IS_ZERO(c28x_fp_exp(f, local)), UN(f->bits, 0), big)); +} + +/** + * \brief The IL locals of one binary32 operation: operand bits and their FPU + * views, the result's bits, exponent, nonzero mantissa and flush, and the + * exact result in binary64. Parallel forms run two operations, a set each. + */ +typedef struct { + const char *xa, *xb, *fa, *fb, *fr, *fe, *fm, *ft, *fw; +} C28xFpLocals; + +static const C28xFpLocals c28x_fp_one = { "xa", "xb", "fa", "fb", "fr", "fe", "fm", "ft", "fw" }; +static const C28xFpLocals c28x_fp_two = { "ya", "yb", "ga", "gb", "gr", "ge", "gm", "gt", "gw" }; + +/** + * \brief Latch \p a and \p b and their FPU views. + */ +static RzILOpEffect *c28x_fp_operands(const C28xFpLocals *l, const C28xFloat *f, RzILOpPure *a, + RzILOpPure *b) { + return SEQ4(SETL(l->xa, a), SETL(l->xb, b), SETL(l->fa, c28x_fp_in(f, l->xa)), + SETL(l->fb, c28x_fp_in(f, l->xb))); +} + +/** + * \brief A dynamic rounding mode is a 32-bit RzFloatRMode value. + */ +static RzILOpBitVector *c28x_fp_rnd(const C28xFloat *f) { + return ITE(VARG(f->rnd), UN(32, RZ_FLOAT_RMODE_RNE), UN(32, RZ_FLOAT_RMODE_RTZ)); +} + +/** + * \brief Deliver the binary32 result \p res of the operands in \p l to \p dst. + * + * A denormal result flushes to +0 and latches LUF, as does a zero product of + * nonzero factors when \p product; \p overflow latches LVF. The FPU never + * delivers NaN, and SPRAAN9A doesn't say what it delivers for one, so + * +infinity stands in. + */ +static RzILOpEffect *c28x_fp_out(const C28xFpLocals *l, const C28xFloat *f, const C28xOperand *dst, + RzILOpFloat *res, bool product, RzILOpBool *overflow) { + RzILOpBool *tiny = AND(IS_ZERO(VARL(l->fe)), VARL(l->fm)); + if (product) { + RzILOpBool *factors = AND(INV(IS_FZERO(VARL(l->fa))), INV(IS_FZERO(VARL(l->fb)))); + RzILOpBool *zero = IS_ZERO(LOGAND(VARL(l->fr), UN(f->bits, c28x_fp_mask(f) >> 1))); + tiny = OR(tiny, AND(zero, factors)); + } + RzILOpPure *nan = AND(EQ(VARL(l->fe), UN(f->bits, f->emax)), VARL(l->fm)); + RzILOpPure *inf = UN(f->bits, f->emax << f->man); + RzILOpPure *val = ITE(VARL(l->ft), UN(f->bits, 0), ITE(nan, inf, VARL(l->fr))); + RzILOpEffect *wr = c28x_fp_write(f, dst, val); + if (!wr) { + rz_il_op_pure_free(res); + rz_il_op_pure_free(tiny); + rz_il_op_pure_free(overflow); + return NULL; + } + RzILOpPure *mant = LOGAND(VARL(l->fr), UN(f->bits, c28x_fp_mant(f))); + RzILOpEffect *luf = SETG("luf", OR(VARG("luf"), VARL(l->ft))); + RzILOpEffect *lvf = SETG("lvf", OR(VARG("lvf"), overflow)); + return SEQ7(SETL(l->fr, F2BV(res)), SETL(l->fe, c28x_fp_exp(f, l->fr)), + SETL(l->fm, NON_ZERO(mant)), SETL(l->ft, tiny), luf, lvf, wr); +} + +/** + * \brief NF and ZF from the binary32 value in \p local; negative zero and + * denormals count as +0 (SPRUHS1C table 1-2). + */ +static RzILOpEffect *c28x_fp_nz(const C28xFloat *f, const char *local) { + RzILOpBool *zero = IS_ZERO(LOGAND(VARL(local), UN(f->bits, f->emax << f->man))); + RzILOpBool *neg = AND(MSB(VARL(local)), INV(DUP(zero))); + return SEQ2(SETG("zf", zero), SETG("nf", neg)); +} + +/** + * \brief The binary32 value in \p local with a denormal as +0 and NaN as + * infinity. + */ +static RzILOpPure *c28x_fp_flush(const C28xFloat *f, const char *local) { + RzILOpPure *mant = NON_ZERO(LOGAND(VARL(local), UN(f->bits, c28x_fp_mant(f)))); + RzILOpPure *tiny = AND(IS_ZERO(c28x_fp_exp(f, local)), mant); + RzILOpPure *nan = AND(EQ(c28x_fp_exp(f, local), UN(f->bits, f->emax)), DUP(mant)); + RzILOpPure *inf = LOGAND(VARL(local), UN(f->bits, c28x_fp_top(f))); + return ITE(tiny, UN(f->bits, 0), ITE(nan, inf, VARL(local))); +} + +static bool c28x_is_stf(const C28xOperand *o) { + return o->kind == C28X_OP_REG && o->reg == C28X_REG_STF; +} + +/** + * \brief NF, ZF, NI and ZI as MOV32 sets them from the word in \p local. + */ +static RzILOpEffect *c28x_fp_movflags(const C28xFloat *f, const char *local) { + RzILOpEffect *ni = SETG("ni", MSB(VARL(local))); + return SEQ3(c28x_fp_nz(f, local), ni, SETG("zi", IS_ZERO(VARL(local)))); +} + +/** + * \brief STF as a word. + */ +static RzILOpPure *c28x_stf_word(void) { + RzILOpPure *w = ITE(VARG("shdws"), UN(32, 0x80000000), UN(32, 0)); + for (size_t i = 0; i < RZ_ARRAY_SIZE(c28x_stf_bits); i++) { + if (c28x_stf_bits[i]) { + w = LOGOR(w, ITE(VARG(c28x_stf_bits[i]), UN(32, 1U << i), UN(32, 0))); + } + } + return w; +} + +/** + * \brief Load STF from the word in \p local; SHDWS keeps its value (SPRUHS1C + * table 1-2). + */ +static RzILOpEffect *c28x_stf_load(const char *local) { + RzILOpEffect *eff = NOP(); + for (size_t i = 0; i < RZ_ARRAY_SIZE(c28x_stf_bits); i++) { + if (c28x_stf_bits[i]) { + RzILOpBool *bit = NON_ZERO(LOGAND(VARL(local), UN(32, 1U << i))); + eff = SEQ2(eff, SETG(c28x_stf_bits[i], bit)); + } + } + return eff; +} + +/** + * \brief An FPU condition (SPRUHS1C table 1-7); NULL for reserved codes. + * + * The table prints LEQ as "ZF == 1 AND NF == 1", which no compare produces; + * it reads as OR, like the C28x LEQ. + */ +static RzILOpBool *c28x_fcond(ut32 cond) { + switch (cond) { + case 0: return INV(VARG("zf")); + case 1: return VARG("zf"); + case 2: return AND(INV(VARG("zf")), INV(VARG("nf"))); + case 3: return INV(VARG("nf")); + case 4: return VARG("nf"); + case 5: return OR(VARG("zf"), VARG("nf")); + case 10: return VARG("tf"); + case 11: return INV(VARG("tf")); + case 12: return VARG("luf"); + case 13: return VARG("lvf"); + case 14: + case 15: return IL_TRUE; + default: return NULL; + } +} + +/** + * \brief Run \p body with the latched address of mem32 operand \p m. + * + * mem32 is a 32-bit access, stepping pointers by two, even where the row + * renders it as loc16, as dis2000 does for the conditional MOV32 loads. + */ +static RzILOpEffect *c28x_with_mem32(const C28xOperand *m, RzILOpEffect *body) { + C28xOperand wide = *m; + wide.wide = true; + return c28x_with_ea(&wide, body); +} + +/** + * \brief The binary64 view of the float in \p local: exact for binary32. + */ +static RzILOpFloat *c28x_fp_widen(const C28xFloat *f, const char *local) { + if (f->bits == 64) { + return VARL(local); + } + return FCONVERT(RZ_FLOAT_IEEE754_BIN_64, RZ_FLOAT_RMODE_RNE, VARL(local)); +} + +/** + * \brief The FPU64 instructions, which compute in binary64 on whole registers. + */ +static const bool c28x_fpu64[] = { + [C28X_INS_ADDF64] = true, + [C28X_INS_SUBF64] = true, + [C28X_INS_MPYF64] = true, + [C28X_INS_MACF64] = true, + [C28X_INS_CMPF64] = true, + [C28X_INS_MAXF64] = true, + [C28X_INS_MINF64] = true, + [C28X_INS_NEGF64] = true, + [C28X_INS_ABSF64] = true, + [C28X_INS_FRACF64] = true, + [C28X_INS_MOV64] = true, +}; + +static const C28xFloat *c28x_fp_of(C28xInsnId id) { + return (size_t)id < RZ_ARRAY_SIZE(c28x_fpu64) && c28x_fpu64[id] ? &c28x_bin64 : &c28x_bin32; +} + +/** + * \brief ADDF32/64, SUBF32/64 or MPYF32/64 (\p id) of \p a and \p b into + * \p dst, as \p in, which reads the operands, and \p out, which writes the + * result, so parallel forms can read every operand before writing anything. + * + * binary32 overflow is past the largest finite value plus half an ulp when + * rounding to nearest and at 2^128 when truncating, which binary64 decides + * exactly. binary64 results have no wider format here: overflow is taken as + * the result rounded to nearest being infinite, which for truncation also + * counts results within half an ulp below 2^1024. + */ +static bool c28x_fp_arith(const C28xFpLocals *l, const C28xFloat *f, C28xInsnId id, + const C28xOperand *dst, RzILOpPure *a, RzILOpPure *b, RzILOpEffect **in, + RzILOpEffect **out) { + if (!a || !b) { + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); + return false; + } + const bool add = id == C28X_INS_ADDF32 || id == C28X_INS_ADDF64; + const bool sub = id == C28X_INS_SUBF32 || id == C28X_INS_SUBF64; + RzILOpFloat *res; + RzILOpFloat *x = c28x_fp_widen(f, l->fa); + RzILOpFloat *y = c28x_fp_widen(f, l->fb); + // binary32 results are also taken exactly in binary64, truncated, and binary64 + // ones rounded to nearest, where overflow gives infinity + RzFloatRMode wide_mode = f->bits == 32 ? RZ_FLOAT_RMODE_RTZ : RZ_FLOAT_RMODE_RNE; + RzILOpFloat *wide; + if (add) { + res = FADD_DYN_RMODE(c28x_fp_rnd(f), VARL(l->fa), VARL(l->fb)); + wide = FADD(wide_mode, x, y); + } else if (sub) { + res = FSUB_DYN_RMODE(c28x_fp_rnd(f), VARL(l->fa), VARL(l->fb)); + wide = FSUB(wide_mode, x, y); + } else { + res = FMUL_DYN_RMODE(c28x_fp_rnd(f), VARL(l->fa), VARL(l->fb)); + wide = FMUL(wide_mode, x, y); + } + RzILOpBool *finite = AND(IS_FINITE(VARL(l->fa)), IS_FINITE(VARL(l->fb))); + RzILOpBool *overflow; + if (f->bits == 32) { + RzILOpFloat *limit = ITE(VARG("rnd32"), F64(0x1p128 - 0x1p103), F64(0x1p128)); + overflow = AND(finite, INV(FORDER(FABS(VARL(l->fw)), limit))); + } else { + overflow = AND(finite, IS_FINF(VARL(l->fw))); + } + RzILOpEffect *o = c28x_fp_out(l, f, dst, res, !add && !sub, overflow); + if (!o) { + rz_il_op_pure_free(wide); + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); + return false; + } + *in = c28x_fp_operands(l, f, a, b); + *out = SEQ2(SETL(l->fw, wide), o); + return true; +} + +/** + * \brief The MOV32 half of a parallel form: MOV32 mem32,RaH, or MOV32 RaH,mem32 + * with its flags. + */ +static RzILOpEffect *c28x_fpu_par_mov32(const C28xOperand *first, const C28xOperand *second) { + if (c28x_is_mem(first)) { + RzILOpPure *v = c28x_fpu_read(second); + return v ? c28x_with_mem32(first, c28x_ea_store(v)) : NULL; + } + RzILOpEffect *wr = c28x_is_mem(second) ? c28x_fpu_write(first, VARL("mv")) : NULL; + if (!wr) { + return NULL; + } + RzILOpEffect *load = SETL("mv", c28x_ea_load(32)); + return c28x_with_mem32(second, SEQ3(load, wr, c28x_fp_movflags(&c28x_bin32, "mv"))); +} + +/** + * \brief ADDF32, SUBF32 and MPYF32 with register and #16FHi operands, with a + * parallel MOV32, and MPYF32 with a parallel ADDF32 or SUBF32. + * + * Parallel halves read their operands before either writes. + */ +static RzILOpEffect *c28x_fpu_arith(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + const C28xOperand *op = insn->ops; + const bool par = insn->nops > 3 && op[3].kind == C28X_OP_PAR; + if (insn->nops != 3 && !par) { + return NULL; + } + RzILOpEffect *in; + RzILOpEffect *out; + RzILOpPure *a = c28x_fp_operand(f, &op[1]); + RzILOpPure *b = c28x_fp_operand(f, &op[2]); + if (!c28x_fp_arith(&c28x_fp_one, f, insn->id, &op[0], a, b, &in, &out)) { + return NULL; + } + if (!par) { + return SEQ2(in, out); + } + if (op[3].imm == C28X_INS_MOV32 && insn->nops == 6) { + RzILOpEffect *mv = c28x_fpu_par_mov32(&op[4], &op[5]); + if (mv) { + return SEQ3(in, mv, out); + } + } else if (insn->nops == 7) { + RzILOpEffect *in2; + RzILOpEffect *out2; + RzILOpPure *e = c28x_fp_read(f, &op[5]); + RzILOpPure *g = c28x_fp_read(f, &op[6]); + const C28xInsnId id = (C28xInsnId)op[3].imm; + if (c28x_fp_arith(&c28x_fp_two, f, id, &op[4], e, g, &in2, &out2)) { + return SEQ4(in, in2, out, out2); + } + } + rz_il_op_effect_free(in); + rz_il_op_effect_free(out); + return NULL; +} + +/** + * \brief MACF32 R3H,R2H,RdH,ReH,RfH || MOV32 RaH,mem32 (or R7H,R6H), its + * MACF64 counterpart on whole registers, and MACF32 R7H,R3H,mem32,*XAR7++. + * + * The first adds the previous product, R3H += R2H, while RdH = ReH * RfH; + * the second on its own is R3H += R2H with R2H = [mem32] * [XAR7++]. Under + * RPT the second alternates with R7H and R6H, which one instruction's IL + * can't show. + */ +static RzILOpEffect *c28x_fpu_macf32(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + const bool single = insn->id == C28X_INS_MACF32 && insn->nops == 4; + const C28xOperand *op = insn->ops; + const C28xFpLocals *l1 = &c28x_fp_one; + const C28xFpLocals *l2 = &c28x_fp_two; + RzILOpEffect *in = NULL; + RzILOpEffect *out = NULL; + RzILOpEffect *in2 = NULL; + RzILOpEffect *out2 = NULL; + if (insn->nops == 8 && op[5].kind == C28X_OP_PAR) { + RzILOpPure *acc = c28x_fp_read(f, &op[0]); + RzILOpPure *prod = c28x_fp_read(f, &op[1]); + RzILOpEffect *mv = NULL; + if (c28x_fp_arith(l1, f, C28X_INS_ADDF32, &op[0], acc, prod, &in, &out)) { + RzILOpPure *e = c28x_fp_read(f, &op[3]); + RzILOpPure *g = c28x_fp_read(f, &op[4]); + if (c28x_fp_arith(l2, f, C28X_INS_MPYF32, &op[2], e, g, &in2, &out2)) { + mv = c28x_fpu_par_mov32(&op[6], &op[7]); + } + } + if (mv) { + return SEQ5(in, in2, mv, out, out2); + } + } else if (single && op[0].reg == C28X_REG_R7H && op[1].reg == C28X_REG_R3H && + c28x_is_mem(&op[2]) && c28x_is_mem(&op[3])) { + const C28xOperand r2 = { .kind = C28X_OP_REG, .reg = C28X_REG_R0H + 2 }; + RzILOpPure *acc = c28x_fpu_read(&op[1]); + RzILOpPure *prod = c28x_fpu_read(&r2); + RzILOpPure *ma = VARL("ma"); + RzILOpPure *mb = VARL("mb"); + if (!c28x_fp_arith(l1, f, C28X_INS_ADDF32, &op[1], acc, prod, &in, &out)) { + rz_il_op_pure_free(ma); + rz_il_op_pure_free(mb); + } else if (c28x_fp_arith(l2, f, C28X_INS_MPYF32, &r2, ma, mb, &in2, &out2)) { + RzILOpEffect *b = c28x_with_mem32(&op[3], SETL("mb", c28x_ea_load(32))); + RzILOpEffect *a = SETL("ma", c28x_ea_load(32)); + RzILOpEffect *loads = c28x_with_mem32(&op[2], SEQ2(a, b)); + return SEQ5(in, loads, in2, out, out2); + } + } + rz_il_op_effect_free(in); + rz_il_op_effect_free(out); + rz_il_op_effect_free(in2); + rz_il_op_effect_free(out2); + return NULL; +} + +/** \brief CMPF32 and CMPF64: ZF for equal, NF for less, on the FPU views of both. */ +static RzILOpEffect *c28x_fpu_cmpf32(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + if (insn->nops != 2) { + return NULL; + } + RzILOpPure *a = c28x_fp_operand(f, &insn->ops[0]); + RzILOpPure *b = c28x_fp_operand(f, &insn->ops[1]); + if (!a || !b) { + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); + return NULL; + } + RzILOpBool *lt = FORDER(VARL("fa"), VARL("fb")); + RzILOpBool *eq = AND(INV(DUP(lt)), INV(FORDER(VARL("fb"), VARL("fa")))); + return SEQ3(c28x_fp_operands(&c28x_fp_one, f, a, b), SETG("zf", eq), SETG("nf", lt)); +} + +/** + * \brief MOV32 ACC/P/XT/XARn,RaH: only ACC as destination sets N and Z. + */ +static RzILOpEffect *c28x_fpu_to_cpu(const C28xOperand *dst, const C28xOperand *src) { + const char *reg = c28x_reg32(dst); + RzILOpPure *v = reg ? c28x_fpu_read(src) : NULL; + if (!v) { + return NULL; + } + RzILOpEffect *set = SETG(reg, v); + if (dst->reg != C28X_REG_ACC) { + return set; + } + return SEQ3(set, SETG("n", MSB(VARG("acc"))), SETG("z", IS_ZERO(VARG("acc")))); +} + +/** + * \brief The MOV32 forms: RaH,mem32{,CNDF}, RaH,RbH{,CNDF}, mem32,RaH and + * the moves between CPU and FPU registers. + * + * Only UNCF, the default condition, sets NF/ZF from the float and NI/ZI from + * the integer; negative zero and denormals count as +0 for NF and ZF. MOV32 + * RaH,RbL and RaL,RbH, which dis2000 decodes but SPRUHS1C doesn't document, + * stay unlifted: MOV32's flags depend on the form. + */ +static RzILOpEffect *c28x_fpu_mov32(const C28xInsn *insn) { + bool high; + const C28xOperand *dst = &insn->ops[0]; + const C28xOperand *src = &insn->ops[1]; + if (insn->nops == 2 && c28x_fpu_name(src, &high)) { + if (c28x_is_mem(dst)) { + return c28x_with_mem32(dst, c28x_ea_store(c28x_fpu_read(src))); + } + return c28x_fpu_to_cpu(dst, src); + } + if (insn->nops == 2 && c28x_fpu_name(dst, &high)) { + if (c28x_is_mem(src)) { + return c28x_with_mem32(src, c28x_fpu_write(dst, c28x_ea_load(32))); + } + const char *reg = c28x_reg32(src); + return reg ? c28x_fpu_write(dst, VARG(reg)) : NULL; + } + if (insn->nops == 2 && c28x_is_stf(src) && c28x_is_mem(dst)) { + return c28x_with_mem32(dst, c28x_ea_store(c28x_stf_word())); + } + if (insn->nops == 2 && c28x_is_stf(dst) && c28x_is_mem(src)) { + RzILOpEffect *load = SETL("sw", c28x_ea_load(32)); + return c28x_with_mem32(src, SEQ2(load, c28x_stf_load("sw"))); + } + if (insn->nops != 3 || insn->ops[2].kind != C28X_OP_FCOND || !c28x_fpu_name(dst, &high)) { + return NULL; + } + const ut32 cond = (ut32)insn->ops[2].imm; + RzILOpBool *take = c28x_fcond(cond); + if (!take) { + return NULL; + } + RzILOpEffect *eff = c28x_fpu_write(dst, VARL("mv")); + if (cond == 15) { + eff = SEQ2(eff, c28x_fp_movflags(&c28x_bin32, "mv")); + } + eff = BRANCH(take, eff, NOP()); + if (c28x_is_mem(src)) { + return c28x_with_mem32(src, SEQ2(SETL("mv", c28x_ea_load(32)), eff)); + } + RzILOpPure *v = c28x_fpu_read(src); + if (!v) { + rz_il_op_effect_free(eff); + return NULL; + } + return SEQ2(SETL("mv", v), eff); +} + +/** + * \brief A conversion between an FPU float and an integer: the float's format, + * the integer's width and signedness, and whether it rounds to nearest (the + * R forms) rather than truncating. + */ +typedef struct { + const C28xFloat *fmt; + ut8 ibits; + bool sgn; + bool round; +} C28xFpuConv; + +static const C28xFpuConv c28x_fpu_convs[] = { + [C28X_INS_I32TOF32] = { &c28x_bin32, 32, true, false }, + [C28X_INS_UI32TOF32] = { &c28x_bin32, 32, false, false }, + [C28X_INS_I16TOF32] = { &c28x_bin32, 16, true, false }, + [C28X_INS_UI16TOF32] = { &c28x_bin32, 16, false, false }, + [C28X_INS_I32TOF64] = { &c28x_bin64, 32, true, false }, + [C28X_INS_UI32TOF64] = { &c28x_bin64, 32, false, false }, + [C28X_INS_I64TOF64] = { &c28x_bin64, 64, true, false }, + [C28X_INS_UI64TOF64] = { &c28x_bin64, 64, false, false }, + [C28X_INS_F32TOI32] = { &c28x_bin32, 32, true, false }, + [C28X_INS_F32TOUI32] = { &c28x_bin32, 32, false, false }, + [C28X_INS_F32TOI16] = { &c28x_bin32, 16, true, false }, + [C28X_INS_F32TOI16R] = { &c28x_bin32, 16, true, true }, + [C28X_INS_F32TOUI16] = { &c28x_bin32, 16, false, false }, + [C28X_INS_F32TOUI16R] = { &c28x_bin32, 16, false, true }, + [C28X_INS_F64TOI32] = { &c28x_bin64, 32, true, false }, + [C28X_INS_F64TOUI32] = { &c28x_bin64, 32, false, false }, + [C28X_INS_F64TOI64] = { &c28x_bin64, 64, true, false }, + [C28X_INS_F64TOUI64] = { &c28x_bin64, 64, false, false }, +}; + +static const C28xFpuConv *c28x_fpu_conv(const C28xInsn *insn) { + if ((size_t)insn->id >= RZ_ARRAY_SIZE(c28x_fpu_convs) || !c28x_fpu_convs[insn->id].fmt) { + return NULL; + } + return insn->nops == 2 ? &c28x_fpu_convs[insn->id] : NULL; +} + +/** + * \brief Latch the \p c->ibits integer in \p src as "xa": the low half of RbH + * or all of it, all of Rb, or memory, whose row renders mem16 as dis2000 does. + */ +static RzILOpEffect *c28x_fpu_int_in(const C28xFpuConv *c, const C28xOperand *src, + RzILOpEffect *body) { + if (c28x_is_mem(src)) { + RzILOpEffect *load = SETL("xa", c28x_ea_load(c->ibits == 16 ? 16 : 32)); + return c28x_with_mem(src, c->ibits != 16, SEQ2(load, body)); + } + RzILOpPure *v = c->ibits == 64 ? c28x_fp_read(&c28x_bin64, src) : c28x_fpu_read(src); + if (!v) { + rz_il_op_effect_free(body); + return NULL; + } + return SEQ2(SETL("xa", c->ibits == 16 ? UNSIGNED(16, v) : v), body); +} + +/** + * \brief The integer-to-float conversions, from a register or memory. + * + * SPRUHS1C documents RND32 and RND64 for multiplication, addition and + * subtraction only; conversions round to nearest even. + */ +static RzILOpEffect *c28x_fpu_itof(const C28xInsn *insn) { + const C28xFpuConv *c = c28x_fpu_conv(insn); + if (!c) { + return NULL; + } + RzILOpFloat *f; + if (c->sgn) { + f = SINT2F(c->fmt->format, RZ_FLOAT_RMODE_RNE, VARL("xa")); + } else { + f = INT2F(c->fmt->format, RZ_FLOAT_RMODE_RNE, VARL("xa")); + } + RzILOpEffect *wr = c28x_fp_write(c->fmt, &insn->ops[0], F2BV(f)); + return wr ? c28x_fpu_int_in(c, &insn->ops[1], wr) : NULL; +} + +/** + * \brief The float-to-integer conversions: the R forms round to nearest even, + * the others truncate, as TI's compiler relies on when it casts with them. + * + * SPRUHS1C documents saturation for F32TOUI16(R) only; the others saturate the + * same way here. The range's bounds are converted toward zero, since 2^31 - 1, + * 2^32 - 1, 2^63 - 1 and 2^64 - 1 needn't be representable. 16-bit results + * fill RaH by sign or zero extension. + */ +static RzILOpEffect *c28x_fpu_ftoi(const C28xInsn *insn) { + const C28xFpuConv *c = c28x_fpu_conv(insn); + RzILOpPure *src = c ? c28x_fp_read(c->fmt, &insn->ops[1]) : NULL; + if (!src) { + return NULL; + } + const ut32 bits = c->ibits; + const ut64 umax = bits == 64 ? UT64_MAX : (1ULL << bits) - 1; + const ut64 hi_bits = c->sgn ? umax >> 1 : umax; + const ut64 lo_bits = c->sgn ? hi_bits + 1 : 0; + RzILOpFloat *hi_f; + RzILOpFloat *lo_f; + RzILOpPure *in_range; + if (c->sgn) { + hi_f = SINT2F(c->fmt->format, RZ_FLOAT_RMODE_RTZ, UN(bits, hi_bits)); + lo_f = SINT2F(c->fmt->format, RZ_FLOAT_RMODE_RTZ, UN(bits, lo_bits)); + in_range = F2SINT(bits, RZ_FLOAT_RMODE_RTZ, VARL("fr")); + } else { + hi_f = INT2F(c->fmt->format, RZ_FLOAT_RMODE_RTZ, UN(bits, hi_bits)); + lo_f = INT2F(c->fmt->format, RZ_FLOAT_RMODE_RTZ, UN(bits, lo_bits)); + in_range = F2INT(bits, RZ_FLOAT_RMODE_RTZ, VARL("fr")); + } + RzILOpBool *over = FORDER(hi_f, VARL("fr")); + RzILOpBool *under = FORDER(VARL("fr"), lo_f); + RzILOpPure *v = ITE(over, UN(bits, hi_bits), ITE(under, UN(bits, lo_bits), in_range)); + RzILOpEffect *wr; + if (bits == 64) { + wr = c28x_fp_write(&c28x_bin64, &insn->ops[0], v); + } else { + if (bits == 16) { + v = c->sgn ? SIGNED(32, v) : UNSIGNED(32, v); + } + wr = c28x_fpu_write(&insn->ops[0], v); + } + if (!wr) { + rz_il_op_pure_free(src); + return NULL; + } + RzFloatRMode mode = c->round ? RZ_FLOAT_RMODE_RNE : RZ_FLOAT_RMODE_RTZ; + RzILOpEffect *in = SEQ2(SETL("xa", src), SETL("fa", c28x_fp_in(c->fmt, "xa"))); + return SEQ3(in, SETL("fr", FROUND(mode, VARL("fa"))), wr); +} + +/** + * \brief F32TOF64 Ra,RbH/mem32 and F32DTOF64 Ra,mem32 widen exactly and set + * NF/ZF from the double; F32DTOF64 also copies mem32 two words up. F64TOF32 + * RaH,Rb rounds as RND32 says, flushes a denormal to +0 and sets no flags. + */ +static RzILOpEffect *c28x_fpu_ftof(const C28xInsn *insn) { + if (insn->nops != 2) { + return NULL; + } + const C28xOperand *dst = &insn->ops[0]; + const C28xOperand *src = &insn->ops[1]; + if (insn->id == C28X_INS_F64TOF32) { + RzILOpPure *v = c28x_fp_read(&c28x_bin64, src); + RzILOpEffect *wr = v ? c28x_fpu_write(dst, c28x_fp_flush(&c28x_bin32, "xr")) : NULL; + if (!wr) { + rz_il_op_pure_free(v); + return NULL; + } + RzILOpBitVector *mode = c28x_fp_rnd(&c28x_bin32); + RzILOpFloat *n = FCONVERT_DYN_RMODE(RZ_FLOAT_IEEE754_BIN_32, mode, VARL("fa")); + RzILOpEffect *in = SEQ2(SETL("xa", v), SETL("fa", c28x_fp_in(&c28x_bin64, "xa"))); + return SEQ3(in, SETL("xr", F2BV(n)), wr); + } + RzILOpFloat *narrow = c28x_fp_in(&c28x_bin32, "xa"); + RzILOpFloat *w = FCONVERT(RZ_FLOAT_IEEE754_BIN_64, RZ_FLOAT_RMODE_RNE, narrow); + RzILOpEffect *wr = c28x_fp_write(&c28x_bin64, dst, VARL("xr")); + if (!wr) { + rz_il_op_pure_free(w); + return NULL; + } + RzILOpEffect *body = SEQ3(SETL("xr", F2BV(w)), wr, c28x_fp_nz(&c28x_bin64, "xr")); + if (c28x_is_mem(src)) { + if (insn->id == C28X_INS_F32DTOF64) { + RzILOpPure *above = c28x_byte(ADD(VARL(C28X_EA_LOCAL), UN(32, 2))); + body = SEQ2(STOREW(above, VARL("xa")), body); + } + return c28x_with_mem32(src, SEQ2(SETL("xa", c28x_ea_load(32)), body)); + } + RzILOpPure *v = insn->id == C28X_INS_F32TOF64 ? c28x_fpu_read(src) : NULL; + if (!v) { + rz_il_op_effect_free(body); + return NULL; + } + return SEQ2(SETL("xa", v), body); +} + +/** + * \brief FRACF32 and FRACF64: Rb less its integer part, which is exact; affect + * no flags. + */ +static RzILOpEffect *c28x_fpu_fracf32(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + RzILOpPure *src = insn->nops == 2 ? c28x_fp_read(f, &insn->ops[1]) : NULL; + if (!src) { + return NULL; + } + RzILOpFloat *ip = FROUND(RZ_FLOAT_RMODE_RTZ, VARL("fa")); + RzILOpPure *frac = F2BV(FSUB(RZ_FLOAT_RMODE_RNE, VARL("fa"), ip)); + RzILOpEffect *wr = c28x_fp_write(f, &insn->ops[0], c28x_fp_flush(f, "xr")); + if (!wr) { + rz_il_op_pure_free(src); + rz_il_op_pure_free(frac); + return NULL; + } + return SEQ4(SETL("xa", src), SETL("fa", c28x_fp_in(f, "xa")), SETL("xr", frac), wr); +} + +/** + * \brief MOVIZ Ra,#16FHiHex, MOVXI RaH/RaL,#16FLoHex, MOVIX RaL,#16I and ZERO Ra. + * + * SPRUHS1C describes MOVIZ and ZERO on RaH alone, but dis2000 names all of Ra + * and TI's FPU64 compiler returns the double 0.0 as ZERO R0 and 2.5 as MOVIZ + * R0,#0x4004 alone: both clear the rest of the 64-bit register. + */ +static RzILOpEffect *c28x_fpu_movi(const C28xInsn *insn) { + const C28xOperand *dst = &insn->ops[0]; + if (insn->id == C28X_INS_ZERO) { + const char *n = c28x_fpu_name64(dst); + return n ? SETG(n, UN(64, 0)) : NULL; + } + if (insn->nops != 2 || insn->ops[1].kind != C28X_OP_IMM) { + return NULL; + } + const ut64 imm = insn->ops[1].imm & 0xffff; + if (insn->id == C28X_INS_MOVIZ) { + const char *n = c28x_fpu_name64(dst); + return n ? SETG(n, UN(64, imm << 48)) : NULL; + } + RzILOpPure *cur = c28x_fpu_read(dst); + if (!cur) { + return NULL; + } + RzILOpPure *v; + if (insn->id == C28X_INS_MOVXI) { + v = LOGOR(LOGAND(cur, UN(32, 0xffff0000)), UN(32, imm)); + } else { + v = LOGOR(LOGAND(cur, UN(32, 0xffff)), UN(32, imm << 16)); + } + return c28x_fpu_write(dst, v); +} + +/** + * \brief ZEROA: SPRUHS1C lists R0H-R7H, as its ZERO page lists only RaH, + * which TI's compiler shows clears all of Ra; ZEROA clears all of each alike. + */ +static RzILOpEffect *c28x_fpu_zeroa(RZ_UNUSED const C28xInsn *insn) { + RzILOpEffect *eff = SETG(c28x_fpu_regs[0], UN(64, 0)); + for (size_t i = 1; i < RZ_ARRAY_SIZE(c28x_fpu_regs); i++) { + eff = SEQ2(eff, SETG(c28x_fpu_regs[i], UN(64, 0))); + } + return eff; +} + +/** + * \brief NEGF32/NEGF64 Ra,Rb{,CNDF} and ABSF32/ABSF64 Ra,Rb: only the sign bit + * changes, and NF/ZF follow the stored value; NEGF sets them only for UNCF, + * its default condition (SPRUHS1C's CNDF note). + */ +static RzILOpEffect *c28x_fpu_negabs(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + RzILOpPure *v = insn->nops >= 2 ? c28x_fp_read(f, &insn->ops[1]) : NULL; + if (!v) { + return NULL; + } + RzILOpPure *res; + bool flags = true; + if (insn->id == C28X_INS_ABSF32 || insn->id == C28X_INS_ABSF64) { + res = LOGAND(VARL("xa"), UN(f->bits, c28x_fp_mask(f) >> 1)); + } else { + const ut32 cond = insn->nops == 3 ? (ut32)insn->ops[2].imm : 0; + RzILOpBool *take = insn->nops == 3 ? c28x_fcond(cond) : NULL; + if (!take) { + rz_il_op_pure_free(v); + return NULL; + } + res = ITE(take, LOGXOR(VARL("xa"), UN(f->bits, 1ULL << (f->bits - 1))), VARL("xa")); + flags = cond == 15; + } + RzILOpEffect *wr = c28x_fp_write(f, &insn->ops[0], VARL("xr")); + if (!wr) { + rz_il_op_pure_free(v); + rz_il_op_pure_free(res); + return NULL; + } + if (!flags) { + return SEQ3(SETL("xa", v), SETL("xr", res), wr); + } + return SEQ4(SETL("xa", v), SETL("xr", res), wr, c28x_fp_nz(f, "xr")); +} + +/** + * \brief MAXF32/MAXF64 and MINF32/MINF64, on a register or #16FHi, and with the + * parallel MOV32/MOV64 that moves only when Ra is replaced. + * + * They compare like CMPF32 and set ZF/NF on RaH against the other operand; a + * NaN result becomes infinity and a denormal one +0. + */ +static RzILOpEffect *c28x_fpu_maxmin(const C28xInsn *insn) { + const C28xFloat *f = c28x_fp_of(insn->id); + const bool par = insn->nops == 5 && insn->ops[2].kind == C28X_OP_PAR; + if (insn->nops != 2 && !par) { + return NULL; + } + RzILOpPure *a = c28x_fp_read(f, &insn->ops[0]); + RzILOpPure *b = c28x_fp_operand(f, &insn->ops[1]); + RzILOpPure *d = par ? c28x_fp_read(f, &insn->ops[4]) : NULL; + RzILOpEffect *mv = par ? c28x_fp_write(f, &insn->ops[3], VARL("pd")) : NULL; + RzILOpEffect *wr = c28x_fp_write(f, &insn->ops[0], c28x_fp_flush(f, "xr")); + if (!a || !b || !wr || (par && (!d || !mv))) { + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); + rz_il_op_pure_free(d); + rz_il_op_effect_free(mv); + rz_il_op_effect_free(wr); + return NULL; + } + RzILOpBool *lt = FORDER(VARL("fa"), VARL("fb")); + RzILOpBool *gt = FORDER(VARL("fb"), VARL("fa")); + const bool max = insn->id == C28X_INS_MAXF32 || insn->id == C28X_INS_MAXF64; + RzILOpBool *take = max ? DUP(lt) : DUP(gt); + RzILOpBool *below = FORDER(VARL("fa"), VARL("fb")); + RzILOpEffect *flags = SEQ2(SETG("zf", AND(INV(lt), INV(gt))), SETG("nf", below)); + RzILOpEffect *set = SEQ2(SETL("xr", ITE(VARL("mt"), VARL("xb"), VARL("xa"))), wr); + RzILOpEffect *in = c28x_fp_operands(&c28x_fp_one, f, a, b); + RzILOpEffect *eff = SEQ4(in, SETL("mt", take), flags, set); + if (par) { + eff = SEQ3(SETL("pd", d), eff, BRANCH(VARL("mt"), mv, NOP())); + } + return eff; +} + +/** + * \brief SETFLG FLAG,VALUE: the flags with a FLAG bit take their VALUE bit. + */ +static RzILOpEffect *c28x_fpu_setflg_op(const C28xOperand *o) { + RzILOpEffect *eff = NOP(); + for (size_t i = 0; i < RZ_ARRAY_SIZE(c28x_stf_bits); i++) { + if (c28x_stf_bits[i] && (o->mask >> i) & 1) { + RzILOpBool *v = (o->imm >> i) & 1 ? IL_TRUE : IL_FALSE; + eff = SEQ2(eff, SETG(c28x_stf_bits[i], v)); + } + } + return eff; +} + +static RzILOpEffect *c28x_fpu_setflg(const C28xInsn *insn) { + if (insn->nops != 1 || insn->ops[0].kind != C28X_OP_FSETFLG) { + return NULL; + } + return c28x_fpu_setflg_op(&insn->ops[0]); +} + +/** + * \brief SAVE FLAG,VALUE copies R0-R7 and STF to their shadows, then works as + * SETFLG and sets SHDWS. + * + * SPRUHS1C names R0H-R7H, but TI's FPU64 compiler brackets code that + * clobbers R0L and R1L with SAVE and RESTORE alone, so the shadows hold all + * of each register. + */ +static RzILOpEffect *c28x_fpu_save(const C28xInsn *insn) { + if (insn->nops != 1 || insn->ops[0].kind != C28X_OP_FSETFLG) { + return NULL; + } + RzILOpEffect *eff = SETG("stfs", c28x_stf_word()); + for (size_t i = 0; i < RZ_ARRAY_SIZE(c28x_fpu_regs); i++) { + eff = SEQ2(eff, SETG(c28x_fpu_shadows[i], VARG(c28x_fpu_regs[i]))); + } + return SEQ3(eff, c28x_fpu_setflg_op(&insn->ops[0]), SETG("shdws", IL_TRUE)); +} + +/** + * \brief RESTORE: R0-R7 and STF from their shadows, SHDWS cleared. + */ +static RzILOpEffect *c28x_fpu_restore(RZ_UNUSED const C28xInsn *insn) { + RzILOpEffect *eff = SEQ2(SETL("sw", VARG("stfs")), c28x_stf_load("sw")); + for (size_t i = 0; i < RZ_ARRAY_SIZE(c28x_fpu_regs); i++) { + eff = SEQ2(eff, SETG(c28x_fpu_regs[i], VARG(c28x_fpu_shadows[i]))); + } + return SEQ2(eff, SETG("shdws", IL_FALSE)); +} + +/** + * \brief The flags a MOVST0 FLAG bit selects: SPRUHS1C shows only the field's + * width. + */ +enum { + C28X_MOVST0_LVF = 1 << 0, + C28X_MOVST0_LUF = 1 << 1, + C28X_MOVST0_NF = 1 << 2, + C28X_MOVST0_NI = 1 << 3, + C28X_MOVST0_ZF = 1 << 4, + C28X_MOVST0_ZI = 1 << 5, + C28X_MOVST0_TF = 1 << 7, +}; + +/** + * \brief OR of the flags \p a and \p b among those \p f selects. + */ +static RzILOpBool *c28x_movst0_any(ut32 f, ut32 sel_a, const char *a, ut32 sel_b, const char *b) { + RzILOpBool *va = f & sel_a ? VARG(a) : IL_FALSE; + return OR(va, f & sel_b ? VARG(b) : IL_FALSE); +} + +/** + * \brief MOVST0 FLAG copies selected STF flags into ST0 and clears a copied + * LVF or LUF (SPRUHS1C table 1-2). + * + * FLAG orders its bits as TI's assembler encodes them: LVF, LUF, NF, NI, ZF, + * ZI, CI and TF. SPRUHS1C documents no CI flag, so that bit changes nothing. + */ +static RzILOpEffect *c28x_fpu_movst0(const C28xInsn *insn) { + if (insn->nops != 1 || insn->ops[0].kind != C28X_OP_FFLAGS) { + return NULL; + } + const ut32 f = (ut32)insn->ops[0].imm; + RzILOpEffect *eff = NOP(); + if (f & (C28X_MOVST0_LVF | C28X_MOVST0_LUF)) { + RzILOpBool *v = c28x_movst0_any(f, C28X_MOVST0_LVF, "lvf", C28X_MOVST0_LUF, "luf"); + eff = SEQ2(eff, SETG("v", v)); + if (f & C28X_MOVST0_LVF) { + eff = SEQ2(eff, SETG("lvf", IL_FALSE)); + } + if (f & C28X_MOVST0_LUF) { + eff = SEQ2(eff, SETG("luf", IL_FALSE)); + } + } + if (f & (C28X_MOVST0_NF | C28X_MOVST0_NI)) { + RzILOpBool *n = c28x_movst0_any(f, C28X_MOVST0_NF, "nf", C28X_MOVST0_NI, "ni"); + eff = SEQ2(eff, SETG("n", n)); + } + if (f & (C28X_MOVST0_ZF | C28X_MOVST0_ZI)) { + RzILOpBool *z = c28x_movst0_any(f, C28X_MOVST0_ZF, "zf", C28X_MOVST0_ZI, "zi"); + eff = SEQ2(eff, SETG("z", z)); + } + if (f & C28X_MOVST0_TF) { + eff = SEQ3(eff, SETG("c", VARG("tf")), SETG("tc", VARG("tf"))); + } + return eff; +} + +/** + * \brief TESTTF CNDF: TF becomes the condition. + */ +static RzILOpEffect *c28x_fpu_testtf(const C28xInsn *insn) { + RzILOpBool *c = insn->nops == 1 ? c28x_fcond((ut32)insn->ops[0].imm) : NULL; + return c ? SETG("tf", c) : NULL; +} + +/** + * \brief SWAPF Ra,Rb{,CNDF}: dis2000 names whole registers, and the swap moves + * them whole. + */ +static RzILOpEffect *c28x_fpu_swapf(const C28xInsn *insn) { + const char *a = insn->nops == 3 ? c28x_fpu_name64(&insn->ops[0]) : NULL; + const char *b = a ? c28x_fpu_name64(&insn->ops[1]) : NULL; + RzILOpBool *c = b ? c28x_fcond((ut32)insn->ops[2].imm) : NULL; + if (!c) { + return NULL; + } + return BRANCH(c, SEQ3(SETL("sa", VARG(a)), SETG(a, VARG(b)), SETG(b, VARL("sa"))), NOP()); +} + +/** + * \brief MOV16 mem16,RaH stores RaH[15:0]. + */ +static RzILOpEffect *c28x_fpu_mov16(const C28xInsn *insn) { + if (insn->nops != 2 || !c28x_is_mem(&insn->ops[0])) { + return NULL; + } + RzILOpPure *v = c28x_fpu_read(&insn->ops[1]); + return v ? c28x_with_mem(&insn->ops[0], false, c28x_ea_store(UNSIGNED(16, v))) : NULL; +} + +/** + * \brief MOVD32 and MOVDD32 RaH,mem32 load like MOV32 and copy the value two + * (MOVD32) or four (MOVDD32) words up, for delay lines. + * + * The MOVDD32 RaL page repeats the RaH form's description and contradicts + * its own flag table, so that form stays unlifted. + */ +static RzILOpEffect *c28x_fpu_movd32(const C28xInsn *insn) { + bool high; + const C28xOperand *dst = &insn->ops[0]; + const C28xOperand *src = &insn->ops[1]; + if (insn->nops != 2 || !c28x_fpu_name(dst, &high) || !high || !c28x_is_mem(src)) { + return NULL; + } + const ut32 up = insn->id == C28X_INS_MOVD32 ? 2 : 4; + RzILOpPure *above = c28x_byte(ADD(VARL(C28X_EA_LOCAL), UN(32, up))); + RzILOpEffect *body = SEQ4(SETL("mv", c28x_ea_load(32)), c28x_fpu_write(dst, VARL("mv")), + STOREW(above, VARL("mv")), c28x_fp_movflags(&c28x_bin32, "mv")); + return c28x_with_mem32(src, body); +} + +/** + * \brief PUSH RB and POP RB move RB as MOVL *SP++ and MOVL *--SP would. + */ +static RzILOpEffect *c28x_fpu_rb(const C28xInsn *insn) { + const C28xOperand *o = &insn->ops[0]; + if (insn->nops != 1 || o->kind != C28X_OP_REG || o->reg != C28X_REG_RB) { + return NULL; + } + const bool push = insn->id == C28X_INS_PUSH; + C28xOperand sp = { .kind = C28X_OP_MEM, .wide = true }; + sp.mode = push ? C28X_AM_SP_POSTINC : C28X_AM_SP_PREDEC; + if (push) { + return c28x_with_ea(&sp, c28x_ea_store(VARG("rb"))); + } + return c28x_with_ea(&sp, SETG("rb", c28x_ea_load(32))); +} + +/* + * TMU (SPRUHS1C chapter 7): operands follow the FPU's rules, results are never + * denormal, NaN or negative zero, and RND32 is ignored. SPRUHS1C calls the + * TMU's rounding inherent in its implementation; results here are the exact + * values rounded to nearest, which hardware may differ from in the last bit. + */ + +static RzILOpFloat *c28x_f64_of(const char *local) { + return FCONVERT(RZ_FLOAT_IEEE754_BIN_64, RZ_FLOAT_RMODE_RNE, VARL(local)); +} + +/** + * \brief The infinity of the sign \p neg, as bits. + */ +static RzILOpPure *c28x_f32_inf(RzILOpBool *neg) { + return ITE(neg, UN(32, 0xff800000), UN(32, 0x7f800000)); +} + +/** + * \brief DIVF32 RaH,RbH,RcH with SPRUHS1C's boundary table: 0/0 is 0 with LVF, + * x/Inf is 0 with LUF (Inf/Inf Inf with LUF), Inf/y and x/0 are Inf with LVF. + * + * Otherwise the TMU tests the exact quotient's exponent: at 2^128 and above + * it gives Inf with LVF, below 2^-126 +0 with LUF. A binary64 quotient holds + * that exponent. + */ +static RzILOpEffect *c28x_tmu_divf32(const C28xInsn *insn) { + if (insn->nops != 3) { + return NULL; + } + RzILOpPure *a = c28x_fpu_read(&insn->ops[1]); + RzILOpPure *b = c28x_fpu_read(&insn->ops[2]); + RzILOpEffect *wr = c28x_fpu_write(&insn->ops[0], VARL("dv")); + if (!a || !b || !wr) { + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); + rz_il_op_effect_free(wr); + return NULL; + } + // za/ia: the dividend is zero/infinite, zb/ib: the divisor is; + // na: the dividend is neither + RzILOpEffect *cls = SEQ5(SETL("za", IS_FZERO(VARL("fa"))), SETL("zb", IS_FZERO(VARL("fb"))), + SETL("ia", IS_FINF(VARL("fa"))), SETL("ib", IS_FINF(VARL("fb"))), + SETL("na", AND(INV(VARL("za")), INV(VARL("ia"))))); + RzILOpBool *finite = AND(VARL("na"), AND(INV(VARL("zb")), INV(VARL("ib")))); + RzILOpFloat *q = FDIV(RZ_FLOAT_RMODE_RNE, c28x_f64_of("fa"), c28x_f64_of("fb")); + RzILOpBool *ov = AND(VARL("fin"), INV(FORDER(FABS(VARL("dq")), F64(0x1p128)))); + RzILOpBool *un = AND(VARL("fin"), FORDER(FABS(VARL("dq")), F64(0x1p-126))); + RzILOpEffect *quot = SEQ2(SETL("fin", finite), SETL("dq", q)); + RzILOpEffect *range = SEQ3(quot, SETL("dov", ov), SETL("dun", un)); + RzILOpBool *neg = XOR(IS_FNEG(VARL("fa")), IS_FNEG(VARL("fb"))); + RzILOpPure *q32 = F2BV(FDIV(RZ_FLOAT_RMODE_RNE, VARL("fa"), VARL("fb"))); + RzILOpPure *normal = ITE(VARL("dun"), UN(32, 0), ITE(VARL("dov"), c28x_f32_inf(neg), q32)); + RzILOpPure *by_inf = ITE(VARL("ib"), UN(32, 0), normal); + RzILOpPure *big = ITE(OR(VARL("ia"), VARL("zb")), c28x_f32_inf(DUP(neg)), by_inf); + RzILOpPure *val = ITE(VARL("za"), UN(32, 0), big); + RzILOpBool *lvf = OR(OR(AND(VARL("za"), VARL("zb")), AND(VARL("ia"), INV(VARL("ib")))), + OR(AND(VARL("na"), VARL("zb")), VARL("dov"))); + RzILOpBool *luf = OR(VARL("ib"), VARL("dun")); + RzILOpEffect *set_lvf = SETG("lvf", OR(VARG("lvf"), lvf)); + RzILOpEffect *set_luf = SETG("luf", OR(VARG("luf"), luf)); + RzILOpEffect *in = c28x_fp_operands(&c28x_fp_one, &c28x_bin32, a, b); + return SEQ7(in, cls, range, SETL("dv", val), wr, set_lvf, set_luf); +} + +/** + * \brief SQRTF32 RaH,RbH: a negative operand gives +0 and +Inf gives +Inf, + * both with LVF (SPRUHS1C). + */ +static RzILOpEffect *c28x_tmu_sqrtf32(const C28xInsn *insn) { + RzILOpPure *a = insn->nops == 2 ? c28x_fpu_read(&insn->ops[1]) : NULL; + RzILOpEffect *wr = a ? c28x_fpu_write(&insn->ops[0], VARL("dv")) : NULL; + if (!wr) { + rz_il_op_pure_free(a); + return NULL; + } + RzILOpPure *root = F2BV(FSQRT(RZ_FLOAT_RMODE_RNE, VARL("fa"))); + RzILOpPure *val = ITE(VARL("dneg"), UN(32, 0), ITE(VARL("dinf"), UN(32, 0x7f800000), root)); + RzILOpEffect *cls = SEQ2(SETL("dneg", IS_FNEG(VARL("fa"))), + SETL("dinf", AND(IS_FINF(VARL("fa")), INV(VARL("dneg"))))); + RzILOpBool *lvf = OR(VARG("lvf"), OR(VARL("dneg"), VARL("dinf"))); + RzILOpEffect *in = SEQ2(SETL("xa", a), SETL("fa", c28x_fp_in(&c28x_bin32, "xa"))); + return SEQ5(in, cls, SETL("dv", val), wr, SETG("lvf", lvf)); +} + +/** + * \brief MPY2PIF32 and DIV2PIF32: RbH times 2pi or 1/2pi. MPY2PIF32 can only + * overflow, to Inf with LVF, and DIV2PIF32 only underflow, to +0 with LUF. + * + * SPRUHS1C gives the constants' precision no more than the rounding; the + * product here takes them in binary64 and rounds to nearest. + */ +static RzILOpEffect *c28x_tmu_2pi(const C28xInsn *insn) { + RzILOpPure *a = insn->nops == 2 ? c28x_fpu_read(&insn->ops[1]) : NULL; + RzILOpEffect *wr = a ? c28x_fpu_write(&insn->ops[0], VARL("dv")) : NULL; + if (!wr) { + rz_il_op_pure_free(a); + return NULL; + } + const bool mpy = insn->id == C28X_INS_MPY2PIF32; + RzILOpFloat *k = F64(mpy ? 0x1.921fb54442d18p+2 : 0x1.45f306dc9c883p-3); + RzILOpFloat *p = FMUL(RZ_FLOAT_RMODE_RNE, c28x_f64_of("fa"), k); + RzILOpPure *p32 = F2BV(FCONVERT(RZ_FLOAT_IEEE754_BIN_32, RZ_FLOAT_RMODE_RNE, VARL("dp"))); + RzILOpBool *out; + RzILOpPure *val; + const char *flag; + if (mpy) { + // past the largest finite value plus half an ulp, rounding to nearest overflows + out = INV(FORDER(FABS(VARL("dp")), F64(0x1p128 - 0x1p103))); + val = ITE(VARL("dx"), c28x_f32_inf(IS_FNEG(VARL("dp"))), p32); + flag = "lvf"; + } else { + out = AND(INV(IS_FZERO(VARL("dp"))), FORDER(FABS(VARL("dp")), F64(0x1p-126))); + val = ITE(VARL("dx"), UN(32, 0), p32); + flag = "luf"; + } + RzILOpEffect *in = SEQ2(SETL("xa", a), SETL("fa", c28x_fp_in(&c28x_bin32, "xa"))); + RzILOpEffect *latch = SETG(flag, OR(VARG(flag), VARL("dx"))); + return SEQ6(in, SETL("dp", p), SETL("dx", out), SETL("dv", val), wr, latch); +} + +/** + * \brief MOV64 Ra,Rb{,CNDF}: only UNCF, the default condition, sets NF/ZF from + * the double and NI/ZI from all 64 bits. + */ +static RzILOpEffect *c28x_fpu_mov64(const C28xInsn *insn) { + const char *a = insn->nops == 3 ? c28x_fpu_name64(&insn->ops[0]) : NULL; + const char *b = a ? c28x_fpu_name64(&insn->ops[1]) : NULL; + const ut32 cond = b ? (ut32)insn->ops[2].imm : 0; + RzILOpBool *take = b ? c28x_fcond(cond) : NULL; + if (!take) { + return NULL; + } + RzILOpEffect *eff = SETG(a, VARL("mv")); + if (cond == 15) { + eff = SEQ2(eff, c28x_fp_movflags(&c28x_bin64, "mv")); + } + return SEQ2(SETL("mv", VARG(b)), BRANCH(take, eff, NOP())); +} + +/* + * Fast integer division (SPRUHS1C chapter 6): ABSI*DIV* keeps the operands' + * signs in NI and TF and makes them unsigned, SUBC4UI32 and SUBC2UI64 run a + * restoring division, and NEGI*, ENEGI* and MNEGI* sign the quotient and + * remainder for truncated, euclidean and floored division. The numerator and + * quotient live in R1H or R1H:R0H, the remainder in R2H or R2H:R4H and the + * denominator in R3H or R3H:R5H, the first register holding the high half. + */ + +typedef enum { + C28X_FD_ABS, + C28X_FD_SUBC, + C28X_FD_NEG, + C28X_FD_ENEG, + C28X_FD_MNEG, +} C28xFintdivStep; + +/** + * \brief A FINTDIV instruction: its step, the numerator's and denominator's + * widths (the quotient's and remainder's), and for ABSI whether the + * denominator is signed. + */ +typedef struct { + C28xFintdivStep step; + ut8 num; + ut8 den; + bool sgn; +} C28xFintdiv; + +static const C28xFintdiv c28x_fintdivs[] = { + [C28X_INS_ABSI32DIV32] = { C28X_FD_ABS, 32, 32, true }, + [C28X_INS_ABSI32DIV32U] = { C28X_FD_ABS, 32, 32, false }, + [C28X_INS_ABSI64DIV32] = { C28X_FD_ABS, 64, 32, true }, + [C28X_INS_ABSI64DIV32U] = { C28X_FD_ABS, 64, 32, false }, + [C28X_INS_ABSI64DIV64] = { C28X_FD_ABS, 64, 64, true }, + [C28X_INS_ABSI64DIV64U] = { C28X_FD_ABS, 64, 64, false }, + [C28X_INS_SUBC4UI32] = { C28X_FD_SUBC, 32, 32, false }, + [C28X_INS_SUBC2UI64] = { C28X_FD_SUBC, 64, 64, false }, + [C28X_INS_NEGI32DIV32] = { C28X_FD_NEG, 32, 32, false }, + [C28X_INS_NEGI64DIV32] = { C28X_FD_NEG, 64, 32, false }, + [C28X_INS_NEGI64DIV64] = { C28X_FD_NEG, 64, 64, false }, + [C28X_INS_ENEGI32DIV32] = { C28X_FD_ENEG, 32, 32, false }, + [C28X_INS_ENEGI64DIV32] = { C28X_FD_ENEG, 64, 32, false }, + [C28X_INS_ENEGI64DIV64] = { C28X_FD_ENEG, 64, 64, false }, + [C28X_INS_MNEGI32DIV32] = { C28X_FD_MNEG, 32, 32, false }, + [C28X_INS_MNEGI64DIV32] = { C28X_FD_MNEG, 64, 32, false }, + [C28X_INS_MNEGI64DIV64] = { C28X_FD_MNEG, 64, 64, false }, +}; + +/** + * \brief RhiH, or the pair RhiH:RloH when \p bits is 64. + */ +static RzILOpPure *c28x_fd_read(ut32 bits, ut32 hi, ut32 lo) { + const C28xOperand h = { .kind = C28X_OP_REG, .reg = C28X_REG_R0H + hi }; + const C28xOperand l = { .kind = C28X_OP_REG, .reg = C28X_REG_R0H + lo }; + RzILOpPure *vh = c28x_fpu_read(&h); + return bits == 32 ? vh : APPEND(vh, c28x_fpu_read(&l)); +} + +static RzILOpEffect *c28x_fd_write(ut32 bits, ut32 hi, ut32 lo, const char *local) { + const C28xOperand h = { .kind = C28X_OP_REG, .reg = C28X_REG_R0H + hi }; + const C28xOperand l = { .kind = C28X_OP_REG, .reg = C28X_REG_R0H + lo }; + if (bits == 32) { + return c28x_fpu_write(&h, VARL(local)); + } + RzILOpEffect *high = c28x_fpu_write(&h, UNSIGNED(32, SHIFTR0(VARL(local), UN(8, 32)))); + return SEQ2(high, c28x_fpu_write(&l, UNSIGNED(32, VARL(local)))); +} + +static RzILOpPure *c28x_fd_neg_if(RzILOpBool *c, const char *local) { + return ITE(c, NEG(VARL(local)), VARL(local)); +} + +/** + * \brief One restoring-division step of SUBC4UI32/SUBC2UI64 on "dr" (the + * remainder, \p w bits) and "dn" (the numerator becoming the quotient). + * + * The page's temp is (w + 1) bits wide and the step subtracts when it's + * non-negative as a signed value. + */ +static RzILOpEffect *c28x_fd_subc_step(ut32 w, ut32 nw) { + RzILOpPure *next = ITE(MSB(VARL("dn")), UN(w + 1, 1), UN(w + 1, 0)); + RzILOpPure *twice = SHIFTL0(UNSIGNED(w + 1, VARL("dr")), UN(8, 1)); + RzILOpPure *temp = SUB(ADD(twice, next), UNSIGNED(w + 1, VARL("dd"))); + RzILOpPure *bit = ITE(MSB(VARL("dn")), UN(w, 1), UN(w, 0)); + RzILOpPure *shifted = LOGOR(SHIFTL0(VARL("dr"), UN(8, 1)), bit); + RzILOpPure *rem = ITE(MSB(VARL("dt")), shifted, UNSIGNED(w, VARL("dt"))); + RzILOpPure *num_shift = SHIFTL0(VARL("dn"), UN(8, 1)); + RzILOpPure *num = ITE(MSB(VARL("dt")), num_shift, LOGOR(DUP(num_shift), UN(nw, 1))); + return SEQ4(SETL("dt", temp), SETL("dq", rem), SETL("dn", num), SETL("dr", VARL("dq"))); +} + +/** \brief The FINTDIV instructions, each as its SPRUHS1C page defines it. */ +static RzILOpEffect *c28x_fpu_fintdiv(const C28xInsn *insn) { + if ((size_t)insn->id >= RZ_ARRAY_SIZE(c28x_fintdivs) || !c28x_fintdivs[insn->id].num) { + return NULL; + } + const C28xFintdiv *d = &c28x_fintdivs[insn->id]; + const ut32 nb = d->num; + const ut32 db = d->den; + RzILOpEffect *num_in = SETL("dn", c28x_fd_read(nb, 1, 0)); + RzILOpEffect *den_in = SETL("dd", c28x_fd_read(db, 3, 5)); + RzILOpEffect *in = SEQ3(num_in, den_in, SETL("dr", c28x_fd_read(db, 2, 4))); + RzILOpEffect *num_out = c28x_fd_write(nb, 1, 0, "dn"); + RzILOpEffect *rem_out = c28x_fd_write(db, 2, 4, "dr"); + RzILOpEffect *body; + switch (d->step) { + case C28X_FD_ABS: { + RzILOpBool *tf = MSB(VARL("dn")); + RzILOpBool *min = EQ(VARL("dn"), UN(nb, 1ULL << (nb - 1))); + if (d->sgn) { + tf = XOR(tf, MSB(VARL("dd"))); + min = OR(min, EQ(VARL("dd"), UN(db, 1ULL << (db - 1)))); + } + RzILOpEffect *lvf = SETG("lvf", OR(VARG("lvf"), min)); + RzILOpEffect *flags = SEQ3(SETG("ni", MSB(VARL("dn"))), SETG("tf", tf), lvf); + RzILOpEffect *num = SETL("dn", c28x_fd_neg_if(MSB(VARL("dn")), "dn")); + body = SEQ3(flags, SETL("dr", UN(db, 0)), num); + if (d->sgn) { + RzILOpEffect *den = SETL("dd", c28x_fd_neg_if(MSB(VARL("dd")), "dd")); + body = SEQ3(body, den, c28x_fd_write(db, 3, 5, "dd")); + } + break; + } + case C28X_FD_SUBC: { + RzILOpEffect *lvf = SETG("lvf", OR(VARG("lvf"), IS_ZERO(VARL("dd")))); + body = SEQ2(SETG("zi", IL_FALSE), lvf); + const ut32 steps = db == 32 ? 4 : 2; + for (ut32 i = 0; i < steps; i++) { + body = SEQ2(body, c28x_fd_subc_step(db, nb)); + } + body = SEQ2(body, SETG("zi", IS_ZERO(VARL("dr")))); + break; + } + case C28X_FD_NEG: { + RzILOpEffect *q = SETL("dn", c28x_fd_neg_if(VARG("tf"), "dn")); + body = SEQ2(q, SETL("dr", c28x_fd_neg_if(VARG("ni"), "dr"))); + break; + } + case C28X_FD_ENEG: + case C28X_FD_MNEG: { + // with a nonzero remainder, the quotient moves one away from zero + RzILOpBool *when = d->step == C28X_FD_ENEG ? VARG("ni") : VARG("tf"); + RzILOpPure *q1 = ITE(VARL("da"), ADD(VARL("dn"), UN(nb, 1)), VARL("dn")); + RzILOpPure *r1 = ITE(VARL("da"), SUB(VARL("dd"), VARL("dr")), VARL("dr")); + RzILOpEffect *adj = SETL("da", AND(when, INV(VARG("zi")))); + RzILOpEffect *fix = SEQ3(adj, SETL("dn", q1), SETL("dr", r1)); + body = SEQ2(fix, SETL("dn", c28x_fd_neg_if(VARG("tf"), "dn"))); + if (d->step == C28X_FD_MNEG) { + RzILOpBool *flip = XOR(VARG("ni"), VARG("tf")); + body = SEQ2(body, SETL("dr", c28x_fd_neg_if(flip, "dr"))); + } + break; + } + default: + rz_il_op_effect_free(in); + rz_il_op_effect_free(num_out); + rz_il_op_effect_free(rem_out); + return NULL; + } + return SEQ4(in, body, num_out, rem_out); +} + +/** + * \brief FPU lifters by instruction id. + * + * PREDIVF64, SUBC3F64 and POSTDIVF64, TI's compiler's double division steps, + * appear nowhere in SPRUHS1C: what each step leaves in R1-R3 is unknown, so + * they stay unlifted. + */ +static const C28xFpuLifter c28x_fpu_lifters[] = { + [C28X_INS_ADDF32] = c28x_fpu_arith, + [C28X_INS_SUBF32] = c28x_fpu_arith, + [C28X_INS_MPYF32] = c28x_fpu_arith, + [C28X_INS_CMPF32] = c28x_fpu_cmpf32, + [C28X_INS_MOV32] = c28x_fpu_mov32, + [C28X_INS_I32TOF32] = c28x_fpu_itof, + [C28X_INS_UI32TOF32] = c28x_fpu_itof, + [C28X_INS_I16TOF32] = c28x_fpu_itof, + [C28X_INS_UI16TOF32] = c28x_fpu_itof, + [C28X_INS_F32TOI32] = c28x_fpu_ftoi, + [C28X_INS_F32TOUI32] = c28x_fpu_ftoi, + [C28X_INS_F32TOI16] = c28x_fpu_ftoi, + [C28X_INS_F32TOI16R] = c28x_fpu_ftoi, + [C28X_INS_F32TOUI16] = c28x_fpu_ftoi, + [C28X_INS_F32TOUI16R] = c28x_fpu_ftoi, + [C28X_INS_FRACF32] = c28x_fpu_fracf32, + [C28X_INS_MOVIZ] = c28x_fpu_movi, + [C28X_INS_MOVXI] = c28x_fpu_movi, + [C28X_INS_MOVIX] = c28x_fpu_movi, + [C28X_INS_ZERO] = c28x_fpu_movi, + [C28X_INS_ZEROA] = c28x_fpu_zeroa, + [C28X_INS_NEGF32] = c28x_fpu_negabs, + [C28X_INS_ABSF32] = c28x_fpu_negabs, + [C28X_INS_MAXF32] = c28x_fpu_maxmin, + [C28X_INS_MINF32] = c28x_fpu_maxmin, + [C28X_INS_MACF32] = c28x_fpu_macf32, + [C28X_INS_DIVF32] = c28x_tmu_divf32, + [C28X_INS_ADDF64] = c28x_fpu_arith, + [C28X_INS_SUBF64] = c28x_fpu_arith, + [C28X_INS_MPYF64] = c28x_fpu_arith, + [C28X_INS_MACF64] = c28x_fpu_macf32, + [C28X_INS_CMPF64] = c28x_fpu_cmpf32, + [C28X_INS_MAXF64] = c28x_fpu_maxmin, + [C28X_INS_MINF64] = c28x_fpu_maxmin, + [C28X_INS_NEGF64] = c28x_fpu_negabs, + [C28X_INS_ABSF64] = c28x_fpu_negabs, + [C28X_INS_FRACF64] = c28x_fpu_fracf32, + [C28X_INS_MOV64] = c28x_fpu_mov64, + [C28X_INS_I32TOF64] = c28x_fpu_itof, + [C28X_INS_UI32TOF64] = c28x_fpu_itof, + [C28X_INS_I64TOF64] = c28x_fpu_itof, + [C28X_INS_UI64TOF64] = c28x_fpu_itof, + [C28X_INS_F64TOI32] = c28x_fpu_ftoi, + [C28X_INS_F64TOUI32] = c28x_fpu_ftoi, + [C28X_INS_F64TOI64] = c28x_fpu_ftoi, + [C28X_INS_F64TOUI64] = c28x_fpu_ftoi, + [C28X_INS_F32TOF64] = c28x_fpu_ftof, + [C28X_INS_F32DTOF64] = c28x_fpu_ftof, + [C28X_INS_F64TOF32] = c28x_fpu_ftof, + [C28X_INS_ABSI32DIV32] = c28x_fpu_fintdiv, + [C28X_INS_ABSI32DIV32U] = c28x_fpu_fintdiv, + [C28X_INS_ABSI64DIV32] = c28x_fpu_fintdiv, + [C28X_INS_ABSI64DIV32U] = c28x_fpu_fintdiv, + [C28X_INS_ABSI64DIV64] = c28x_fpu_fintdiv, + [C28X_INS_ABSI64DIV64U] = c28x_fpu_fintdiv, + [C28X_INS_SUBC4UI32] = c28x_fpu_fintdiv, + [C28X_INS_SUBC2UI64] = c28x_fpu_fintdiv, + [C28X_INS_NEGI32DIV32] = c28x_fpu_fintdiv, + [C28X_INS_NEGI64DIV32] = c28x_fpu_fintdiv, + [C28X_INS_NEGI64DIV64] = c28x_fpu_fintdiv, + [C28X_INS_ENEGI32DIV32] = c28x_fpu_fintdiv, + [C28X_INS_ENEGI64DIV32] = c28x_fpu_fintdiv, + [C28X_INS_ENEGI64DIV64] = c28x_fpu_fintdiv, + [C28X_INS_MNEGI32DIV32] = c28x_fpu_fintdiv, + [C28X_INS_MNEGI64DIV32] = c28x_fpu_fintdiv, + [C28X_INS_MNEGI64DIV64] = c28x_fpu_fintdiv, + [C28X_INS_SQRTF32] = c28x_tmu_sqrtf32, + [C28X_INS_MPY2PIF32] = c28x_tmu_2pi, + [C28X_INS_DIV2PIF32] = c28x_tmu_2pi, + [C28X_INS_SETFLG] = c28x_fpu_setflg, + [C28X_INS_SAVE] = c28x_fpu_save, + [C28X_INS_RESTORE] = c28x_fpu_restore, + [C28X_INS_MOVST0] = c28x_fpu_movst0, + [C28X_INS_TESTTF] = c28x_fpu_testtf, + [C28X_INS_SWAPF] = c28x_fpu_swapf, + [C28X_INS_MOV16] = c28x_fpu_mov16, + [C28X_INS_MOVD32] = c28x_fpu_movd32, + [C28X_INS_MOVDD32] = c28x_fpu_movd32, + [C28X_INS_PUSH] = c28x_fpu_rb, + [C28X_INS_POP] = c28x_fpu_rb, +}; + +/** \brief Lift the FPU instruction \p insn; NULL while it has no IL yet. */ +RZ_IPI RzILOpEffect *c28x_lift_fpu(const C28xInsn *insn, RZ_UNUSED ut64 pc) { + if ((size_t)insn->id >= RZ_ARRAY_SIZE(c28x_fpu_lifters) || !c28x_fpu_lifters[insn->id]) { + return NULL; + } + return c28x_fpu_lifters[insn->id](insn); +} diff --git a/librz/arch/isa/tms320/c28x/c28x_rowdefs.h b/librz/arch/isa/tms320/c28x/c28x_rowdefs.h index 0e7cf91378..e38eaf1d2e 100644 --- a/librz/arch/isa/tms320/c28x/c28x_rowdefs.h +++ b/librz/arch/isa/tms320/c28x/c28x_rowdefs.h @@ -77,7 +77,18 @@ { C28X_OD_INTR, (lo_), 4, 0 } // A row is repeatable under RPT, which the analysis layer reports as a hint. -#define RPTABLE .repeatable = true +#define RPTABLE .repeatable = true +#define FREG(lo_) { C28X_OD_REGSEL, (lo_), 3, C28X_REG_R0H } +#define FREGFIX(n_) { C28X_OD_REG, 0, 0, C28X_REG_R##n_##H } +#define FREGL(lo_) { C28X_OD_REGSEL, (lo_), 3, C28X_REG_R0L } +#define FREG64(lo_) { C28X_OD_REGSEL, (lo_), 3, C28X_REG_R0 } +// FPU register n of a group of four from base_: MOV32 between CPU and FPU +// registers addresses RnL at data address 0x0f10 + 4n +#define FREGM(base_) { C28X_OD_REGSEL, 2, 2, (base_) } +#define FCOND(lo_) { C28X_OD_FCOND, (lo_), 4, 0 } +#define FFLAGS(lo_) { C28X_OD_FFLAGS, (lo_), 8, 0 } +#define FSETFLG { C28X_OD_FSETFLG, 0, 11, 11 } +#define FZERO { C28X_OD_FZERO, 0, 0, 0 } #define PAR(id_) { C28X_OD_PAR, 0, 0, C28X_INS_##id_ } #define VRREGH(lo_) { C28X_OD_REGSEL_HIGH, (lo_), 3, C28X_REG_VR0 } #define VRREGL4(lo_) { C28X_OD_REGSEL_LOW, (lo_), 4, C28X_REG_VR0 } diff --git a/librz/arch/isa/tms320/c28x/c28x_rows_fpu.inc b/librz/arch/isa/tms320/c28x/c28x_rows_fpu.inc new file mode 100644 index 0000000000..11043940dd --- /dev/null +++ b/librz/arch/isa/tms320/c28x/c28x_rows_fpu.inc @@ -0,0 +1,179 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +// TMS320C28x FPU32, FPU64, TMU and fast integer division rows, ordered by +// opcode, derived from TI's dis2000 (C2000 CGT 20.2.6.LTS) and checked against +// it on random encodings of every row. The trailing comment is the +// instruction's syntax line. +// clang-format off + { OP(0xff000000, 0xad000000), .mnem = "movst0", RZTYPE(MOV), .ops = { FFLAGS(16) } }, // MOVST0 flags + { OP(0xfff00000, 0xe0000000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), LOC32(0), FREG(8) } }, // MPYF32 RaH,RbH,RcH || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0100000), .mnem = "addf32", RZTYPE(ADD), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), LOC32(0), FREG(8) } }, // ADDF32 RaH,RbH,RcH || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0200000), .mnem = "subf32", RZTYPE(SUB), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), LOC32(0), FREG(8) } }, // SUBF32 RaH,RbH,RcH || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0400000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREG(8) } }, // MPYF64 Ra,Rb,Rc || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0500000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREG(8) } }, // ADDF64 Ra,Rb,Rc || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0600000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREG(8) } }, // SUBF64 Ra,Rb,Rc || MOV32 mem32,RdH + { OP(0xfff00000, 0xe0800000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREGL(8) } }, // MPYF64 Ra,Rb,Rc || MOV32 mem32,RdL + { OP(0xfff00000, 0xe0900000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREGL(8) } }, // ADDF64 Ra,Rb,Rc || MOV32 mem32,RdL + { OP(0xfff00000, 0xe0a00000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), LOC32(0), FREGL(8) } }, // SUBF64 Ra,Rb,Rc || MOV32 mem32,RdL + { OP(0xffff0000, 0xe2000000), .mnem = "mov32", RZTYPE(STORE), .len = 4, .ops = { LOC32(0), REG(STF) } }, // MOV32 mem32,STF + { OP(0xffff0000, 0xe2020000), .mnem = "mov32", RZTYPE(STORE), .len = 4, .ops = { LOC32(0), FREGL(8) } }, // MOV32 mem32,RaL + { OP(0xffff0000, 0xe2030000), .mnem = "mov32", RZTYPE(STORE), .len = 4, .ops = { LOC32(0), FREG(8) } }, // MOV32 mem32,RaH + // MOV32 between CPU and FPU registers is VMOV32 *(0:16bit) at the FPU + // register's data address, 0x0f10 + 4n for RnL. dis2000 names offsets 1-3 + // of each group RnH; the assembler emits only offsets 0 and 2. + { OP(0xff00fff3, 0xbd000f10), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R0L), LOC32(16) } }, // MOV32 RaL,loc32 + { OP(0xff00fff3, 0xbd000f20), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R4L), LOC32(16) } }, // MOV32 RaL,loc32 + { OP(0xff00fff2, 0xbd000f12), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R0H), LOC32(16) } }, // MOV32 RaH,loc32 + { OP(0xff00fff2, 0xbd000f22), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R4H), LOC32(16) } }, // MOV32 RaH,loc32 + { OP(0xff00fff3, 0xbd000f11), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R0H), LOC32(16) } }, // MOV32 RaH,loc32 + { OP(0xff00fff3, 0xbd000f21), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGM(C28X_REG_R4H), LOC32(16) } }, // MOV32 RaH,loc32 + { OP(0xff00fff3, 0xbf000f10), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R0L) } }, // MOV32 loc32,RaL + { OP(0xff00fff3, 0xbf000f20), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R4L) } }, // MOV32 loc32,RaL + { OP(0xff00fff2, 0xbf000f12), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R0H) } }, // MOV32 loc32,RaH + { OP(0xff00fff2, 0xbf000f22), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R4H) } }, // MOV32 loc32,RaH + { OP(0xff00fff3, 0xbf000f11), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R0H) } }, // MOV32 loc32,RaH + { OP(0xff00fff3, 0xbf000f21), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { LOC32(16), FREGM(C28X_REG_R4H) } }, // MOV32 loc32,RaH + { OP(0xfffff800, 0xe2130000), .mnem = "mov16", RZTYPE(STORE), .len = 4, .ops = { LOC32(0), FREG(8) } }, // MOV16 mem32,RaH + { OP(0xfffff800, 0xe2210000), .mnem = "f32dtof64", RZTYPE(LOAD), .len = 4, .ops = { FREG64(8), LOC32(0) } }, // F32DTOF64 Ra,mem32 + { OP(0xffff0000, 0xe2230000), .mnem = "movd32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // MOVD32 RaH,mem32 + { OP(0xffff0000, 0xe2420000), .mnem = "movdd32", RZTYPE(LOAD), .len = 4, .ops = { FREGL(8), LOC32(0) } }, // MOVDD32 RaL,mem32 + { OP(0xffff0000, 0xe2430000), .mnem = "movdd32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // MOVDD32 RaH,mem32 + { OP(0xffff0000, 0xe2500000), .mnem = "macf32", RZTYPE(MUL), .len = 4, .ops = { FREG(8), FREG(11), LOC32(0), INDR(XAR_POSTINC, 7) } }, // MACF32 RaH,RbH,mem32,*XAR7++ + { OP(0xffffffc0, 0xe2700000), .mnem = "mpy2pif32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // MPY2PIF32 RaH,RbH + { OP(0xffffffc0, 0xe2710000), .mnem = "div2pif32", RZTYPE(DIV), .len = 4, .ops = { FREG(0), FREG(3) } }, // DIV2PIF32 RaH,RbH + { OP(0xffffffc0, 0xe2720000), .mnem = "log2f32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // LOG2F32 RaH,RbH + { OP(0xffffffc0, 0xe2730000), .mnem = "iexp2f32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // IEXP2F32 RaH,RbH + { OP(0xfffffe00, 0xe2740000), .mnem = "divf32", RZTYPE(DIV), .len = 4, .ops = { FREG(0), FREG(3), FREG(6) } }, // DIVF32 RaH,RbH,RcH + { OP(0xffffffc0, 0xe2770000), .mnem = "sqrtf32", RZTYPE(DIV), .len = 4, .ops = { FREG(0), FREG(3) } }, // SQRTF32 RaH,RbH + { OP(0xffffffc0, 0xe2780000), .mnem = "sinpuf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // SINPUF32 RaH,RbH + { OP(0xffffffc0, 0xe2790000), .mnem = "cospuf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // COSPUF32 RaH,RbH + { OP(0xffffffc0, 0xe27a0000), .mnem = "atanpuf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3) } }, // ATANPUF32 RaH,RbH + { OP(0xfffff000, 0xe27c0000), .mnem = "quadf32", RZTYPE(CMP), .len = 4, .ops = { FREG(0), FREG(3), FREG(6), FREG(9) } }, // QUADF32 RaH,RbH,RcH,RdH + { OP(0xffffff00, 0xe2800000), .mnem = "mov32", RZTYPE(LOAD), .len = 4, .ops = { REG(STF), LOC32(0) } }, // MOV32 STF,mem32 + { OP(0xfffff800, 0xe2840000), .mnem = "ui32tof32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // UI32TOF32 RaH,mem32 + { OP(0xfffff800, 0xe2850000), .mnem = "ui32tof64", RZTYPE(LOAD), .len = 4, .ops = { FREG64(8), LOC32(0) } }, // UI32TOF64 Ra,mem32 + { OP(0xfffff800, 0xe2880000), .mnem = "i32tof32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // I32TOF32 RaH,mem32 + { OP(0xfffff800, 0xe2890000), .mnem = "i32tof64", RZTYPE(LOAD), .len = 4, .ops = { FREG64(8), LOC32(0) } }, // I32TOF64 Ra,mem32 + { OP(0xfffff800, 0xe28c0000), .mnem = "f32tof64", RZTYPE(LOAD), .len = 4, .ops = { FREG64(8), LOC32(0) } }, // F32TOF64 Ra,mem32 + { OP(0xfff00000, 0xe2900000), .mnem = "mov32", RZTYPE(LOAD), .len = 4, .ops = { FREGL(8), LOC16(0), FCOND(16) } }, // MOV32 RaL,mem16,CNDF + { OP(0xfff00000, 0xe2a00000), .mnem = "mov32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC16(0), FCOND(16) } }, // MOV32 RaH,mem16,CNDF + { OP(0xfffff800, 0xe2c40000), .mnem = "ui16tof32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // UI16TOF32 RaH,mem32 + { OP(0xfffff800, 0xe2c80000), .mnem = "i16tof32", RZTYPE(LOAD), .len = 4, .ops = { FREG(8), LOC32(0) } }, // I16TOF32 RaH,mem32 + { OP(0xfff00000, 0xe3000000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MPYF32 RaH,RbH,RcH || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3100000), .mnem = "addf32", RZTYPE(ADD), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), FREG(8), LOC32(0) } }, // ADDF32 RaH,RbH,RcH || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3200000), .mnem = "subf32", RZTYPE(SUB), .len = 4, .ops = { FREG(11), FREG(14), FREG(17), PAR(MOV32), FREG(8), LOC32(0) } }, // SUBF32 RaH,RbH,RcH || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3300000), .mnem = "macf32", RZTYPE(MUL), .len = 4, .ops = { FREGFIX(3), FREGFIX(2), FREG(11), FREG(14), FREG(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MACF32 R3H,R2H,RaH,RbH,RcH || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3400000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MPYF64 Ra,Rb,Rc || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3500000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREG(8), LOC32(0) } }, // ADDF64 Ra,Rb,Rc || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3600000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREG(8), LOC32(0) } }, // SUBF64 Ra,Rb,Rc || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3700000), .mnem = "macf64", RZTYPE(MUL), .len = 4, .ops = { REG(R3), REG(R2), FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MACF64 R3,R2,Ra,Rb,Rc || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3800000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREGL(8), LOC32(0) } }, // MPYF64 Ra,Rb,Rc || MOV32 RdL,mem32 + { OP(0xfff00000, 0xe3900000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREGL(8), LOC32(0) } }, // ADDF64 Ra,Rb,Rc || MOV32 RdL,mem32 + { OP(0xfff00000, 0xe3a00000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREGL(8), LOC32(0) } }, // SUBF64 Ra,Rb,Rc || MOV32 RdL,mem32 + { OP(0xfff00000, 0xe3b00000), .mnem = "macf64", RZTYPE(MUL), .len = 4, .ops = { REG(R3), REG(R2), FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREGL(8), LOC32(0) } }, // MACF64 R3,R2,Ra,Rb,Rc || MOV32 RdL,mem32 + { OP(0xfff00000, 0xe3c00000), .mnem = "macf32", RZTYPE(MUL), .len = 4, .ops = { FREGFIX(7), FREGFIX(6), FREG(11), FREG(14), FREG(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MACF32 R7H,R6H,RaH,RbH,RcH || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3d00000), .mnem = "macf64", RZTYPE(MUL), .len = 4, .ops = { REG(R7), REG(R6), FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREG(8), LOC32(0) } }, // MACF64 R7,R6,Ra,Rb,Rc || MOV32 RdH,mem32 + { OP(0xfff00000, 0xe3e00000), .mnem = "macf64", RZTYPE(MUL), .len = 4, .ops = { REG(R7), REG(R6), FREG64(11), FREG64(14), FREG64(17), PAR(MOV32), FREGL(8), LOC32(0) } }, // MACF64 R7,R6,Ra,Rb,Rc || MOV32 RdL,mem32 + { OP(0xffff0000, 0xe5620000), .mnem = "restore", RZTYPE(MOV) }, // RESTORE + { OP(0xfff70000, 0xe5630000), .mnem = "zeroa", RZTYPE(MOV) }, // ZEROA + { OP(0xffff0000, 0xe5640000), .mnem = "subc4ui32", RZTYPE(DIV), .ops = { FREGFIX(2), FREGFIX(1), FREGFIX(3) } }, // SUBC4UI32 R2H,R1H,R3H + { OP(0xffff0000, 0xe5650000), .mnem = "subc2ui64", RZTYPE(DIV), .ops = { REG(R2H_R4H), REG(R1H_R0H), REG(R3H_R5H) } }, // SUBC2UI64 R2H:R4H,R1H:R0H,R3H:R5H + { OP(0xffff0000, 0xe5660000), .mnem = "subc3f64", RZTYPE(DIV), .ops = { REG(R2), REG(R1), REG(R3) } }, // SUBC3F64 R2,R1,R3 + { OP(0xffff0000, 0xe5680000), .mnem = "absi32div32", RZTYPE(DIV), .ops = { FREGFIX(2), FREGFIX(1), FREGFIX(3) } }, // ABSI32DIV32 R2H,R1H,R3H + { OP(0xffff0000, 0xe5690000), .mnem = "absi32div32u", RZTYPE(DIV), .ops = { FREGFIX(2), FREGFIX(1) } }, // ABSI32DIV32U R2H,R1H + { OP(0xffff0000, 0xe56a0000), .mnem = "negi32div32", RZTYPE(DIV), .ops = { FREGFIX(1), FREGFIX(2) } }, // NEGI32DIV32 R1H,R2H + { OP(0xffff0000, 0xe56b0000), .mnem = "enegi32div32", RZTYPE(DIV), .ops = { FREGFIX(1), FREGFIX(2), FREGFIX(3) } }, // ENEGI32DIV32 R1H,R2H,R3H + { OP(0xffff0000, 0xe56c0000), .mnem = "mnegi32div32", RZTYPE(DIV), .ops = { FREGFIX(1), FREGFIX(2), FREGFIX(3) } }, // MNEGI32DIV32 R1H,R2H,R3H + { OP(0xfff00000, 0xe5800000), .mnem = "testtf", RZTYPE(CMP), .ops = { FCOND(16) } }, // TESTTF CNDF + { OP(0xfff00000, 0xe5900000), .mnem = "zero", RZTYPE(MOV), .ops = { FREG64(16) } }, // ZERO Ra + { OP(0xfff80000, 0xe5a00000), .mnem = "cmpf32", RZTYPE(CMP), .ops = { FREG(16), FZERO } }, // CMPF32 RaH,#0.0 + { OP(0xffff0000, 0xe5a80000), .mnem = "absi64div32", RZTYPE(DIV), .ops = { FREGFIX(2), REG(R1H_R0H), FREGFIX(3) } }, // ABSI64DIV32 R2H,R1H:R0H,R3H + { OP(0xffff0000, 0xe5a90000), .mnem = "absi64div32u", RZTYPE(DIV), .ops = { FREGFIX(2), REG(R1H_R0H) } }, // ABSI64DIV32U R2H,R1H:R0H + { OP(0xffff0000, 0xe5aa0000), .mnem = "negi64div32", RZTYPE(DIV), .ops = { REG(R1H_R0H), FREGFIX(2) } }, // NEGI64DIV32 R1H:R0H,R2H + { OP(0xffff0000, 0xe5ab0000), .mnem = "enegi64div32", RZTYPE(DIV), .ops = { REG(R1H_R0H), FREGFIX(2), FREGFIX(3) } }, // ENEGI64DIV32 R1H:R0H,R2H,R3H + { OP(0xffff0000, 0xe5ac0000), .mnem = "mnegi64div32", RZTYPE(DIV), .ops = { REG(R1H_R0H), FREGFIX(2), FREGFIX(3) } }, // MNEGI64DIV32 R1H:R0H,R2H,R3H + { OP(0xfff80000, 0xe5b00000), .mnem = "cmpf64", RZTYPE(CMP), .ops = { FREG64(16), FZERO } }, // CMPF64 Ra,#0.0 + { OP(0xffff0000, 0xe5b80000), .mnem = "absi64div64", RZTYPE(DIV), .ops = { REG(R2H_R4H), REG(R1H_R0H), REG(R3H_R5H) } }, // ABSI64DIV64 R2H:R4H,R1H:R0H,R3H:R5H + { OP(0xffff0000, 0xe5b90000), .mnem = "absi64div64u", RZTYPE(DIV), .ops = { REG(R2H_R4H), REG(R1H_R0H) } }, // ABSI64DIV64U R2H:R4H,R1H:R0H + { OP(0xffff0000, 0xe5ba0000), .mnem = "negi64div64", RZTYPE(DIV), .ops = { REG(R1H_R0H), REG(R2H_R4H) } }, // NEGI64DIV64 R1H:R0H,R2H:R4H + { OP(0xffff0000, 0xe5bb0000), .mnem = "enegi64div64", RZTYPE(DIV), .ops = { REG(R1H_R0H), REG(R2H_R4H), REG(R3H_R5H) } }, // ENEGI64DIV64 R1H:R0H,R2H:R4H,R3H:R5H + { OP(0xffff0000, 0xe5bc0000), .mnem = "mnegi64div64", RZTYPE(DIV), .ops = { REG(R1H_R0H), REG(R2H_R4H), REG(R3H_R5H) } }, // MNEGI64DIV64 R1H:R0H,R2H:R4H,R3H:R5H + { OP(0xffff0000, 0xe5be0000), .mnem = "predivf64", RZTYPE(DIV), .ops = { FREGFIX(0), REG(R2), REG(R1), REG(R3) } }, // PREDIVF64 R0H,R2,R1,R3 + { OP(0xffff0000, 0xe5bf0000), .mnem = "postdivf64", RZTYPE(DIV), .ops = { REG(R1), FREGFIX(0) } }, // POSTDIVF64 R1,R0H + { OP(0xffc00000, 0xe6000000), .mnem = "setflg", RZTYPE(MOV), .len = 4, .ops = { FSETFLG } }, // SETFLG flag=value,... + { OP(0xffc00000, 0xe6400000), .mnem = "save", RZTYPE(MOV), .len = 4, .ops = { FSETFLG } }, // SAVE flag=value,... + { OP(0xffffffc0, 0xe6840000), .mnem = "f64toi32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG64(3) } }, // F64TOI32 RaH,Rb + { OP(0xffffffc0, 0xe6848000), .mnem = "f64toi64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // F64TOI64 Ra,Rb + { OP(0xffffffc0, 0xe6850000), .mnem = "i32tof64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG(3) } }, // I32TOF64 Ra,RbH + { OP(0xffffffc0, 0xe6858000), .mnem = "i64tof64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // I64TOF64 Ra,Rb + { OP(0xffffffc0, 0xe6860000), .mnem = "f64toui32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG64(3) } }, // F64TOUI32 RaH,Rb + { OP(0xffffffc0, 0xe6868000), .mnem = "f64toui64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // F64TOUI64 Ra,Rb + { OP(0xffffffc0, 0xe6870000), .mnem = "ui32tof64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG(3) } }, // UI32TOF64 Ra,RbH + { OP(0xffffffc0, 0xe6878000), .mnem = "ui64tof64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // UI64TOF64 Ra,Rb + { OP(0xffffffc0, 0xe6880000), .mnem = "f32toi32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOI32 RaH,RbH + { OP(0xffffffc0, 0xe6890000), .mnem = "i32tof32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // I32TOF32 RaH,RbH + { OP(0xffffffc0, 0xe68a0000), .mnem = "f32toui32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOUI32 RaH,RbH + { OP(0xffffffc0, 0xe68b0000), .mnem = "ui32tof32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // UI32TOF32 RaH,RbH + { OP(0xffffffc0, 0xe68c0000), .mnem = "f32toi16", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOI16 RaH,RbH + { OP(0xffffffc0, 0xe68c8000), .mnem = "f32toi16r", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOI16R RaH,RbH + { OP(0xffffffc0, 0xe68d0000), .mnem = "i16tof32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // I16TOF32 RaH,RbH + { OP(0xffffffc0, 0xe68e0000), .mnem = "f32toui16", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOUI16 RaH,RbH + { OP(0xffffffc0, 0xe68e8000), .mnem = "f32toui16r", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // F32TOUI16R RaH,RbH + { OP(0xffffffc0, 0xe68f0000), .mnem = "ui16tof32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // UI16TOF32 RaH,RbH + { OP(0xffffffc0, 0xe6900000), .mnem = "f64tof32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG64(3) } }, // F64TOF32 RaH,Rb + { OP(0xffffffc0, 0xe6910000), .mnem = "f32tof64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG(3) } }, // F32TOF64 Ra,RbH + { OP(0xffffffc0, 0xe6920000), .mnem = "eisqrtf32", RZTYPE(DIV), .len = 4, .ops = { FREG(0), FREG(3) } }, // EISQRTF32 RaH,RbH + { OP(0xffffffc0, 0xe6928000), .mnem = "eisqrtf64", RZTYPE(DIV), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // EISQRTF64 Ra,Rb + { OP(0xffffffc0, 0xe6930000), .mnem = "einvf32", RZTYPE(DIV), .len = 4, .ops = { FREG(0), FREG(3) } }, // EINVF32 RaH,RbH + { OP(0xffffffc0, 0xe6938000), .mnem = "einvf64", RZTYPE(DIV), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // EINVF64 Ra,Rb + { OP(0xffffffc0, 0xe6940000), .mnem = "cmpf32", RZTYPE(CMP), .len = 4, .ops = { FREG(0), FREG(3) } }, // CMPF32 RaH,RbH + { OP(0xffffffc0, 0xe6950000), .mnem = "absf32", RZTYPE(ABS), .len = 4, .ops = { FREG(0), FREG(3) } }, // ABSF32 RaH,RbH + { OP(0xffffffc0, 0xe6960000), .mnem = "maxf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), FREG(3) } }, // MAXF32 RaH,RbH + { OP(0xffffffc0, 0xe6970000), .mnem = "minf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), FREG(3) } }, // MINF32 RaH,RbH + { OP(0xffffffc0, 0xe6980000), .mnem = "cmpf64", RZTYPE(CMP), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // CMPF64 Ra,Rb + { OP(0xffffffc0, 0xe6990000), .mnem = "absf64", RZTYPE(ABS), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // ABSF64 Ra,Rb + { OP(0xffffffc0, 0xe69a0000), .mnem = "maxf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // MAXF64 Ra,Rb + { OP(0xffffffc0, 0xe69b0000), .mnem = "minf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // MINF64 Ra,Rb + { OP(0xffff0000, 0xe69c0000), .mnem = "maxf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), FREG(3), PAR(MOV32), FREG(6), FREG(9) } }, // MAXF32 RaH,RbH || MOV32 RcH,RdH + { OP(0xffff0000, 0xe69d0000), .mnem = "minf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), FREG(3), PAR(MOV32), FREG(6), FREG(9) } }, // MINF32 RaH,RbH || MOV32 RcH,RdH + { OP(0xffff0000, 0xe69e0000), .mnem = "maxf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), FREG64(3), PAR(MOV64), FREG64(6), FREG64(9) } }, // MAXF64 Ra,Rb || MOV64 Rc,Rd + { OP(0xffff0000, 0xe69f0000), .mnem = "minf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), FREG64(3), PAR(MOV64), FREG64(6), FREG64(9) } }, // MINF64 Ra,Rb || MOV64 Rc,Rd + { OP(0xfff00000, 0xe6a00000), .mnem = "negf32", RZTYPE(CPL), .len = 4, .ops = { FREG(0), FREG(3), FCOND(16) } }, // NEGF32 RaH,RbH,CNDF + { OP(0xfff00000, 0xe6b00000), .mnem = "negf64", RZTYPE(CPL), .len = 4, .ops = { FREG64(0), FREG64(3), FCOND(16) } }, // NEGF64 Ra,Rb,CNDF + { OP(0xfff00000, 0xe6c00000), .mnem = "mov32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), FREG(3), FCOND(16) } }, // MOV32 RaH,RbH,CNDF + { OP(0xfff00000, 0xe6d00000), .mnem = "mov64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), FREG64(3), FCOND(16) } }, // MOV64 Ra,Rb,CNDF + { OP(0xfff00000, 0xe6e00000), .mnem = "swapf", RZTYPE(XCHG), .len = 4, .ops = { FREG64(0), FREG64(3), FCOND(16) } }, // SWAPF Ra,Rb,CNDF + { OP(0xffffffc0, 0xe6f10000), .mnem = "fracf32", RZTYPE(CAST), .len = 4, .ops = { FREG(0), FREG(3) } }, // FRACF32 RaH,RbH + { OP(0xffffffc0, 0xe6f18000), .mnem = "fracf64", RZTYPE(CAST), .len = 4, .ops = { FREG64(0), FREG64(3) } }, // FRACF64 Ra,Rb + { OP(0xffffffc0, 0xe6f40000), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREG(0), FREGL(3) } }, // MOV32 RaH,RbL + { OP(0xffffffc0, 0xe6f50000), .mnem = "mov32", RZTYPE(MOV), .len = 4, .ops = { FREGL(0), FREG(3) } }, // MOV32 RaL,RbH + { OP(0xffff0000, 0xe7000000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3), FREG(6) } }, // MPYF32 RaH,RbH,RcH + { OP(0xffff0000, 0xe7100000), .mnem = "addf32", RZTYPE(ADD), .len = 4, .ops = { FREG(0), FREG(3), FREG(6) } }, // ADDF32 RaH,RbH,RcH + { OP(0xffff0000, 0xe7200000), .mnem = "subf32", RZTYPE(SUB), .len = 4, .ops = { FREG(0), FREG(3), FREG(6) } }, // SUBF32 RaH,RbH,RcH + { OP(0xfffc0000, 0xe7400000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3), FREG(6), PAR(ADDF32), FREG(9), FREG(12), FREG(15) } }, // MPYF32 RaH,RbH,RcH || ADDF32 RdH,ReH,RfH + { OP(0xfffc0000, 0xe7500000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), FREG(3), FREG(6), PAR(SUBF32), FREG(9), FREG(12), FREG(15) } }, // MPYF32 RaH,RbH,RcH || SUBF32 RdH,ReH,RfH + { OP(0xffff0000, 0xe7800000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(0), FREG64(3), FREG64(6) } }, // MPYF64 Ra,Rb,Rc + { OP(0xffff0000, 0xe7900000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(0), FREG64(3), FREG64(6) } }, // ADDF64 Ra,Rb,Rc + { OP(0xffff0000, 0xe7a00000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(0), FREG64(3), FREG64(6) } }, // SUBF64 Ra,Rb,Rc + { OP(0xfff00000, 0xe7c00000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(0), FREG64(3), FREG64(6), PAR(ADDF64), FREG64(9), FREG64(12), FREG64(15) } }, // MPYF64 Ra,Rb,Rc || ADDF64 Rd,Re,Rf + { OP(0xfff00000, 0xe7d00000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(0), FREG64(3), FREG64(6), PAR(SUBF64), FREG64(9), FREG64(12), FREG64(15) } }, // MPYF64 Ra,Rb,Rc || SUBF64 Rd,Re,Rf + { OP(0xfff80000, 0xe8000000), .mnem = "moviz", RZTYPE(MOV), .len = 4, .ops = { FREG64(0), IMMU(3, 16) } }, // MOVIZ Ra,#16bit + { OP(0xfff80000, 0xe8080000), .mnem = "movxi", RZTYPE(MOV), .len = 4, .ops = { FREG(0), IMMU(3, 16) } }, // MOVXI RaH,#16bit + { OP(0xfff80000, 0xe8100000), .mnem = "cmpf32", RZTYPE(CMP), .len = 4, .ops = { FREG(0), IMMU(3, 16) } }, // CMPF32 RaH,#16bit + { OP(0xfff80000, 0xe8200000), .mnem = "maxf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), IMMU(3, 16) } }, // MAXF32 RaH,#16bit + { OP(0xfff80000, 0xe8300000), .mnem = "minf32", RZTYPE(CMOV), .len = 4, .ops = { FREG(0), IMMU(3, 16) } }, // MINF32 RaH,#16bit + { OP(0xffc00000, 0xe8400000), .mnem = "mpyf32", RZTYPE(MUL), .len = 4, .ops = { FREG(0), IMMU(6, 16), FREG(3) } }, // MPYF32 RaH,#16bit,RbH + { OP(0xffc00000, 0xe8800000), .mnem = "addf32", RZTYPE(ADD), .len = 4, .ops = { FREG(0), IMMU(6, 16), FREG(3) } }, // ADDF32 RaH,#16bit,RbH + { OP(0xffc00000, 0xe8c00000), .mnem = "subf32", RZTYPE(SUB), .len = 4, .ops = { FREG(0), IMMU(6, 16), FREG(3) } }, // SUBF32 RaH,#16bit,RbH + { OP(0xfff80000, 0xe9000000), .mnem = "movix", RZTYPE(MOV), .len = 4, .ops = { FREGL(0), IMMU(3, 16) } }, // MOVIX RaL,#16bit + { OP(0xfff80000, 0xe9080000), .mnem = "movxi", RZTYPE(MOV), .len = 4, .ops = { FREGL(0), IMMU(3, 16) } }, // MOVXI RaL,#16bit + { OP(0xfff80000, 0xe9100000), .mnem = "cmpf64", RZTYPE(CMP), .len = 4, .ops = { FREG64(0), IMMU(3, 16) } }, // CMPF64 Ra,#16bit + { OP(0xfff80000, 0xe9200000), .mnem = "maxf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), IMMU(3, 16) } }, // MAXF64 Ra,#16bit + { OP(0xfff80000, 0xe9300000), .mnem = "minf64", RZTYPE(CMOV), .len = 4, .ops = { FREG64(0), IMMU(3, 16) } }, // MINF64 Ra,#16bit + { OP(0xffc00000, 0xe9400000), .mnem = "mpyf64", RZTYPE(MUL), .len = 4, .ops = { FREG64(0), IMMU(6, 16), FREG64(3) } }, // MPYF64 Ra,#16bit,Rb + { OP(0xffc00000, 0xe9800000), .mnem = "addf64", RZTYPE(ADD), .len = 4, .ops = { FREG64(0), IMMU(6, 16), FREG64(3) } }, // ADDF64 Ra,#16bit,Rb + { OP(0xffc00000, 0xe9c00000), .mnem = "subf64", RZTYPE(SUB), .len = 4, .ops = { FREG64(0), IMMU(6, 16), FREG64(3) } }, // SUBF64 Ra,#16bit,Rb + { OP(0xffff0000, 0xfff00000), .mnem = "push", RZTYPE(PUSH), .ops = { REG(RB) } }, // PUSH RB + { OP(0xffff0000, 0xfff10000), .mnem = "pop", RZTYPE(POP), .ops = { REG(RB) } }, // POP RB + // clang-format on diff --git a/librz/arch/isa/tms320/c28x/c28x_rowundefs.h b/librz/arch/isa/tms320/c28x/c28x_rowundefs.h index 5acc065886..26c65afb37 100644 --- a/librz/arch/isa/tms320/c28x/c28x_rowundefs.h +++ b/librz/arch/isa/tms320/c28x/c28x_rowundefs.h @@ -37,6 +37,15 @@ #undef AXAT #undef INTRN #undef RPTABLE +#undef FREG +#undef FREGFIX +#undef FREGL +#undef FREG64 +#undef FREGM +#undef FCOND +#undef FFLAGS +#undef FSETFLG +#undef FZERO #undef PAR #undef VRREGH #undef VRREGL4 diff --git a/librz/arch/meson.build b/librz/arch/meson.build index a7f56e2c7e..f0dac12147 100644 --- a/librz/arch/meson.build +++ b/librz/arch/meson.build @@ -342,6 +342,7 @@ arch_isa_sources = [ 'isa/tms320/c28x/c28x_analysis.c', 'isa/tms320/c28x/c28x_il.c', 'isa/tms320/c28x/c28x_il_vcu.c', + 'isa/tms320/c28x/c28x_il_fpu.c', 'isa/tms320/tms320c55x_insn.c', 'isa/v810/v810_disas.c', 'isa/v810/v810_il.c', diff --git a/librz/arch/p/analysis/analysis_tms320.c b/librz/arch/p/analysis/analysis_tms320.c index a6905d03a6..7eaaa91d62 100644 --- a/librz/arch/p/analysis/analysis_tms320.c +++ b/librz/arch/p/analysis/analysis_tms320.c @@ -650,7 +650,51 @@ static char *get_reg_profile(RZ_BORROW RzAnalysis *a) { "gpr eallow .1 86.0 0\n" // Protected-register write enable "gpr loop .1 87.0 0\n" // LOOPZ/LOOPNZ in progress "ctr dbgstat .16 132 0\n" // Debug status, saved with IER on interrupts - "gpr idlestat .1 134.0 0\n"); // IDLE in progress + "gpr idlestat .1 134.0 0\n" // IDLE in progress + "fpu r0 .64 136 0\n" // FPU register; RnH and RnL are its halves + "fpu r0h .32 140 0\n" + "fpu r0l .32 136 0\n" + "fpu r1 .64 144 0\n" + "fpu r1h .32 148 0\n" + "fpu r1l .32 144 0\n" + "fpu r2 .64 152 0\n" + "fpu r2h .32 156 0\n" + "fpu r2l .32 152 0\n" + "fpu r3 .64 160 0\n" + "fpu r3h .32 164 0\n" + "fpu r3l .32 160 0\n" + "fpu r4 .64 168 0\n" + "fpu r4h .32 172 0\n" + "fpu r4l .32 168 0\n" + "fpu r5 .64 176 0\n" + "fpu r5h .32 180 0\n" + "fpu r5l .32 176 0\n" + "fpu r6 .64 184 0\n" + "fpu r6h .32 188 0\n" + "fpu r6l .32 184 0\n" + "fpu r7 .64 192 0\n" + "fpu r7h .32 196 0\n" + "fpu r7l .32 192 0\n" + "gpr lvf .1 200.0 0\n" // Latched overflow + "gpr luf .1 200.1 0\n" // Latched underflow + "gpr nf .1 200.2 0\n" // Negative float + "gpr zf .1 200.3 0\n" // Zero float + "gpr ni .1 200.4 0\n" // Negative integer + "gpr zi .1 200.5 0\n" // Zero integer + "gpr tf .1 200.6 0\n" // Test flag + "gpr rnd32 .1 201.0 0\n" // Round to nearest (else to zero), 32-bit + "gpr rnd64 .1 201.1 0\n" // The same for 64-bit + "gpr shdws .1 201.2 0\n" // Shadow registers hold SAVE state + "gpr rb .32 204 0\n" // Repeat block + "fpu r0s .64 208 0\n" // SAVE/RESTORE shadow of Rn + "fpu r1s .64 216 0\n" + "fpu r2s .64 224 0\n" + "fpu r3s .64 232 0\n" + "fpu r4s .64 240 0\n" + "fpu r5s .64 248 0\n" + "fpu r6s .64 256 0\n" + "fpu r7s .64 264 0\n" + "ctr stfs .32 272 0\n"); // SAVE/RESTORE shadow of STF } if (cpu0 && rz_str_casecmp(cpu0, "c5x") == 0) { // TMS320C5x: the C2x register file plus the C5x additions — the 32-bit diff --git a/test/db/asm/tms320_c28x_32 b/test/db/asm/tms320_c28x_32 index 987e951b5f..007d7d03bf 100644 --- a/test/db/asm/tms320_c28x_32 +++ b/test/db/asm/tms320_c28x_32 @@ -144,6 +144,173 @@ d "vcmac vr5, vr4, vr3, vr2, vr1, vr0" 01e5 0x0 d "vccmac vr5, vr4, vr3, vr2, vr1, vr0" 0fe5 0x0 d "vitbm2 vr0" 0ce5 0x0 d "vitbm3 vr0, vr1, vr2" 0de5 0x0 +# FPU32, FPU64, TMU and fast integer division; texts agree with TI dis2000 20.2.6.LTS +d "mov32 r0h, @acc" a9bd120f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var acc)) (bv 8 0x20) false))) +d "mov32 r0l, @acc" a9bd100f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff00000000)) (cast 64 false (var acc)))) +d "mov32 r0h, @acc" a9bd110f 0x0 (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var acc)) (bv 8 0x20) false))) +d "mov32 r7h, @xt" acbd2e0f 0x0 (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var xt)) (bv 8 0x20) false))) +d "mov32 r4l, @p" abbd200f 0x0 (set r4 (| (& (var r4) (bv 64 0xffffffff00000000)) (cast 64 false (var p)))) +d "mov32 r0h, *xar4++" 84bd120f 0x0 (seq (set _ea (var xar4)) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (bv 8 0x20) false))) (set xar4 (+ (var xar4) (bv 32 0x2)))) +d "mov32 @acc, r0h" a9bf120f 0x0 (seq (set acc (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set n (msb (var acc))) (set z (is_zero (var acc)))) +d "mov32 @xar5, r7h" a5bf2e0f 0x0 (set xar5 (cast 32 false (>> (var r7) (bv 8 0x20) false))) +d "movst0 lvf,ni,zi,ci" 69ad 0x0 (seq nop (set v (|| (var lvf) false)) (set lvf false) (set n (|| false (var ni))) (set z (|| false (var zi)))) +d "mpyf32 r3h, r7h, r2h || mov32 *-sp[30], r7h" 05e05edf 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x1e)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "addf32 r3h, r7h, r1h || mov32 @0x1f, r2h" 13e01fda 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x1f))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "subf32 r5h, r7h, r4h || mov32 *-sp[38], r2h" 29e066ea 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "mpyf64 r6, r3, r5 || mov32 @0x14, r6h" 4ae014f6 0x0 (seq (set xa (var r3)) (set xb (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x14))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r5, r1, r2 || mov32 *-sp[5], r3h" 54e0456b 0x0 (seq (set xa (var r1)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x5)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r7, r6, r2 || mov32 *-sp[48], r0h" 65e070b8 0x0 (seq (set xa (var r6)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x30)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "mpyf64 r6, r7, r4 || mov32 *-sp[2], r5l" 89e042f5 0x0 (seq (set xa (var r7)) (set xb (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x2)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r5))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r5, r7, r1 || mov32 *+xar1[2], r6l" 93e0d1ee 0x0 (seq (set xa (var r7)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (+ (var xar1) (bv 32 0x2))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r6))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r6, r6, r3 || mov32 *sp++, r5l" a7e0bdb5 0x0 (seq (set xa (var r6)) (set xb (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (var sp))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r5))) (set sp (+ (var sp) (bv 16 0x2))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "mov32 *+xar1[3], stf" 00e2d9dd 0x0 (seq (set _ea (+ (var xar1) (bv 32 0x3))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (| (| (| (| (| (| (| (| (| (ite (var shdws) (bv 32 0x80000000) (bv 32 0x0)) (ite (var lvf) (bv 32 0x1) (bv 32 0x0))) (ite (var luf) (bv 32 0x2) (bv 32 0x0))) (ite (var nf) (bv 32 0x4) (bv 32 0x0))) (ite (var zf) (bv 32 0x8) (bv 32 0x0))) (ite (var ni) (bv 32 0x10) (bv 32 0x0))) (ite (var zi) (bv 32 0x20) (bv 32 0x0))) (ite (var tf) (bv 32 0x40) (bv 32 0x0))) (ite (var rnd32) (bv 32 0x200) (bv 32 0x0))) (ite (var rnd64) (bv 32 0x400) (bv 32 0x0))))) +d "mov32 *+xar4[2], r3l" 02e2d4eb 0x0 (seq (set _ea (+ (var xar4) (bv 32 0x2))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (var r3)))) +d "mov32 *+xar2[ar0], r5h" 03e29295 0x0 (seq (set _ea (+ (var xar2) (cast 32 false (cast 16 false (var xar0))))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) +d "mov16 *-sp[28], r5h" 13e25c05 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1c)))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (cast 16 false (cast 32 false (>> (var r5) (bv 8 0x20) false))))) +d "f32dtof64 r1, *+xar6[0]" 21e2c601 0x0 (seq (set _ea (+ (var xar6) (bv 32 0x0))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x2))) (bv 32 0x2)) (var xa)) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r1 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000))))))) +d "movd32 r7h, *+xar5[5]" 23e2ed2f 0x0 (seq (set _ea (+ (var xar5) (bv 32 0x5))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x2))) (bv 32 0x2)) (var mv)) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv)))) +d "movdd32 r0l, @0x36" 42e23618 0x0 +d "movdd32 r6h, @0x28" 43e22866 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x28))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (storew 0 (* (cast 32 false (+ (var _ea) (bv 32 0x4))) (bv 32 0x2)) (var mv)) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv)))) +d "macf32 r0h, r2h, *+xar1[1], *xar7++" 50e2c990 0x0 +d "mpy2pif32 r2h, r4h" 70e22200 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dp (*. rne (fconvert ieee754-bin64 rne (var fa)) (float 1 (bv 64 0x401921fb54442d18) ))) (set dx (! (<. (fabs (var dp)) (float 1 (bv 64 0x47effffff0000000) )))) (set dv (ite (var dx) (ite (is_fneg (var dp)) (bv 32 0xff800000) (bv 32 0x7f800000)) (fbits (fconvert ieee754-bin32 rne (var dp))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (var dx)))) +d "div2pif32 r0h, r4h" 71e22000 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dp (*. rne (fconvert ieee754-bin64 rne (var fa)) (float 1 (bv 64 0x3fc45f306dc9c883) ))) (set dx (&& (! (is_fzero (var dp))) (<. (fabs (var dp)) (float 1 (bv 64 0x3810000000000000) )))) (set dv (ite (var dx) (bv 32 0x0) (fbits (fconvert ieee754-bin32 rne (var dp))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set luf (|| (var luf) (var dx)))) +d "log2f32 r7h, r4h" 72e22700 0x0 +d "iexp2f32 r0h, r1h" 73e20800 0x0 +d "divf32 r0h, r6h, r0h" 74e23000 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set za (is_fzero (var fa))) (set zb (is_fzero (var fb))) (set ia (is_inf (var fa))) (set ib (is_inf (var fb))) (set na (&& (! (var za)) (! (var ia)))) (set fin (&& (var na) (&& (! (var zb)) (! (var ib))))) (set dq (/. rne (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set dov (&& (var fin) (! (<. (fabs (var dq)) (float 1 (bv 64 0x47f0000000000000) ))))) (set dun (&& (var fin) (<. (fabs (var dq)) (float 1 (bv 64 0x3810000000000000) )))) (set dv (ite (var za) (bv 32 0x0) (ite (|| (var ia) (var zb)) (ite (^^ (is_fneg (var fa)) (is_fneg (var fb))) (bv 32 0xff800000) (bv 32 0x7f800000)) (ite (var ib) (bv 32 0x0) (ite (var dun) (bv 32 0x0) (ite (var dov) (ite (^^ (is_fneg (var fa)) (is_fneg (var fb))) (bv 32 0xff800000) (bv 32 0x7f800000)) (fbits (/. rne (var fa) (var fb))))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (|| (|| (&& (var za) (var zb)) (&& (var ia) (! (var ib)))) (|| (&& (var na) (var zb)) (var dov))))) (set luf (|| (var luf) (|| (var ib) (var dun))))) +d "sqrtf32 r3h, r2h" 77e21300 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set dneg (is_fneg (var fa))) (set dinf (&& (is_inf (var fa)) (! (var dneg)))) (set dv (ite (var dneg) (bv 32 0x0) (ite (var dinf) (bv 32 0x7f800000) (fbits (fsqrt rne (var fa)))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dv)) (bv 8 0x20) false))) (set lvf (|| (var lvf) (|| (var dneg) (var dinf))))) +d "sinpuf32 r2h, r1h" 78e20a00 0x0 +d "cospuf32 r3h, r7h" 79e23b00 0x0 +d "atanpuf32 r5h, r1h" 7ae20d00 0x0 +d "quadf32 r5h, r7h, r3h, r4h" 7ce2fd08 0x0 +d "mov32 stf, *-sp[53]" 80e27500 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x35)))) (set sw (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) nop (set lvf (! (is_zero (& (var sw) (bv 32 0x1))))) (set luf (! (is_zero (& (var sw) (bv 32 0x2))))) (set nf (! (is_zero (& (var sw) (bv 32 0x4))))) (set zf (! (is_zero (& (var sw) (bv 32 0x8))))) (set ni (! (is_zero (& (var sw) (bv 32 0x10))))) (set zi (! (is_zero (& (var sw) (bv 32 0x20))))) (set tf (! (is_zero (& (var sw) (bv 32 0x40))))) (set rnd32 (! (is_zero (& (var sw) (bv 32 0x200))))) (set rnd64 (! (is_zero (& (var sw) (bv 32 0x400)))))) +d "ui32tof32 r5h, *-sp[31]" 84e25f05 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1f)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "ui32tof64 r1, *-sp[1]" 85e24101 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x1)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (fbits (fcast_float ieee754-bin64 rne (var xa))))) +d "i32tof32 r7h, *-sp[3]" 88e24307 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x3)))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "i32tof64 r3, *arp0" 89e2b003 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r3 (fbits (fcast_sfloat ieee754-bin64 rne (var xa)))) (set arp (bv 3 0x0))) +d "f32tof64 r3, @0x12" 8ce21203 0x0 (seq (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x12))) (set xa (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r3 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000))))))) +d "mov32 r2l, *+xar7[1]" 98e2cfc2 0x0 +d "mov32 r6h, *-sp[38], unc" aee2660e 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (branch true (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) nop)) +d "ui16tof32 r7h, *arp7" c4e2b707 0x0 (seq (set _ea (ite (== (var arp) (bv 3 0x0)) (var xar0) (ite (== (var arp) (bv 3 0x1)) (var xar1) (ite (== (var arp) (bv 3 0x2)) (var xar2) (ite (== (var arp) (bv 3 0x3)) (var xar3) (ite (== (var arp) (bv 3 0x4)) (var xar4) (ite (== (var arp) (bv 3 0x5)) (var xar5) (ite (== (var arp) (bv 3 0x6)) (var xar6) (var xar7))))))))) (set xa (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false))) (set arp (bv 3 0x7))) +d "i16tof32 r2h, *-sp[49]" c8e27102 0x0 (seq (set _ea (cast 32 false (- (var sp) (bv 16 0x31)))) (set xa (loadw 0 16 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "mpyf32 r1h, r7h, r1h || mov32 r1h, *+xar7[7]" 03e3ffc9 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (+ (var xar7) (bv 32 0x7))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "addf32 r7h, r2h, r2h || mov32 r3h, *--xar4" 14e38cbb 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set xar4 (- (var xar4) (bv 32 0x2))) (set _ea (var xar4)) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "subf32 r4h, r4h, r3h || mov32 r7h, *-sp[22]" 27e35627 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x16)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "macf32 r3h, r2h, r0h, r5h, r0h || mov32 r2h, *-sp[40]" 31e36842 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x28)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (*. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false)))) +d "mpyf64 r0, r3, r2 || mov32 r1h, *-sp[28]" 44e35cc1 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x1c)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r7, r5, r6 || mov32 r4h, @0x35" 5de3357c 0x0 (seq (set xa (var r5)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x35))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r4, r4, r2 || mov32 r0h, *+xar7[2]" 65e3d720 0x0 (seq (set xa (var r4)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (+ (var xar7) (bv 32 0x2))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r4 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "macf64 r3, r2, r0, r7, r6 || mov32 r1h, @0x0e" 7de30ec1 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r7)) (set yb (var r6)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0xe))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r0 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "mpyf64 r0, r6, r4 || mov32 r2l, @0x3c" 89e33c82 0x0 (seq (set xa (var r6)) (set xb (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x3c))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r3, r4, r2 || mov32 r6l, *-sp[38]" 95e3661e 0x0 (seq (set xa (var r4)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0x26)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r1, r0, r2 || mov32 r2l, @0x33" a4e3330a 0x0 (seq (set xa (var r0)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x33))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r1 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "macf64 r3, r2, r0, r6, r4 || mov32 r5l, @0x20" b9e32085 0x0 (seq (set xa (var r3)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r4)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x20))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r0 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "macf32 r7h, r6h, r4h, r1h, r2h || mov32 r2h, @0x1b" c4e31b62 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x1b))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (*. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false)))) +d "macf64 r7, r6, r1, r6, r1 || mov32 r6h, @0x22" d3e3228e 0x0 (seq (set xa (var r7)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r1)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (| (<< (cast 32 false (var dp)) (bv 32 0x6) false) (bv 32 0x22))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r1 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "macf64 r7, r6, r5, r2, r5 || mov32 r5l, *-sp[11]" eae34bad 0x0 (seq (set xa (var r7)) (set xb (var r6)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r2)) (set yb (var r5)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set _ea (cast 32 false (- (var sp) (bv 16 0xb)))) (set mv (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2)))) (set r5 (| (& (var r5) (bv 64 0xffffffff00000000)) (cast 64 false (var mv)))) (set zf (is_zero (& (var mv) (bv 32 0x7f800000)))) (set nf (&& (msb (var mv)) (! (is_zero (& (var mv) (bv 32 0x7f800000)))))) (set ni (msb (var mv))) (set zi (is_zero (var mv))) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r7 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (*. rne (var ga) (var gb))) (set gr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (|| (&& (is_zero (var ge)) (var gm)) (&& (is_zero (& (var gr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var ga))) (! (is_fzero (var gb))))))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r5 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "restore" 62e5 0x0 (seq (set sw (var stfs)) nop (set lvf (! (is_zero (& (var sw) (bv 32 0x1))))) (set luf (! (is_zero (& (var sw) (bv 32 0x2))))) (set nf (! (is_zero (& (var sw) (bv 32 0x4))))) (set zf (! (is_zero (& (var sw) (bv 32 0x8))))) (set ni (! (is_zero (& (var sw) (bv 32 0x10))))) (set zi (! (is_zero (& (var sw) (bv 32 0x20))))) (set tf (! (is_zero (& (var sw) (bv 32 0x40))))) (set rnd32 (! (is_zero (& (var sw) (bv 32 0x200))))) (set rnd64 (! (is_zero (& (var sw) (bv 32 0x400))))) (set r0 (var r0s)) (set r1 (var r1s)) (set r2 (var r2s)) (set r3 (var r3s)) (set r4 (var r4s)) (set r5 (var r5s)) (set r6 (var r6s)) (set r7 (var r7s)) (set shdws false)) +d "zeroa" 63e5 0x0 (seq (set r0 (bv 64 0x0)) (set r1 (bv 64 0x0)) (set r2 (bv 64 0x0)) (set r3 (bv 64 0x0)) (set r4 (bv 64 0x0)) (set r5 (bv 64 0x0)) (set r6 (bv 64 0x0)) (set r7 (bv 64 0x0))) +d "subc4ui32 r2h, r1h, r3h" 64e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set zi false) (set lvf (|| (var lvf) (is_zero (var dd)))) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 33 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 33 0x1) (bv 33 0x0))) (cast 33 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 32 0x1) (bv 32 0x0))) (cast 32 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 32 0x1)))) (set dr (var dq)) (set zi (is_zero (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "subc2ui64 r2h:r4h, r1h:r0h, r3h:r5h" 65e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set zi false) (set lvf (|| (var lvf) (is_zero (var dd)))) (set dt (- (+ (<< (cast 65 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 65 0x1) (bv 65 0x0))) (cast 65 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 64 0x1) (bv 64 0x0))) (cast 64 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 64 0x1)))) (set dr (var dq)) (set dt (- (+ (<< (cast 65 false (var dr)) (bv 8 0x1) false) (ite (msb (var dn)) (bv 65 0x1) (bv 65 0x0))) (cast 65 false (var dd)))) (set dq (ite (msb (var dt)) (| (<< (var dr) (bv 8 0x1) false) (ite (msb (var dn)) (bv 64 0x1) (bv 64 0x0))) (cast 64 false (var dt)))) (set dn (ite (msb (var dt)) (<< (var dn) (bv 8 0x1) false) (| (<< (var dn) (bv 8 0x1) false) (bv 64 0x1)))) (set dr (var dq)) (set zi (is_zero (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "subc3f64 r2, r1, r3" 66e5 0x0 +d "absi32div32 r2h, r1h, r3h" 68e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 32 0x80000000)) (== (var dd) (bv 32 0x80000000))))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dd)) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "absi32div32u r2h, r1h" 69e5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 32 0x80000000)))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "negi32div32 r1h, r2h" 6ae5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "enegi32div32 r1h, r2h, r3h" 6be5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 32 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "mnegi32div32 r1h, r2h, r3h" 6ce5 0x0 (seq (set dn (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 32 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var dn)) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "testtf tf" 8ae5 0x0 (set tf (var tf)) +d "zero r5" 95e5 0x0 (set r5 (bv 64 0x0)) +d "cmpf32 r1h, #0.0" a1e5 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set xb (bv 32 0x0)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "absi64div32 r2h, r1h:r0h, r3h" a8e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 64 0x8000000000000000)) (== (var dd) (bv 32 0x80000000))))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (var dd)) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "absi64div32u r2h, r1h:r0h" a9e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 64 0x8000000000000000)))) (set dr (bv 32 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "negi64div32 r1h:r0h, r2h" aae5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "enegi64div32 r1h:r0h, r2h, r3h" abe5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "mnegi64div32 r1h:r0h, r2h, r3h" ace5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set dr (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (var dr)) (bv 8 0x20) false)))) +d "cmpf64 r2, #0.0" b2e5 0x0 (seq (set xa (var r2)) (set xb (bv 64 0x0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "absi64div64 r2h:r4h, r1h:r0h, r3h:r5h" b8e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set ni (msb (var dn))) (set tf (^^ (msb (var dn)) (msb (var dd)))) (set lvf (|| (var lvf) (|| (== (var dn) (bv 64 0x8000000000000000)) (== (var dd) (bv 64 0x8000000000000000))))) (set dr (bv 64 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set dd (ite (msb (var dd)) (~- (var dd)) (var dd))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dd) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dd))) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "absi64div64u r2h:r4h, r1h:r0h" b9e5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set ni (msb (var dn))) (set tf (msb (var dn))) (set lvf (|| (var lvf) (== (var dn) (bv 64 0x8000000000000000)))) (set dr (bv 64 0x0)) (set dn (ite (msb (var dn)) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "negi64div64 r1h:r0h, r2h:r4h" bae5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (var ni) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "enegi64div64 r1h:r0h, r2h:r4h, r3h:r5h" bbe5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set da (&& (var ni) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "mnegi64div64 r1h:r0h, r2h:r4h, r3h:r5h" bce5 0x0 (seq (set dn (append (cast 32 false (>> (var r1) (bv 8 0x20) false)) (cast 32 false (>> (var r0) (bv 8 0x20) false)))) (set dd (append (cast 32 false (>> (var r3) (bv 8 0x20) false)) (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set dr (append (cast 32 false (>> (var r2) (bv 8 0x20) false)) (cast 32 false (>> (var r4) (bv 8 0x20) false)))) (set da (&& (var tf) (! (var zi)))) (set dn (ite (var da) (+ (var dn) (bv 64 0x1)) (var dn))) (set dr (ite (var da) (- (var dd) (var dr)) (var dr))) (set dn (ite (var tf) (~- (var dn)) (var dn))) (set dr (ite (^^ (var ni) (var tf)) (~- (var dr)) (var dr))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dn) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dn))) (bv 8 0x20) false))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (>> (var dr) (bv 8 0x20) false))) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (var dr))) (bv 8 0x20) false)))) +d "predivf64 r0h, r2, r1, r3" bee5 0x0 +d "postdivf64 r1, r0h" bfe5 0x0 +d "setflg luf=0,zf=0,ni=1,zi=0,rndq32=1,rndf32=1" 19e695d7 0x0 (seq nop (set luf false) (set zf false) (set ni true) (set zi false) (set rnd32 true)) +d "save nf=0,zf=1,ni=1,zi=0,tf=1,rndq16=1" 47e6dae1 0x0 (seq (set stfs (| (| (| (| (| (| (| (| (| (ite (var shdws) (bv 32 0x80000000) (bv 32 0x0)) (ite (var lvf) (bv 32 0x1) (bv 32 0x0))) (ite (var luf) (bv 32 0x2) (bv 32 0x0))) (ite (var nf) (bv 32 0x4) (bv 32 0x0))) (ite (var zf) (bv 32 0x8) (bv 32 0x0))) (ite (var ni) (bv 32 0x10) (bv 32 0x0))) (ite (var zi) (bv 32 0x20) (bv 32 0x0))) (ite (var tf) (bv 32 0x40) (bv 32 0x0))) (ite (var rnd32) (bv 32 0x200) (bv 32 0x0))) (ite (var rnd64) (bv 32 0x400) (bv 32 0x0)))) (set r0s (var r0)) (set r1s (var r1)) (set r2s (var r2)) (set r3s (var r3)) (set r4s (var r4)) (set r5s (var r5)) (set r6s (var r6)) (set r7s (var r7)) nop (set nf false) (set zf true) (set ni true) (set zi false) (set tf true) (set shdws true)) +d "f64toi32 r0h, r1" 84e60800 0x0 (seq (set xa (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_sfloat ieee754-bin64 rtz (bv 32 0x7fffffff)) (var fr)) (bv 32 0x7fffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin64 rtz (bv 32 0x80000000))) (bv 32 0x80000000) (fcast_sint 32 rtz (var fr))))) (bv 8 0x20) false)))) +d "f64toi64 r3, r5" 84e62b80 0x0 (seq (set xa (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r3 (ite (<. (fcast_sfloat ieee754-bin64 rtz (bv 64 0x7fffffffffffffff)) (var fr)) (bv 64 0x7fffffffffffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin64 rtz (bv 64 0x8000000000000000))) (bv 64 0x8000000000000000) (fcast_sint 64 rtz (var fr)))))) +d "i32tof64 r2, r5h" 85e62a00 0x0 (seq (set xa (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set r2 (fbits (fcast_sfloat ieee754-bin64 rne (var xa))))) +d "i64tof64 r6, r7" 85e63e80 0x0 (seq (set xa (var r7)) (set r6 (fbits (fcast_sfloat ieee754-bin64 rne (var xa))))) +d "f64toui32 r5h, r3" 86e61d00 0x0 (seq (set xa (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_float ieee754-bin64 rtz (bv 32 0xffffffff)) (var fr)) (bv 32 0xffffffff) (ite (<. (var fr) (fcast_float ieee754-bin64 rtz (bv 32 0x0))) (bv 32 0x0) (fcast_int 32 rtz (var fr))))) (bv 8 0x20) false)))) +d "f64toui64 r1, r4" 86e62180 0x0 (seq (set xa (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (ite (<. (fcast_float ieee754-bin64 rtz (bv 64 0xffffffffffffffff)) (var fr)) (bv 64 0xffffffffffffffff) (ite (<. (var fr) (fcast_float ieee754-bin64 rtz (bv 64 0x0))) (bv 64 0x0) (fcast_int 64 rtz (var fr)))))) +d "ui32tof64 r0, r1h" 87e60800 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set r0 (fbits (fcast_float ieee754-bin64 rne (var xa))))) +d "ui64tof64 r0, r4" 87e62080 0x0 (seq (set xa (var r4)) (set r0 (fbits (fcast_float ieee754-bin64 rne (var xa))))) +d "f32toi32 r1h, r6h" 88e63100 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 32 0x7fffffff)) (var fr)) (bv 32 0x7fffffff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 32 0x80000000))) (bv 32 0x80000000) (fcast_sint 32 rtz (var fr))))) (bv 8 0x20) false)))) +d "i32tof32 r1h, r6h" 89e63100 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "f32toui32 r1h, r4h" 8ae62100 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 32 0xffffffff)) (var fr)) (bv 32 0xffffffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 32 0x0))) (bv 32 0x0) (fcast_int 32 rtz (var fr))))) (bv 8 0x20) false)))) +d "ui32tof32 r4h, r2h" 8be61400 0x0 (seq (set xa (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "f32toi16 r6h, r0h" 8ce60600 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 (msb (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr))))) (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr)))))) (bv 8 0x20) false)))) +d "f32toi16r r2h, r7h" 8ce63a80 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rne (var fa))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 (msb (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr))))) (ite (<. (fcast_sfloat ieee754-bin32 rtz (bv 16 0x7fff)) (var fr)) (bv 16 0x7fff) (ite (<. (var fr) (fcast_sfloat ieee754-bin32 rtz (bv 16 0x8000))) (bv 16 0x8000) (fcast_sint 16 rtz (var fr)))))) (bv 8 0x20) false)))) +d "i16tof32 r0h, r5h" 8de62800 0x0 (seq (set xa (cast 16 false (cast 32 false (>> (var r5) (bv 8 0x20) false)))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_sfloat ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "f32toui16 r7h, r7h" 8ee63f00 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rtz (var fa))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 16 0xffff)) (var fr)) (bv 16 0xffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 16 0x0))) (bv 16 0x0) (fcast_int 16 rtz (var fr)))))) (bv 8 0x20) false)))) +d "f32toui16r r2h, r5h" 8ee62a80 0x0 (seq (set xa (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fr (fround rne (var fa))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (cast 32 false (ite (<. (fcast_float ieee754-bin32 rtz (bv 16 0xffff)) (var fr)) (bv 16 0xffff) (ite (<. (var fr) (fcast_float ieee754-bin32 rtz (bv 16 0x0))) (bv 16 0x0) (fcast_int 16 rtz (var fr)))))) (bv 8 0x20) false)))) +d "ui16tof32 r2h, r1h" 8fe60a00 0x0 (seq (set xa (cast 16 false (cast 32 false (>> (var r1) (bv 8 0x20) false)))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (fbits (fcast_float ieee754-bin32 rne (var xa)))) (bv 8 0x20) false)))) +d "f64tof32 r1h, r4" 90e62100 0x0 (seq (set xa (var r4)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set xr (fbits (fconvert ieee754-bin32 (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa)))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "f32tof64 r4, r4h" 91e62400 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xr (fbits (fconvert ieee754-bin64 rne (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )))) (set r4 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000))))))) +d "eisqrtf32 r0h, r5h" 92e62800 0x0 +d "eisqrtf64 r6, r4" 92e62680 0x0 +d "einvf32 r4h, r0h" 93e60400 0x0 +d "einvf64 r4, r6" 93e63480 0x0 +d "cmpf32 r3h, r2h" 94e61300 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "absf32 r1h, r0h" 95e60100 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xr (& (var xa) (bv 32 0x7fffffff))) (set r1 (| (& (var r1) (bv 64 0xffffffff)) (<< (cast 64 false (var xr)) (bv 8 0x20) false))) (set zf (is_zero (& (var xr) (bv 32 0x7f800000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 32 0x7f800000))))))) +d "maxf32 r3h, r7h" 96e63b00 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "minf32 r3h, r3h" 97e61b00 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "cmpf64 r0, r7" 98e63800 0x0 (seq (set xa (var r0)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "absf64 r6, r5" 99e62e00 0x0 (seq (set xa (var r5)) (set xr (& (var xa) (bv 64 0x7fffffffffffffff))) (set r6 (var xr)) (set zf (is_zero (& (var xr) (bv 64 0x7ff0000000000000)))) (set nf (&& (msb (var xr)) (! (is_zero (& (var xr) (bv 64 0x7ff0000000000000))))))) +d "maxf64 r1, r0" 9ae60100 0x0 (seq (set xa (var r1)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r1 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr))))) +d "minf64 r5, r2" 9be61500 0x0 (seq (set xa (var r5)) (set xb (var r2)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr))))) +d "maxf32 r4h, r5h || mov32 r0h, r7h" 9ce62cae 0x0 (seq (set pd (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r4 (| (& (var r4) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))) (branch (var mt) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var pd)) (bv 8 0x20) false))) nop)) +d "minf32 r3h, r1h || mov32 r5h, r2h" 9de64bb5 0x0 (seq (set pd (cast 32 false (>> (var r2) (bv 8 0x20) false))) (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false))) (branch (var mt) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (var pd)) (bv 8 0x20) false))) nop)) +d "maxf64 r1, r1 || mov64 r3, r2" 9ee6c9c4 0x0 (seq (set pd (var r2)) (set xa (var r1)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r1 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))) (branch (var mt) (set r3 (var pd)) nop)) +d "minf64 r5, r7 || mov64 r3, r5" 9fe6fd9a 0x0 (seq (set pd (var r5)) (set xa (var r5)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr)))) (branch (var mt) (set r3 (var pd)) nop)) +d "negf32 r0h, r1h, geq" a3e68817 0x0 (seq (set xa (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set xr (ite (! (var nf)) (^ (var xa) (bv 32 0x80000000)) (var xa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (var xr)) (bv 8 0x20) false)))) +d "negf64 r5, r5" b7e6adb9 0x0 +d "mov32 r6h, r4h, lu" cce666ec 0x0 (seq (set mv (cast 32 false (>> (var r4) (bv 8 0x20) false))) (branch (var luf) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (var mv)) (bv 8 0x20) false))) nop)) +d "mov64 r4, r0" d6e6c471 0x0 +d "swapf r3, r1, unc" eee68be1 0x0 (branch true (seq (set sa (var r3)) (set r3 (var r1)) (set r1 (var sa))) nop) +d "fracf32 r0h, r4h" f1e62000 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set xr (fbits (-. rne (var fa) (fround rtz (var fa))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "fracf64 r6, r5" f1e62e80 0x0 (seq (set xa (var r5)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set xr (fbits (-. rne (var fa) (fround rtz (var fa))))) (set r6 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr))))) +d "mov32 r0h, r5l" f4e62800 0x0 +d "mov32 r7l, r3h" f5e61f00 0x0 +d "mpyf32 r0h, r6h, r0h" 00e730a8 0x0 (seq (set xa (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "addf32 r3h, r3h, r3h" 10e7dbde 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "subf32 r6h, r4h, r5h" 20e766b3 0x0 (seq (set xa (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r6 (| (& (var r6) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "mpyf32 r7h, r7h, r5h || addf32 r7h, r7h, r6h" 43e77f7f 0x0 (seq (set xa (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r5) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (+. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false)))) +d "mpyf32 r2h, r3h, r1h || subf32 r5h, r6h, r4h" 52e75a6a 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (cast 32 false (>> (var r1) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set ya (cast 32 false (>> (var r6) (bv 8 0x20) false))) (set yb (cast 32 false (>> (var r4) (bv 8 0x20) false))) (set ga (float 0 (ite (is_zero (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var ya) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var ya) (bv 32 0xff800000)) (var ya))) )) (set gb (float 0 (ite (is_zero (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var yb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var yb) (bv 32 0xff800000)) (var yb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false))) (set gw (-. rtz (fconvert ieee754-bin64 rne (var ga)) (fconvert ieee754-bin64 rne (var gb)))) (set gr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x17) false) (bv 32 0xff))) (set gm (! (is_zero (& (var gr) (bv 32 0x7fffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (! (<. (fabs (var gw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r5 (| (& (var r5) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var gt) (bv 32 0x0) (ite (&& (== (var ge) (bv 32 0xff)) (var gm)) (bv 32 0x7f800000) (var gr)))) (bv 8 0x20) false)))) +d "mpyf64 r2, r7, r1" 80e77afa 0x0 (seq (set xa (var r7)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r2 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r6, r0, r1" 90e746ac 0x0 (seq (set xa (var r0)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r3, r6, r3" a0e7f374 0x0 (seq (set xa (var r6)) (set xb (var r3)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r3 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "mpyf64 r0, r7, r7 || addf64 r6, r6, r0" cce7f86d 0x0 (seq (set xa (var r7)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r0)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (+. rne (var ga) (var gb))) (set gr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r6 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "mpyf64 r0, r0, r0 || subf64 r5, r6, r4" dee7006a 0x0 (seq (set xa (var r0)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set ya (var r6)) (set yb (var r4)) (set ga (float 1 (ite (is_zero (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var ya) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var ya) (bv 64 0xfff0000000000000)) (var ya))) )) (set gb (float 1 (ite (is_zero (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var yb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var yb) (bv 64 0xfff0000000000000)) (var yb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r0 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr)))) (set gw (-. rne (var ga) (var gb))) (set gr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var ga) (var gb)))) (set ge (& (>> (var gr) (bv 8 0x34) false) (bv 64 0x7ff))) (set gm (! (is_zero (& (var gr) (bv 64 0xfffffffffffff))))) (set gt (&& (is_zero (var ge)) (var gm))) (set luf (|| (var luf) (var gt))) (set lvf (|| (var lvf) (&& (&& (is_finite (var ga)) (is_finite (var gb))) (is_inf (var gw))))) (set r5 (ite (var gt) (bv 64 0x0) (ite (&& (== (var ge) (bv 64 0x7ff)) (var gm)) (bv 64 0x7ff0000000000000) (var gr))))) +d "moviz r0, #0x67c5" 03e8283e 0x0 (set r0 (bv 64 0x67c5000000000000)) +d "movxi r3h, #0x2c77" 09e8bb63 0x0 (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (| (& (cast 32 false (>> (var r3) (bv 8 0x20) false)) (bv 32 0xffff0000)) (bv 32 0x2c77))) (bv 8 0x20) false))) +d "cmpf32 r0h, #0x34dc" 11e8e0a6 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xb (bv 32 0x34dc0000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "maxf32 r0h, #0x7914" 23e8a0c8 0x0 (seq (set xa (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set xb (bv 32 0x79140000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "minf32 r3h, #0x63ce" 33e8731e 0x0 (seq (set xa (cast 32 false (>> (var r3) (bv 8 0x20) false))) (set xb (bv 32 0x63ce0000)) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r3 (| (& (var r3) (bv 64 0xffffffff)) (<< (cast 64 false (ite (&& (is_zero (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff))) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (bv 32 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (! (is_zero (& (var xr) (bv 32 0x7fffff))))) (& (var xr) (bv 32 0xff800000)) (var xr)))) (bv 8 0x20) false)))) +d "mpyf32 r7h, #0x4b81, r7h" 52e87fe0 0x0 (seq (set xa (bv 32 0x4b810000)) (set xb (cast 32 false (>> (var r7) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (*. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (*. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 32 0x7fffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r7 (| (& (var r7) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "addf32 r0h, #0x6187, r0h" 98e8c061 0x0 (seq (set xa (bv 32 0x61870000)) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (+. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (+. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r0 (| (& (var r0) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "subf32 r2h, #0xc674, r0h" f1e8029d 0x0 (seq (set xa (bv 32 0xc6740000)) (set xb (cast 32 false (>> (var r0) (bv 8 0x20) false))) (set fa (float 0 (ite (is_zero (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xa) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xa) (bv 32 0xff800000)) (var xa))) )) (set fb (float 0 (ite (is_zero (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff))) (bv 32 0x0) (ite (== (& (>> (var xb) (bv 8 0x17) false) (bv 32 0xff)) (bv 32 0xff)) (& (var xb) (bv 32 0xff800000)) (var xb))) )) (set fw (-. rtz (fconvert ieee754-bin64 rne (var fa)) (fconvert ieee754-bin64 rne (var fb)))) (set fr (fbits (-. (ite (var rnd32) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x17) false) (bv 32 0xff))) (set fm (! (is_zero (& (var fr) (bv 32 0x7fffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (! (<. (fabs (var fw)) (ite (var rnd32) (float 1 (bv 64 0x47effffff0000000) ) (float 1 (bv 64 0x47f0000000000000) ))))))) (set r2 (| (& (var r2) (bv 64 0xffffffff)) (<< (cast 64 false (ite (var ft) (bv 32 0x0) (ite (&& (== (var fe) (bv 32 0xff)) (var fm)) (bv 32 0x7f800000) (var fr)))) (bv 8 0x20) false)))) +d "movix r7l, #0x22cb" 01e95f16 0x0 (set r7 (| (& (var r7) (bv 64 0xffffffff00000000)) (cast 64 false (| (& (cast 32 false (var r7)) (bv 32 0xffff)) (bv 32 0x22cb0000))))) +d "movxi r4l, #0xcc36" 0ee9b461 0x0 (set r4 (| (& (var r4) (bv 64 0xffffffff00000000)) (cast 64 false (| (& (cast 32 false (var r4)) (bv 32 0xffff0000)) (bv 32 0xcc36))))) +d "cmpf64 r7, #0xa9e4" 15e9274f 0x0 (seq (set xa (var r7)) (set xb (bv 64 0xa9e4000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb)))) +d "maxf64 r7, #0x9d41" 24e90fea 0x0 (seq (set xa (var r7)) (set xb (bv 64 0x9d41000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fa) (var fb))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r7 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr))))) +d "minf64 r5, #0x884f" 34e97d42 0x0 (seq (set xa (var r5)) (set xb (bv 64 0x884f000000000000)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set mt (<. (var fb) (var fa))) (set zf (&& (! (<. (var fa) (var fb))) (! (<. (var fb) (var fa))))) (set nf (<. (var fa) (var fb))) (set xr (ite (var mt) (var xb) (var xa))) (set r5 (ite (&& (is_zero (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff))) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (bv 64 0x0) (ite (&& (== (& (>> (var xr) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (! (is_zero (& (var xr) (bv 64 0xfffffffffffff))))) (& (var xr) (bv 64 0xfff0000000000000)) (var xr))))) +d "mpyf64 r6, #0x8675, r0" 61e9469d 0x0 (seq (set xa (bv 64 0x8675000000000000)) (set xb (var r0)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (*. rne (var fa) (var fb))) (set fr (fbits (*. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (|| (&& (is_zero (var fe)) (var fm)) (&& (is_zero (& (var fr) (bv 64 0x7fffffffffffffff))) (&& (! (is_fzero (var fa))) (! (is_fzero (var fb))))))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r6 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "addf64 r1, #0x8516, r1" a1e98945 0x0 (seq (set xa (bv 64 0x8516000000000000)) (set xb (var r1)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (+. rne (var fa) (var fb))) (set fr (fbits (+. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r1 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "subf64 r5, #0x55a9, r7" d5e97d6a 0x0 (seq (set xa (bv 64 0x55a9000000000000)) (set xb (var r7)) (set fa (float 1 (ite (is_zero (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xa) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xa) (bv 64 0xfff0000000000000)) (var xa))) )) (set fb (float 1 (ite (is_zero (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff))) (bv 64 0x0) (ite (== (& (>> (var xb) (bv 8 0x34) false) (bv 64 0x7ff)) (bv 64 0x7ff)) (& (var xb) (bv 64 0xfff0000000000000)) (var xb))) )) (set fw (-. rne (var fa) (var fb))) (set fr (fbits (-. (ite (var rnd64) (bv 32 0x0) (bv 32 0x4)) (var fa) (var fb)))) (set fe (& (>> (var fr) (bv 8 0x34) false) (bv 64 0x7ff))) (set fm (! (is_zero (& (var fr) (bv 64 0xfffffffffffff))))) (set ft (&& (is_zero (var fe)) (var fm))) (set luf (|| (var luf) (var ft))) (set lvf (|| (var lvf) (&& (&& (is_finite (var fa)) (is_finite (var fb))) (is_inf (var fw))))) (set r5 (ite (var ft) (bv 64 0x0) (ite (&& (== (var fe) (bv 64 0x7ff)) (var fm)) (bv 64 0x7ff0000000000000) (var fr))))) +d "push rb" f0ff 0x0 (seq (set _ea (cast 32 false (var sp))) (storew 0 (* (cast 32 false (var _ea)) (bv 32 0x2)) (var rb)) (set sp (+ (var sp) (bv 16 0x2)))) +d "pop rb" f1ff 0x0 (seq (set sp (- (var sp) (bv 16 0x2))) (set _ea (cast 32 false (var sp))) (set rb (loadw 0 32 (* (cast 32 false (var _ea)) (bv 32 0x2))))) +d "mov32 r2h, @0x34" a6e23412 0x0 +d "setflg" 00e60000 0x0 nop +d "movst0 #0" 00ad 0x0 nop # VCU parallel forms, second-word operands, FFT and CRC; texts agree with TI dis2000 20.2.6.LTS d "vcfft2 vr7, vr6, vr4, vr2, vr1, vr0, #0x1" 31a1 0x0 d "vcfft3 vr5, vr4, vr3, vr2, vr0, #0x1" 33a1 0x0 diff --git a/test/db/rzil/tms320_c28x b/test/db/rzil/tms320_c28x index 9a785ab1c6..48d989ebb3 100644 --- a/test/db/rzil/tms320_c28x +++ b/test/db/rzil/tms320_c28x @@ -3038,3 +3038,2408 @@ vrevb vr1 vr1 = 0x78563412 EOF RUN + +# FPU32, FPU64 and TMU + +NAME=C28x RzIL VM: FPU arithmetic, compare and 32-bit conversions +FILE=malloc://8192 +CMDS=<