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Implement V_FFBH_I32 (#3965)
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@@ -219,6 +219,7 @@ public:
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void V_NOT_B32(const GcnInst& inst);
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void V_BFREV_B32(const GcnInst& inst);
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void V_FFBH_U32(const GcnInst& inst);
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void V_FFBH_I32(const GcnInst& inst);
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void V_FFBL_B32(const GcnInst& inst);
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void V_FREXP_EXP_I32_F64(const GcnInst& inst);
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void V_FREXP_MANT_F64(const GcnInst& inst);
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@@ -188,6 +188,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_FFBH_U32(inst);
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case Opcode::V_FFBL_B32:
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return V_FFBL_B32(inst);
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case Opcode::V_FFBH_I32:
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return V_FFBH_I32(inst);
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case Opcode::V_FREXP_EXP_I32_F64:
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return V_FREXP_EXP_I32_F64(inst);
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case Opcode::V_FREXP_MANT_F64:
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@@ -948,6 +950,19 @@ void Translator::V_FFBL_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.FindILsb(src0));
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}
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void Translator::V_FFBH_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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// Gcn wants the MSB position counting from the left, but SPIR-V counts from the rightmost (LSB)
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// position
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const IR::U32 msb_pos = ir.FindSMsb(src0);
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const IR::U32 pos_from_left = ir.ISub(ir.Imm32(31), msb_pos);
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// Select 0xFFFFFFFF if src0 was 0 or -1
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const IR::U32 minusOne = ir.Imm32(~0U);
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const IR::U1 cond =
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ir.LogicalAnd(ir.INotEqual(src0, ir.Imm32(0)), ir.INotEqual(src0, minusOne));
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SetDst(inst.dst[0], IR::U32{ir.Select(cond, pos_from_left, minusOne)});
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}
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void Translator::V_FREXP_EXP_I32_F64(const GcnInst& inst) {
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const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
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SetDst(inst.dst[0], ir.FPFrexpExp(src0));
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