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Add AVX and AVX2 runtime feature detection (GH #671)
There are no corresponding defines in config.h at the moment. Programs will have to use the preprocessor macros __AVX__ and __AVX2__ to determine when they are available.
This commit is contained in:
Jeffrey Walton
parent
207c6fcb1a
commit
0ccdc197b7
49
cpu.cpp
49
cpu.cpp
@ -21,6 +21,14 @@
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# include <unistd.h>
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#endif
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//#if CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X86
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//# if defined(_MSC_VER)
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//# include <intrin.h>
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//# else
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//# include <immintrin.h>
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//# endif
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//#endif
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// Capability queries, requires Glibc 2.16, http://lwn.net/Articles/519085/
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// CRYPTOPP_GLIBC_VERSION not used because config.h is missing <feature.h>
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#if (((__GLIBC__ * 100) + __GLIBC_MINOR__) >= 216)
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@ -187,6 +195,8 @@ bool CRYPTOPP_SECTION_INIT g_hasSSE2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSSE3 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE41 = false;
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bool CRYPTOPP_SECTION_INIT g_hasSSE42 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAVX = false;
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bool CRYPTOPP_SECTION_INIT g_hasAVX2 = false;
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bool CRYPTOPP_SECTION_INIT g_hasAESNI = false;
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bool CRYPTOPP_SECTION_INIT g_hasCLMUL = false;
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bool CRYPTOPP_SECTION_INIT g_hasADX = false;
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@ -245,12 +255,38 @@ void DetectX86Features()
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g_hasAESNI = g_hasSSE2 && ((cpuid1[2] & (1<<25)) != 0);
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g_hasCLMUL = g_hasSSE2 && ((cpuid1[2] & (1<< 1)) != 0);
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// AVX is similar to SSE, but check both bits 27 (SSE) and 28 (AVX).
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// https://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
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CRYPTOPP_CONSTANT(YMM_FLAG = (3 << 1))
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CRYPTOPP_CONSTANT(AVX_FLAG = (3 << 27))
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if ((cpuid1[2] & AVX_FLAG) == AVX_FLAG)
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{
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#if defined(__GNUC__)
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// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71659 and
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// http://www.agner.org/optimize/vectorclass/read.php?i=65
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word32 a=0, d=0;
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__asm __volatile
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(
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// GCC 4.1/Binutils 2.17 cannot consume xgetbv
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// "xgetbv" : "=a"(a), "=d"(d) : "c"(0) :
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".byte 0x0f, 0x01, 0xd0" "\n\t"
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: "=a"(a), "=d"(d) : "c"(0) :
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);
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word64 xcr0 = a | static_cast<word64>(d) << 32;
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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#else
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word64 xcr0 = _xgetbv(0);
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g_hasAVX = (xcr0 & YMM_FLAG) == YMM_FLAG;
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#endif
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}
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if (IsIntel(cpuid0))
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{
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CRYPTOPP_CONSTANT(RDRAND_FLAG = (1 << 30))
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CRYPTOPP_CONSTANT(RDSEED_FLAG = (1 << 18))
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CRYPTOPP_CONSTANT( ADX_FLAG = (1 << 19))
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CRYPTOPP_CONSTANT( SHA_FLAG = (1 << 29))
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CRYPTOPP_CONSTANT( AVX2_FLAG = (1 << 5))
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g_isP4 = ((cpuid1[0] >> 8) & 0xf) == 0xf;
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g_cacheLineSize = 8 * GETBYTE(cpuid1[1], 1);
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@ -263,6 +299,7 @@ void DetectX86Features()
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g_hasRDSEED = (cpuid2[1] /*EBX*/ & RDSEED_FLAG) != 0;
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g_hasADX = (cpuid2[1] /*EBX*/ & ADX_FLAG) != 0;
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g_hasSHA = (cpuid2[1] /*EBX*/ & SHA_FLAG) != 0;
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g_hasAVX2 = (cpuid2[1] /*EBX*/ & AVX2_FLAG) != 0;
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}
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}
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}
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@ -272,6 +309,7 @@ void DetectX86Features()
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CRYPTOPP_CONSTANT(RDSEED_FLAG = (1 << 18))
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CRYPTOPP_CONSTANT( ADX_FLAG = (1 << 19))
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CRYPTOPP_CONSTANT( SHA_FLAG = (1 << 29))
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CRYPTOPP_CONSTANT( AVX2_FLAG = (1 << 5))
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CpuId(0x80000005, 0, cpuid2);
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g_cacheLineSize = GETBYTE(cpuid2[2], 0);
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@ -284,6 +322,7 @@ void DetectX86Features()
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g_hasRDSEED = (cpuid2[1] /*EBX*/ & RDSEED_FLAG) != 0;
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g_hasADX = (cpuid2[1] /*EBX*/ & ADX_FLAG) != 0;
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g_hasSHA = (cpuid2[1] /*EBX*/ & SHA_FLAG) != 0;
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g_hasAVX2 = (cpuid2[1] /*EBX*/ & AVX2_FLAG) != 0;
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}
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}
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}
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@ -300,11 +339,11 @@ void DetectX86Features()
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{
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// Extended features available
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CpuId(0xC0000001, 0, cpuid2);
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g_hasPadlockRNG = (cpuid2[3] /*EDX*/ & RNG_FLAGS) != 0;
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g_hasPadlockACE = (cpuid2[3] /*EDX*/ & ACE_FLAGS) != 0;
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g_hasPadlockACE2 = (cpuid2[3] /*EDX*/ & ACE2_FLAGS) != 0;
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g_hasPadlockPHE = (cpuid2[3] /*EDX*/ & PHE_FLAGS) != 0;
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g_hasPadlockPMM = (cpuid2[3] /*EDX*/ & PMM_FLAGS) != 0;
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g_hasPadlockRNG = (cpuid2[3] /*EDX*/ & RNG_FLAGS) == RNG_FLAGS;
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g_hasPadlockACE = (cpuid2[3] /*EDX*/ & ACE_FLAGS) == ACE_FLAGS;
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g_hasPadlockACE2 = (cpuid2[3] /*EDX*/ & ACE2_FLAGS) == ACE2_FLAGS;
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g_hasPadlockPHE = (cpuid2[3] /*EDX*/ & PHE_FLAGS) == PHE_FLAGS;
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g_hasPadlockPMM = (cpuid2[3] /*EDX*/ & PMM_FLAGS) == PMM_FLAGS;
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}
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}
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30
cpu.h
30
cpu.h
@ -85,6 +85,8 @@ extern CRYPTOPP_DLL bool g_hasSSE2;
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extern CRYPTOPP_DLL bool g_hasSSSE3;
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extern CRYPTOPP_DLL bool g_hasSSE41;
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extern CRYPTOPP_DLL bool g_hasSSE42;
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extern CRYPTOPP_DLL bool g_hasAVX;
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extern CRYPTOPP_DLL bool g_hasAVX2;
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extern CRYPTOPP_DLL bool g_hasAESNI;
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extern CRYPTOPP_DLL bool g_hasCLMUL;
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extern CRYPTOPP_DLL bool g_hasSHA;
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@ -158,6 +160,7 @@ inline bool HasSSE42()
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/// \brief Determines AES-NI availability
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/// \returns true if AES-NI is determined to be available, false otherwise
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/// \details HasAESNI() is a runtime check performed using CPUID
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/// \since Crypto++ 5.6.1
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasAESNI()
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{
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@ -169,6 +172,7 @@ inline bool HasAESNI()
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/// \brief Determines Carryless Multiply availability
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/// \returns true if pclmulqdq is determined to be available, false otherwise
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/// \details HasCLMUL() is a runtime check performed using CPUID
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/// \since Crypto++ 5.6.1
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasCLMUL()
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{
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@ -180,6 +184,7 @@ inline bool HasCLMUL()
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/// \brief Determines SHA availability
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/// \returns true if SHA is determined to be available, false otherwise
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/// \details HasSHA() is a runtime check performed using CPUID
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/// \since Crypto++ 6.0
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasSHA()
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{
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@ -191,6 +196,7 @@ inline bool HasSHA()
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/// \brief Determines ADX availability
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/// \returns true if ADX is determined to be available, false otherwise
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/// \details HasADX() is a runtime check performed using CPUID
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/// \since Crypto++ 7.0
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasADX()
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{
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@ -199,6 +205,30 @@ inline bool HasADX()
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return g_hasADX;
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}
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/// \brief Determines AVX availability
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/// \returns true if AVX is determined to be available, false otherwise
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/// \details HasAVX() is a runtime check performed using CPUID
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/// \since Crypto++ 7.1
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasAVX()
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{
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if (!g_x86DetectionDone)
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DetectX86Features();
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return g_hasAVX;
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}
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/// \brief Determines AVX2 availability
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/// \returns true if AVX2 is determined to be available, false otherwise
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/// \details HasAVX2() is a runtime check performed using CPUID
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/// \since Crypto++ 7.1
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/// \note This function is only available on Intel IA-32 platforms
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inline bool HasAVX2()
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{
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if (!g_x86DetectionDone)
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DetectX86Features();
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return g_hasAVX2;
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}
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/// \brief Determines if the CPU is an Intel P4
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/// \returns true if the CPU is a P4, false otherwise
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/// \details IsP4() is a runtime check performed using CPUID
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15
validat1.cpp
15
validat1.cpp
@ -369,11 +369,20 @@ bool TestSettings()
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bool hasSSSE3 = HasSSSE3();
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bool hasSSE41 = HasSSE41();
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bool hasSSE42 = HasSSE42();
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bool hasAVX = HasAVX();
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bool hasAVX2 = HasAVX2();
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bool hasAESNI = HasAESNI();
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bool hasCLMUL = HasCLMUL();
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bool hasRDRAND = HasRDRAND();
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bool hasRDSEED = HasRDSEED();
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bool hasSHA = HasSHA();
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bool isP4 = IsP4();
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std::cout << "hasSSE2 == " << hasSSE2 << ", hasSSSE3 == " << hasSSSE3 << ", hasSSE4.1 == " << hasSSE41 << ", hasSSE4.2 == " << hasSSE42;
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std::cout << ", hasAESNI == " << HasAESNI() << ", hasCLMUL == " << HasCLMUL() << ", hasRDRAND == " << HasRDRAND() << ", hasRDSEED == " << HasRDSEED();
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std::cout << ", hasSHA == " << HasSHA() << ", isP4 == " << isP4 << "\n";
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std::cout << "hasSSE2 == " << hasSSE2 << ", hasSSSE3 == " << hasSSSE3 << ", hasSSE4.1 == " << hasSSE41;
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std::cout << ", hasSSE4.2 == " << hasSSE42 << ", hasAVX == " << hasAVX << ", hasAVX2 == " << hasAVX2;
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std::cout << ", hasAESNI == " << hasAESNI << ", hasCLMUL == " << hasCLMUL << ", hasRDRAND == " << HasRDRAND;
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std::cout << ", hasRDSEED == " << HasRDSEED << ", hasSHA == " << HasSHA() << ", isP4 == " << isP4;
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std::cout << "\n";
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#elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
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bool hasNEON = HasNEON();
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