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Jeffrey Walton
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93
ppc_simd.h
93
ppc_simd.h
@ -64,7 +64,7 @@
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//
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// inline uint32x4_p VecLoad(const byte src[16])
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// {
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// #if defined(_ARCH_PWR8)
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// #if defined(__VSX__) || defined(_ARCH_PWR8)
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// return (uint32x4_p) *(uint8x16_p*)((byte*)src);
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// #else
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// return VecLoad_ALTIVEC(src);
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@ -180,15 +180,13 @@ typedef __vector unsigned int uint32x4_p;
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#if defined(__VSX__) || defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Vector of 64-bit elements
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/// \details uint64x2_p is available on POWER7 with VSX and above. Some supporting
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/// functions, like 64-bit <tt>vec_add</tt> (<tt>vaddudm</tt>), did not
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/// arrive until POWER8. GCC supports <tt>vec_xl</tt> and <tt>vec_xst</tt>
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/// for 64-bit elements, but other compilers do not.
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/// \details uint64x2_p is available on POWER7 with VSX and above. Most
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/// supporting functions, like 64-bit <tt>vec_add</tt> (<tt>vaddudm</tt>)
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/// and <tt>vec_sub</tt> (<tt>vsubudm</tt>), did not arrive until POWER8.
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/// \par Wraps
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/// __vector unsigned long long
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/// \since Crypto++ 6.0
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typedef __vector unsigned long long uint64x2_p;
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#endif // VSX or ARCH_PWR8
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/// \brief The 0 vector
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@ -374,7 +372,7 @@ inline uint32x4_p VecLoad(const word32 src[4])
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#if defined(_ARCH_PWR9)
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return (uint32x4_p)vec_xl(0, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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return (uint32x4_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(CONST_V8_CAST(addr));
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@ -406,7 +404,7 @@ inline uint32x4_p VecLoad(int off, const word32 src[4])
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#if defined(_ARCH_PWR9)
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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return (uint32x4_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(CONST_V8_CAST(addr));
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@ -440,7 +438,7 @@ inline uint64x2_p VecLoad(const word64 src[2])
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#if defined(_ARCH_PWR9)
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return (uint64x2_p)vec_xl(0, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// The 32-bit cast is not a typo. Compiler workaround.
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return (uint64x2_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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@ -474,7 +472,7 @@ inline uint64x2_p VecLoad(int off, const word64 src[2])
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#if defined(_ARCH_PWR9)
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return (uint64x2_p)vec_xl(off, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// The 32-bit cast is not a typo. Compiler workaround.
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return (uint64x2_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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@ -560,7 +558,7 @@ inline uint32x4_p VecLoadAligned(const word32 src[4])
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#if defined(_ARCH_PWR9)
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return (uint32x4_p)vec_xl(0, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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return (uint32x4_p)vec_xl(0, CONST_V32_CAST(src));
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#else
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return (uint32x4_p)vec_ld(0, CONST_V8_CAST(src));
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@ -589,7 +587,7 @@ inline uint32x4_p VecLoadAligned(int off, const word32 src[4])
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#if defined(_ARCH_PWR9)
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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return (uint32x4_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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return (uint32x4_p)vec_ld(off, CONST_V8_CAST(src));
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@ -620,7 +618,7 @@ inline uint64x2_p VecLoadAligned(const word64 src[4])
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#if defined(_ARCH_PWR9)
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return (uint64x2_p)vec_xl(0, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// The 32-bit cast is not a typo. Compiler workaround.
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return (uint64x2_p)vec_xl(0, CONST_V32_CAST(src));
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#else
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@ -650,7 +648,7 @@ inline uint64x2_p VecLoadAligned(int off, const word64 src[4])
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#if defined(_ARCH_PWR9)
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return (uint64x2_p)vec_xl(off, CONST_V8_CAST(src));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// The 32-bit cast is not a typo. Compiler workaround.
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return (uint64x2_p)vec_xl(0, CONST_V32_CAST(addr));
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#else
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@ -905,7 +903,7 @@ inline void VecStore(const T data, word32 dest[4])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, 0, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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VecStore_ALTIVEC((uint8x16_p)data, NCONST_V8_CAST(addr));
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@ -940,7 +938,7 @@ inline void VecStore(const T data, int off, word32 dest[4])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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VecStore_ALTIVEC((uint8x16_p)data, NCONST_V8_CAST(addr));
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@ -975,7 +973,7 @@ inline void VecStore(const T data, word64 dest[2])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, 0, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// 32-bit cast is not a typo. Compiler workaround.
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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@ -1012,7 +1010,7 @@ inline void VecStore(const T data, int off, word64 dest[2])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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// 32-bit cast is not a typo. Compiler workaround.
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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@ -1107,7 +1105,7 @@ inline void VecStoreAligned(const T data, word32 dest[4])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, 0, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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vec_st((uint8x16_p)data, 0, NCONST_V8_CAST(addr));
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@ -1141,7 +1139,7 @@ inline void VecStoreAligned(const T data, int off, word32 dest[4])
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#if defined(_ARCH_PWR9)
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vec_xst((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#elif (defined(_ARCH_PWR7) && defined(__VSX__)) || defined(_ARCH_PWR8)
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#elif defined(__VSX__) || defined(_ARCH_PWR8)
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vec_xst((uint32x4_p)data, 0, NCONST_V32_CAST(addr));
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#else
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vec_st((uint8x16_p)data, 0, NCONST_V8_CAST(addr));
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@ -1650,6 +1648,7 @@ inline uint32x4_p VecShiftRight(const uint32x4_p vec)
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return vec_sr(vec, m);
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}
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// 64-bit elements available at POWER7 with VSX, but vec_rl and vec_sl require POWER8
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#if defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Rotate a vector left
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@ -1762,10 +1761,15 @@ inline T VecMergeHigh(const T vec1, const T vec2)
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/// \brief Broadcast 32-bit word to a vector
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/// \param val the 32-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splats
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/// \since Crypto++ 8.3
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inline uint32x4_p VecSplatWord(word32 val)
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{
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#if defined(_ARCH_PWR8)
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// Apple Altivec does not offer vec_splats. GCC offers
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// vec_splats back to -mcpu=power4. We can't test
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// further back because -mcpu=power3 is not supported.
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#if defined(_ARCH_PWR4)
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return vec_splats(val);
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#else
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const word32 x[4] = {val,val,val,val};
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@ -1777,41 +1781,21 @@ inline uint32x4_p VecSplatWord(word32 val)
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/// \tparam the element number
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/// \param val the 32-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splat
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/// \since Crypto++ 8.3
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template <unsigned int N>
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inline uint32x4_p VecSplatElement(const uint32x4_p val)
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{
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#if defined(_ARCH_PWR8)
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return vec_splat(val, N);
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#else
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enum {E=N&3};
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if (E == 0)
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{
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const uint8x16_p m = {0,1,2,3, 0,1,2,3, 0,1,2,3, 0,1,2,3};
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return vec_perm(val, val, m);
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}
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else if (E == 1)
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{
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const uint8x16_p m = {4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7};
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return vec_perm(val, val, m);
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}
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else if (E == 2)
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{
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const uint8x16_p m = {8,9,10,11, 8,9,10,11, 8,9,10,11, 8,9,10,11};
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return vec_perm(val, val, m);
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}
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else // (E == 3)
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{
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const uint8x16_p m = {12,13,14,15, 12,13,14,15, 12,13,14,15, 12,13,14,15};
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return vec_perm(val, val, m);
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}
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#endif
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}
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#if defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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#if defined(__VSX__) || defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Broadcast 64-bit double word to a vector
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/// \param val the 64-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splats
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/// \since Crypto++ 8.3
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inline uint64x2_p VecSplatWord(word64 val)
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{
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@ -1823,11 +1807,13 @@ inline uint64x2_p VecSplatWord(word64 val)
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/// \tparam the element number
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/// \param val the 64-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splat
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/// \since Crypto++ 8.3
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template <unsigned int N>
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inline uint64x2_p VecSplatElement(const uint64x2_p val)
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{
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#if defined(_ARCH_PWR8)
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#if defined(__VSX__) || defined(_ARCH_PWR8)
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return vec_splat(val, N);
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#else
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enum {E=N&1};
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@ -2060,6 +2046,7 @@ template<unsigned int C>
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inline uint32x4_p VecRotateLeft64(const uint32x4_p val)
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{
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#if defined(_ARCH_PWR8)
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// 64-bit elements available at POWER7 with VSX, but vec_rl and vec_sl require POWER8
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return (uint32x4_p)VecRotateLeft<C>((uint64x2_p)val);
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#else
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// C=0, 32, or 64 needs special handling. That is S32 and S64 below.
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@ -2111,6 +2098,7 @@ inline uint32x4_p VecRotateLeft64<8>(const uint32x4_p val)
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return VecPermute(val, m);
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}
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// 64-bit elements available at POWER7 with VSX, but vec_rl and vec_sl require POWER8
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#if defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Rotate a vector left as if uint64x2_p
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/// \tparam C rotate bit count
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@ -2141,6 +2129,7 @@ template<unsigned int C>
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inline uint32x4_p VecRotateRight64(const uint32x4_p val)
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{
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#if defined(_ARCH_PWR8)
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// 64-bit elements available at POWER7 with VSX, but vec_rl and vec_sl require POWER8
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return (uint32x4_p)VecRotateRight<C>((uint64x2_p)val);
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#else
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// C=0, 32, or 64 needs special handling. That is S32 and S64 below.
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@ -2193,7 +2182,7 @@ inline uint32x4_p VecRotateRight64<8>(const uint32x4_p val)
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return VecPermute(val, m);
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}
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#if defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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#if defined(__VSX__) || defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Rotate a vector right as if uint64x2_p
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/// \tparam C rotate bit count
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/// \param vec the vector
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@ -2267,6 +2256,8 @@ inline T1 VecXor64(const T1 vec1, const T2 vec2)
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/// \brief Broadcast 64-bit double word to a vector
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/// \param val the 64-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splats
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/// \since Crypto++ 8.3
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inline uint32x4_p VecSplatWord64(word64 val)
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{
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@ -2283,11 +2274,13 @@ inline uint32x4_p VecSplatWord64(word64 val)
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/// \tparam the element number
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/// \param val the 64-bit value
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/// \returns vector
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/// \par Wraps
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/// vec_splat
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/// \since Crypto++ 8.3
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template <unsigned int N>
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inline uint32x4_p VecSplatElement64(const uint32x4_p val)
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{
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#if defined(_ARCH_PWR8)
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#if defined(__VSX__) && defined(_ARCH_PWR8)
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return vec_splat((uint64x2_p)val, N);
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#else
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enum {E=N&1};
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@ -2304,7 +2297,7 @@ inline uint32x4_p VecSplatElement64(const uint32x4_p val)
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#endif
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}
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#if defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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#if defined(__VSX__) || defined(_ARCH_PWR8) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Broadcast 64-bit element to a vector
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/// \tparam the element number
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/// \param val the 64-bit value
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