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Update documentation
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Jeffrey Walton
parent
2c44518fcb
commit
803c1a78e7
47
cpu.h
47
cpu.h
@ -51,7 +51,7 @@ NAMESPACE_BEGIN(CryptoPP)
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
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#define CRYPTOPP_CPUID_AVAILABLE
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#define CRYPTOPP_CPUID_AVAILABLE 1
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// Hide from Doxygen
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#ifndef CRYPTOPP_DOXYGEN_PROCESSING
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@ -82,6 +82,7 @@ CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[
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//! \returns true if SSE2 is determined to be available, false otherwise
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//! \details MMX, SSE and SSE2 are core processor features for x86_64, and
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//! the function always returns true for the platform.
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasSSE2()
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{
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#if CRYPTOPP_BOOL_X64
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@ -96,7 +97,7 @@ inline bool HasSSE2()
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//! \brief Determines SSSE3 availability
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//! \returns true if SSSE3 is determined to be available, false otherwise
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//! \details HasSSSE3() is a runtime check performed using CPUID
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//! \note Some Clang compilers incorrectly omit SSSE3 even though its native to the processor.
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasSSSE3()
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{
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if (!g_x86DetectionDone)
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@ -107,6 +108,7 @@ inline bool HasSSSE3()
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//! \brief Determines SSE4.1 availability
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//! \returns true if SSE4.1 is determined to be available, false otherwise
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//! \details HasSSE41() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasSSE41()
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{
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if (!g_x86DetectionDone)
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@ -117,6 +119,7 @@ inline bool HasSSE41()
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//! \brief Determines SSE4.2 availability
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//! \returns true if SSE4.2 is determined to be available, false otherwise
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//! \details HasSSE42() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasSSE42()
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{
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if (!g_x86DetectionDone)
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@ -127,6 +130,7 @@ inline bool HasSSE42()
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//! \brief Determines AES-NI availability
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//! \returns true if AES-NI is determined to be available, false otherwise
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//! \details HasAESNI() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasAESNI()
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{
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if (!g_x86DetectionDone)
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@ -137,6 +141,7 @@ inline bool HasAESNI()
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//! \brief Determines Carryless Multiply availability
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//! \returns true if pclmulqdq is determined to be available, false otherwise
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//! \details HasCLMUL() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasCLMUL()
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{
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if (!g_x86DetectionDone)
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@ -147,6 +152,7 @@ inline bool HasCLMUL()
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//! \brief Determines SHA availability
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//! \returns true if SHA is determined to be available, false otherwise
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//! \details HasSHA() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasSHA()
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{
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if (!g_x86DetectionDone)
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@ -157,6 +163,7 @@ inline bool HasSHA()
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//! \brief Determines if the CPU is an Intel P4
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//! \returns true if the CPU is a P4, false otherwise
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//! \details IsP4() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool IsP4()
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{
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if (!g_x86DetectionDone)
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@ -167,6 +174,7 @@ inline bool IsP4()
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//! \brief Determines RDRAND availability
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//! \returns true if RDRAND is determined to be available, false otherwise
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//! \details HasRDRAND() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasRDRAND()
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{
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if (!g_x86DetectionDone)
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@ -177,6 +185,7 @@ inline bool HasRDRAND()
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//! \brief Determines RDSEED availability
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//! \returns true if RDSEED is determined to be available, false otherwise
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//! \details HasRDSEED() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasRDSEED()
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{
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if (!g_x86DetectionDone)
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@ -187,6 +196,7 @@ inline bool HasRDSEED()
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//! \brief Determines Padlock RNG availability
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//! \returns true if VIA Padlock RNG is determined to be available, false otherwise
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//! \details HasPadlockRNG() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasPadlockRNG()
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{
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if (!g_x86DetectionDone)
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@ -197,6 +207,7 @@ inline bool HasPadlockRNG()
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//! \brief Determines Padlock ACE availability
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//! \returns true if VIA Padlock ACE is determined to be available, false otherwise
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//! \details HasPadlockACE() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasPadlockACE()
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{
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if (!g_x86DetectionDone)
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@ -207,6 +218,7 @@ inline bool HasPadlockACE()
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//! \brief Determines Padlock ACE2 availability
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//! \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
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//! \details HasPadlockACE2() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasPadlockACE2()
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{
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if (!g_x86DetectionDone)
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@ -217,6 +229,7 @@ inline bool HasPadlockACE2()
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//! \brief Determines Padlock PHE availability
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//! \returns true if VIA Padlock PHE is determined to be available, false otherwise
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//! \details HasPadlockPHE() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasPadlockPHE()
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{
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if (!g_x86DetectionDone)
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@ -227,6 +240,7 @@ inline bool HasPadlockPHE()
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//! \brief Determines Padlock PMM availability
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//! \returns true if VIA Padlock PMM is determined to be available, false otherwise
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//! \details HasPadlockPMM() is a runtime check performed using CPUID
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//! \note This function is only available on Intel IA-32 platforms
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inline bool HasPadlockPMM()
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{
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if (!g_x86DetectionDone)
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@ -247,12 +261,16 @@ inline int GetCacheLineSize()
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DetectX86Features();
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return g_cacheLineSize;
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}
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#endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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#elif (CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64)
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#if CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64 || CRYPTOPP_DOXYGEN_PROCESSING
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// Hide from Doxygen
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#ifndef CRYPTOPP_DOXYGEN_PROCESSING
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extern bool g_ArmDetectionDone;
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extern bool g_hasNEON, g_hasPMULL, g_hasCRC32, g_hasAES, g_hasSHA1, g_hasSHA2;
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void CRYPTOPP_API DetectArmFeatures();
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#endif // CRYPTOPP_DOXYGEN_PROCESSING
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//! \brief Determine if an ARM processor has Advanced SIMD available
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//! \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
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@ -260,6 +278,7 @@ void CRYPTOPP_API DetectArmFeatures();
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
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//! (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasNEON()
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{
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// ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64
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@ -278,6 +297,7 @@ inline bool HasNEON()
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
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//! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasPMULL()
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{
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if (!g_ArmDetectionDone)
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@ -292,6 +312,7 @@ inline bool HasPMULL()
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
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//! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasCRC32()
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{
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#if defined(__aarch32__) || defined(__aarch64__)
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@ -310,6 +331,7 @@ inline bool HasCRC32()
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
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//! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasAES()
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{
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#if defined(__aarch32__) || defined(__aarch64__)
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@ -328,6 +350,7 @@ inline bool HasAES()
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
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//! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasSHA1()
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{
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#if defined(__aarch32__) || defined(__aarch64__)
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@ -346,6 +369,7 @@ inline bool HasSHA1()
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//! \details Runtime support requires compile time support. When compiling with GCC, you may
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//! need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
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//! <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
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//! \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
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inline bool HasSHA2()
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{
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#if defined(__aarch32__) || defined(__aarch64__)
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@ -356,7 +380,10 @@ inline bool HasSHA2()
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return false;
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#endif
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}
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#endif // CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARM64
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// Non-Intel systems
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#if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64)
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//! \brief Provides the cache line size at runtime
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//! \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
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//! \details GetCacheLineSize() provides is an estimate using CRYPTOPP_L1_CACHE_LINE_SIZE.
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@ -365,17 +392,9 @@ inline int GetCacheLineSize()
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{
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return CRYPTOPP_L1_CACHE_LINE_SIZE;
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}
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#endif // Non-Intel systems
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#else
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inline int GetCacheLineSize()
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{
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return CRYPTOPP_L1_CACHE_LINE_SIZE;
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}
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#endif // X86/X32/X64 and ARM
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#endif
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#endif // CRYPTOPP_GENERATE_X64_MASM
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#if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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@ -549,7 +568,7 @@ inline int GetCacheLineSize()
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ASL(labelPrefix##9)\
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AS2( add outputPtr, increment*16)
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#endif // X86/X32/X64
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#endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
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NAMESPACE_END
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