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More Clang and XLC workarounds (PR #904)
I think this is the final set. Clang 3.8 is OK on Ubuntu Xenial. XLC 11.0 is OK on Power 7. Clang 3.4 crashes on gcc110.fsffrance.org, but it looks like another compiler bug. I'm not spending time trying to work around it. Clang sucks days of your life at times...
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@ -11,10 +11,10 @@ int main(int argc, char* argv[])
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__vector unsigned int b = vec_ld(0, (unsigned int*)argv[0]);
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__vector unsigned int c = vec_xor(a, b);
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# if defined(__VSX__)
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__vector unsigned int x = {5,6,7,8};
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__vector unsigned int y = vec_xl(0, (unsigned int*)argv[0]);
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__vector unsigned int z = vec_xor(x, y);
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# if defined(__VSX__)
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__vector unsigned long long xx = {1,2};
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__vector unsigned long long yy = (__vector unsigned long long)y;
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# endif
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@ -8,7 +8,7 @@ int main(int argc, char* argv[])
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{
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#if defined(_ARCH_PWR8)
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__vector unsigned long long r = {1, 2};
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__vector unsigned int s = vec_xl(0, (unsigned int*)argv[0]);
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__vector unsigned int s = vec_xl(0, (unsigned int*)argv[0]); // Power7
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__vector unsigned long long w = (__vector unsigned long long)r;
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__vector unsigned long long x = (__vector unsigned long long)s;
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__vector unsigned long long y = vec_xor(w, x);
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42
ppc_simd.h
42
ppc_simd.h
@ -45,9 +45,9 @@
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/// slightly different implementations.
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/// \since Crypto++ 6.0, LLVM Clang compiler support since Crypto++ 8.0
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// Use __ALTIVEC__, _ARCH_PWR7 and _ARCH_PWR8 when detecting actual
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// availaibility of the feature for the source file being compiled. The
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// preprocessor macros depend on compiler options like -maltivec; and
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// Use __ALTIVEC__, _ARCH_PWR7, __VSX__, and _ARCH_PWR8 when detecting
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// actual availaibility of the feature for the source file being compiled.
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// The preprocessor macros depend on compiler options like -maltivec; and
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// not compiler versions.
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// For GCC see https://gcc.gnu.org/onlinedocs/gcc/Basic-PowerPC-Built-in-Functions.html
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@ -262,11 +262,11 @@ inline uint32x4_p VecLoad(const byte src[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V32_CAST(src));
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#elif defined(__VSX__) // will this ever be taken?
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(off, src);
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#endif
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@ -290,11 +290,11 @@ inline uint32x4_p VecLoad(int off, const byte src[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V32_CAST(src));
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#elif defined(__VSX__) // will this ever be taken?
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(off, src);
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#endif
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@ -393,11 +393,11 @@ inline uint32x4_p VecLoadAligned(const byte src[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V32_CAST(src));
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#elif defined(__VSX__) // will this ever be taken?
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(off, src);
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#endif
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@ -420,11 +420,11 @@ inline uint32x4_p VecLoadAligned(int off, const byte src[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V8_CAST(src));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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return (uint32x4_p)vec_xl(off, CONST_V32_CAST(src));
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#elif defined(__VSX__) // will this ever be taken?
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return (uint32x4_p)vec_vsx_ld(off, CONST_V32_CAST(src));
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#else
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return (uint32x4_p)VecLoad_ALTIVEC(off, src);
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#endif
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@ -582,11 +582,11 @@ inline void VecStore(const T data, byte dest[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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vec_xst((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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vec_vsx_st((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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vec_xst((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#elif defined(__VSX__) // will this ever be taken?
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vec_vsx_st((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#else
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VecStore_ALTIVEC((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#endif
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@ -613,11 +613,11 @@ inline void VecStore(const T data, int off, byte dest[16])
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#if defined(_ARCH_PWR9)
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// ISA 3.0 provides vec_xl for short* and char*
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vec_xst((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#elif defined(__VSX__) && defined(__GNUC__) && !defined(__clang__)
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vec_vsx_st((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#elif defined(_ARCH_PWR7)
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#elif defined(_ARCH_PWR7) && defined(__VSX__)
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// ISA 2.06 provides vec_xl, but it lacks short* and char*
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vec_xst((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#elif defined(__VSX__) // will this ever be taken?
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vec_vsx_st((uint32x4_p)data, off, NCONST_V32_CAST(dest));
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#else
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VecStore_ALTIVEC((uint8x16_p)data, off, NCONST_V8_CAST(dest));
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#endif
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