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Fix Aarch64 RotateRight32<8> typo
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@ -18,15 +18,6 @@
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// #undef CRYPTOPP_SSE41_AVAILABLE
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// #undef CRYPTOPP_ARM_NEON_AVAILABLE
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// GCC generates bad code when using the table-based 32-bit rotates. Or,
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// GAS assembles it incorrectly (this may be the case since both GCC and
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// Clang produce the same failure). SIMON uses the same code but with a
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// different round function, and SIMON is OK. Jake Lee warned about this
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// at http://stackoverflow.com/q/47617331/608639.
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#if (defined(__aarch32__) || defined(__aarch64__)) && defined(__GNUC__)
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# define WORKAROUND_GCC_AARCH64_BUG 1
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#endif
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#if (CRYPTOPP_SSSE3_AVAILABLE)
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# include <pmmintrin.h>
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# include <tmmintrin.h>
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@ -86,7 +77,6 @@ inline uint32x4_t RotateRight32(const uint32x4_t& val)
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return vorrq_u32(a, b);
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}
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#if (defined(__aarch32__) || defined(__aarch64__)) && !defined(WORKAROUND_GCC_AARCH64_BUG)
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// Faster than two Shifts and an Or. Thanks to Louis Wingers and Bryan Weeks.
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template <>
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inline uint32x4_t RotateLeft32<8>(const uint32x4_t& val)
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@ -111,14 +101,13 @@ inline uint32x4_t RotateRight32<8>(const uint32x4_t& val)
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const uint8_t maskb[16] = { 12,15,14,13, 8,11,10,9, 4,7,6,5, 0,3,2,1 };
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const uint8x16_t mask = vld1q_u8(maskb);
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#else
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const uint8_t maskb[16] = { 1,2,3,0, 5,6,7,4, 9,10,11,8, 13,14,14,12 };
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const uint8_t maskb[16] = { 1,2,3,0, 5,6,7,4, 9,10,11,8, 13,14,15,12 };
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const uint8x16_t mask = vld1q_u8(maskb);
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#endif
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return vreinterpretq_u32_u8(
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vqtbl1q_u8(vreinterpretq_u8_u32(val), mask));
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}
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#endif
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inline uint32x4_t Shuffle32(const uint32x4_t& val)
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{
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