Commit Graph

29 Commits

Author SHA1 Message Date
Jeffrey Walton
9c5ea3a17e
Update BLAKE2s to avoid dependency on b 2020-07-06 21:55:10 -04:00
Jeffrey Walton
a830b24e7a
Silence GCC warnings in BLAKE2 2020-06-29 08:31:25 -04:00
Jeffrey Walton
3bdcb5b8e0
Update comments 2020-06-29 05:22:27 -04:00
Jeffrey Walton
827f2ebcad
Speedup BLAKE2s message loading on PowerPC 2020-06-29 05:17:59 -04:00
Jeffrey Walton
1e0ae42a87
Fix BLAKE2s on AIX 2020-06-29 04:26:47 -04:00
Jeffrey Walton
25cdab6d32
Use little-endian mask during BLAKE2 loads 2020-06-28 02:34:52 -04:00
Jeffrey Walton
e007e98501
Update comments 2020-04-11 08:36:02 -04:00
Jeffrey Walton
6f21803445
Update file header comments 2020-04-11 05:57:26 -04:00
Jeffrey Walton
e65d10dad1
Remove unneeded PPC64 BLAKE2_Compress32_CORE 2020-04-06 21:16:49 -04:00
Jeffrey Walton
117a39bafd
Fix unaligned PPC64 loads in BLAKSE2s 2020-04-05 23:16:21 -04:00
Jeffrey Walton
e4ccdb90c0
Use Altivec as minimum ISA for Blake2s 2020-04-05 21:41:34 -04:00
Jeffrey Walton
fa39314b7a
Add XLC 12 loads and stores for AIX (PR #907)
Add XLC 12 loads and stores for AIX
2019-10-26 22:11:49 -04:00
Jeffrey Walton
60eedb97ba
Fix ARM headers and Android compile (PR #896)
* Test fix ARM headers
This problem has been festering for some time. The header file includes are slightly different than the ISA options. Some platforms need an include, others don't.

* Fix cryptest-android.sh and cryptest-ios.sh

* Fix MSVC ARM32 and ARM64 compile

* Split ARM32 and ARM64 recipes in GNUmakefile
2019-10-16 21:00:45 -04:00
Jeffrey Walton
eeb7dadc76
Fix missing _mm_roti_epi32 and _mm_roti_epi64 under GCC (GH #859) 2019-07-02 19:10:11 -04:00
Jeffrey Walton
e40de18538
Update comments 2019-05-28 20:18:58 -04:00
Jeffrey Walton
39418a8512
Use PowerPC unaligned loads and stores with Power8 (GH #825, PR #826)
Use PowerPC unaligned loads and stores with Power8. Formerly we were using Power7 as the floor because the IBM POWER Architecture manuals said unaligned loads and stores were available. However, some compilers generate bad code for unaligned loads and stores using `-march=power7`, so bump to a known good.
2019-04-27 20:35:01 -04:00
Jeffrey Walton
c22f37f051
Clear unused variable warning on AIX 2019-01-22 02:35:25 -05:00
Jeffrey Walton
822ca11579
Cleanup headers after Microsoft ARM64 port 2019-01-04 11:33:28 -05:00
Jeffrey Walton
02f7fda54b
Fix <arm_neon.h> include for ARM64 with MSVC compiler (GH #776) 2019-01-04 11:25:55 -05:00
Jeffrey Walton
727de927cc
Add CRYPTOPP_POWER7_ALTIVEC for XLC 12 on AIX workaround 2018-11-24 01:11:54 -05:00
Jeffrey Walton
0998b40d2d
Disable Altivec for BLAKE2s on AIX 7.1 and XLC 12.01 (GH #743) 2018-11-21 00:25:05 -05:00
Jeffrey Walton
a65d55a3fd
Rewrite BLAKE2 classes
The ParameterBlocks for BLAKE2 had undefined behavior. We relied on the compiler packing the bytes in the structure, then we used the first byte as the start of an array.

This rewrite does things correctly. We don't memset the structure, and we don't treat the structure as a contiguous array.
2018-11-20 23:32:35 -05:00
Jeffrey Walton
3129ad4d70
Fix LLVM Clang compile on PowerPC 2018-11-19 02:28:29 -05:00
Jeffrey Walton
1a06aadbf0
Update comments 2018-11-18 14:54:37 -05:00
Jeffrey Walton
2e68e95a92
Add BLAKE2s and ChaCha CORE SIMD function (GH #656)
The CORE function provides the implementation for ChaCha_OperateKeystream_ALTIVEC, ChaCha_OperateKeystream_POWER7, BLAKE2_Compress32_ALTIVEC and BLAKE2_Compress32_POWER7. Depending on the options used to compile the source files, either POWER7 or ALTIVEC will be used.
This is needed to support the "new toolchain, ancient hardware" use case.
2018-11-18 14:43:48 -05:00
Jeffrey Walton
f6e04e5f33
Rename PPC vector functions from VectorFunc to VecFunc 2018-11-15 15:17:49 -05:00
Jeffrey Walton
8b4da4ca68
Update comments 2018-11-15 04:12:35 -05:00
Jeffrey Walton
89faf39228
Cleanup BLAKE2s 2018-11-15 03:35:39 -05:00
Jeffrey Walton
896225069d
Rename files with dashes to underscores (GH #736)
Also see https://groups.google.com/forum/#!topic/cryptopp-users/HBz-6gZZFOA on the mailing list
2018-11-10 08:00:14 -05:00