mirror of
https://github.com/shadps4-emu/ext-cryptopp.git
synced 2024-11-27 03:40:22 +00:00
450 lines
14 KiB
C++
450 lines
14 KiB
C++
// arm_simd.h - written and placed in public domain by Jeffrey Walton
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/// \file arm_simd.h
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/// \brief Support functions for ARM and vector operations
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#ifndef CRYPTOPP_ARM_SIMD_H
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#define CRYPTOPP_ARM_SIMD_H
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#include "config.h"
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#if (CRYPTOPP_ARM_NEON_HEADER)
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# include <stdint.h>
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# include <arm_neon.h>
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#endif
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#if (CRYPTOPP_ARM_ACLE_HEADER)
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# include <stdint.h>
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# include <arm_acle.h>
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#endif
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#if (CRYPTOPP_ARM_CRC32_AVAILABLE) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \name CRC32 checksum
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//@{
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/// \brief CRC32 checksum
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/// \param crc the starting crc value
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/// \param val the value to checksum
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/// \return CRC32 value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32B (uint32_t crc, uint8_t val)
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{
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#if defined(_MSC_VER)
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return __crc32b(crc, val);
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#else
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__asm__ ("crc32b %w0, %w0, %w1 \n\t"
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:"+r" (crc) : "r" (val) );
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return crc;
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#endif
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}
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/// \brief CRC32 checksum
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/// \param crc the starting crc value
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/// \param val the value to checksum
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/// \return CRC32 value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32W (uint32_t crc, uint32_t val)
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{
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#if defined(_MSC_VER)
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return __crc32w(crc, val);
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#else
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__asm__ ("crc32w %w0, %w0, %w1 \n\t"
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:"+r" (crc) : "r" (val) );
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return crc;
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#endif
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}
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/// \brief CRC32 checksum
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/// \param crc the starting crc value
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/// \param vals the values to checksum
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/// \return CRC32 value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32Wx4 (uint32_t crc, const uint32_t vals[4])
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{
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#if defined(_MSC_VER)
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return __crc32w(__crc32w(__crc32w(__crc32w(
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crc, vals[0]), vals[1]), vals[2]), vals[3]);
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#else
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__asm__ ("crc32w %w0, %w0, %w1 \n\t"
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"crc32w %w0, %w0, %w2 \n\t"
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"crc32w %w0, %w0, %w3 \n\t"
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"crc32w %w0, %w0, %w4 \n\t"
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:"+r" (crc) : "r" (vals[0]), "r" (vals[1]),
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"r" (vals[2]), "r" (vals[3]));
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return crc;
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#endif
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}
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//@}
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/// \name CRC32-C checksum
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/// \brief CRC32-C checksum
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/// \param crc the starting crc value
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/// \param val the value to checksum
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/// \return CRC32-C value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32CB (uint32_t crc, uint8_t val)
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{
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#if defined(_MSC_VER)
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return __crc32cb(crc, val);
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#else
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__asm__ ("crc32cb %w0, %w0, %w1 \n\t"
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:"+r" (crc) : "r" (val) );
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return crc;
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#endif
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}
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/// \brief CRC32-C checksum
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/// \param crc the starting crc value
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/// \param val the value to checksum
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/// \return CRC32-C value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32CW (uint32_t crc, uint32_t val)
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{
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#if defined(_MSC_VER)
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return __crc32cw(crc, val);
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#else
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__asm__ ("crc32cw %w0, %w0, %w1 \n\t"
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:"+r" (crc) : "r" (val) );
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return crc;
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#endif
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}
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/// \brief CRC32-C checksum
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/// \param crc the starting crc value
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/// \param vals the values to checksum
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/// \return CRC32-C value
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/// \since Crypto++ 8.6
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inline uint32_t CRC32CWx4 (uint32_t crc, const uint32_t vals[4])
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{
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#if defined(_MSC_VER)
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return __crc32cw(__crc32cw(__crc32cw(__crc32cw(
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crc, vals[0]), vals[1]), vals[2]), vals[3]);
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#else
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__asm__ ("crc32cw %w0, %w0, %w1 \n\t"
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"crc32cw %w0, %w0, %w2 \n\t"
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"crc32cw %w0, %w0, %w3 \n\t"
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"crc32cw %w0, %w0, %w4 \n\t"
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:"+r" (crc) : "r" (vals[0]), "r" (vals[1]),
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"r" (vals[2]), "r" (vals[3]));
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return crc;
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#endif
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}
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//@}
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#endif // CRYPTOPP_ARM_CRC32_AVAILABLE
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#if (CRYPTOPP_ARM_PMULL_AVAILABLE) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \name Polynomial multiplication
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//@{
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL_00() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x00)</tt>.
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/// The <tt>0x00</tt> indicates the low 64-bits of <tt>a</tt> and <tt>b</tt>
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/// are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_00(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 0) };
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const __n64 y = { vgetq_lane_u64(b, 0) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),0),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),0)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL_01 performs() polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x01)</tt>.
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/// The <tt>0x01</tt> indicates the low 64-bits of <tt>a</tt> and high
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/// 64-bits of <tt>b</tt> are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_01(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 0) };
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const __n64 y = { vgetq_lane_u64(b, 1) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (a), "w" (vget_high_u64(b)) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),0),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),1)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL_10() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x10)</tt>.
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/// The <tt>0x10</tt> indicates the high 64-bits of <tt>a</tt> and low
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/// 64-bits of <tt>b</tt> are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_10(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 1) };
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const __n64 y = { vgetq_lane_u64(b, 0) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (vget_high_u64(a)), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),1),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),0)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL_11() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x11)</tt>.
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/// The <tt>0x11</tt> indicates the high 64-bits of <tt>a</tt> and <tt>b</tt>
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/// are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_11(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 1) };
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const __n64 y = { vgetq_lane_u64(b, 1) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull2 %0.1q, %1.2d, %2.2d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),1),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),1)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL() performs vmull_p64(). PMULL is provided as
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/// GCC inline assembly due to Clang and lack of support for the intrinsic.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 0) };
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const __n64 y = { vgetq_lane_u64(b, 0) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),0),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),0)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first value
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/// \param b the second value
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/// \return vector product
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/// \details PMULL_HIGH() performs vmull_high_p64(). PMULL_HIGH is provided as
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/// GCC inline assembly due to Clang and lack of support for the intrinsic.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_HIGH(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 1) };
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const __n64 y = { vgetq_lane_u64(b, 1) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm__ ("pmull2 %0.1q, %1.2d, %2.2d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),1),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),1))));
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#endif
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}
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/// \brief Vector extraction
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/// \param a the first value
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/// \param b the second value
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/// \param c the byte count
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/// \return vector
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/// \details VEXT_U8() extracts the first <tt>c</tt> bytes of vector
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/// <tt>a</tt> and the remaining bytes in <tt>b</tt>. VEXT_U8 is provided
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/// as GCC inline assembly due to Clang and lack of support for the intrinsic.
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/// \since Crypto++ 8.0
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inline uint64x2_t VEXT_U8(uint64x2_t a, uint64x2_t b, unsigned int c)
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{
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#if defined(_MSC_VER)
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return vreinterpretq_u64_u8(vextq_u8(
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vreinterpretq_u8_u64(a), vreinterpretq_u8_u64(b), c));
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#else
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uint64x2_t r;
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__asm__ ("ext %0.16b, %1.16b, %2.16b, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (c) );
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return r;
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#endif
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}
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/// \brief Vector extraction
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/// \tparam C the byte count
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/// \param a the first value
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/// \param b the second value
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/// \return vector
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/// \details VEXT_U8() extracts the first <tt>C</tt> bytes of vector
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/// <tt>a</tt> and the remaining bytes in <tt>b</tt>. VEXT_U8 is provided
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/// as GCC inline assembly due to Clang and lack of support for the intrinsic.
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/// \since Crypto++ 8.0
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template <unsigned int C>
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inline uint64x2_t VEXT_U8(uint64x2_t a, uint64x2_t b)
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{
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// https://github.com/weidai11/cryptopp/issues/366
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#if defined(_MSC_VER)
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return vreinterpretq_u64_u8(vextq_u8(
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vreinterpretq_u8_u64(a), vreinterpretq_u8_u64(b), C));
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#else
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uint64x2_t r;
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__asm__ ("ext %0.16b, %1.16b, %2.16b, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (C) );
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return r;
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#endif
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}
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//@}
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#endif // CRYPTOPP_ARM_PMULL_AVAILABLE
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#if CRYPTOPP_ARM_SHA3_AVAILABLE || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \name ARMv8.2 operations
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//@{
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/// \brief Three-way XOR
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/// \param a the first value
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/// \param b the second value
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/// \param c the third value
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/// \return three-way exclusive OR of the values
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/// \details VEOR3() performs veor3q_u64(). VEOR3 is provided as GCC inline assembly due
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/// to Clang and lack of support for the intrinsic.
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/// \details VEOR3 requires ARMv8.2.
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/// \since Crypto++ 8.6
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inline uint64x2_t VEOR3(uint64x2_t a, uint64x2_t b, uint64x2_t c)
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{
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#if defined(_MSC_VER)
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return veor3q_u64(a, b, c);
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#else
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uint64x2_t r;
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__asm__ ("eor3 %0.16b, %1.16b, %2.16b, %3.16b \n\t"
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:"=w" (r) : "w" (a), "w" (b), "w" (c));
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return r;
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#endif
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}
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/// \brief XOR and rotate
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/// \param a the first value
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/// \param b the second value
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/// \param c the third value
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/// \return two-way exclusive OR of the values, then rotated by imm6
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/// \details VXARQ() performs vxarq_u64(). VXARQ is provided as GCC inline assembly due
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/// to Clang and lack of support for the intrinsic.
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/// \details VXARQ requires ARMv8.2.
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/// \since Crypto++ 8.6
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inline uint64x2_t VXAR(uint64x2_t a, uint64x2_t b, const int imm6)
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{
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#if defined(_MSC_VER)
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return vxarq_u64(a, b, imm6);
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#else
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uint64x2_t r;
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__asm__ ("xar %0.2d, %1.2d, %2.2d, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (imm6));
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return r;
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#endif
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}
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/// \brief XOR and rotate
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/// \tparam C the rotate amount
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/// \param a the first value
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/// \param b the second value
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/// \return two-way exclusive OR of the values, then rotated by C
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/// \details VXARQ() performs vxarq_u64(). VXARQ is provided as GCC inline assembly due
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/// to Clang and lack of support for the intrinsic.
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/// \details VXARQ requires ARMv8.2.
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/// \since Crypto++ 8.6
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template <unsigned int C>
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inline uint64x2_t VXAR(uint64x2_t a, uint64x2_t b)
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{
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#if defined(_MSC_VER)
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return vxarq_u64(a, b, C);
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#else
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uint64x2_t r;
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__asm__ ("xar %0.2d, %1.2d, %2.2d, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (C));
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|
return r;
|
|
#endif
|
|
}
|
|
|
|
/// \brief XOR and rotate
|
|
/// \param a the first value
|
|
/// \param b the second value
|
|
/// \return two-way exclusive OR of the values, then rotated 1-bit
|
|
/// \details VRAX1() performs vrax1q_u64(). VRAX1 is provided as GCC inline assembly due
|
|
/// to Clang and lack of support for the intrinsic.
|
|
/// \details VRAX1 requires ARMv8.2.
|
|
/// \since Crypto++ 8.6
|
|
inline uint64x2_t VRAX1(uint64x2_t a, uint64x2_t b)
|
|
{
|
|
#if defined(_MSC_VER)
|
|
return vrax1q_u64(a, b);
|
|
#else
|
|
uint64x2_t r;
|
|
__asm__ ("rax1 %0.2d, %1.2d, %2.2d \n\t"
|
|
:"=w" (r) : "w" (a), "w" (b));
|
|
return r;
|
|
#endif
|
|
}
|
|
//@}
|
|
#endif // CRYPTOPP_ARM_SHA3_AVAILABLE
|
|
|
|
#endif // CRYPTOPP_ARM_SIMD_H
|