mirror of
https://github.com/shadps4-emu/ext-cryptopp.git
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189 lines
6.2 KiB
C++
189 lines
6.2 KiB
C++
// arm_simd.h - written and placed in public domain by Jeffrey Walton
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/// \file arm_simd.h
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/// \brief Support functions for ARM and vector operations
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#ifndef CRYPTOPP_ARM_SIMD_H
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#define CRYPTOPP_ARM_SIMD_H
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#include "config.h"
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#if (CRYPTOPP_ARM_NEON_HEADER)
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# include <arm_neon.h>
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#endif
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#if (CRYPTOPP_ARM_ACLE_HEADER)
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# include <stdint.h>
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# include <arm_acle.h>
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#endif
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#if (CRYPTOPP_ARM_PMULL_AVAILABLE) || defined(CRYPTOPP_DOXYGEN_PROCESSING)
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/// \brief Polynomial multiplication
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/// \param a the first term
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/// \param b the second term
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/// \return vector product
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/// \details PMULL_00() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x00)</tt>.
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/// The <tt>0x00</tt> indicates the low 64-bits of <tt>a</tt> and <tt>b</tt>
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/// are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_00(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 0) };
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const __n64 y = { vgetq_lane_u64(b, 0) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm __volatile("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),0),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),0)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first term
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/// \param b the second term
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/// \return vector product
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/// \details PMULL_01 performs() polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x01)</tt>.
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/// The <tt>0x01</tt> indicates the low 64-bits of <tt>a</tt> and high
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/// 64-bits of <tt>b</tt> are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_01(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 0) };
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const __n64 y = { vgetq_lane_u64(b, 1) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm __volatile("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (a), "w" (vget_high_u64(b)) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),0),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),1)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first term
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/// \param b the second term
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/// \return vector product
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/// \details PMULL_10() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x10)</tt>.
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/// The <tt>0x10</tt> indicates the high 64-bits of <tt>a</tt> and low
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/// 64-bits of <tt>b</tt> are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_10(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 1) };
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const __n64 y = { vgetq_lane_u64(b, 0) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm __volatile("pmull %0.1q, %1.1d, %2.1d \n\t"
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:"=w" (r) : "w" (vget_high_u64(a)), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),1),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),0)));
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#endif
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}
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/// \brief Polynomial multiplication
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/// \param a the first term
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/// \param b the second term
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/// \return vector product
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/// \details PMULL_11() performs polynomial multiplication and presents
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/// the result like Intel's <tt>c = _mm_clmulepi64_si128(a, b, 0x11)</tt>.
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/// The <tt>0x11</tt> indicates the high 64-bits of <tt>a</tt> and <tt>b</tt>
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/// are multiplied.
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/// \note An Intel XMM register is composed of 128-bits. The leftmost bit
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/// is MSB and numbered 127, while the rightmost bit is LSB and
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/// numbered 0.
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/// \since Crypto++ 8.0
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inline uint64x2_t PMULL_11(const uint64x2_t a, const uint64x2_t b)
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{
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#if defined(_MSC_VER)
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const __n64 x = { vgetq_lane_u64(a, 1) };
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const __n64 y = { vgetq_lane_u64(b, 1) };
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return vmull_p64(x, y);
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#elif defined(__GNUC__)
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uint64x2_t r;
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__asm __volatile("pmull2 %0.1q, %1.2d, %2.2d \n\t"
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:"=w" (r) : "w" (a), "w" (b) );
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return r;
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#else
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return (uint64x2_t)(vmull_p64(
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vgetq_lane_u64(vreinterpretq_u64_u8(a),1),
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vgetq_lane_u64(vreinterpretq_u64_u8(b),1)));
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#endif
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}
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/// \brief Vector extraction
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/// \param a the first term
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/// \param b the second term
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/// \param c the byte count
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/// \return vector
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/// \details VEXT_U8() extracts the first <tt>c</tt> bytes of vector
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/// <tt>a</tt> and the remaining bytes in <tt>b</tt>.
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/// \since Crypto++ 8.0
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inline uint64x2_t VEXT_U8(uint64x2_t a, uint64x2_t b, unsigned int c)
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{
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#if defined(_MSC_VER)
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return (uint64x2_t)vextq_u8(
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vreinterpretq_u8_u64(a), vreinterpretq_u8_u64(b), c);
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#else
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uint64x2_t r;
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__asm __volatile("ext %0.16b, %1.16b, %2.16b, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (c) );
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return r;
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#endif
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}
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/// \brief Vector extraction
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/// \tparam C the byte count
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/// \param a the first term
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/// \param b the second term
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/// \return vector
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/// \details VEXT_U8() extracts the first <tt>C</tt> bytes of vector
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/// <tt>a</tt> and the remaining bytes in <tt>b</tt>.
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/// \since Crypto++ 8.0
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template <unsigned int C>
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inline uint64x2_t VEXT_U8(uint64x2_t a, uint64x2_t b)
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{
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// https://github.com/weidai11/cryptopp/issues/366
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#if defined(_MSC_VER)
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return (uint64x2_t)vextq_u8(
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vreinterpretq_u8_u64(a), vreinterpretq_u8_u64(b), C);
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#else
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uint64x2_t r;
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__asm __volatile("ext %0.16b, %1.16b, %2.16b, %3 \n\t"
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:"=w" (r) : "w" (a), "w" (b), "I" (C) );
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return r;
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#endif
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}
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#endif // CRYPTOPP_ARM_PMULL_AVAILABLE
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#endif // CRYPTOPP_ARM_SIMD_H
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