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fix lane inst decoding (#1051)

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baggins183 2024-09-24 02:29:57 -07:00 committed by GitHub
parent 1620eea37b
commit 7f9bc0abbd
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2 changed files with 13 additions and 15 deletions
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27
src/shader_recompiler/frontend/decode.cpp
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@ -503,9 +503,8 @@ void GcnDecodeContext::decodeInstructionVOP1(u32 hexInstruction) {
OpcodeVOP1 vop1Op = static_cast<OpcodeVOP1>(op); OpcodeVOP1 vop1Op = static_cast<OpcodeVOP1>(op);
if (vop1Op == OpcodeVOP1::V_READFIRSTLANE_B32) { if (vop1Op == OpcodeVOP1::V_READFIRSTLANE_B32) {
m_instruction.dst[1].field = getOperandField(vdst); m_instruction.dst[0].field = getOperandField(vdst);
m_instruction.dst[1].type = ScalarType::Uint32; m_instruction.dst[0].type = ScalarType::Uint32;
m_instruction.dst[1].code = vdst;
} }
} }
@ -547,13 +546,15 @@ void GcnDecodeContext::decodeInstructionVOP2(u32 hexInstruction) {
m_instruction.dst_count = 1; m_instruction.dst_count = 1;
OpcodeVOP2 vop2Op = static_cast<OpcodeVOP2>(op); OpcodeVOP2 vop2Op = static_cast<OpcodeVOP2>(op);
if (vop2Op == OpcodeVOP2::V_READLANE_B32 || vop2Op == OpcodeVOP2::V_WRITELANE_B32) { if (vop2Op == OpcodeVOP2::V_READLANE_B32) {
// vsrc1 is scalar for lane instructions // vsrc1 is scalar for lane instructions
m_instruction.src[1].field = getOperandField(vsrc1); m_instruction.src[1].field = getOperandField(vsrc1);
// dst is sgpr // dst is sgpr
m_instruction.dst[1].field = OperandField::ScalarGPR; m_instruction.dst[0].field = getOperandField(vdst);
m_instruction.dst[1].type = ScalarType::Uint32; m_instruction.dst[0].type = ScalarType::Uint32;
m_instruction.dst[1].code = vdst; } else if (vop2Op == OpcodeVOP2::V_WRITELANE_B32) {
m_instruction.src[1].field = getOperandField(vsrc1);
// dst is vgpr, as normal
} else if (IsVop3BEncoding(m_instruction.opcode)) { } else if (IsVop3BEncoding(m_instruction.opcode)) {
m_instruction.dst[1].field = OperandField::VccLo; m_instruction.dst[1].field = OperandField::VccLo;
m_instruction.dst[1].type = ScalarType::Uint64; m_instruction.dst[1].type = ScalarType::Uint64;
@ -660,13 +661,11 @@ void GcnDecodeContext::decodeInstructionVOP3(uint64_t hexInstruction) {
m_instruction.dst[1].field = getOperandField(vdst); m_instruction.dst[1].field = getOperandField(vdst);
m_instruction.dst[1].type = ScalarType::Uint64; m_instruction.dst[1].type = ScalarType::Uint64;
m_instruction.dst[1].code = vdst; m_instruction.dst[1].code = vdst;
} else if (vop3Op >= OpcodeVOP3::V_READLANE_B32 && vop3Op <= OpcodeVOP3::V_WRITELANE_B32) { } else if (vop3Op == OpcodeVOP3::V_READLANE_B32 ||
// vsrc1 is scalar for lane instructions vop3Op == OpcodeVOP3::V_READFIRSTLANE_B32) {
m_instruction.src[1].field = getOperandField(src1); m_instruction.dst[0].field = getOperandField(vdst);
// dst is sgpr for lane instruction m_instruction.dst[0].type = ScalarType::Uint32;
m_instruction.dst[1].field = OperandField::ScalarGPR; // WRITELANE can be decoded like other VOP3's
m_instruction.dst[1].type = ScalarType::Uint32;
m_instruction.dst[1].code = vdst;
} }
} }

1
src/shader_recompiler/frontend/translate/data_share.cpp
View File

@ -64,7 +64,6 @@ void Translator::S_BARRIER() {
// VOP2 // VOP2
void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) { void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
const IR::ScalarReg dst{inst.dst[0].code};
const IR::U32 value{GetSrc(inst.src[0])}; const IR::U32 value{GetSrc(inst.src[0])};
if (info.stage != Stage::Compute) { if (info.stage != Stage::Compute) {