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docs/Design: Fix links (#633)
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@ -5,14 +5,14 @@ support for other versions of the ARM architecture, having a interpreter mode, a
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for other architectures.
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Users of this library interact with it primarily through the interface provided in
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[`include/dynarmic`](../include/dynarmic). Users specify how dynarmic's CPU core interacts with
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[`src/dynarmic/interface`](../src/dynarmic/interface). Users specify how dynarmic's CPU core interacts with
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the rest of their system providing an implementation of the relevant `UserCallbacks` interface.
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Users setup the CPU state using member functions of `Jit`, then call `Jit::Execute` to start CPU
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execution. The callbacks defined on `UserCallbacks` may be called from dynamically generated code,
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so users of the library should not depend on the stack being in a walkable state for unwinding.
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* A32: [`Jit`](../include/dynarmic/A32/a32.h), [`UserCallbacks`](../include/dynarmic/A32/config.h)
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* A64: [`Jit`](../include/dynarmic/A64/a64.h), [`UserCallbacks`](../include/dynarmic/A64/config.h)
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* A32: [`Jit`](../src/dynarmic/interface/A32/a32.h), [`UserCallbacks`](../src/dynarmic/interface/A32/config.h)
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* A64: [`Jit`](../src/dynarmic/interface/A64/a64.h), [`UserCallbacks`](../src/dynarmic/interface/A64/config.h)
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Dynarmic reads instructions from memory by calling `UserCallbacks::MemoryReadCode`. These
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instructions then pass through several stages:
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@ -26,19 +26,19 @@ instructions then pass through several stages:
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Using the A32 frontend with the x64 backend as an example:
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* Decoding is done by [double dispatch](https://en.wikipedia.org/wiki/Visitor_pattern) in
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../src/frontend/A32/decoder/).
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* Translation is done by the visitors in `src/frontend/A32/translate/translate_{arm,thumb}.cpp`.
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The function [`Translate`](../src/frontend/A32/translate/translate.h) takes a starting memory location,
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[`src/frontend/A32/decoder/{arm.h,thumb16.h,thumb32.h}`](../src/dynarmic/frontend/A32/decoder/).
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* Translation is done by the visitors in [`src/dynarmic/frontend/A32/translate/translate_{arm,thumb}.cpp`](../src/dynarmic/frontend/A32/translate/).
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The function [`Translate`](../src/dynarmic/frontend/A32/translate/translate.h) takes a starting memory location,
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some CPU state, and memory reader callback and returns a basic block of IR.
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* The IR can be found under [`src/frontend/ir/`](../src/frontend/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/ir_opt/).
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* Emission is done by `EmitX64` which can be found in `src/backend_x64/emit_x64.{h,cpp}`.
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* Execution is performed by calling `BlockOfCode::RunCode` in `src/backend_x64/block_of_code.{h,cpp}`.
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* The IR can be found under [`src/frontend/ir/`](../src/dynarmic/ir/).
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* Optimizations can be found under [`src/ir_opt/`](../src/dynarmic/ir/opt/).
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* Emission is done by `EmitX64` which can be found in [`src/dynarmic/backend/x64/emit_x64.{h,cpp}`](../src/dynarmic/backend/x64/).
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* Execution is performed by calling `BlockOfCode::RunCode` in [`src/dynarmic/backend/x64/block_of_code.{h,cpp}`](../src/dynarmic/backend/x64/).
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## Decoder
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The decoder is a double dispatch decoder. Each instruction is represented by a line in the relevant
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instruction table. Here is an example line from [`arm.h`](../src/frontend/A32/decoder/arm.h):
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instruction table. Here is an example line from [`arm.h`](../src/dynarmic/frontend/A32/decoder/arm.h):
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INST(&V::arm_ADC_imm, "ADC (imm)", "cccc0010101Snnnnddddrrrrvvvvvvvv")
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@ -61,7 +61,7 @@ error results.
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## Translator
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The translator is a visitor that uses the decoder to decode instructions. The translator generates IR code with the
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help of the [`IREmitter` class](../src/frontend/ir/ir_emitter.h). An example of a translation function follows:
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help of the [`IREmitter` class](../src/dynarmic/ir/ir_emitter.h). An example of a translation function follows:
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bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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@ -107,7 +107,7 @@ function analyser in the medium-term future.
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Dynarmic's intermediate representation is typed. Each microinstruction may take zero or more arguments and may
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return zero or more arguments. A subset of the microinstructions available is documented below.
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A complete list of microinstructions can be found in [src/frontend/ir/opcodes.inc](../src/frontend/ir/opcodes.inc).
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A complete list of microinstructions can be found in [src/dynarmic/ir/opcodes.inc](../src/dynarmic/ir/opcodes.inc).
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The below lists some commonly used microinstructions.
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