Expose the XCR0 register for x86 to allow users to control XSAVE
behavior. This register is a bit odd. It's the only one of its type
(extended control register), and usually accessed via XGETBV/XSETBV.
* Make __ctl_wr work for an arbitrary number of parameters
* Rename test_arm64_v8_pac to test_arm64_v8_cas as it tests CAS not PAC
* Add PAuth helpers for signing, stripping and authentication of pointers
Add UC_CTL_PAUTH_SIGN, UC_CTL_PAUTH_STRIP and UC_CTL_PAUTH_AUTH as an
architecture-independent interface to pointer authentication operations
without having to execute instructions on the virtual CPU. This is
useful in many scenarios, for instance when rebasing signed pointers as
part of loading code that runs with PAuth.
The C interfaces are covered by a unit test. The Python interfaces have
been tested in a real world project.
* Fifth PR, add myself to CREDITS.TXT
* Remove static_assert for better portability
* Make test_arm64 slightly more robust
* Add test for vanilla PAuth without helpers and refactor tests
* Typecast arguments to PAuth uc_ctl_* macros
Fixes issue where literal arguments would be written to variable
argument memory as an int, but subsequently read from va_list as a
uint64_t, which on some platforms might be a different size and lead to
corruption of later arguments, breaking PAuth helper functionality or
causing segmentation faults.
* Clean up PAuth test init code for reuse by future tests
* modify uc_priv.h to use 64 bit hwaddr type for length for uc_write_mem_t and uc_read_mem_t
* propogate 64 bit address support to memory function inside unicorn.h
* modify physical memory functions to ensure 64 bit support for size parameters
* apply uint64_t size handling inside the memory handling main functions
* remove INT_MAX size check as we now use a 64 bit address
* add @secretnonempty unit test for large memory addresses to avoid regression
* replace size_t in python3 bindings with u64
* adjust rust bindings
* use format.sh script to improve formatting
* small adjustments to java bindings, because jlong type is sometimes already used
* adjust dotnet bindings to reflect new type sizes
* adjust pascal bindings
* adjust ruby bindings
* adjust vb6 bindings
* adjust zig bindings for 64 bit size support
* fix build.zig.zon for newer zig versions
* add haskell binding support for 64 bit sizes
* use mlugg/setup-zig instead of goto-bus-stop/setup-zig github action to get access to current zig releases
* use uint64_t instead of size_t for uc_mem_unmap
* add whitespace between functions to preserver formatting
* add precompiler check for android and abort execution of testcase to avoid infinite low memory killer loop
* downgrade zig version to 0.14.0 again to ensure that pipeline can run through
* adjust rust mmio_unwrap type to use u64
* change ffi size type of uc_mem_map_ptr into u64
* add warning to rust slicing
* return read_mem_as_vec to earlier state, leave usize as argument because there cannot be larger vec![] anyway
* adjust regions inside MmioCallbackScope to use u64 for region sizes
* adjust regions inside MmioCallbackScope to use u64 for region sizes inside search vec
* finalize dotnet bindings inside IBinding.fs
* fix typo
* adjust types inside Unicorn.fs
* finalize type wrangling inside F# bindings, setting MemRead and MemWrite to correct types
* fix missing bracket inside bindings/rust/src/lib.rs
* replace ffi interface to hook interface inside rust lib
* fix testcases to use u64 for longer references
Co-authored-by: r0b0t <[email protected]>
uc_query expects a size_t *, while we are passing uc_arch *. This has
been working for a while as gcc just warned about this, however with
latest gcc this changed into an error:
unicorn.c:122:34: error: passing argument 3 of ‘uc_query’ from incompatible pointer type [-Wincompatible-pointer-types]
206 | uc_query(_uc, UC_QUERY_ARCH, &arch);
unicorn.h:689:60: note: expected ‘size_t *’ {aka ‘long unsigned int *’} but argument is of type ‘uc_arch *’
689 | uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result);
Fix this issue by querying the result into a size_t and later downcast
the result into an uc_arch enum.
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.
The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.
The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
A number of x86 registers were removed for #1440, causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.
Restore the old numbering.
Fixes#1492.
unknown-1-0