icons example

icons.h

@@ -0,0 +1,156 @@
+#ifndef _ICONS_H
+#define _ICONS_H
+
+static unsigned char icon_rocket[762] =
+{
+    0x89, 0x50, 0x4E, 0x47, 0x0D, 0x0A, 0x1A, 0x0A, 0x00, 0x00,
+    0x00, 0x0D, 0x49, 0x48, 0x44, 0x52, 0x00, 0x00, 0x00, 0x10,
+    0x00, 0x00, 0x00, 0x10, 0x08, 0x06, 0x00, 0x00, 0x00, 0x1F,
+    0xF3, 0xFF, 0x61, 0x00, 0x00, 0x00, 0x19, 0x74, 0x45, 0x58,
+    0x74, 0x53, 0x6F, 0x66, 0x74, 0x77, 0x61, 0x72, 0x65, 0x00,
+    0x41, 0x64, 0x6F, 0x62, 0x65, 0x20, 0x49, 0x6D, 0x61, 0x67,
+    0x65, 0x52, 0x65, 0x61, 0x64, 0x79, 0x71, 0xC9, 0x65, 0x3C,
+    0x00, 0x00, 0x02, 0x9C, 0x49, 0x44, 0x41, 0x54, 0x78, 0xDA,
+    0x84, 0x53, 0x5F, 0x48, 0x53, 0x61, 0x14, 0xFF, 0x7D, 0x77,
+    0xB7, 0xCD, 0x70, 0xFD, 0xD9, 0x6A, 0xA4, 0x73, 0xEB, 0x1F,
+    0xC3, 0x94, 0xB6, 0x5D, 0x72, 0x62, 0xA1, 0x08, 0x8A, 0x84,
+    0x82, 0x42, 0x24, 0x95, 0xD1, 0xC3, 0x4A, 0xCB, 0xE8, 0xA9,
+    0x57, 0x09, 0x7A, 0x2C, 0x0A, 0x7B, 0xA8, 0x40, 0x82, 0x09,
+    0xBD, 0xF8, 0x62, 0x0F, 0xBE, 0x04, 0x3E, 0xA4, 0x0F, 0x19,
+    0xE4, 0x88, 0x89, 0x6D, 0x12, 0x2B, 0x88, 0x48, 0x99, 0xA3,
+    0x39, 0x75, 0x13, 0xAE, 0x4D, 0xE7, 0xEE, 0x76, 0xEF, 0xED,
+    0xFB, 0xAE, 0xDD, 0xE1, 0x14, 0xEA, 0xC0, 0x8F, 0xEF, 0xE3,
+    0x9C, 0xFB, 0xFB, 0x9D, 0x73, 0xBE, 0x73, 0x2E, 0xC1, 0x2E,
+    0x33, 0x18, 0x0C, 0xE0, 0x38, 0x0E, 0xB2, 0x2C, 0x43, 0x51,
+    0x94, 0x9D, 0x21, 0xE1, 0x27, 0x21, 0x8F, 0x56, 0x55, 0xD5,
+    0x9A, 0x05, 0x4C, 0x1B, 0xD4, 0x91, 0x00, 0x86, 0x79, 0xBB,
+    0xDD, 0x0E, 0x42, 0x88, 0x06, 0x66, 0xEC, 0x8C, 0xC7, 0xE3,
+    0xBB, 0x75, 0x05, 0x8A, 0xF3, 0xCE, 0x9C, 0xD4, 0x55, 0xE8,
+    0xB9, 0x86, 0xEA, 0xDA, 0x5A, 0x48, 0x0B, 0x0B, 0x78, 0x3B,
+    0x3A, 0x7A, 0x87, 0xAF, 0xAC, 0xAC, 0xD4, 0x32, 0x32, 0xE8,
+    0xB6, 0x4B, 0x40, 0x23, 0x4B, 0x52, 0x3E, 0x30, 0x37, 0x17,
+    0x81, 0xF3, 0xD5, 0x6B, 0x4C, 0x09, 0x35, 0xF0, 0xD5, 0xD7,
+    0xE3, 0x10, 0x20, 0x71, 0xF8, 0xB7, 0x15, 0xC9, 0xC1, 0xE0,
+    0x34, 0xAB, 0x0F, 0xE1, 0xF0, 0x17, 0x78, 0x83, 0xDF, 0xB0,
+    0x10, 0x8B, 0xE1, 0x08, 0x21, 0x5B, 0xDC, 0xFF, 0xC8, 0xB3,
+    0x9F, 0xC3, 0x81, 0xB3, 0x6E, 0x2F, 0x0E, 0x1C, 0x6F, 0xC1,
+    0xEC, 0xEC, 0x57, 0x58, 0x2C, 0x15, 0x88, 0x51, 0x72, 0xC5,
+    0xD8, 0xA4, 0x78, 0x14, 0xD8, 0x22, 0x3E, 0x9F, 0x6F, 0x4F,
+    0x0B, 0xA1, 0x50, 0xA8, 0x98, 0xB9, 0xF3, 0x72, 0x2F, 0x0E,
+    0x57, 0x35, 0x6B, 0xFE, 0x54, 0xEC, 0x03, 0x5E, 0x0C, 0x0E,
+    0xC2, 0x68, 0xE4, 0xC4, 0x8E, 0x8E, 0xC6, 0x97, 0x65, 0x65,
+    0x65, 0xEF, 0x78, 0x16, 0x50, 0x55, 0xF5, 0x3A, 0x7D, 0x71,
+    0x27, 0xBB, 0x67, 0x32, 0x99, 0x02, 0x7D, 0xC8, 0x8D, 0x5C,
+    0x4E, 0x0A, 0x2C, 0x2D, 0x25, 0xE0, 0x3C, 0xE9, 0x41, 0xB5,
+    0xD7, 0xA7, 0x09, 0x7C, 0xE7, 0xC5, 0x12, 0x32, 0xFD, 0xEE,
+    0x13, 0x11, 0x04, 0x96, 0x0C, 0x03, 0x43, 0x43, 0x43, 0x4F,
+    0x57, 0x56, 0x56, 0x90, 0x4E, 0xA7, 0xD1, 0xD4, 0xD4, 0x84,
+    0x48, 0x24, 0x82, 0x86, 0x86, 0x0B, 0xF8, 0x31, 0xBF, 0x86,
+    0x50, 0x34, 0xAD, 0x55, 0xD8, 0x5C, 0x57, 0x25, 0xF6, 0xDD,
+    0xEC, 0x2C, 0x92, 0xB5, 0xB1, 0x5B, 0xAD, 0x56, 0x36, 0x73,
+    0x79, 0x66, 0x66, 0xA6, 0xE0, 0x72, 0xB9, 0xEA, 0x19, 0x99,
+    0xF5, 0xC8, 0x19, 0x38, 0x4C, 0x87, 0x3F, 0xA2, 0xE6, 0x94,
+    0x00, 0xA1, 0xC6, 0x41, 0x71, 0x4C, 0xBC, 0x7A, 0xA5, 0xAD,
+    0x84, 0xAC, 0x8D, 0xDD, 0x66, 0xB3, 0xB1, 0x16, 0x58, 0xE6,
+    0xBB, 0xD1, 0x68, 0x34, 0xC0, 0xC8, 0x39, 0x29, 0x87, 0xE4,
+    0xEF, 0x24, 0x14, 0x5E, 0x01, 0x51, 0x09, 0x5A, 0xCF, 0x5D,
+    0x2A, 0x29, 0x5B, 0x27, 0x6F, 0x6E, 0x6E, 0x82, 0xEB, 0x5B,
+    0x5D, 0xC5, 0xED, 0x54, 0x0A, 0xFD, 0xAA, 0x9A, 0x77, 0xBB,
+    0xDD, 0xF7, 0x4D, 0xE5, 0xA6, 0x22, 0xD9, 0x62, 0xB1, 0xC0,
+    0xE1, 0x74, 0xAC, 0x7B, 0x3C, 0x27, 0x86, 0x77, 0x92, 0x19,
+    0x71, 0x71, 0x71, 0x51, 0x03, 0x3F, 0xB0, 0x2D, 0x66, 0x43,
+    0x05, 0x6E, 0x9C, 0xE9, 0xC1, 0x7C, 0x7B, 0x5B, 0xFB, 0x93,
+    0x91, 0xF1, 0x91, 0x07, 0xCC, 0x69, 0x2E, 0x37, 0xAF, 0x07,
+    0xC7, 0x83, 0x07, 0xCD, 0x66, 0x73, 0x3E, 0x9B, 0xCD, 0x6A,
+    0xE4, 0x14, 0x4D, 0xC6, 0x04, 0x74, 0xD3, 0x67, 0xD7, 0x02,
+    0x3F, 0x92, 0xBD, 0x5D, 0xEA, 0xE9, 0xC7, 0xF7, 0x14, 0xBB,
+    0xBF, 0xCB, 0xFF, 0x4C, 0x27, 0x7B, 0x1A, 0x3D, 0xAC, 0x45,
+    0x22, 0x8A, 0x22, 0x12, 0x89, 0x44, 0x09, 0x59, 0x17, 0xD8,
+    0x4F, 0xB3, 0x5B, 0x70, 0x11, 0x71, 0x4C, 0x22, 0xD9, 0x3F,
+    0xA6, 0xD8, 0x6F, 0xA9, 0xEA, 0xAF, 0xEE, 0xD6, 0xEE, 0xC0,
+    0xC4, 0xFB, 0x89, 0x37, 0x9C, 0x91, 0x43, 0x3E, 0x9F, 0xE7,
+    0xE8, 0x78, 0x51, 0x28, 0x14, 0xF6, 0x6C, 0x1B, 0x59, 0x03,
+    0x1C, 0xB2, 0x17, 0xEE, 0xEC, 0x32, 0x5C, 0x53, 0xCB, 0xC8,
+    0x3E, 0x07, 0x22, 0x73, 0x74, 0xC3, 0x68, 0xCC, 0xC4, 0xF3,
+    0x7C, 0x35, 0x1D, 0x5F, 0x1D, 0xAD, 0x60, 0x99, 0x8A, 0x8C,
+    0x53, 0x5F, 0x0E, 0xDB, 0x31, 0x06, 0x89, 0x81, 0x09, 0x58,
+    0xA9, 0x6E, 0xF9, 0x43, 0x40, 0x1C, 0x06, 0x58, 0x0A, 0x23,
+    0xC5, 0x3E, 0x0A, 0x5E, 0x5B, 0x7E, 0xBA, 0x67, 0x14, 0xEC,
+    0xBF, 0x66, 0x31, 0xF9, 0xEF, 0xA9, 0xDF, 0xE5, 0x3F, 0x02,
+    0x0C, 0x00, 0xA5, 0xE1, 0x2F, 0x71, 0xD8, 0x1A, 0xDF, 0xDB,
+    0x00, 0x00, 0x00, 0x00, 0x49, 0x45, 0x4E, 0x44, 0xAE, 0x42,
+    0x60, 0x82
+};
+
+static unsigned char icon_adler32[664] =
+{
+    0x89, 0x50, 0x4E, 0x47, 0x0D, 0x0A, 0x1A, 0x0A, 0x00, 0x00,
+    0x00, 0x0D, 0x49, 0x48, 0x44, 0x52, 0x00, 0x00, 0x00, 0x10,
+    0x00, 0x00, 0x00, 0x10, 0x08, 0x06, 0x00, 0x00, 0x00, 0x1F,
+    0xF3, 0xFF, 0x61, 0x00, 0x00, 0x00, 0x19, 0x74, 0x45, 0x58,
+    0x74, 0x53, 0x6F, 0x66, 0x74, 0x77, 0x61, 0x72, 0x65, 0x00,
+    0x41, 0x64, 0x6F, 0x62, 0x65, 0x20, 0x49, 0x6D, 0x61, 0x67,
+    0x65, 0x52, 0x65, 0x61, 0x64, 0x79, 0x71, 0xC9, 0x65, 0x3C,
+    0x00, 0x00, 0x02, 0x3A, 0x49, 0x44, 0x41, 0x54, 0x78, 0xDA,
+    0x94, 0x93, 0x5F, 0x68, 0x92, 0x51, 0x18, 0xC6, 0x9F, 0xF3,
+    0x7D, 0x1A, 0x7C, 0x3A, 0x06, 0xC2, 0x24, 0x02, 0xBB, 0x30,
+    0x2A, 0x71, 0x88, 0x8D, 0xA0, 0x6E, 0xB2, 0xD2, 0x41, 0x17,
+    0x81, 0xCA, 0x17, 0x2B, 0xFA, 0x03, 0x0A, 0xC1, 0x12, 0x26,
+    0x06, 0x6D, 0xC4, 0x90, 0xBA, 0x30, 0x2F, 0xB2, 0x3F, 0x17,
+    0x5D, 0xEC, 0x22, 0xA8, 0x0D, 0x22, 0xA4, 0xBA, 0xC8, 0xD1,
+    0x4D, 0xD1, 0x45, 0x20, 0x6B, 0x83, 0xC8, 0x88, 0x99, 0x11,
+    0xC4, 0xA8, 0x51, 0x17, 0x93, 0x2E, 0xEC, 0x62, 0xD6, 0x14,
+    0x75, 0x47, 0x4F, 0xBE, 0x67, 0x4C, 0x08, 0x6C, 0xE1, 0x81,
+    0xC3, 0xCB, 0x7B, 0xDE, 0xDF, 0xF3, 0xF0, 0x9E, 0xF7, 0x3B,
+    0x1F, 0x53, 0x27, 0xD5, 0x3B, 0x00, 0xF6, 0xA1, 0xF7, 0x55,
+    0xE0, 0xB7, 0xF8, 0x84, 0x01, 0x2D, 0x0C, 0xF1, 0x2B, 0x4F,
+    0x7C, 0xE7, 0xE6, 0x9E, 0xC1, 0x6A, 0xB5, 0xFE, 0x57, 0x55,
+    0x2A, 0x95, 0xF0, 0xD8, 0x7B, 0x02, 0x86, 0xD4, 0x59, 0x46,
+    0xB9, 0xD2, 0x36, 0x60, 0x67, 0xB2, 0xB3, 0x68, 0x34, 0x1A,
+    0x18, 0xEE, 0xDF, 0x8E, 0x62, 0xB1, 0xB8, 0x65, 0x24, 0x8E,
+    0x78, 0xD2, 0x6D, 0x18, 0x34, 0xC1, 0x34, 0x4D, 0x43, 0xA5,
+    0x52, 0xC1, 0x60, 0x5D, 0xC3, 0xF2, 0xDB, 0x65, 0x1C, 0xB7,
+    0xEE, 0xEC, 0x1A, 0xA9, 0x4E, 0x1C, 0xF1, 0xA4, 0x23, 0x03,
+    0xA6, 0x5E, 0x54, 0x5F, 0xCF, 0x8E, 0x26, 0x8F, 0x38, 0xD6,
+    0x8C, 0xB8, 0x7A, 0x3B, 0x8B, 0x5F, 0x95, 0xE6, 0x3F, 0xDB,
+    0xEF, 0x37, 0xAB, 0xB8, 0x3E, 0x39, 0x8C, 0xA5, 0xBE, 0x75,
+    0x8C, 0xCC, 0x24, 0xE6, 0xF9, 0x14, 0x3F, 0x0A, 0x75, 0x4C,
+    0x9D, 0xD7, 0x1F, 0xE9, 0xC2, 0x15, 0x73, 0x09, 0xAF, 0xD7,
+    0x2B, 0x0A, 0x85, 0x82, 0x68, 0xB5, 0x5A, 0x22, 0x9F, 0xCF,
+    0x8B, 0x50, 0x28, 0x24, 0x23, 0xE5, 0x74, 0x4E, 0x75, 0xE2,
+    0x88, 0x27, 0x9D, 0x10, 0x02, 0x8A, 0x68, 0x0A, 0x76, 0xDA,
+    0xEE, 0xC4, 0xDC, 0xD8, 0x05, 0x70, 0xCE, 0x91, 0x4A, 0xA5,
+    0xA0, 0xEB, 0x3A, 0x9C, 0x4E, 0x27, 0xCA, 0xE5, 0x32, 0x12,
+    0x89, 0x84, 0xCC, 0x1D, 0x0E, 0x87, 0xAC, 0x13, 0x47, 0x3C,
+    0xE9, 0xA8, 0x2B, 0x03, 0xDD, 0xE5, 0xE1, 0xE7, 0x3C, 0xAE,
+    0xBD, 0xFB, 0x06, 0x0B, 0xB7, 0x20, 0x10, 0x08, 0xC0, 0xEF,
+    0xF7, 0x23, 0x9D, 0x4E, 0xA3, 0x56, 0xAB, 0xC1, 0xE3, 0xF1,
+    0x20, 0x12, 0x89, 0x20, 0x93, 0xC9, 0x48, 0x83, 0x43, 0x53,
+    0x77, 0x61, 0x3F, 0x68, 0xEF, 0xCC, 0x40, 0x01, 0x87, 0x72,
+    0xD2, 0xB6, 0x07, 0xAF, 0xCE, 0x87, 0xE4, 0x84, 0x49, 0x18,
+    0x0C, 0x06, 0xA5, 0x11, 0x19, 0x84, 0xC3, 0x61, 0x24, 0x93,
+    0x49, 0x79, 0x4E, 0x75, 0xE2, 0x88, 0x27, 0xDD, 0x46, 0x07,
+    0x1C, 0x2C, 0xFD, 0xE5, 0x23, 0x6E, 0x2C, 0xAE, 0xC0, 0xB4,
+    0x6E, 0x42, 0x2C, 0x16, 0x83, 0xDB, 0xED, 0x46, 0x2E, 0x97,
+    0x03, 0x63, 0x4C, 0xEE, 0x78, 0x3C, 0x2E, 0x87, 0x48, 0x9D,
+    0xF9, 0xEE, 0x3F, 0x80, 0x6D, 0xBF, 0x8D, 0x0C, 0x58, 0xC7,
+    0x60, 0x64, 0xC7, 0x2E, 0xB8, 0x7C, 0x4E, 0x5C, 0x7E, 0x9F,
+    0x45, 0x34, 0x1A, 0xFD, 0x6B, 0xF2, 0x74, 0x85, 0xCD, 0x65,
+    0xB5, 0x68, 0x98, 0xF6, 0x1D, 0xC3, 0x27, 0x53, 0x1D, 0x0B,
+    0x7C, 0xA1, 0x73, 0x05, 0xF6, 0xB4, 0xF8, 0x15, 0x97, 0xBE,
+    0xBF, 0xC1, 0xCD, 0xF1, 0xC3, 0x60, 0x5E, 0x86, 0x97, 0xF7,
+    0x4E, 0x75, 0x8D, 0x54, 0x27, 0x8E, 0xF8, 0xCD, 0x0E, 0x14,
+    0x34, 0xC0, 0xAA, 0xD5, 0x2A, 0x8C, 0x46, 0x23, 0x16, 0xD5,
+    0xDF, 0x18, 0x18, 0x1C, 0xC0, 0xF3, 0x9F, 0x2B, 0x5D, 0x23,
+    0xD5, 0x89, 0x23, 0x9E, 0x74, 0xD2, 0x40, 0x94, 0x05, 0x9B,
+    0xDE, 0x7D, 0x00, 0xED, 0x6F, 0x8D, 0x17, 0xAB, 0x3F, 0x60,
+    0x36, 0x9B, 0xB7, 0x8C, 0xC4, 0x11, 0x4F, 0x3A, 0xF9, 0x12,
+    0xB1, 0x17, 0x33, 0xE8, 0xC3, 0x50, 0xCF, 0xFF, 0xE2, 0x1A,
+    0x3E, 0x88, 0x25, 0x31, 0x4A, 0x2E, 0xDB, 0xDA, 0xDB, 0xD2,
+    0xDE, 0x6A, 0x0F, 0x72, 0x7A, 0xEF, 0xAB, 0xED, 0x97, 0x58,
+    0xFF, 0x23, 0xC0, 0x00, 0xB1, 0x22, 0x28, 0x4D, 0x19, 0x8C,
+    0xC8, 0xAB, 0x00, 0x00, 0x00, 0x00, 0x49, 0x45, 0x4E, 0x44,
+    0xAE, 0x42, 0x60, 0x82
+};
+
+#endif //_ICONS_H

pluginsdk/BeaEngine/BeaEngine.h

@@ -1,392 +0,0 @@
-#ifndef _BEA_ENGINE_
-#define _BEA_ENGINE_
-#if  defined(__cplusplus) && defined(__BORLANDC__)
-namespace BeaEngine
-{
-#endif
-
-#include "macros.h"
-#include "export.h"
-#include "basic_types.h"
-
-#if !defined(BEA_ENGINE_STATIC)
-#if defined(BUILD_BEA_ENGINE_DLL)
-#define BEA_API bea__api_export__
-#else
-#define BEA_API bea__api_import__
-#endif
-#else
-#define BEA_API
-#endif
-
-
-#define INSTRUCT_LENGTH 64
-
-#pragma pack(1)
-typedef struct
-{
-    UInt8 W_;
-    UInt8 R_;
-    UInt8 X_;
-    UInt8 B_;
-    UInt8 state;
-} REX_Struct  ;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct
-{
-    int Number;
-    int NbUndefined;
-    UInt8 LockPrefix;
-    UInt8 OperandSize;
-    UInt8 AddressSize;
-    UInt8 RepnePrefix;
-    UInt8 RepPrefix;
-    UInt8 FSPrefix;
-    UInt8 SSPrefix;
-    UInt8 GSPrefix;
-    UInt8 ESPrefix;
-    UInt8 CSPrefix;
-    UInt8 DSPrefix;
-    UInt8 BranchTaken;
-    UInt8 BranchNotTaken;
-    REX_Struct REX;
-    char alignment[2];
-} PREFIXINFO  ;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct
-{
-    UInt8 OF_;
-    UInt8 SF_;
-    UInt8 ZF_;
-    UInt8 AF_;
-    UInt8 PF_;
-    UInt8 CF_;
-    UInt8 TF_;
-    UInt8 IF_;
-    UInt8 DF_;
-    UInt8 NT_;
-    UInt8 RF_;
-    UInt8 alignment;
-} EFLStruct  ;
-#pragma pack()
-
-#pragma pack(4)
-typedef struct
-{
-    Int32 BaseRegister;
-    Int32 IndexRegister;
-    Int32 Scale;
-    Int64 Displacement;
-} MEMORYTYPE ;
-#pragma pack()
-
-
-#pragma pack(1)
-typedef struct
-{
-    Int32 Category; //INSTRUCTION_TYPE
-    Int32 Opcode;
-    char Mnemonic[16];
-    Int32 BranchType; //BRANCH_TYPE
-    EFLStruct Flags;
-    UInt64 AddrValue;
-    Int64 Immediat;
-    UInt32 ImplicitModifiedRegs;
-} INSTRTYPE;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct
-{
-    char ArgMnemonic[64];
-    Int32 ArgType; //ARGUMENTS_TYPE
-    Int32 ArgSize;
-    Int32 ArgPosition;
-    UInt32 AccessMode;
-    MEMORYTYPE Memory;
-    UInt32 SegmentReg;
-} ARGTYPE;
-#pragma pack()
-
-/* reserved structure used for thread-safety */
-/* unusable by customer */
-#pragma pack(1)
-typedef struct
-{
-    UIntPtr EIP_;
-    UInt64 EIP_VA;
-    UIntPtr EIP_REAL;
-    Int32 OriginalOperandSize;
-    Int32 OperandSize;
-    Int32 MemDecoration;
-    Int32 AddressSize;
-    Int32 MOD_;
-    Int32 RM_;
-    Int32 INDEX_;
-    Int32 SCALE_;
-    Int32 BASE_;
-    Int32 MMX_;
-    Int32 SSE_;
-    Int32 CR_;
-    Int32 DR_;
-    Int32 SEG_;
-    Int32 REGOPCODE;
-    UInt32 DECALAGE_EIP;
-    Int32 FORMATNUMBER;
-    Int32 SYNTAX_;
-    UInt64 EndOfBlock;
-    Int32 RelativeAddress;
-    UInt32 Architecture;
-    Int32 ImmediatSize;
-    Int32 NB_PREFIX;
-    Int32 PrefRepe;
-    Int32 PrefRepne;
-    UInt32 SEGMENTREGS;
-    UInt32 SEGMENTFS;
-    Int32 third_arg;
-    Int32 TAB_;
-    Int32 ERROR_OPCODE;
-    REX_Struct REX;
-    Int32 OutOfBlock;
-} InternalDatas;
-#pragma pack()
-
-/* ************** main structure ************ */
-#pragma pack(1)
-typedef struct _Disasm
-{
-    UIntPtr EIP;
-    UInt64 VirtualAddr;
-    UInt32 SecurityBlock;
-    char CompleteInstr[INSTRUCT_LENGTH];
-    UInt32 Archi;
-    UInt64 Options;
-    INSTRTYPE Instruction;
-    ARGTYPE Argument1;
-    ARGTYPE Argument2;
-    ARGTYPE Argument3;
-    PREFIXINFO Prefix;
-    InternalDatas Reserved_;
-} DISASM, *PDISASM, *LPDISASM;
-#pragma pack()
-
-#define ESReg 1
-#define DSReg 2
-#define FSReg 3
-#define GSReg 4
-#define CSReg 5
-#define SSReg 6
-
-#define InvalidPrefix 4
-#define SuperfluousPrefix 2
-#define NotUsedPrefix 0
-#define MandatoryPrefix 8
-#define InUsePrefix 1
-
-#define LowPosition 0
-#define HighPosition 1
-
-enum INSTRUCTION_TYPE
-{
-    GENERAL_PURPOSE_INSTRUCTION   =    0x10000,
-    FPU_INSTRUCTION               =    0x20000,
-    MMX_INSTRUCTION               =    0x40000,
-    SSE_INSTRUCTION               =    0x80000,
-    SSE2_INSTRUCTION              =   0x100000,
-    SSE3_INSTRUCTION              =   0x200000,
-    SSSE3_INSTRUCTION             =   0x400000,
-    SSE41_INSTRUCTION             =   0x800000,
-    SSE42_INSTRUCTION             =  0x1000000,
-    SYSTEM_INSTRUCTION            =  0x2000000,
-    VM_INSTRUCTION                =  0x4000000,
-    UNDOCUMENTED_INSTRUCTION      =  0x8000000,
-    AMD_INSTRUCTION               = 0x10000000,
-    ILLEGAL_INSTRUCTION           = 0x20000000,
-    AES_INSTRUCTION               = 0x40000000,
-    CLMUL_INSTRUCTION             = (int)0x80000000,
-
-
-    DATA_TRANSFER = 0x1,
-    ARITHMETIC_INSTRUCTION,
-    LOGICAL_INSTRUCTION,
-    SHIFT_ROTATE,
-    BIT_UInt8,
-    CONTROL_TRANSFER,
-    STRING_INSTRUCTION,
-    InOutINSTRUCTION,
-    ENTER_LEAVE_INSTRUCTION,
-    FLAG_CONTROL_INSTRUCTION,
-    SEGMENT_REGISTER,
-    MISCELLANEOUS_INSTRUCTION,
-    COMPARISON_INSTRUCTION,
-    LOGARITHMIC_INSTRUCTION,
-    TRIGONOMETRIC_INSTRUCTION,
-    UNSUPPORTED_INSTRUCTION,
-    LOAD_CONSTANTS,
-    FPUCONTROL,
-    STATE_MANAGEMENT,
-    CONVERSION_INSTRUCTION,
-    SHUFFLE_UNPACK,
-    PACKED_SINGLE_PRECISION,
-    SIMD128bits,
-    SIMD64bits,
-    CACHEABILITY_CONTROL,
-    FP_INTEGER_CONVERSION,
-    SPECIALIZED_128bits,
-    SIMD_FP_PACKED,
-    SIMD_FP_HORIZONTAL ,
-    AGENT_SYNCHRONISATION,
-    PACKED_ALIGN_RIGHT  ,
-    PACKED_SIGN,
-    PACKED_BLENDING_INSTRUCTION,
-    PACKED_TEST,
-    PACKED_MINMAX,
-    HORIZONTAL_SEARCH,
-    PACKED_EQUALITY,
-    STREAMING_LOAD,
-    INSERTION_EXTRACTION,
-    DOT_PRODUCT,
-    SAD_INSTRUCTION,
-    ACCELERATOR_INSTRUCTION,    /* crc32, popcnt (sse4.2) */
-    ROUND_INSTRUCTION
-};
-
-enum EFLAGS_STATES
-{
-    TE_ = 1,
-    MO_ = 2,
-    RE_ = 4,
-    SE_ = 8,
-    UN_ = 0x10,
-    PR_ = 0x20
-};
-
-enum BRANCH_TYPE
-{
-    //JO vs JNO
-    JO = 1,
-    JNO = -1,
-    //JC=JB=JNAE vs JNC=JNB=JAE
-    JC = 2,
-    JB = 2,
-    JNAE = 2,
-    JNC = -2,
-    JNB = -2,
-    JAE = -2,
-    //JE=JZ vs JNE=JNZ
-    JE = 3,
-    JZ = 3,
-    JNE = -3,
-    JNZ = -3,
-    //JA=JNBE vs JNA=JBE
-    JA = 4,
-    JNBE = 4,
-    JNA = -4,
-    JBE = -4,
-    //JS vs JNS
-    JS = 5,
-    JNS = -5,
-    //JP=JPE vs JNP=JPO
-    JP = 6,
-    JPE = 6,
-    JNP = -6,
-    JPO = -6,
-    //JL=JNGE vs JNL=JGE
-    JL = 7,
-    JNGE = 7,
-    JNL = -7,
-    JGE = -7,
-    //JG=JNLE vs JNG=JLE
-    JG = 8,
-    JNLE = 8,
-    JNG = -8,
-    JLE = -8,
-    //others
-    JECXZ = 9,
-    JmpType = 10,
-    CallType = 11,
-    RetType = 12,
-};
-
-enum ARGUMENTS_TYPE
-{
-    NO_ARGUMENT = 0x10000000,
-    REGISTER_TYPE = 0x20000000,
-    MEMORY_TYPE = 0x40000000,
-    CONSTANT_TYPE = (int)0x80000000,
-
-    MMX_REG = 0x10000,
-    GENERAL_REG = 0x20000,
-    FPU_REG = 0x40000,
-    SSE_REG = 0x80000,
-    CR_REG = 0x100000,
-    DR_REG = 0x200000,
-    SPECIAL_REG = 0x400000,
-    MEMORY_MANAGEMENT_REG = 0x800000,
-    SEGMENT_REG = 0x1000000,
-
-    RELATIVE_ = 0x4000000,
-    ABSOLUTE_ = 0x8000000,
-
-    READ = 0x1,
-    WRITE = 0x2,
-
-    REG0 = 0x1,
-    REG1 = 0x2,
-    REG2 = 0x4,
-    REG3 = 0x8,
-    REG4 = 0x10,
-    REG5 = 0x20,
-    REG6 = 0x40,
-    REG7 = 0x80,
-    REG8 = 0x100,
-    REG9 = 0x200,
-    REG10 = 0x400,
-    REG11 = 0x800,
-    REG12 = 0x1000,
-    REG13 = 0x2000,
-    REG14 = 0x4000,
-    REG15 = 0x8000
-};
-
-enum SPECIAL_INFO
-{
-    UNKNOWN_OPCODE = -1,
-    OUT_OF_BLOCK = 0,
-
-    /* === mask = 0xff */
-    NoTabulation      = 0x00000000,
-    Tabulation        = 0x00000001,
-
-    /* === mask = 0xff00 */
-    MasmSyntax        = 0x00000000,
-    GoAsmSyntax       = 0x00000100,
-    NasmSyntax        = 0x00000200,
-    ATSyntax          = 0x00000400,
-
-    /* === mask = 0xff0000 */
-    PrefixedNumeral   = 0x00010000,
-    SuffixedNumeral   = 0x00020000,
-    NoformatNumeral   = 0x00030000,
-    CleanNumeral      = 0x00000000,
-
-    /* === mask = 0xff000000 */
-    ShowSegmentRegs   = 0x01000000
-};
-
-#ifdef __cplusplus
-extern "C"
-#endif
-
-BEA_API int __bea_callspec__ Disasm(LPDISASM pDisAsm);
-BEA_API const__ char* __bea_callspec__ BeaEngineVersion(void);
-BEA_API const__ char* __bea_callspec__ BeaEngineRevision(void);
-#if  defined(__cplusplus) && defined(__BORLANDC__)
-};
-using namespace BeaEngine;
-#endif
-#endif

pluginsdk/BeaEngine/basic_types.h

@@ -1,272 +0,0 @@
-/**
- * @file   basic_types.h
- * @author  <[email protected]>
- * @date   Thu Dec 24 19:31:22 2009
- *
- * @brief  Definitions of fixed-size integer types for various platforms
- *
- * This file is part of BeaEngine.
- *
- *    BeaEngine is free software: you can redistribute it and/or modify
- *    it under the terms of the GNU Lesser General Public License as published by
- *    the Free Software Foundation, either version 3 of the License, or
- *    (at your option) any later version.
- *
- *    BeaEngine is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU Lesser General Public License for more details.
- *
- *    You should have received a copy of the GNU Lesser General Public License
- *    along with BeaEngine.  If not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef __BEA_BASIC_TYPES_HPP__
-#define __BEA_BASIC_TYPES_HPP__
-
-#include <stddef.h>
-
-#if defined(__GNUC__) || defined (__INTEL_COMPILER) || defined(__LCC__) || defined(__POCC__)
-#include <stdint.h>
-#endif
-
-#if defined(_MSC_VER) && !defined(__BORLANDC__)
-/*
-* Windows/Visual C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed __int64         Int64;
-typedef unsigned __int64       UInt64;
-#if defined(_WIN64)
-#define BEA_PTR_IS_64_BIT 1
-typedef signed __int64     IntPtr;
-typedef unsigned __int64   UIntPtr;
-#else
-typedef signed long        IntPtr;
-typedef size_t             UIntPtr;
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__POCC__)
-/*
-* PellesC
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed long long       Int64;
-typedef unsigned long long     UInt64;
-#if defined(_WIN64)
-#define BEA_PTR_IS_64_BIT 1
-typedef signed long long   IntPtr;
-typedef unsigned long long UIntPtr;
-#else
-typedef signed long        IntPtr;
-typedef size_t             UIntPtr;
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__GNUC__) || defined(__LCC__)
-/*
-* Unix/GCC
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef intptr_t               IntPtr;
-typedef uintptr_t              UIntPtr;
-#if defined(__LP64__)
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-typedef signed long        Int64;
-typedef unsigned long      UInt64;
-#else
-#if defined (__INTEL_COMPILER) || defined (__ICC) || defined (_ICC)
-typedef __int64           Int64;
-typedef unsigned __int64  UInt64;
-#else
-typedef signed long long   Int64;
-typedef unsigned long long UInt64;
-#endif
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__DECCXX)
-/*
-* Compaq C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed __int64         Int64;
-typedef unsigned __int64       UInt64;
-#if defined(__VMS)
-#if defined(__32BITS)
-typedef signed long    IntPtr;
-typedef unsigned long  UIntPtr;
-#else
-typedef Int64          IntPtr;
-typedef UInt64         UIntPtr;
-#define BEA_PTR_IS_64_BIT 1
-#endif
-#else
-typedef signed long        IntPtr;
-typedef unsigned long      UIntPtr;
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__HP_aCC)
-/*
-* HP Ansi C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed long            IntPtr;
-typedef unsigned long          UIntPtr;
-#if defined(__LP64__)
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-typedef signed long        Int64;
-typedef unsigned long      UInt64;
-#else
-typedef signed long long   Int64;
-typedef unsigned long long UInt64;
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__SUNPRO_CC) || defined(__SUNPRO_C)
-/*
-* SUN Forte C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed long            IntPtr;
-typedef unsigned long          UIntPtr;
-#if defined(__sparcv9)
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-typedef signed long        Int64;
-typedef unsigned long      UInt64;
-#else
-typedef signed long long   Int64;
-typedef unsigned long long UInt64;
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__IBMCPP__)
-/*
-* IBM XL C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed long            IntPtr;
-typedef unsigned long          UIntPtr;
-#if defined(__64BIT__)
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-typedef signed long        Int64;
-typedef unsigned long      UInt64;
-#else
-typedef signed long long   Int64;
-typedef unsigned long long UInt64;
-#endif
-#define BEA_HAVE_INT64 1
-#elif defined(__BORLANDC__)
-/*
-* Borland C/C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef unsigned __int64       Int64;
-typedef signed __int64         UInt64;
-typedef signed long            IntPtr;
-typedef unsigned long          UIntPtr;
-#define BEA_HAVE_INT64 1
-#elif defined(__WATCOMC__)
-/*
-* Watcom C/C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef unsigned __int64       Int64;
-typedef signed __int64         UInt64;
-#define BEA_HAVE_INT64 1
-typedef size_t                 UIntPtr;
-#elif defined(__sgi)
-/*
-* MIPSpro C++
-*/
-typedef signed char            Int8;
-typedef unsigned char          UInt8;
-typedef signed short           Int16;
-typedef unsigned short         UInt16;
-typedef signed int             Int32;
-typedef unsigned int           UInt32;
-typedef signed long            IntPtr;
-typedef unsigned long          UIntPtr;
-#if _MIPS_SZLONG == 64
-#define BEA_PTR_IS_64_BIT 1
-#define BEA_LONG_IS_64_BIT 1
-typedef signed long        Int64;
-typedef unsigned long      UInt64;
-#else
-typedef signed long long   Int64;
-typedef unsigned long long UInt64;
-#endif
-#define BEA_HAVE_INT64 1
-#endif
-
-#if defined(_MSC_VER) || defined(__BORLANDC__)
-#define W64LIT(x) x##ui64
-#else
-#define W64LIT(x) x##ULL
-#endif
-
-
-#ifndef C_STATIC_ASSERT
-#define C_STATIC_ASSERT(tag_name, x)            \
-       typedef int cache_static_assert_ ## tag_name[(x) * 2-1]
-#endif
-
-C_STATIC_ASSERT(sizeof_Int8 , (sizeof(Int8)  == 1));
-C_STATIC_ASSERT(sizeof_UInt8, (sizeof(UInt8) == 1));
-
-C_STATIC_ASSERT(sizeof_Int16 , (sizeof(Int16)  == 2));
-C_STATIC_ASSERT(sizeof_UInt16, (sizeof(UInt16) == 2));
-
-C_STATIC_ASSERT(sizeof_Int32 , (sizeof(Int32)  == 4));
-C_STATIC_ASSERT(sizeof_UInt32, (sizeof(UInt32) == 4));
-
-C_STATIC_ASSERT(sizeof_Int64 , (sizeof(Int64)  == 8));
-C_STATIC_ASSERT(sizeof_UInt64, (sizeof(UInt64) == 8));
-
-#endif

pluginsdk/BeaEngine/export.h

@@ -1,173 +0,0 @@
-/**
- * @file   export.h
- * @author [email protected]
- * @date   Mon Sep 22 09:28:54 2008
- *
- * @brief  This file sets things up for C dynamic library function definitions and
- *         static inlined functions
- *
- * This file is part of BeaEngine.
- *
- *    BeaEngine is free software: you can redistribute it and/or modify
- *    it under the terms of the GNU Lesser General Public License as published by
- *    the Free Software Foundation, either version 3 of the License, or
- *    (at your option) any later version.
- *
- *    BeaEngine is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU Lesser General Public License for more details.
- *
- *    You should have received a copy of the GNU Lesser General Public License
- *    along with BeaEngine.  If not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef __BEA_EXPORT_H__
-#define __BEA_EXPORT_H__
-
-
-/*  Set up for C function definitions, even when using C++ */
-
-#ifdef __cplusplus
-#define CPP_VISIBLE_BEGIN extern "C" {
-#define CPP_VISIBLE_END }
-#else
-#define CPP_VISIBLE_BEGIN
-#define CPP_VISIBLE_END
-#endif
-
-#if defined(_MSC_VER)
-#pragma warning( disable: 4251 )
-#endif
-
-/* Some compilers use a special export keyword */
-#ifndef bea__api_export__
-# if defined(__BEOS__)
-#  if defined(__GNUC__)
-#   define bea__api_export__        __declspec(dllexport)
-#  else
-#   define bea__api_export__        __declspec(export)
-#  endif
-# elif defined(_WIN32) || defined(_WIN64)
-#  ifdef __BORLANDC__
-#    define bea__api_export__   __declspec(dllexport)
-#    define bea__api_import__     __declspec(dllimport)
-#  elif defined(__WATCOMC__)
-#    define bea__api_export__    __declspec(dllexport)
-#    define bea__api_import__
-#  else
-#   define bea__api_export__        __declspec(dllexport)
-#   define bea__api_import__        __declspec(dllimport)
-#  endif
-# elif defined(__OS2__)
-#  ifdef __WATCOMC__
-#    define bea__api_export__    __declspec(dllexport)
-#    define bea__api_import__
-#  else
-#   define bea__api_export__
-#   define bea__api_import__
-#  endif
-# else
-#  if defined(_WIN32) && defined(__GNUC__) && __GNUC__ >= 4
-#   define bea__api_export__        __attribubea__ ((visibility("default")))
-#   define bea__api_import__        __attribubea__ ((visibility("default")))
-#  else
-#   define bea__api_export__
-#   define bea__api_import__
-#  endif
-# endif
-#endif
-
-/* Use C calling convention by default*/
-
-#ifndef __bea_callspec__
-#if defined(BEA_USE_STDCALL)
-#if defined(__WIN32__) || defined(WIN32) || defined(_WIN32) || defined(_WIN64)
-#if defined(__BORLANDC__) || defined(__WATCOMC__) || defined(_MSC_VER) || defined(__MINGW32__) || defined(__POCC__)
-#define __bea_callspec__     __stdcall
-#else
-#define __bea_callspec__
-#endif
-#else
-#ifdef __OS2__
-#define __bea_callspec__ _System
-#else
-#define __bea_callspec__
-#endif
-#endif
-#else
-#define __bea_callspec__
-#endif
-#endif
-
-#ifdef __SYMBIAN32__
-#    ifndef EKA2
-#        undef bea__api_export__
-#        undef bea__api_import__
-#        define bea__api_export__
-#        define bea__api_import__
-#    elif !defined(__WINS__)
-#        undef bea__api_export__
-#        undef bea__api_import__
-#        define bea__api_export__ __declspec(dllexport)
-#        define bea__api_import__ __declspec(dllexport)
-#    endif /* !EKA2 */
-#endif /* __SYMBIAN32__ */
-
-
-#if defined(__GNUC__) && (__GNUC__ > 2)
-#define BEA_EXPECT_CONDITIONAL(c)    (__builtin_expect((c), 1))
-#define BEA_UNEXPECT_CONDITIONAL(c)  (__builtin_expect((c), 0))
-#else
-#define BEA_EXPECT_CONDITIONAL(c)    (c)
-#define BEA_UNEXPECT_CONDITIONAL(c)  (c)
-#endif
-
-
-/* Set up compiler-specific options for inlining functions */
-#ifndef BEA_HAS_INLINE
-#if defined(__GNUC__) || defined(__POCC__) || defined(__WATCOMC__) || defined(__SUNPRO_C)
-#define BEA_HAS_INLINE
-#else
-/* Add any special compiler-specific cases here */
-#if defined(_MSC_VER) || defined(__BORLANDC__) ||    \
-  defined(__DMC__) || defined(__SC__) ||        \
-  defined(__WATCOMC__) || defined(__LCC__) ||        \
-  defined(__DECC) || defined(__EABI__)
-#ifndef __inline__
-#define __inline__    __inline
-#endif
-#define BEA_HAS_INLINE
-#else
-#if !defined(__MRC__) && !defined(_SGI_SOURCE)
-#ifndef __inline__
-#define __inline__ inline
-#endif
-#define BEA_HAS_INLINE
-#endif /* Not a funky compiler */
-#endif /* Visual C++ */
-#endif /* GNU C */
-#endif /* CACHE_HAS_INLINE */
-
-/* If inlining isn't supported, remove "__inline__", turning static
-   inlined functions into static functions (resulting in code bloat
-   in all files which include the offending header files)
-*/
-#ifndef BEA_HAS_INLINE
-#define __inline__
-#endif
-
-/* fix a bug with gcc under windows */
-
-#if defined(__WIN32__) || defined(WIN32) || defined(_WIN32) || defined(_WIN64)
-#if defined(__MINGW32__)
-#define const__
-#else
-#define const__ const
-#endif
-#else
-#define const__ const
-#endif
-
-
-
-#endif

pluginsdk/BeaEngine/macros.h

@@ -1,41 +0,0 @@
-#ifndef __BEAENGINE_MACROS_H__
-#define __BEAENGINE_MACROS_H__
-/*
-============================================================================
- Compiler Silencing macros
-
- Some compilers complain about parameters that are not used.  This macro
- should keep them quiet.
- ============================================================================
- */
-
-# if defined (__GNUC__) && ((__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 2)))
-#   define BEA_UNUSED_ARG(a) (void) (a)
-#elif defined (ghs) || defined (__GNUC__) || defined (__hpux) || defined (__sgi) || defined (__DECCXX) || defined (__rational__) || defined (__USLC__) || defined (BEA__RM544) || defined (__DCC__) || defined (__PGI) || defined (__TANDEM) || defined(__BORLANDC__)
-/*
- Some compilers complain about "statement with no effect" with (a).
- This eliminates the warnings, and no code is generated for the null
- conditional statement.  Note, that may only be true if -O is enabled,
- such as with GreenHills (ghs) 1.8.8.
- */
-
-# define BEA_UNUSED_ARG(a) do {/* null */} while (&a == 0)
-#elif defined (__DMC__)
-#if defined(__cplusplus)
-#define BEA_UNUSED_ID(identifier)
-template <class T>
-inline void BEA_UNUSED_ARG(const T & BEA_UNUSED_ID(t)) { }
-#else
-#define BEA_UNUSED_ARG(a)
-#endif
-#else /* ghs || __GNUC__ || ..... */
-# define BEA_UNUSED_ARG(a) (a)
-#endif /* ghs || __GNUC__ || ..... */
-
-#if defined (_MSC_VER) || defined(__sgi) || defined (ghs) || defined (__DECCXX) || defined(__BORLANDC__) || defined (BEA_RM544) || defined (__USLC__) || defined (__DCC__) || defined (__PGI) || defined (__TANDEM) || (defined (__HP_aCC) && (__HP_aCC >= 60500))
-# define BEA_NOTREACHED(a)
-#else  /* __sgi || ghs || ..... */
-# define BEA_NOTREACHED(a) a
-#endif /* __sgi || ghs || ..... */
-
-#endif /* __BEAENGINE_MACROS_H__ */

pluginsdk/_dbgfunctions.h

@@ -65,6 +65,8 @@ typedef bool (*GETCMDLINE)(char* cmdline, size_t* cbsize);
 typedef bool (*SETCMDLINE)(const char* cmdline);
 typedef duint (*FILEOFFSETTOVA)(const char* modname, duint offset);
 typedef duint (*VATOFILEOFFSET)(duint va);
+typedef duint (*GETADDRFROMLINE)(const char* szSourceFile, int line);
+typedef bool(*GETSOURCEFROMADDR)(duint addr, char* szSourceFile, int* line);
 
 typedef struct DBGFUNCTIONS_
 {
@@ -100,6 +102,8 @@ typedef struct DBGFUNCTIONS_
     SETCMDLINE SetCmdline;
     FILEOFFSETTOVA FileOffsetToVa;
     VATOFILEOFFSET VaToFileOffset;
+    GETADDRFROMLINE GetAddrFromLine;
+    GETSOURCEFROMADDR GetSourceFromAddr;
 } DBGFUNCTIONS;
 
 #ifdef BUILD_DBG

pluginsdk/_plugins.h

@@ -210,6 +210,8 @@ PLUG_IMPEXP int _plugin_menuadd(int hMenu, const char* title);
 PLUG_IMPEXP bool _plugin_menuaddentry(int hMenu, int hEntry, const char* title);
 PLUG_IMPEXP bool _plugin_menuaddseparator(int hMenu);
 PLUG_IMPEXP bool _plugin_menuclear(int hMenu);
+PLUG_IMPEXP void _plugin_menuseticon(int hMenu, const ICONDATA* icon);
+PLUG_IMPEXP void _plugin_menuentryseticon(int pluginHandle, int hEntry, const ICONDATA* icon);
 
 #ifdef __cplusplus
 }

pluginsdk/bridgemain.h

@@ -37,7 +37,7 @@ extern "C"
 
 //Bridge defines
 #define MAX_SETTING_SIZE 65536
-#define DBG_VERSION 24
+#define DBG_VERSION 25
 
 //Bridge functions
 BRIDGE_IMPEXP const char* BridgeInit();
@@ -501,6 +501,12 @@ typedef struct
 #endif
 } REGISTERCONTEXT;
 
+typedef struct
+{
+    DWORD code;
+    const char* name;
+} LASTERROR;
+
 typedef struct
 {
     REGISTERCONTEXT regcontext;
@@ -510,6 +516,7 @@ typedef struct
     MXCSRFIELDS MxCsrFields;
     X87STATUSWORDFIELDS x87StatusWordFields;
     X87CONTROLWORDFIELDS x87ControlWordFields;
+    LASTERROR lastError;
 } REGDUMP;
 
 typedef struct
@@ -540,8 +547,8 @@ typedef struct
 typedef struct
 {
     int ThreadNumber;
-    HANDLE hThread;
+    HANDLE Handle;
-    DWORD dwThreadId;
+    DWORD ThreadId;
     duint ThreadStartAddress;
     duint ThreadLocalBase;
     char threadName[MAX_THREAD_NAME_SIZE];
@@ -749,7 +756,10 @@ typedef enum
     GUI_UPDATE_CALLSTACK,           // param1=unused,               param2=unused
     GUI_SYMBOL_REFRESH_CURRENT,     // param1=unused,               param2=unused
     GUI_UPDATE_MEMORY_VIEW,         // param1=unused,               param2=unused
-    GUI_REF_INITIALIZE              // param1=const char* name      param2=unused
+    GUI_REF_INITIALIZE,             // param1=const char* name,     param2=unused
+    GUI_LOAD_SOURCE_FILE,           // param1=const char* path,     param2=line
+    GUI_MENU_SET_ICON,              // param1=int hMenu,            param2=ICONINFO*
+    GUI_MENU_SET_ENTRY_ICON         // param1=int hEntry,           param2=ICONINFO*
 } GUIMSG;
 
 //GUI structures
@@ -766,6 +776,12 @@ typedef struct
     duint end;
 } SELECTIONDATA;
 
+typedef struct
+{
+    const void* data;
+    duint size;
+} ICONDATA;
+
 //GUI functions
 BRIDGE_IMPEXP void GuiDisasmAt(duint addr, duint cip);
 BRIDGE_IMPEXP void GuiSetDebugState(DBGSTATE state);
@@ -826,6 +842,9 @@ BRIDGE_IMPEXP void GuiRepaintTableView();
 BRIDGE_IMPEXP void GuiUpdatePatches();
 BRIDGE_IMPEXP void GuiUpdateCallStack();
 BRIDGE_IMPEXP void GuiUpdateMemoryView();
+BRIDGE_IMPEXP void GuiLoadSourceFile(const char* path, int line);
+BRIDGE_IMPEXP void GuiMenuSetIcon(int hMenu, const ICONDATA* icon);
+BRIDGE_IMPEXP void GuiMenuSetEntryIcon(int hEntry, const ICONDATA* icon);
 
 #ifdef __cplusplus
 }

pluginsdk/capstone/arm.h

@@ -0,0 +1,897 @@
+#ifndef CAPSTONE_ARM_H
+#define CAPSTONE_ARM_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> ARM shift type
+typedef enum arm_shifter
+{
+    ARM_SFT_INVALID = 0,
+    ARM_SFT_ASR,    // shift with immediate const
+    ARM_SFT_LSL,    // shift with immediate const
+    ARM_SFT_LSR,    // shift with immediate const
+    ARM_SFT_ROR,    // shift with immediate const
+    ARM_SFT_RRX,    // shift with immediate const
+    ARM_SFT_ASR_REG,    // shift with register
+    ARM_SFT_LSL_REG,    // shift with register
+    ARM_SFT_LSR_REG,    // shift with register
+    ARM_SFT_ROR_REG,    // shift with register
+    ARM_SFT_RRX_REG,    // shift with register
+} arm_shifter;
+
+//> ARM condition code
+typedef enum arm_cc
+{
+    ARM_CC_INVALID = 0,
+    ARM_CC_EQ,            // Equal                      Equal
+    ARM_CC_NE,            // Not equal                  Not equal, or unordered
+    ARM_CC_HS,            // Carry set                  >, ==, or unordered
+    ARM_CC_LO,            // Carry clear                Less than
+    ARM_CC_MI,            // Minus, negative            Less than
+    ARM_CC_PL,            // Plus, positive or zero     >, ==, or unordered
+    ARM_CC_VS,            // Overflow                   Unordered
+    ARM_CC_VC,            // No overflow                Not unordered
+    ARM_CC_HI,            // Unsigned higher            Greater than, or unordered
+    ARM_CC_LS,            // Unsigned lower or same     Less than or equal
+    ARM_CC_GE,            // Greater than or equal      Greater than or equal
+    ARM_CC_LT,            // Less than                  Less than, or unordered
+    ARM_CC_GT,            // Greater than               Greater than
+    ARM_CC_LE,            // Less than or equal         <, ==, or unordered
+    ARM_CC_AL             // Always (unconditional)     Always (unconditional)
+} arm_cc;
+
+typedef enum arm_sysreg
+{
+    //> Special registers for MSR
+    ARM_SYSREG_INVALID = 0,
+
+    // SPSR* registers can be OR combined
+    ARM_SYSREG_SPSR_C = 1,
+    ARM_SYSREG_SPSR_X = 2,
+    ARM_SYSREG_SPSR_S = 4,
+    ARM_SYSREG_SPSR_F = 8,
+
+    // CPSR* registers can be OR combined
+    ARM_SYSREG_CPSR_C = 16,
+    ARM_SYSREG_CPSR_X = 32,
+    ARM_SYSREG_CPSR_S = 64,
+    ARM_SYSREG_CPSR_F = 128,
+
+    // independent registers
+    ARM_SYSREG_APSR = 256,
+    ARM_SYSREG_APSR_G,
+    ARM_SYSREG_APSR_NZCVQ,
+    ARM_SYSREG_APSR_NZCVQG,
+
+    ARM_SYSREG_IAPSR,
+    ARM_SYSREG_IAPSR_G,
+    ARM_SYSREG_IAPSR_NZCVQG,
+
+    ARM_SYSREG_EAPSR,
+    ARM_SYSREG_EAPSR_G,
+    ARM_SYSREG_EAPSR_NZCVQG,
+
+    ARM_SYSREG_XPSR,
+    ARM_SYSREG_XPSR_G,
+    ARM_SYSREG_XPSR_NZCVQG,
+
+    ARM_SYSREG_IPSR,
+    ARM_SYSREG_EPSR,
+    ARM_SYSREG_IEPSR,
+
+    ARM_SYSREG_MSP,
+    ARM_SYSREG_PSP,
+    ARM_SYSREG_PRIMASK,
+    ARM_SYSREG_BASEPRI,
+    ARM_SYSREG_BASEPRI_MAX,
+    ARM_SYSREG_FAULTMASK,
+    ARM_SYSREG_CONTROL,
+} arm_sysreg;
+
+//> The memory barrier constants map directly to the 4-bit encoding of
+//> the option field for Memory Barrier operations.
+typedef enum arm_mem_barrier
+{
+    ARM_MB_INVALID = 0,
+    ARM_MB_RESERVED_0,
+    ARM_MB_OSHLD,
+    ARM_MB_OSHST,
+    ARM_MB_OSH,
+    ARM_MB_RESERVED_4,
+    ARM_MB_NSHLD,
+    ARM_MB_NSHST,
+    ARM_MB_NSH,
+    ARM_MB_RESERVED_8,
+    ARM_MB_ISHLD,
+    ARM_MB_ISHST,
+    ARM_MB_ISH,
+    ARM_MB_RESERVED_12,
+    ARM_MB_LD,
+    ARM_MB_ST,
+    ARM_MB_SY,
+} arm_mem_barrier;
+
+//> Operand type for instruction's operands
+typedef enum arm_op_type
+{
+    ARM_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+    ARM_OP_REG, // = CS_OP_REG (Register operand).
+    ARM_OP_IMM, // = CS_OP_IMM (Immediate operand).
+    ARM_OP_MEM, // = CS_OP_MEM (Memory operand).
+    ARM_OP_FP,  // = CS_OP_FP (Floating-Point operand).
+    ARM_OP_CIMM = 64, // C-Immediate (coprocessor registers)
+    ARM_OP_PIMM, // P-Immediate (coprocessor registers)
+    ARM_OP_SETEND,  // operand for SETEND instruction
+    ARM_OP_SYSREG,  // MSR/MSR special register operand
+} arm_op_type;
+
+//> Operand type for SETEND instruction
+typedef enum arm_setend_type
+{
+    ARM_SETEND_INVALID = 0, // Uninitialized.
+    ARM_SETEND_BE,  // BE operand.
+    ARM_SETEND_LE, // LE operand
+} arm_setend_type;
+
+typedef enum arm_cpsmode_type
+{
+    ARM_CPSMODE_INVALID = 0,
+    ARM_CPSMODE_IE = 2,
+    ARM_CPSMODE_ID = 3
+} arm_cpsmode_type;
+
+//> Operand type for SETEND instruction
+typedef enum arm_cpsflag_type
+{
+    ARM_CPSFLAG_INVALID = 0,
+    ARM_CPSFLAG_F = 1,
+    ARM_CPSFLAG_I = 2,
+    ARM_CPSFLAG_A = 4,
+    ARM_CPSFLAG_NONE = 16,  // no flag
+} arm_cpsflag_type;
+
+//> Data type for elements of vector instructions.
+typedef enum arm_vectordata_type
+{
+    ARM_VECTORDATA_INVALID = 0,
+
+    // Integer type
+    ARM_VECTORDATA_I8,
+    ARM_VECTORDATA_I16,
+    ARM_VECTORDATA_I32,
+    ARM_VECTORDATA_I64,
+
+    // Signed integer type
+    ARM_VECTORDATA_S8,
+    ARM_VECTORDATA_S16,
+    ARM_VECTORDATA_S32,
+    ARM_VECTORDATA_S64,
+
+    // Unsigned integer type
+    ARM_VECTORDATA_U8,
+    ARM_VECTORDATA_U16,
+    ARM_VECTORDATA_U32,
+    ARM_VECTORDATA_U64,
+
+    // Data type for VMUL/VMULL
+    ARM_VECTORDATA_P8,
+
+    // Floating type
+    ARM_VECTORDATA_F32,
+    ARM_VECTORDATA_F64,
+
+    // Convert float <-> float
+    ARM_VECTORDATA_F16F64,  // f16.f64
+    ARM_VECTORDATA_F64F16,  // f64.f16
+    ARM_VECTORDATA_F32F16,  // f32.f16
+    ARM_VECTORDATA_F16F32,  // f32.f16
+    ARM_VECTORDATA_F64F32,  // f64.f32
+    ARM_VECTORDATA_F32F64,  // f32.f64
+
+    // Convert integer <-> float
+    ARM_VECTORDATA_S32F32,  // s32.f32
+    ARM_VECTORDATA_U32F32,  // u32.f32
+    ARM_VECTORDATA_F32S32,  // f32.s32
+    ARM_VECTORDATA_F32U32,  // f32.u32
+    ARM_VECTORDATA_F64S16,  // f64.s16
+    ARM_VECTORDATA_F32S16,  // f32.s16
+    ARM_VECTORDATA_F64S32,  // f64.s32
+    ARM_VECTORDATA_S16F64,  // s16.f64
+    ARM_VECTORDATA_S16F32,  // s16.f64
+    ARM_VECTORDATA_S32F64,  // s32.f64
+    ARM_VECTORDATA_U16F64,  // u16.f64
+    ARM_VECTORDATA_U16F32,  // u16.f32
+    ARM_VECTORDATA_U32F64,  // u32.f64
+    ARM_VECTORDATA_F64U16,  // f64.u16
+    ARM_VECTORDATA_F32U16,  // f32.u16
+    ARM_VECTORDATA_F64U32,  // f64.u32
+} arm_vectordata_type;
+
+// Instruction's operand referring to memory
+// This is associated with ARM_OP_MEM operand type above
+typedef struct arm_op_mem
+{
+    unsigned int base;  // base register
+    unsigned int index; // index register
+    int scale;  // scale for index register (can be 1, or -1)
+    int disp;   // displacement/offset value
+} arm_op_mem;
+
+// Instruction operand
+typedef struct cs_arm_op
+{
+    int vector_index;   // Vector Index for some vector operands (or -1 if irrelevant)
+    struct
+    {
+        arm_shifter type;
+        unsigned int value;
+    } shift;
+    arm_op_type type;   // operand type
+    union
+    {
+        unsigned int reg;   // register value for REG/SYSREG operand
+        int32_t imm;            // immediate value for C-IMM, P-IMM or IMM operand
+        double fp;          // floating point value for FP operand
+        arm_op_mem mem;     // base/index/scale/disp value for MEM operand
+        arm_setend_type setend; // SETEND instruction's operand type
+    };
+    // in some instructions, an operand can be subtracted or added to
+    // the base register,
+    bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added.
+} cs_arm_op;
+
+// Instruction structure
+typedef struct cs_arm
+{
+    bool usermode;  // User-mode registers to be loaded (for LDM/STM instructions)
+    int vector_size;    // Scalar size for vector instructions
+    arm_vectordata_type vector_data; // Data type for elements of vector instructions
+    arm_cpsmode_type cps_mode;  // CPS mode for CPS instruction
+    arm_cpsflag_type cps_flag;  // CPS mode for CPS instruction
+    arm_cc cc;          // conditional code for this insn
+    bool update_flags;  // does this insn update flags?
+    bool writeback;     // does this insn write-back?
+    arm_mem_barrier mem_barrier;    // Option for some memory barrier instructions
+
+    // Number of operands of this instruction,
+    // or 0 when instruction has no operand.
+    uint8_t op_count;
+
+    cs_arm_op operands[36]; // operands for this instruction.
+} cs_arm;
+
+//> ARM registers
+typedef enum arm_reg
+{
+    ARM_REG_INVALID = 0,
+    ARM_REG_APSR,
+    ARM_REG_APSR_NZCV,
+    ARM_REG_CPSR,
+    ARM_REG_FPEXC,
+    ARM_REG_FPINST,
+    ARM_REG_FPSCR,
+    ARM_REG_FPSCR_NZCV,
+    ARM_REG_FPSID,
+    ARM_REG_ITSTATE,
+    ARM_REG_LR,
+    ARM_REG_PC,
+    ARM_REG_SP,
+    ARM_REG_SPSR,
+    ARM_REG_D0,
+    ARM_REG_D1,
+    ARM_REG_D2,
+    ARM_REG_D3,
+    ARM_REG_D4,
+    ARM_REG_D5,
+    ARM_REG_D6,
+    ARM_REG_D7,
+    ARM_REG_D8,
+    ARM_REG_D9,
+    ARM_REG_D10,
+    ARM_REG_D11,
+    ARM_REG_D12,
+    ARM_REG_D13,
+    ARM_REG_D14,
+    ARM_REG_D15,
+    ARM_REG_D16,
+    ARM_REG_D17,
+    ARM_REG_D18,
+    ARM_REG_D19,
+    ARM_REG_D20,
+    ARM_REG_D21,
+    ARM_REG_D22,
+    ARM_REG_D23,
+    ARM_REG_D24,
+    ARM_REG_D25,
+    ARM_REG_D26,
+    ARM_REG_D27,
+    ARM_REG_D28,
+    ARM_REG_D29,
+    ARM_REG_D30,
+    ARM_REG_D31,
+    ARM_REG_FPINST2,
+    ARM_REG_MVFR0,
+    ARM_REG_MVFR1,
+    ARM_REG_MVFR2,
+    ARM_REG_Q0,
+    ARM_REG_Q1,
+    ARM_REG_Q2,
+    ARM_REG_Q3,
+    ARM_REG_Q4,
+    ARM_REG_Q5,
+    ARM_REG_Q6,
+    ARM_REG_Q7,
+    ARM_REG_Q8,
+    ARM_REG_Q9,
+    ARM_REG_Q10,
+    ARM_REG_Q11,
+    ARM_REG_Q12,
+    ARM_REG_Q13,
+    ARM_REG_Q14,
+    ARM_REG_Q15,
+    ARM_REG_R0,
+    ARM_REG_R1,
+    ARM_REG_R2,
+    ARM_REG_R3,
+    ARM_REG_R4,
+    ARM_REG_R5,
+    ARM_REG_R6,
+    ARM_REG_R7,
+    ARM_REG_R8,
+    ARM_REG_R9,
+    ARM_REG_R10,
+    ARM_REG_R11,
+    ARM_REG_R12,
+    ARM_REG_S0,
+    ARM_REG_S1,
+    ARM_REG_S2,
+    ARM_REG_S3,
+    ARM_REG_S4,
+    ARM_REG_S5,
+    ARM_REG_S6,
+    ARM_REG_S7,
+    ARM_REG_S8,
+    ARM_REG_S9,
+    ARM_REG_S10,
+    ARM_REG_S11,
+    ARM_REG_S12,
+    ARM_REG_S13,
+    ARM_REG_S14,
+    ARM_REG_S15,
+    ARM_REG_S16,
+    ARM_REG_S17,
+    ARM_REG_S18,
+    ARM_REG_S19,
+    ARM_REG_S20,
+    ARM_REG_S21,
+    ARM_REG_S22,
+    ARM_REG_S23,
+    ARM_REG_S24,
+    ARM_REG_S25,
+    ARM_REG_S26,
+    ARM_REG_S27,
+    ARM_REG_S28,
+    ARM_REG_S29,
+    ARM_REG_S30,
+    ARM_REG_S31,
+
+    ARM_REG_ENDING,     // <-- mark the end of the list or registers
+
+    //> alias registers
+    ARM_REG_R13 = ARM_REG_SP,
+    ARM_REG_R14 = ARM_REG_LR,
+    ARM_REG_R15 = ARM_REG_PC,
+
+    ARM_REG_SB = ARM_REG_R9,
+    ARM_REG_SL = ARM_REG_R10,
+    ARM_REG_FP = ARM_REG_R11,
+    ARM_REG_IP = ARM_REG_R12,
+} arm_reg;
+
+//> ARM instruction
+typedef enum arm_insn
+{
+    ARM_INS_INVALID = 0,
+
+    ARM_INS_ADC,
+    ARM_INS_ADD,
+    ARM_INS_ADR,
+    ARM_INS_AESD,
+    ARM_INS_AESE,
+    ARM_INS_AESIMC,
+    ARM_INS_AESMC,
+    ARM_INS_AND,
+    ARM_INS_BFC,
+    ARM_INS_BFI,
+    ARM_INS_BIC,
+    ARM_INS_BKPT,
+    ARM_INS_BL,
+    ARM_INS_BLX,
+    ARM_INS_BX,
+    ARM_INS_BXJ,
+    ARM_INS_B,
+    ARM_INS_CDP,
+    ARM_INS_CDP2,
+    ARM_INS_CLREX,
+    ARM_INS_CLZ,
+    ARM_INS_CMN,
+    ARM_INS_CMP,
+    ARM_INS_CPS,
+    ARM_INS_CRC32B,
+    ARM_INS_CRC32CB,
+    ARM_INS_CRC32CH,
+    ARM_INS_CRC32CW,
+    ARM_INS_CRC32H,
+    ARM_INS_CRC32W,
+    ARM_INS_DBG,
+    ARM_INS_DMB,
+    ARM_INS_DSB,
+    ARM_INS_EOR,
+    ARM_INS_VMOV,
+    ARM_INS_FLDMDBX,
+    ARM_INS_FLDMIAX,
+    ARM_INS_VMRS,
+    ARM_INS_FSTMDBX,
+    ARM_INS_FSTMIAX,
+    ARM_INS_HINT,
+    ARM_INS_HLT,
+    ARM_INS_ISB,
+    ARM_INS_LDA,
+    ARM_INS_LDAB,
+    ARM_INS_LDAEX,
+    ARM_INS_LDAEXB,
+    ARM_INS_LDAEXD,
+    ARM_INS_LDAEXH,
+    ARM_INS_LDAH,
+    ARM_INS_LDC2L,
+    ARM_INS_LDC2,
+    ARM_INS_LDCL,
+    ARM_INS_LDC,
+    ARM_INS_LDMDA,
+    ARM_INS_LDMDB,
+    ARM_INS_LDM,
+    ARM_INS_LDMIB,
+    ARM_INS_LDRBT,
+    ARM_INS_LDRB,
+    ARM_INS_LDRD,
+    ARM_INS_LDREX,
+    ARM_INS_LDREXB,
+    ARM_INS_LDREXD,
+    ARM_INS_LDREXH,
+    ARM_INS_LDRH,
+    ARM_INS_LDRHT,
+    ARM_INS_LDRSB,
+    ARM_INS_LDRSBT,
+    ARM_INS_LDRSH,
+    ARM_INS_LDRSHT,
+    ARM_INS_LDRT,
+    ARM_INS_LDR,
+    ARM_INS_MCR,
+    ARM_INS_MCR2,
+    ARM_INS_MCRR,
+    ARM_INS_MCRR2,
+    ARM_INS_MLA,
+    ARM_INS_MLS,
+    ARM_INS_MOV,
+    ARM_INS_MOVT,
+    ARM_INS_MOVW,
+    ARM_INS_MRC,
+    ARM_INS_MRC2,
+    ARM_INS_MRRC,
+    ARM_INS_MRRC2,
+    ARM_INS_MRS,
+    ARM_INS_MSR,
+    ARM_INS_MUL,
+    ARM_INS_MVN,
+    ARM_INS_ORR,
+    ARM_INS_PKHBT,
+    ARM_INS_PKHTB,
+    ARM_INS_PLDW,
+    ARM_INS_PLD,
+    ARM_INS_PLI,
+    ARM_INS_QADD,
+    ARM_INS_QADD16,
+    ARM_INS_QADD8,
+    ARM_INS_QASX,
+    ARM_INS_QDADD,
+    ARM_INS_QDSUB,
+    ARM_INS_QSAX,
+    ARM_INS_QSUB,
+    ARM_INS_QSUB16,
+    ARM_INS_QSUB8,
+    ARM_INS_RBIT,
+    ARM_INS_REV,
+    ARM_INS_REV16,
+    ARM_INS_REVSH,
+    ARM_INS_RFEDA,
+    ARM_INS_RFEDB,
+    ARM_INS_RFEIA,
+    ARM_INS_RFEIB,
+    ARM_INS_RSB,
+    ARM_INS_RSC,
+    ARM_INS_SADD16,
+    ARM_INS_SADD8,
+    ARM_INS_SASX,
+    ARM_INS_SBC,
+    ARM_INS_SBFX,
+    ARM_INS_SDIV,
+    ARM_INS_SEL,
+    ARM_INS_SETEND,
+    ARM_INS_SHA1C,
+    ARM_INS_SHA1H,
+    ARM_INS_SHA1M,
+    ARM_INS_SHA1P,
+    ARM_INS_SHA1SU0,
+    ARM_INS_SHA1SU1,
+    ARM_INS_SHA256H,
+    ARM_INS_SHA256H2,
+    ARM_INS_SHA256SU0,
+    ARM_INS_SHA256SU1,
+    ARM_INS_SHADD16,
+    ARM_INS_SHADD8,
+    ARM_INS_SHASX,
+    ARM_INS_SHSAX,
+    ARM_INS_SHSUB16,
+    ARM_INS_SHSUB8,
+    ARM_INS_SMC,
+    ARM_INS_SMLABB,
+    ARM_INS_SMLABT,
+    ARM_INS_SMLAD,
+    ARM_INS_SMLADX,
+    ARM_INS_SMLAL,
+    ARM_INS_SMLALBB,
+    ARM_INS_SMLALBT,
+    ARM_INS_SMLALD,
+    ARM_INS_SMLALDX,
+    ARM_INS_SMLALTB,
+    ARM_INS_SMLALTT,
+    ARM_INS_SMLATB,
+    ARM_INS_SMLATT,
+    ARM_INS_SMLAWB,
+    ARM_INS_SMLAWT,
+    ARM_INS_SMLSD,
+    ARM_INS_SMLSDX,
+    ARM_INS_SMLSLD,
+    ARM_INS_SMLSLDX,
+    ARM_INS_SMMLA,
+    ARM_INS_SMMLAR,
+    ARM_INS_SMMLS,
+    ARM_INS_SMMLSR,
+    ARM_INS_SMMUL,
+    ARM_INS_SMMULR,
+    ARM_INS_SMUAD,
+    ARM_INS_SMUADX,
+    ARM_INS_SMULBB,
+    ARM_INS_SMULBT,
+    ARM_INS_SMULL,
+    ARM_INS_SMULTB,
+    ARM_INS_SMULTT,
+    ARM_INS_SMULWB,
+    ARM_INS_SMULWT,
+    ARM_INS_SMUSD,
+    ARM_INS_SMUSDX,
+    ARM_INS_SRSDA,
+    ARM_INS_SRSDB,
+    ARM_INS_SRSIA,
+    ARM_INS_SRSIB,
+    ARM_INS_SSAT,
+    ARM_INS_SSAT16,
+    ARM_INS_SSAX,
+    ARM_INS_SSUB16,
+    ARM_INS_SSUB8,
+    ARM_INS_STC2L,
+    ARM_INS_STC2,
+    ARM_INS_STCL,
+    ARM_INS_STC,
+    ARM_INS_STL,
+    ARM_INS_STLB,
+    ARM_INS_STLEX,
+    ARM_INS_STLEXB,
+    ARM_INS_STLEXD,
+    ARM_INS_STLEXH,
+    ARM_INS_STLH,
+    ARM_INS_STMDA,
+    ARM_INS_STMDB,
+    ARM_INS_STM,
+    ARM_INS_STMIB,
+    ARM_INS_STRBT,
+    ARM_INS_STRB,
+    ARM_INS_STRD,
+    ARM_INS_STREX,
+    ARM_INS_STREXB,
+    ARM_INS_STREXD,
+    ARM_INS_STREXH,
+    ARM_INS_STRH,
+    ARM_INS_STRHT,
+    ARM_INS_STRT,
+    ARM_INS_STR,
+    ARM_INS_SUB,
+    ARM_INS_SVC,
+    ARM_INS_SWP,
+    ARM_INS_SWPB,
+    ARM_INS_SXTAB,
+    ARM_INS_SXTAB16,
+    ARM_INS_SXTAH,
+    ARM_INS_SXTB,
+    ARM_INS_SXTB16,
+    ARM_INS_SXTH,
+    ARM_INS_TEQ,
+    ARM_INS_TRAP,
+    ARM_INS_TST,
+    ARM_INS_UADD16,
+    ARM_INS_UADD8,
+    ARM_INS_UASX,
+    ARM_INS_UBFX,
+    ARM_INS_UDF,
+    ARM_INS_UDIV,
+    ARM_INS_UHADD16,
+    ARM_INS_UHADD8,
+    ARM_INS_UHASX,
+    ARM_INS_UHSAX,
+    ARM_INS_UHSUB16,
+    ARM_INS_UHSUB8,
+    ARM_INS_UMAAL,
+    ARM_INS_UMLAL,
+    ARM_INS_UMULL,
+    ARM_INS_UQADD16,
+    ARM_INS_UQADD8,
+    ARM_INS_UQASX,
+    ARM_INS_UQSAX,
+    ARM_INS_UQSUB16,
+    ARM_INS_UQSUB8,
+    ARM_INS_USAD8,
+    ARM_INS_USADA8,
+    ARM_INS_USAT,
+    ARM_INS_USAT16,
+    ARM_INS_USAX,
+    ARM_INS_USUB16,
+    ARM_INS_USUB8,
+    ARM_INS_UXTAB,
+    ARM_INS_UXTAB16,
+    ARM_INS_UXTAH,
+    ARM_INS_UXTB,
+    ARM_INS_UXTB16,
+    ARM_INS_UXTH,
+    ARM_INS_VABAL,
+    ARM_INS_VABA,
+    ARM_INS_VABDL,
+    ARM_INS_VABD,
+    ARM_INS_VABS,
+    ARM_INS_VACGE,
+    ARM_INS_VACGT,
+    ARM_INS_VADD,
+    ARM_INS_VADDHN,
+    ARM_INS_VADDL,
+    ARM_INS_VADDW,
+    ARM_INS_VAND,
+    ARM_INS_VBIC,
+    ARM_INS_VBIF,
+    ARM_INS_VBIT,
+    ARM_INS_VBSL,
+    ARM_INS_VCEQ,
+    ARM_INS_VCGE,
+    ARM_INS_VCGT,
+    ARM_INS_VCLE,
+    ARM_INS_VCLS,
+    ARM_INS_VCLT,
+    ARM_INS_VCLZ,
+    ARM_INS_VCMP,
+    ARM_INS_VCMPE,
+    ARM_INS_VCNT,
+    ARM_INS_VCVTA,
+    ARM_INS_VCVTB,
+    ARM_INS_VCVT,
+    ARM_INS_VCVTM,
+    ARM_INS_VCVTN,
+    ARM_INS_VCVTP,
+    ARM_INS_VCVTT,
+    ARM_INS_VDIV,
+    ARM_INS_VDUP,
+    ARM_INS_VEOR,
+    ARM_INS_VEXT,
+    ARM_INS_VFMA,
+    ARM_INS_VFMS,
+    ARM_INS_VFNMA,
+    ARM_INS_VFNMS,
+    ARM_INS_VHADD,
+    ARM_INS_VHSUB,
+    ARM_INS_VLD1,
+    ARM_INS_VLD2,
+    ARM_INS_VLD3,
+    ARM_INS_VLD4,
+    ARM_INS_VLDMDB,
+    ARM_INS_VLDMIA,
+    ARM_INS_VLDR,
+    ARM_INS_VMAXNM,
+    ARM_INS_VMAX,
+    ARM_INS_VMINNM,
+    ARM_INS_VMIN,
+    ARM_INS_VMLA,
+    ARM_INS_VMLAL,
+    ARM_INS_VMLS,
+    ARM_INS_VMLSL,
+    ARM_INS_VMOVL,
+    ARM_INS_VMOVN,
+    ARM_INS_VMSR,
+    ARM_INS_VMUL,
+    ARM_INS_VMULL,
+    ARM_INS_VMVN,
+    ARM_INS_VNEG,
+    ARM_INS_VNMLA,
+    ARM_INS_VNMLS,
+    ARM_INS_VNMUL,
+    ARM_INS_VORN,
+    ARM_INS_VORR,
+    ARM_INS_VPADAL,
+    ARM_INS_VPADDL,
+    ARM_INS_VPADD,
+    ARM_INS_VPMAX,
+    ARM_INS_VPMIN,
+    ARM_INS_VQABS,
+    ARM_INS_VQADD,
+    ARM_INS_VQDMLAL,
+    ARM_INS_VQDMLSL,
+    ARM_INS_VQDMULH,
+    ARM_INS_VQDMULL,
+    ARM_INS_VQMOVUN,
+    ARM_INS_VQMOVN,
+    ARM_INS_VQNEG,
+    ARM_INS_VQRDMULH,
+    ARM_INS_VQRSHL,
+    ARM_INS_VQRSHRN,
+    ARM_INS_VQRSHRUN,
+    ARM_INS_VQSHL,
+    ARM_INS_VQSHLU,
+    ARM_INS_VQSHRN,
+    ARM_INS_VQSHRUN,
+    ARM_INS_VQSUB,
+    ARM_INS_VRADDHN,
+    ARM_INS_VRECPE,
+    ARM_INS_VRECPS,
+    ARM_INS_VREV16,
+    ARM_INS_VREV32,
+    ARM_INS_VREV64,
+    ARM_INS_VRHADD,
+    ARM_INS_VRINTA,
+    ARM_INS_VRINTM,
+    ARM_INS_VRINTN,
+    ARM_INS_VRINTP,
+    ARM_INS_VRINTR,
+    ARM_INS_VRINTX,
+    ARM_INS_VRINTZ,
+    ARM_INS_VRSHL,
+    ARM_INS_VRSHRN,
+    ARM_INS_VRSHR,
+    ARM_INS_VRSQRTE,
+    ARM_INS_VRSQRTS,
+    ARM_INS_VRSRA,
+    ARM_INS_VRSUBHN,
+    ARM_INS_VSELEQ,
+    ARM_INS_VSELGE,
+    ARM_INS_VSELGT,
+    ARM_INS_VSELVS,
+    ARM_INS_VSHLL,
+    ARM_INS_VSHL,
+    ARM_INS_VSHRN,
+    ARM_INS_VSHR,
+    ARM_INS_VSLI,
+    ARM_INS_VSQRT,
+    ARM_INS_VSRA,
+    ARM_INS_VSRI,
+    ARM_INS_VST1,
+    ARM_INS_VST2,
+    ARM_INS_VST3,
+    ARM_INS_VST4,
+    ARM_INS_VSTMDB,
+    ARM_INS_VSTMIA,
+    ARM_INS_VSTR,
+    ARM_INS_VSUB,
+    ARM_INS_VSUBHN,
+    ARM_INS_VSUBL,
+    ARM_INS_VSUBW,
+    ARM_INS_VSWP,
+    ARM_INS_VTBL,
+    ARM_INS_VTBX,
+    ARM_INS_VCVTR,
+    ARM_INS_VTRN,
+    ARM_INS_VTST,
+    ARM_INS_VUZP,
+    ARM_INS_VZIP,
+    ARM_INS_ADDW,
+    ARM_INS_ASR,
+    ARM_INS_DCPS1,
+    ARM_INS_DCPS2,
+    ARM_INS_DCPS3,
+    ARM_INS_IT,
+    ARM_INS_LSL,
+    ARM_INS_LSR,
+    ARM_INS_ASRS,
+    ARM_INS_LSRS,
+    ARM_INS_ORN,
+    ARM_INS_ROR,
+    ARM_INS_RRX,
+    ARM_INS_SUBS,
+    ARM_INS_SUBW,
+    ARM_INS_TBB,
+    ARM_INS_TBH,
+    ARM_INS_CBNZ,
+    ARM_INS_CBZ,
+    ARM_INS_MOVS,
+    ARM_INS_POP,
+    ARM_INS_PUSH,
+
+    // special instructions
+    ARM_INS_NOP,
+    ARM_INS_YIELD,
+    ARM_INS_WFE,
+    ARM_INS_WFI,
+    ARM_INS_SEV,
+    ARM_INS_SEVL,
+    ARM_INS_VPUSH,
+    ARM_INS_VPOP,
+
+    ARM_INS_ENDING, // <-- mark the end of the list of instructions
+} arm_insn;
+
+//> Group of ARM instructions
+typedef enum arm_insn_group
+{
+    ARM_GRP_INVALID = 0, // = CS_GRP_INVALID
+
+    //> Generic groups
+    // all jump instructions (conditional+direct+indirect jumps)
+    ARM_GRP_JUMP,   // = CS_GRP_JUMP
+
+    //> Architecture-specific groups
+    ARM_GRP_CRYPTO = 128,
+    ARM_GRP_DATABARRIER,
+    ARM_GRP_DIVIDE,
+    ARM_GRP_FPARMV8,
+    ARM_GRP_MULTPRO,
+    ARM_GRP_NEON,
+    ARM_GRP_T2EXTRACTPACK,
+    ARM_GRP_THUMB2DSP,
+    ARM_GRP_TRUSTZONE,
+    ARM_GRP_V4T,
+    ARM_GRP_V5T,
+    ARM_GRP_V5TE,
+    ARM_GRP_V6,
+    ARM_GRP_V6T2,
+    ARM_GRP_V7,
+    ARM_GRP_V8,
+    ARM_GRP_VFP2,
+    ARM_GRP_VFP3,
+    ARM_GRP_VFP4,
+    ARM_GRP_ARM,
+    ARM_GRP_MCLASS,
+    ARM_GRP_NOTMCLASS,
+    ARM_GRP_THUMB,
+    ARM_GRP_THUMB1ONLY,
+    ARM_GRP_THUMB2,
+    ARM_GRP_PREV8,
+    ARM_GRP_FPVMLX,
+    ARM_GRP_MULOPS,
+    ARM_GRP_CRC,
+    ARM_GRP_DPVFP,
+    ARM_GRP_V6M,
+
+    ARM_GRP_ENDING,
+} arm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/capstone/capstone.h

@@ -0,0 +1,670 @@
+#ifndef CAPSTONE_ENGINE_H
+#define CAPSTONE_ENGINE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdlib.h>
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#pragma warning(disable:4100)
+#ifdef CAPSTONE_SHARED
+#define CAPSTONE_EXPORT __declspec(dllexport)
+#else    // defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT
+#endif
+#else
+#ifdef __GNUC__
+#define CAPSTONE_EXPORT __attribute__((visibility("default")))
+#else
+#define CAPSTONE_EXPORT
+#endif
+#endif
+
+#ifdef __GNUC__
+#define CAPSTONE_DEPRECATED __attribute__((deprecated))
+#elif defined(_MSC_VER)
+#define CAPSTONE_DEPRECATED __declspec(deprecated)
+#else
+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
+#define CAPSTONE_DEPRECATED
+#endif
+
+// Capstone API version
+#define CS_API_MAJOR 3
+#define CS_API_MINOR 0
+
+// Macro to create combined version which can be compared to
+// result of cs_version() API.
+#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
+
+// Handle using with all API
+typedef size_t csh;
+
+// Architecture type
+typedef enum cs_arch
+{
+    CS_ARCH_ARM = 0,    // ARM architecture (including Thumb, Thumb-2)
+    CS_ARCH_ARM64,      // ARM-64, also called AArch64
+    CS_ARCH_MIPS,       // Mips architecture
+    CS_ARCH_X86,        // X86 architecture (including x86 & x86-64)
+    CS_ARCH_PPC,        // PowerPC architecture
+    CS_ARCH_SPARC,      // Sparc architecture
+    CS_ARCH_SYSZ,       // SystemZ architecture
+    CS_ARCH_XCORE,      // XCore architecture
+    CS_ARCH_MAX,
+    CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
+} cs_arch;
+
+// Support value to verify diet mode of the engine.
+// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
+// in diet mode.
+#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
+
+// Support value to verify X86 reduce mode of the engine.
+// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
+// in X86 reduce mode.
+#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
+
+// Mode type
+typedef enum cs_mode
+{
+    CS_MODE_LITTLE_ENDIAN = 0,  // little-endian mode (default mode)
+    CS_MODE_ARM = 0,    // 32-bit ARM
+    CS_MODE_16 = 1 << 1,    // 16-bit mode (X86)
+    CS_MODE_32 = 1 << 2,    // 32-bit mode (X86)
+    CS_MODE_64 = 1 << 3,    // 64-bit mode (X86, PPC)
+    CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
+    CS_MODE_MCLASS = 1 << 5,    // ARM's Cortex-M series
+    CS_MODE_V8 = 1 << 6,    // ARMv8 A32 encodings for ARM
+    CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS)
+    CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
+    CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
+    CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS)
+    CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc)
+    CS_MODE_BIG_ENDIAN = 1 << 31,   // big-endian mode
+    CS_MODE_MIPS32 = CS_MODE_32,    // Mips32 ISA (Mips)
+    CS_MODE_MIPS64 = CS_MODE_64,    // Mips64 ISA (Mips)
+} cs_mode;
+
+typedef void* (*cs_malloc_t)(size_t size);
+typedef void* (*cs_calloc_t)(size_t nmemb, size_t size);
+typedef void* (*cs_realloc_t)(void* ptr, size_t size);
+typedef void (*cs_free_t)(void* ptr);
+typedef int (*cs_vsnprintf_t)(char* str, size_t size, const char* format, va_list ap);
+
+
+// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
+// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
+typedef struct cs_opt_mem
+{
+    cs_malloc_t malloc;
+    cs_calloc_t calloc;
+    cs_realloc_t realloc;
+    cs_free_t free;
+    cs_vsnprintf_t vsnprintf;
+} cs_opt_mem;
+
+// Runtime option for the disassembled engine
+typedef enum cs_opt_type
+{
+    CS_OPT_SYNTAX = 1,  // Asssembly output syntax
+    CS_OPT_DETAIL,  // Break down instruction structure into details
+    CS_OPT_MODE,    // Change engine's mode at run-time
+    CS_OPT_MEM, // User-defined dynamic memory related functions
+    CS_OPT_SKIPDATA, // Skip data when disassembling. Then engine is in SKIPDATA mode.
+    CS_OPT_SKIPDATA_SETUP, // Setup user-defined function for SKIPDATA option
+} cs_opt_type;
+
+// Runtime option value (associated with option type above)
+typedef enum cs_opt_value
+{
+    CS_OPT_OFF = 0,  // Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA.
+    CS_OPT_ON = 3, // Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+    CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX).
+    CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+    CS_OPT_SYNTAX_ATT,   // X86 ATT asm syntax (CS_OPT_SYNTAX).
+    CS_OPT_SYNTAX_NOREGNAME, // Prints register name with only number (CS_OPT_SYNTAX)
+} cs_opt_value;
+
+//> Common instruction operand types - to be consistent across all architectures.
+typedef enum cs_op_type
+{
+    CS_OP_INVALID = 0,  // uninitialized/invalid operand.
+    CS_OP_REG,          // Register operand.
+    CS_OP_IMM,          // Immediate operand.
+    CS_OP_MEM,          // Memory operand.
+    CS_OP_FP,           // Floating-Point operand.
+} cs_op_type;
+
+//> Common instruction groups - to be consistent across all architectures.
+typedef enum cs_group_type
+{
+    CS_GRP_INVALID = 0,  // uninitialized/invalid group.
+    CS_GRP_JUMP,    // all jump instructions (conditional+direct+indirect jumps)
+    CS_GRP_CALL,    // all call instructions
+    CS_GRP_RET,     // all return instructions
+    CS_GRP_INT,     // all interrupt instructions (int+syscall)
+    CS_GRP_IRET,    // all interrupt return instructions
+} cs_group_type;
+
+/*
+ User-defined callback function for SKIPDATA option.
+ See tests/test_skipdata.c for sample code demonstrating this API.
+
+ @code: the input buffer containing code to be disassembled.
+        This is the same buffer passed to cs_disasm().
+ @code_size: size (in bytes) of the above @code buffer.
+ @offset: the position of the currently-examining byte in the input
+      buffer @code mentioned above.
+ @user_data: user-data passed to cs_option() via @user_data field in
+      cs_opt_skipdata struct below.
+
+ @return: return number of bytes to skip, or 0 to immediately stop disassembling.
+*/
+typedef size_t (*cs_skipdata_cb_t)(const uint8_t* code, size_t code_size, size_t offset, void* user_data);
+
+// User-customized setup for SKIPDATA option
+typedef struct cs_opt_skipdata
+{
+    // Capstone considers data to skip as special "instructions".
+    // User can specify the string for this instruction's "mnemonic" here.
+    // By default (if @mnemonic is NULL), Capstone use ".byte".
+    const char* mnemonic;
+
+    // User-defined callback function to be called when Capstone hits data.
+    // If the returned value from this callback is positive (>0), Capstone
+    // will skip exactly that number of bytes & continue. Otherwise, if
+    // the callback returns 0, Capstone stops disassembling and returns
+    // immediately from cs_disasm()
+    // NOTE: if this callback pointer is NULL, Capstone would skip a number
+    // of bytes depending on architectures, as following:
+    // Arm:     2 bytes (Thumb mode) or 4 bytes.
+    // Arm64:   4 bytes.
+    // Mips:    4 bytes.
+    // PowerPC: 4 bytes.
+    // Sparc:   4 bytes.
+    // SystemZ: 2 bytes.
+    // X86:     1 bytes.
+    // XCore:   2 bytes.
+    cs_skipdata_cb_t callback;  // default value is NULL
+
+    // User-defined data to be passed to @callback function pointer.
+    void* user_data;
+} cs_opt_skipdata;
+
+
+#include "arm.h"
+#include "arm64.h"
+#include "mips.h"
+#include "ppc.h"
+#include "sparc.h"
+#include "systemz.h"
+#include "x86.h"
+#include "xcore.h"
+
+// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
+typedef struct cs_detail
+{
+    uint8_t regs_read[12]; // list of implicit registers read by this insn
+    uint8_t regs_read_count; // number of implicit registers read by this insn
+
+    uint8_t regs_write[20]; // list of implicit registers modified by this insn
+    uint8_t regs_write_count; // number of implicit registers modified by this insn
+
+    uint8_t groups[8]; // list of group this instruction belong to
+    uint8_t groups_count; // number of groups this insn belongs to
+
+    // Architecture-specific instruction info
+    union
+    {
+        cs_x86 x86; // X86 architecture, including 16-bit, 32-bit & 64-bit mode
+        cs_arm64 arm64; // ARM64 architecture (aka AArch64)
+        cs_arm arm;     // ARM architecture (including Thumb/Thumb2)
+        cs_mips mips;   // MIPS architecture
+        cs_ppc ppc; // PowerPC architecture
+        cs_sparc sparc; // Sparc architecture
+        cs_sysz sysz;   // SystemZ architecture
+        cs_xcore xcore; // XCore architecture
+    };
+} cs_detail;
+
+// Detail information of disassembled instruction
+typedef struct cs_insn
+{
+    // Instruction ID
+    // Find the instruction id from header file of corresponding architecture,
+    // such as arm.h for ARM, x86.h for X86, etc...
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    // NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
+    unsigned int id;
+
+    // Address (EIP) of this instruction
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    uint64_t address;
+
+    // Size of this instruction
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    uint16_t size;
+    // Machine bytes of this instruction, with number of bytes indicated by @size above
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    uint8_t bytes[16];
+
+    // Ascii text of instruction mnemonic
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    char mnemonic[32];
+
+    // Ascii text of instruction operands
+    // This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+    char op_str[160];
+
+    // Pointer to cs_detail.
+    // NOTE: detail pointer is only valid when both requirements below are met:
+    // (1) CS_OP_DETAIL = CS_OPT_ON
+    // (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
+    //
+    // NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
+    //     is not NULL, its content is still irrelevant.
+    cs_detail* detail;
+} cs_insn;
+
+
+// Calculate the offset of a disassembled instruction in its buffer, given its position
+// in its array of disassembled insn
+// NOTE: this macro works with position (>=1), not index
+#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
+
+
+// All type of errors encountered by Capstone API.
+// These are values returned by cs_errno()
+typedef enum cs_err
+{
+    CS_ERR_OK = 0,   // No error: everything was fine
+    CS_ERR_MEM,      // Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
+    CS_ERR_ARCH,     // Unsupported architecture: cs_open()
+    CS_ERR_HANDLE,   // Invalid handle: cs_op_count(), cs_op_index()
+    CS_ERR_CSH,      // Invalid csh argument: cs_close(), cs_errno(), cs_option()
+    CS_ERR_MODE,     // Invalid/unsupported mode: cs_open()
+    CS_ERR_OPTION,   // Invalid/unsupported option: cs_option()
+    CS_ERR_DETAIL,   // Information is unavailable because detail option is OFF
+    CS_ERR_MEMSETUP, // Dynamic memory management uninitialized (see CS_OPT_MEM)
+    CS_ERR_VERSION,  // Unsupported version (bindings)
+    CS_ERR_DIET,     // Access irrelevant data in "diet" engine
+    CS_ERR_SKIPDATA, // Access irrelevant data for "data" instruction in SKIPDATA mode
+    CS_ERR_X86_ATT,  // X86 AT&T syntax is unsupported (opt-out at compile time)
+    CS_ERR_X86_INTEL, // X86 Intel syntax is unsupported (opt-out at compile time)
+} cs_err;
+
+/*
+ Return combined API version & major and minor version numbers.
+
+ @major: major number of API version
+ @minor: minor number of API version
+
+ @return hexical number as (major << 8 | minor), which encodes both
+     major & minor versions.
+     NOTE: This returned value can be compared with version number made
+     with macro CS_MAKE_VERSION
+
+ For example, second API version would return 1 in @major, and 1 in @minor
+ The return value would be 0x0101
+
+ NOTE: if you only care about returned value, but not major and minor values,
+ set both @major & @minor arguments to NULL.
+*/
+CAPSTONE_EXPORT
+unsigned int cs_version(int* major, int* minor);
+
+
+/*
+ This API can be used to either ask for archs supported by this library,
+ or check to see if the library was compile with 'diet' option (or called
+ in 'diet' mode).
+
+ To check if a particular arch is supported by this library, set @query to
+ arch mode (CS_ARCH_* value).
+ To verify if this library supports all the archs, use CS_ARCH_ALL.
+
+ To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
+
+ @return True if this library supports the given arch, or in 'diet' mode.
+*/
+CAPSTONE_EXPORT
+bool cs_support(int query);
+
+/*
+ Initialize CS handle: this must be done before any usage of CS.
+
+ @arch: architecture type (CS_ARCH_*)
+ @mode: hardware mode. This is combined of CS_MODE_*
+ @handle: pointer to handle, which will be updated at return time
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err cs_open(cs_arch arch, cs_mode mode, csh* handle);
+
+/*
+ Close CS handle: MUST do to release the handle when it is not used anymore.
+ NOTE: this must be only called when there is no longer usage of Capstone,
+ not even access to cs_insn array. The reason is the this API releases some
+ cached memory, thus access to any Capstone API after cs_close() might crash
+ your application.
+
+ In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
+
+ @handle: pointer to a handle returned by cs_open()
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err cs_close(csh* handle);
+
+/*
+ Set option for disassembling engine at runtime
+
+ @handle: handle returned by cs_open()
+ @type: type of option to be set
+ @value: option value corresponding with @type
+
+ @return: CS_ERR_OK on success, or other value on failure.
+ Refer to cs_err enum for detailed error.
+
+ NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
+ so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
+ even before cs_open()
+*/
+CAPSTONE_EXPORT
+cs_err cs_option(csh handle, cs_opt_type type, size_t value);
+
+/*
+ Report the last error number when some API function fail.
+ Like glibc's errno, cs_errno might not retain its old value once accessed.
+
+ @handle: handle returned by cs_open()
+
+ @return: error code of cs_err enum type (CS_ERR_*, see above)
+*/
+CAPSTONE_EXPORT
+cs_err cs_errno(csh handle);
+
+
+/*
+ Return a string describing given error code.
+
+ @code: error code (see CS_ERR_* above)
+
+ @return: returns a pointer to a string that describes the error code
+    passed in the argument @code
+*/
+CAPSTONE_EXPORT
+const char* cs_strerror(cs_err code);
+
+/*
+ Disassemble binary code, given the code buffer, size, address and number
+ of instructions to be decoded.
+ This API dynamicly allocate memory to contain disassembled instruction.
+ Resulted instructions will be put into @*insn
+
+ NOTE 1: this API will automatically determine memory needed to contain
+ output disassembled instructions in @insn.
+
+ NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
+ cs_disasm(). The reason is that with cs_disasm(), based on limited available
+ memory, we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case @count=0,
+ when cs_disasm() runs uncontrolly (until either end of input buffer, or
+ when it encounters an invalid instruction).
+
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled.
+ @code_size: size of the above code buffer.
+ @address: address of the first instruction in given raw code buffer.
+ @insn: array of instructions filled in by this API.
+       NOTE: @insn will be allocated by this function, and should be freed
+       with cs_free() API.
+ @count: number of instrutions to be disassembled, or 0 to get all of them
+
+ @return: the number of succesfully disassembled instructions,
+ or 0 if this function failed to disassemble the given code
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+size_t cs_disasm(csh handle,
+                 const uint8_t* code, size_t code_size,
+                 uint64_t address,
+                 size_t count,
+                 cs_insn** insn);
+
+/*
+  Deprecated function - to be retired in the next version!
+  Use cs_disasm() instead of cs_disasm_ex()
+*/
+CAPSTONE_EXPORT
+CAPSTONE_DEPRECATED
+size_t cs_disasm_ex(csh handle,
+                    const uint8_t* code, size_t code_size,
+                    uint64_t address,
+                    size_t count,
+                    cs_insn** insn);
+
+/*
+ Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
+
+ @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
+ @count: number of cs_insn structures returned by cs_disasm(), or 1
+     to free memory allocated by cs_malloc().
+*/
+CAPSTONE_EXPORT
+void cs_free(cs_insn* insn, size_t count);
+
+
+/*
+ Allocate memory for 1 instruction to be used by cs_disasm_iter().
+
+ @handle: handle returned by cs_open()
+
+ NOTE: when no longer in use, you can reclaim the memory allocated for
+ this instruction with cs_free(insn, 1)
+*/
+CAPSTONE_EXPORT
+cs_insn* cs_malloc(csh handle);
+
+/*
+ Fast API to disassemble binary code, given the code buffer, size, address
+ and number of instructions to be decoded.
+ This API put the resulted instruction into a given cache in @insn.
+ See tests/test_iter.c for sample code demonstrating this API.
+
+ NOTE 1: this API will update @code, @size & @address to point to the next
+ instruction in the input buffer. Therefore, it is covenient to use
+ cs_disasm_iter() inside a loop to quickly iterate all the instructions.
+ While decoding one instruction at a time can also be achieved with
+ cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
+ faster on random input.
+
+ NOTE 2: the cache in @insn can be created with cs_malloc() API.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, this API is recommended over cs_disasm(), which
+ allocates memory based on the number of instructions to be disassembled.
+ The reason is that with cs_disasm(), based on limited available memory,
+ we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case
+ @count=0, when cs_disasm() runs uncontrolly (until either end of input
+ buffer, or when it encounters an invalid instruction).
+
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled
+ @code_size: size of above code
+ @address: address of the first insn in given raw code buffer
+ @insn: pointer to instruction to be filled in by this API.
+
+ @return: true if this API successfully decode 1 instruction,
+ or false otherwise.
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+bool cs_disasm_iter(csh handle,
+                    const uint8_t** code, size_t* size,
+                    uint64_t* address, cs_insn* insn);
+
+/*
+ Return friendly name of regiser in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM,
+ x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because engine does not
+ store register name.
+
+ @handle: handle returned by cs_open()
+ @reg_id: register id
+
+ @return: string name of the register, or NULL if @reg_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char* cs_reg_name(csh handle, unsigned int reg_id);
+
+/*
+ Return friendly name of an instruction in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store instruction name.
+
+ @handle: handle returned by cs_open()
+ @insn_id: instruction id
+
+ @return: string name of the instruction, or NULL if @insn_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char* cs_insn_name(csh handle, unsigned int insn_id);
+
+/*
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char* cs_group_name(csh handle, unsigned int group_id);
+
+/*
+ Check if a disassembled instruction belong to a particular group.
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @group_id matches any member of insn->groups array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default).
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @groups array.
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @group_id: group that you want to check if this instruction belong to.
+
+ @return: true if this instruction indeed belongs to aboved group, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool cs_insn_group(csh handle, const cs_insn* insn, unsigned int group_id);
+
+/*
+ Check if a disassembled instruction IMPLICITLY used a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_read array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction used it.
+
+ @return: true if this instruction indeed implicitly used aboved register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool cs_reg_read(csh handle, const cs_insn* insn, unsigned int reg_id);
+
+/*
+ Check if a disassembled instruction IMPLICITLY modified a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_write array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction modified it.
+
+ @return: true if this instruction indeed implicitly modified aboved register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool cs_reg_write(csh handle, const cs_insn* insn, unsigned int reg_id);
+
+/*
+ Count the number of operands of a given type.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+
+ @return: number of operands of given type @op_type in instruction @insn,
+ or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int cs_op_count(csh handle, const cs_insn* insn, unsigned int op_type);
+
+/*
+ Retrieve the position of operand of given type in <arch>.operands[] array.
+ Later, the operand can be accessed using the returned position.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+ @position: position of the operand to be found. This must be in the range
+            [1, cs_op_count(handle, insn, op_type)]
+
+ @return: index of operand of given type @op_type in <arch>.operands[] array
+ in instruction @insn, or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int cs_op_index(csh handle, const cs_insn* insn, unsigned int op_type,
+                unsigned int position);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/capstone/mips.h

@@ -0,0 +1,911 @@
+#ifndef CAPSTONE_MIPS_H
+#define CAPSTONE_MIPS_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+// GCC MIPS toolchain has a default macro called "mips" which breaks
+// compilation
+#undef mips
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Operand type for instruction's operands
+typedef enum mips_op_type
+{
+    MIPS_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+    MIPS_OP_REG, // = CS_OP_REG (Register operand).
+    MIPS_OP_IMM, // = CS_OP_IMM (Immediate operand).
+    MIPS_OP_MEM, // = CS_OP_MEM (Memory operand).
+} mips_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with MIPS_OP_MEM operand type above
+typedef struct mips_op_mem
+{
+    unsigned int base;  // base register
+    int64_t disp;   // displacement/offset value
+} mips_op_mem;
+
+// Instruction operand
+typedef struct cs_mips_op
+{
+    mips_op_type type;  // operand type
+    union
+    {
+        unsigned int reg;   // register value for REG operand
+        int64_t imm;        // immediate value for IMM operand
+        mips_op_mem mem;    // base/index/scale/disp value for MEM operand
+    };
+} cs_mips_op;
+
+// Instruction structure
+typedef struct cs_mips
+{
+    // Number of operands of this instruction,
+    // or 0 when instruction has no operand.
+    uint8_t op_count;
+    cs_mips_op operands[8]; // operands for this instruction.
+} cs_mips;
+
+//> MIPS registers
+typedef enum mips_reg
+{
+    MIPS_REG_INVALID = 0,
+    //> General purpose registers
+    MIPS_REG_0,
+    MIPS_REG_1,
+    MIPS_REG_2,
+    MIPS_REG_3,
+    MIPS_REG_4,
+    MIPS_REG_5,
+    MIPS_REG_6,
+    MIPS_REG_7,
+    MIPS_REG_8,
+    MIPS_REG_9,
+    MIPS_REG_10,
+    MIPS_REG_11,
+    MIPS_REG_12,
+    MIPS_REG_13,
+    MIPS_REG_14,
+    MIPS_REG_15,
+    MIPS_REG_16,
+    MIPS_REG_17,
+    MIPS_REG_18,
+    MIPS_REG_19,
+    MIPS_REG_20,
+    MIPS_REG_21,
+    MIPS_REG_22,
+    MIPS_REG_23,
+    MIPS_REG_24,
+    MIPS_REG_25,
+    MIPS_REG_26,
+    MIPS_REG_27,
+    MIPS_REG_28,
+    MIPS_REG_29,
+    MIPS_REG_30,
+    MIPS_REG_31,
+
+    //> DSP registers
+    MIPS_REG_DSPCCOND,
+    MIPS_REG_DSPCARRY,
+    MIPS_REG_DSPEFI,
+    MIPS_REG_DSPOUTFLAG,
+    MIPS_REG_DSPOUTFLAG16_19,
+    MIPS_REG_DSPOUTFLAG20,
+    MIPS_REG_DSPOUTFLAG21,
+    MIPS_REG_DSPOUTFLAG22,
+    MIPS_REG_DSPOUTFLAG23,
+    MIPS_REG_DSPPOS,
+    MIPS_REG_DSPSCOUNT,
+
+    //> ACC registers
+    MIPS_REG_AC0,
+    MIPS_REG_AC1,
+    MIPS_REG_AC2,
+    MIPS_REG_AC3,
+
+    //> COP registers
+    MIPS_REG_CC0,
+    MIPS_REG_CC1,
+    MIPS_REG_CC2,
+    MIPS_REG_CC3,
+    MIPS_REG_CC4,
+    MIPS_REG_CC5,
+    MIPS_REG_CC6,
+    MIPS_REG_CC7,
+
+    //> FPU registers
+    MIPS_REG_F0,
+    MIPS_REG_F1,
+    MIPS_REG_F2,
+    MIPS_REG_F3,
+    MIPS_REG_F4,
+    MIPS_REG_F5,
+    MIPS_REG_F6,
+    MIPS_REG_F7,
+    MIPS_REG_F8,
+    MIPS_REG_F9,
+    MIPS_REG_F10,
+    MIPS_REG_F11,
+    MIPS_REG_F12,
+    MIPS_REG_F13,
+    MIPS_REG_F14,
+    MIPS_REG_F15,
+    MIPS_REG_F16,
+    MIPS_REG_F17,
+    MIPS_REG_F18,
+    MIPS_REG_F19,
+    MIPS_REG_F20,
+    MIPS_REG_F21,
+    MIPS_REG_F22,
+    MIPS_REG_F23,
+    MIPS_REG_F24,
+    MIPS_REG_F25,
+    MIPS_REG_F26,
+    MIPS_REG_F27,
+    MIPS_REG_F28,
+    MIPS_REG_F29,
+    MIPS_REG_F30,
+    MIPS_REG_F31,
+
+    MIPS_REG_FCC0,
+    MIPS_REG_FCC1,
+    MIPS_REG_FCC2,
+    MIPS_REG_FCC3,
+    MIPS_REG_FCC4,
+    MIPS_REG_FCC5,
+    MIPS_REG_FCC6,
+    MIPS_REG_FCC7,
+
+    //> AFPR128
+    MIPS_REG_W0,
+    MIPS_REG_W1,
+    MIPS_REG_W2,
+    MIPS_REG_W3,
+    MIPS_REG_W4,
+    MIPS_REG_W5,
+    MIPS_REG_W6,
+    MIPS_REG_W7,
+    MIPS_REG_W8,
+    MIPS_REG_W9,
+    MIPS_REG_W10,
+    MIPS_REG_W11,
+    MIPS_REG_W12,
+    MIPS_REG_W13,
+    MIPS_REG_W14,
+    MIPS_REG_W15,
+    MIPS_REG_W16,
+    MIPS_REG_W17,
+    MIPS_REG_W18,
+    MIPS_REG_W19,
+    MIPS_REG_W20,
+    MIPS_REG_W21,
+    MIPS_REG_W22,
+    MIPS_REG_W23,
+    MIPS_REG_W24,
+    MIPS_REG_W25,
+    MIPS_REG_W26,
+    MIPS_REG_W27,
+    MIPS_REG_W28,
+    MIPS_REG_W29,
+    MIPS_REG_W30,
+    MIPS_REG_W31,
+
+    MIPS_REG_HI,
+    MIPS_REG_LO,
+
+    MIPS_REG_P0,
+    MIPS_REG_P1,
+    MIPS_REG_P2,
+
+    MIPS_REG_MPL0,
+    MIPS_REG_MPL1,
+    MIPS_REG_MPL2,
+
+    MIPS_REG_ENDING,    // <-- mark the end of the list or registers
+
+    // alias registers
+    MIPS_REG_ZERO = MIPS_REG_0,
+    MIPS_REG_AT = MIPS_REG_1,
+    MIPS_REG_V0 = MIPS_REG_2,
+    MIPS_REG_V1 = MIPS_REG_3,
+    MIPS_REG_A0 = MIPS_REG_4,
+    MIPS_REG_A1 = MIPS_REG_5,
+    MIPS_REG_A2 = MIPS_REG_6,
+    MIPS_REG_A3 = MIPS_REG_7,
+    MIPS_REG_T0 = MIPS_REG_8,
+    MIPS_REG_T1 = MIPS_REG_9,
+    MIPS_REG_T2 = MIPS_REG_10,
+    MIPS_REG_T3 = MIPS_REG_11,
+    MIPS_REG_T4 = MIPS_REG_12,
+    MIPS_REG_T5 = MIPS_REG_13,
+    MIPS_REG_T6 = MIPS_REG_14,
+    MIPS_REG_T7 = MIPS_REG_15,
+    MIPS_REG_S0 = MIPS_REG_16,
+    MIPS_REG_S1 = MIPS_REG_17,
+    MIPS_REG_S2 = MIPS_REG_18,
+    MIPS_REG_S3 = MIPS_REG_19,
+    MIPS_REG_S4 = MIPS_REG_20,
+    MIPS_REG_S5 = MIPS_REG_21,
+    MIPS_REG_S6 = MIPS_REG_22,
+    MIPS_REG_S7 = MIPS_REG_23,
+    MIPS_REG_T8 = MIPS_REG_24,
+    MIPS_REG_T9 = MIPS_REG_25,
+    MIPS_REG_K0 = MIPS_REG_26,
+    MIPS_REG_K1 = MIPS_REG_27,
+    MIPS_REG_GP = MIPS_REG_28,
+    MIPS_REG_SP = MIPS_REG_29,
+    MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
+    MIPS_REG_RA = MIPS_REG_31,
+
+    MIPS_REG_HI0 = MIPS_REG_AC0,
+    MIPS_REG_HI1 = MIPS_REG_AC1,
+    MIPS_REG_HI2 = MIPS_REG_AC2,
+    MIPS_REG_HI3 = MIPS_REG_AC3,
+
+    MIPS_REG_LO0 = MIPS_REG_HI0,
+    MIPS_REG_LO1 = MIPS_REG_HI1,
+    MIPS_REG_LO2 = MIPS_REG_HI2,
+    MIPS_REG_LO3 = MIPS_REG_HI3,
+} mips_reg;
+
+//> MIPS instruction
+typedef enum mips_insn
+{
+    MIPS_INS_INVALID = 0,
+
+    MIPS_INS_ABSQ_S,
+    MIPS_INS_ADD,
+    MIPS_INS_ADDIUPC,
+    MIPS_INS_ADDQH,
+    MIPS_INS_ADDQH_R,
+    MIPS_INS_ADDQ,
+    MIPS_INS_ADDQ_S,
+    MIPS_INS_ADDSC,
+    MIPS_INS_ADDS_A,
+    MIPS_INS_ADDS_S,
+    MIPS_INS_ADDS_U,
+    MIPS_INS_ADDUH,
+    MIPS_INS_ADDUH_R,
+    MIPS_INS_ADDU,
+    MIPS_INS_ADDU_S,
+    MIPS_INS_ADDVI,
+    MIPS_INS_ADDV,
+    MIPS_INS_ADDWC,
+    MIPS_INS_ADD_A,
+    MIPS_INS_ADDI,
+    MIPS_INS_ADDIU,
+    MIPS_INS_ALIGN,
+    MIPS_INS_ALUIPC,
+    MIPS_INS_AND,
+    MIPS_INS_ANDI,
+    MIPS_INS_APPEND,
+    MIPS_INS_ASUB_S,
+    MIPS_INS_ASUB_U,
+    MIPS_INS_AUI,
+    MIPS_INS_AUIPC,
+    MIPS_INS_AVER_S,
+    MIPS_INS_AVER_U,
+    MIPS_INS_AVE_S,
+    MIPS_INS_AVE_U,
+    MIPS_INS_BADDU,
+    MIPS_INS_BAL,
+    MIPS_INS_BALC,
+    MIPS_INS_BALIGN,
+    MIPS_INS_BC,
+    MIPS_INS_BC0F,
+    MIPS_INS_BC0FL,
+    MIPS_INS_BC0T,
+    MIPS_INS_BC0TL,
+    MIPS_INS_BC1EQZ,
+    MIPS_INS_BC1F,
+    MIPS_INS_BC1FL,
+    MIPS_INS_BC1NEZ,
+    MIPS_INS_BC1T,
+    MIPS_INS_BC1TL,
+    MIPS_INS_BC2EQZ,
+    MIPS_INS_BC2F,
+    MIPS_INS_BC2FL,
+    MIPS_INS_BC2NEZ,
+    MIPS_INS_BC2T,
+    MIPS_INS_BC2TL,
+    MIPS_INS_BC3F,
+    MIPS_INS_BC3FL,
+    MIPS_INS_BC3T,
+    MIPS_INS_BC3TL,
+    MIPS_INS_BCLRI,
+    MIPS_INS_BCLR,
+    MIPS_INS_BEQ,
+    MIPS_INS_BEQC,
+    MIPS_INS_BEQL,
+    MIPS_INS_BEQZALC,
+    MIPS_INS_BEQZC,
+    MIPS_INS_BGEC,
+    MIPS_INS_BGEUC,
+    MIPS_INS_BGEZ,
+    MIPS_INS_BGEZAL,
+    MIPS_INS_BGEZALC,
+    MIPS_INS_BGEZALL,
+    MIPS_INS_BGEZALS,
+    MIPS_INS_BGEZC,
+    MIPS_INS_BGEZL,
+    MIPS_INS_BGTZ,
+    MIPS_INS_BGTZALC,
+    MIPS_INS_BGTZC,
+    MIPS_INS_BGTZL,
+    MIPS_INS_BINSLI,
+    MIPS_INS_BINSL,
+    MIPS_INS_BINSRI,
+    MIPS_INS_BINSR,
+    MIPS_INS_BITREV,
+    MIPS_INS_BITSWAP,
+    MIPS_INS_BLEZ,
+    MIPS_INS_BLEZALC,
+    MIPS_INS_BLEZC,
+    MIPS_INS_BLEZL,
+    MIPS_INS_BLTC,
+    MIPS_INS_BLTUC,
+    MIPS_INS_BLTZ,
+    MIPS_INS_BLTZAL,
+    MIPS_INS_BLTZALC,
+    MIPS_INS_BLTZALL,
+    MIPS_INS_BLTZALS,
+    MIPS_INS_BLTZC,
+    MIPS_INS_BLTZL,
+    MIPS_INS_BMNZI,
+    MIPS_INS_BMNZ,
+    MIPS_INS_BMZI,
+    MIPS_INS_BMZ,
+    MIPS_INS_BNE,
+    MIPS_INS_BNEC,
+    MIPS_INS_BNEGI,
+    MIPS_INS_BNEG,
+    MIPS_INS_BNEL,
+    MIPS_INS_BNEZALC,
+    MIPS_INS_BNEZC,
+    MIPS_INS_BNVC,
+    MIPS_INS_BNZ,
+    MIPS_INS_BOVC,
+    MIPS_INS_BPOSGE32,
+    MIPS_INS_BREAK,
+    MIPS_INS_BSELI,
+    MIPS_INS_BSEL,
+    MIPS_INS_BSETI,
+    MIPS_INS_BSET,
+    MIPS_INS_BZ,
+    MIPS_INS_BEQZ,
+    MIPS_INS_B,
+    MIPS_INS_BNEZ,
+    MIPS_INS_BTEQZ,
+    MIPS_INS_BTNEZ,
+    MIPS_INS_CACHE,
+    MIPS_INS_CEIL,
+    MIPS_INS_CEQI,
+    MIPS_INS_CEQ,
+    MIPS_INS_CFC1,
+    MIPS_INS_CFCMSA,
+    MIPS_INS_CINS,
+    MIPS_INS_CINS32,
+    MIPS_INS_CLASS,
+    MIPS_INS_CLEI_S,
+    MIPS_INS_CLEI_U,
+    MIPS_INS_CLE_S,
+    MIPS_INS_CLE_U,
+    MIPS_INS_CLO,
+    MIPS_INS_CLTI_S,
+    MIPS_INS_CLTI_U,
+    MIPS_INS_CLT_S,
+    MIPS_INS_CLT_U,
+    MIPS_INS_CLZ,
+    MIPS_INS_CMPGDU,
+    MIPS_INS_CMPGU,
+    MIPS_INS_CMPU,
+    MIPS_INS_CMP,
+    MIPS_INS_COPY_S,
+    MIPS_INS_COPY_U,
+    MIPS_INS_CTC1,
+    MIPS_INS_CTCMSA,
+    MIPS_INS_CVT,
+    MIPS_INS_C,
+    MIPS_INS_CMPI,
+    MIPS_INS_DADD,
+    MIPS_INS_DADDI,
+    MIPS_INS_DADDIU,
+    MIPS_INS_DADDU,
+    MIPS_INS_DAHI,
+    MIPS_INS_DALIGN,
+    MIPS_INS_DATI,
+    MIPS_INS_DAUI,
+    MIPS_INS_DBITSWAP,
+    MIPS_INS_DCLO,
+    MIPS_INS_DCLZ,
+    MIPS_INS_DDIV,
+    MIPS_INS_DDIVU,
+    MIPS_INS_DERET,
+    MIPS_INS_DEXT,
+    MIPS_INS_DEXTM,
+    MIPS_INS_DEXTU,
+    MIPS_INS_DI,
+    MIPS_INS_DINS,
+    MIPS_INS_DINSM,
+    MIPS_INS_DINSU,
+    MIPS_INS_DIV,
+    MIPS_INS_DIVU,
+    MIPS_INS_DIV_S,
+    MIPS_INS_DIV_U,
+    MIPS_INS_DLSA,
+    MIPS_INS_DMFC0,
+    MIPS_INS_DMFC1,
+    MIPS_INS_DMFC2,
+    MIPS_INS_DMOD,
+    MIPS_INS_DMODU,
+    MIPS_INS_DMTC0,
+    MIPS_INS_DMTC1,
+    MIPS_INS_DMTC2,
+    MIPS_INS_DMUH,
+    MIPS_INS_DMUHU,
+    MIPS_INS_DMUL,
+    MIPS_INS_DMULT,
+    MIPS_INS_DMULTU,
+    MIPS_INS_DMULU,
+    MIPS_INS_DOTP_S,
+    MIPS_INS_DOTP_U,
+    MIPS_INS_DPADD_S,
+    MIPS_INS_DPADD_U,
+    MIPS_INS_DPAQX_SA,
+    MIPS_INS_DPAQX_S,
+    MIPS_INS_DPAQ_SA,
+    MIPS_INS_DPAQ_S,
+    MIPS_INS_DPAU,
+    MIPS_INS_DPAX,
+    MIPS_INS_DPA,
+    MIPS_INS_DPOP,
+    MIPS_INS_DPSQX_SA,
+    MIPS_INS_DPSQX_S,
+    MIPS_INS_DPSQ_SA,
+    MIPS_INS_DPSQ_S,
+    MIPS_INS_DPSUB_S,
+    MIPS_INS_DPSUB_U,
+    MIPS_INS_DPSU,
+    MIPS_INS_DPSX,
+    MIPS_INS_DPS,
+    MIPS_INS_DROTR,
+    MIPS_INS_DROTR32,
+    MIPS_INS_DROTRV,
+    MIPS_INS_DSBH,
+    MIPS_INS_DSHD,
+    MIPS_INS_DSLL,
+    MIPS_INS_DSLL32,
+    MIPS_INS_DSLLV,
+    MIPS_INS_DSRA,
+    MIPS_INS_DSRA32,
+    MIPS_INS_DSRAV,
+    MIPS_INS_DSRL,
+    MIPS_INS_DSRL32,
+    MIPS_INS_DSRLV,
+    MIPS_INS_DSUB,
+    MIPS_INS_DSUBU,
+    MIPS_INS_EHB,
+    MIPS_INS_EI,
+    MIPS_INS_ERET,
+    MIPS_INS_EXT,
+    MIPS_INS_EXTP,
+    MIPS_INS_EXTPDP,
+    MIPS_INS_EXTPDPV,
+    MIPS_INS_EXTPV,
+    MIPS_INS_EXTRV_RS,
+    MIPS_INS_EXTRV_R,
+    MIPS_INS_EXTRV_S,
+    MIPS_INS_EXTRV,
+    MIPS_INS_EXTR_RS,
+    MIPS_INS_EXTR_R,
+    MIPS_INS_EXTR_S,
+    MIPS_INS_EXTR,
+    MIPS_INS_EXTS,
+    MIPS_INS_EXTS32,
+    MIPS_INS_ABS,
+    MIPS_INS_FADD,
+    MIPS_INS_FCAF,
+    MIPS_INS_FCEQ,
+    MIPS_INS_FCLASS,
+    MIPS_INS_FCLE,
+    MIPS_INS_FCLT,
+    MIPS_INS_FCNE,
+    MIPS_INS_FCOR,
+    MIPS_INS_FCUEQ,
+    MIPS_INS_FCULE,
+    MIPS_INS_FCULT,
+    MIPS_INS_FCUNE,
+    MIPS_INS_FCUN,
+    MIPS_INS_FDIV,
+    MIPS_INS_FEXDO,
+    MIPS_INS_FEXP2,
+    MIPS_INS_FEXUPL,
+    MIPS_INS_FEXUPR,
+    MIPS_INS_FFINT_S,
+    MIPS_INS_FFINT_U,
+    MIPS_INS_FFQL,
+    MIPS_INS_FFQR,
+    MIPS_INS_FILL,
+    MIPS_INS_FLOG2,
+    MIPS_INS_FLOOR,
+    MIPS_INS_FMADD,
+    MIPS_INS_FMAX_A,
+    MIPS_INS_FMAX,
+    MIPS_INS_FMIN_A,
+    MIPS_INS_FMIN,
+    MIPS_INS_MOV,
+    MIPS_INS_FMSUB,
+    MIPS_INS_FMUL,
+    MIPS_INS_MUL,
+    MIPS_INS_NEG,
+    MIPS_INS_FRCP,
+    MIPS_INS_FRINT,
+    MIPS_INS_FRSQRT,
+    MIPS_INS_FSAF,
+    MIPS_INS_FSEQ,
+    MIPS_INS_FSLE,
+    MIPS_INS_FSLT,
+    MIPS_INS_FSNE,
+    MIPS_INS_FSOR,
+    MIPS_INS_FSQRT,
+    MIPS_INS_SQRT,
+    MIPS_INS_FSUB,
+    MIPS_INS_SUB,
+    MIPS_INS_FSUEQ,
+    MIPS_INS_FSULE,
+    MIPS_INS_FSULT,
+    MIPS_INS_FSUNE,
+    MIPS_INS_FSUN,
+    MIPS_INS_FTINT_S,
+    MIPS_INS_FTINT_U,
+    MIPS_INS_FTQ,
+    MIPS_INS_FTRUNC_S,
+    MIPS_INS_FTRUNC_U,
+    MIPS_INS_HADD_S,
+    MIPS_INS_HADD_U,
+    MIPS_INS_HSUB_S,
+    MIPS_INS_HSUB_U,
+    MIPS_INS_ILVEV,
+    MIPS_INS_ILVL,
+    MIPS_INS_ILVOD,
+    MIPS_INS_ILVR,
+    MIPS_INS_INS,
+    MIPS_INS_INSERT,
+    MIPS_INS_INSV,
+    MIPS_INS_INSVE,
+    MIPS_INS_J,
+    MIPS_INS_JAL,
+    MIPS_INS_JALR,
+    MIPS_INS_JALRS,
+    MIPS_INS_JALS,
+    MIPS_INS_JALX,
+    MIPS_INS_JIALC,
+    MIPS_INS_JIC,
+    MIPS_INS_JR,
+    MIPS_INS_JRADDIUSP,
+    MIPS_INS_JRC,
+    MIPS_INS_JALRC,
+    MIPS_INS_LB,
+    MIPS_INS_LBUX,
+    MIPS_INS_LBU,
+    MIPS_INS_LD,
+    MIPS_INS_LDC1,
+    MIPS_INS_LDC2,
+    MIPS_INS_LDC3,
+    MIPS_INS_LDI,
+    MIPS_INS_LDL,
+    MIPS_INS_LDPC,
+    MIPS_INS_LDR,
+    MIPS_INS_LDXC1,
+    MIPS_INS_LH,
+    MIPS_INS_LHX,
+    MIPS_INS_LHU,
+    MIPS_INS_LL,
+    MIPS_INS_LLD,
+    MIPS_INS_LSA,
+    MIPS_INS_LUXC1,
+    MIPS_INS_LUI,
+    MIPS_INS_LW,
+    MIPS_INS_LWC1,
+    MIPS_INS_LWC2,
+    MIPS_INS_LWC3,
+    MIPS_INS_LWL,
+    MIPS_INS_LWPC,
+    MIPS_INS_LWR,
+    MIPS_INS_LWUPC,
+    MIPS_INS_LWU,
+    MIPS_INS_LWX,
+    MIPS_INS_LWXC1,
+    MIPS_INS_LI,
+    MIPS_INS_MADD,
+    MIPS_INS_MADDF,
+    MIPS_INS_MADDR_Q,
+    MIPS_INS_MADDU,
+    MIPS_INS_MADDV,
+    MIPS_INS_MADD_Q,
+    MIPS_INS_MAQ_SA,
+    MIPS_INS_MAQ_S,
+    MIPS_INS_MAXA,
+    MIPS_INS_MAXI_S,
+    MIPS_INS_MAXI_U,
+    MIPS_INS_MAX_A,
+    MIPS_INS_MAX,
+    MIPS_INS_MAX_S,
+    MIPS_INS_MAX_U,
+    MIPS_INS_MFC0,
+    MIPS_INS_MFC1,
+    MIPS_INS_MFC2,
+    MIPS_INS_MFHC1,
+    MIPS_INS_MFHI,
+    MIPS_INS_MFLO,
+    MIPS_INS_MINA,
+    MIPS_INS_MINI_S,
+    MIPS_INS_MINI_U,
+    MIPS_INS_MIN_A,
+    MIPS_INS_MIN,
+    MIPS_INS_MIN_S,
+    MIPS_INS_MIN_U,
+    MIPS_INS_MOD,
+    MIPS_INS_MODSUB,
+    MIPS_INS_MODU,
+    MIPS_INS_MOD_S,
+    MIPS_INS_MOD_U,
+    MIPS_INS_MOVE,
+    MIPS_INS_MOVF,
+    MIPS_INS_MOVN,
+    MIPS_INS_MOVT,
+    MIPS_INS_MOVZ,
+    MIPS_INS_MSUB,
+    MIPS_INS_MSUBF,
+    MIPS_INS_MSUBR_Q,
+    MIPS_INS_MSUBU,
+    MIPS_INS_MSUBV,
+    MIPS_INS_MSUB_Q,
+    MIPS_INS_MTC0,
+    MIPS_INS_MTC1,
+    MIPS_INS_MTC2,
+    MIPS_INS_MTHC1,
+    MIPS_INS_MTHI,
+    MIPS_INS_MTHLIP,
+    MIPS_INS_MTLO,
+    MIPS_INS_MTM0,
+    MIPS_INS_MTM1,
+    MIPS_INS_MTM2,
+    MIPS_INS_MTP0,
+    MIPS_INS_MTP1,
+    MIPS_INS_MTP2,
+    MIPS_INS_MUH,
+    MIPS_INS_MUHU,
+    MIPS_INS_MULEQ_S,
+    MIPS_INS_MULEU_S,
+    MIPS_INS_MULQ_RS,
+    MIPS_INS_MULQ_S,
+    MIPS_INS_MULR_Q,
+    MIPS_INS_MULSAQ_S,
+    MIPS_INS_MULSA,
+    MIPS_INS_MULT,
+    MIPS_INS_MULTU,
+    MIPS_INS_MULU,
+    MIPS_INS_MULV,
+    MIPS_INS_MUL_Q,
+    MIPS_INS_MUL_S,
+    MIPS_INS_NLOC,
+    MIPS_INS_NLZC,
+    MIPS_INS_NMADD,
+    MIPS_INS_NMSUB,
+    MIPS_INS_NOR,
+    MIPS_INS_NORI,
+    MIPS_INS_NOT,
+    MIPS_INS_OR,
+    MIPS_INS_ORI,
+    MIPS_INS_PACKRL,
+    MIPS_INS_PAUSE,
+    MIPS_INS_PCKEV,
+    MIPS_INS_PCKOD,
+    MIPS_INS_PCNT,
+    MIPS_INS_PICK,
+    MIPS_INS_POP,
+    MIPS_INS_PRECEQU,
+    MIPS_INS_PRECEQ,
+    MIPS_INS_PRECEU,
+    MIPS_INS_PRECRQU_S,
+    MIPS_INS_PRECRQ,
+    MIPS_INS_PRECRQ_RS,
+    MIPS_INS_PRECR,
+    MIPS_INS_PRECR_SRA,
+    MIPS_INS_PRECR_SRA_R,
+    MIPS_INS_PREF,
+    MIPS_INS_PREPEND,
+    MIPS_INS_RADDU,
+    MIPS_INS_RDDSP,
+    MIPS_INS_RDHWR,
+    MIPS_INS_REPLV,
+    MIPS_INS_REPL,
+    MIPS_INS_RINT,
+    MIPS_INS_ROTR,
+    MIPS_INS_ROTRV,
+    MIPS_INS_ROUND,
+    MIPS_INS_SAT_S,
+    MIPS_INS_SAT_U,
+    MIPS_INS_SB,
+    MIPS_INS_SC,
+    MIPS_INS_SCD,
+    MIPS_INS_SD,
+    MIPS_INS_SDBBP,
+    MIPS_INS_SDC1,
+    MIPS_INS_SDC2,
+    MIPS_INS_SDC3,
+    MIPS_INS_SDL,
+    MIPS_INS_SDR,
+    MIPS_INS_SDXC1,
+    MIPS_INS_SEB,
+    MIPS_INS_SEH,
+    MIPS_INS_SELEQZ,
+    MIPS_INS_SELNEZ,
+    MIPS_INS_SEL,
+    MIPS_INS_SEQ,
+    MIPS_INS_SEQI,
+    MIPS_INS_SH,
+    MIPS_INS_SHF,
+    MIPS_INS_SHILO,
+    MIPS_INS_SHILOV,
+    MIPS_INS_SHLLV,
+    MIPS_INS_SHLLV_S,
+    MIPS_INS_SHLL,
+    MIPS_INS_SHLL_S,
+    MIPS_INS_SHRAV,
+    MIPS_INS_SHRAV_R,
+    MIPS_INS_SHRA,
+    MIPS_INS_SHRA_R,
+    MIPS_INS_SHRLV,
+    MIPS_INS_SHRL,
+    MIPS_INS_SLDI,
+    MIPS_INS_SLD,
+    MIPS_INS_SLL,
+    MIPS_INS_SLLI,
+    MIPS_INS_SLLV,
+    MIPS_INS_SLT,
+    MIPS_INS_SLTI,
+    MIPS_INS_SLTIU,
+    MIPS_INS_SLTU,
+    MIPS_INS_SNE,
+    MIPS_INS_SNEI,
+    MIPS_INS_SPLATI,
+    MIPS_INS_SPLAT,
+    MIPS_INS_SRA,
+    MIPS_INS_SRAI,
+    MIPS_INS_SRARI,
+    MIPS_INS_SRAR,
+    MIPS_INS_SRAV,
+    MIPS_INS_SRL,
+    MIPS_INS_SRLI,
+    MIPS_INS_SRLRI,
+    MIPS_INS_SRLR,
+    MIPS_INS_SRLV,
+    MIPS_INS_SSNOP,
+    MIPS_INS_ST,
+    MIPS_INS_SUBQH,
+    MIPS_INS_SUBQH_R,
+    MIPS_INS_SUBQ,
+    MIPS_INS_SUBQ_S,
+    MIPS_INS_SUBSUS_U,
+    MIPS_INS_SUBSUU_S,
+    MIPS_INS_SUBS_S,
+    MIPS_INS_SUBS_U,
+    MIPS_INS_SUBUH,
+    MIPS_INS_SUBUH_R,
+    MIPS_INS_SUBU,
+    MIPS_INS_SUBU_S,
+    MIPS_INS_SUBVI,
+    MIPS_INS_SUBV,
+    MIPS_INS_SUXC1,
+    MIPS_INS_SW,
+    MIPS_INS_SWC1,
+    MIPS_INS_SWC2,
+    MIPS_INS_SWC3,
+    MIPS_INS_SWL,
+    MIPS_INS_SWR,
+    MIPS_INS_SWXC1,
+    MIPS_INS_SYNC,
+    MIPS_INS_SYSCALL,
+    MIPS_INS_TEQ,
+    MIPS_INS_TEQI,
+    MIPS_INS_TGE,
+    MIPS_INS_TGEI,
+    MIPS_INS_TGEIU,
+    MIPS_INS_TGEU,
+    MIPS_INS_TLBP,
+    MIPS_INS_TLBR,
+    MIPS_INS_TLBWI,
+    MIPS_INS_TLBWR,
+    MIPS_INS_TLT,
+    MIPS_INS_TLTI,
+    MIPS_INS_TLTIU,
+    MIPS_INS_TLTU,
+    MIPS_INS_TNE,
+    MIPS_INS_TNEI,
+    MIPS_INS_TRUNC,
+    MIPS_INS_V3MULU,
+    MIPS_INS_VMM0,
+    MIPS_INS_VMULU,
+    MIPS_INS_VSHF,
+    MIPS_INS_WAIT,
+    MIPS_INS_WRDSP,
+    MIPS_INS_WSBH,
+    MIPS_INS_XOR,
+    MIPS_INS_XORI,
+
+    //> some alias instructions
+    MIPS_INS_NOP,
+    MIPS_INS_NEGU,
+
+    //> special instructions
+    MIPS_INS_JALR_HB,   // jump and link with Hazard Barrier
+    MIPS_INS_JR_HB,     // jump register with Hazard Barrier
+
+    MIPS_INS_ENDING,
+} mips_insn;
+
+//> Group of MIPS instructions
+typedef enum mips_insn_group
+{
+    MIPS_GRP_INVALID = 0, // = CS_GRP_INVALID
+
+    //> Generic groups
+    // all jump instructions (conditional+direct+indirect jumps)
+    MIPS_GRP_JUMP,  // = CS_GRP_JUMP
+
+    //> Architecture-specific groups
+    MIPS_GRP_BITCOUNT = 128,
+    MIPS_GRP_DSP,
+    MIPS_GRP_DSPR2,
+    MIPS_GRP_FPIDX,
+    MIPS_GRP_MSA,
+    MIPS_GRP_MIPS32R2,
+    MIPS_GRP_MIPS64,
+    MIPS_GRP_MIPS64R2,
+    MIPS_GRP_SEINREG,
+    MIPS_GRP_STDENC,
+    MIPS_GRP_SWAP,
+    MIPS_GRP_MICROMIPS,
+    MIPS_GRP_MIPS16MODE,
+    MIPS_GRP_FP64BIT,
+    MIPS_GRP_NONANSFPMATH,
+    MIPS_GRP_NOTFP64BIT,
+    MIPS_GRP_NOTINMICROMIPS,
+    MIPS_GRP_NOTNACL,
+    MIPS_GRP_NOTMIPS32R6,
+    MIPS_GRP_NOTMIPS64R6,
+    MIPS_GRP_CNMIPS,
+    MIPS_GRP_MIPS32,
+    MIPS_GRP_MIPS32R6,
+    MIPS_GRP_MIPS64R6,
+    MIPS_GRP_MIPS2,
+    MIPS_GRP_MIPS3,
+    MIPS_GRP_MIPS3_32,
+    MIPS_GRP_MIPS3_32R2,
+    MIPS_GRP_MIPS4_32,
+    MIPS_GRP_MIPS4_32R2,
+    MIPS_GRP_MIPS5_32R2,
+    MIPS_GRP_GP32BIT,
+    MIPS_GRP_GP64BIT,
+
+    MIPS_GRP_ENDING,
+} mips_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/capstone/platform.h

@@ -0,0 +1,28 @@
+/* Capstone Disassembly Engine */
+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#ifndef CAPSTONE_PLATFORM_H
+#define CAPSTONE_PLATFORM_H
+
+#if !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+// MSVC
+
+// stdbool.h
+#if (_MSC_VER < 1800)
+#ifndef __cplusplus
+typedef unsigned char bool;
+#define false 0
+#define true 1
+#endif
+
+#else
+// VisualStudio 2013+ -> C99 is supported
+#include <stdbool.h>
+#endif
+
+#else // not MSVC -> C99 is supported
+#include <stdbool.h>
+#endif
+
+#endif

pluginsdk/capstone/sparc.h

@@ -0,0 +1,529 @@
+#ifndef CAPSTONE_SPARC_H
+#define CAPSTONE_SPARC_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+// GCC SPARC toolchain has a default macro called "sparc" which breaks
+// compilation
+#undef sparc
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Enums corresponding to Sparc condition codes, both icc's and fcc's.
+typedef enum sparc_cc
+{
+    SPARC_CC_INVALID = 0,   // invalid CC (default)
+    //> Integer condition codes
+    SPARC_CC_ICC_A   =  8 + 256, // Always
+    SPARC_CC_ICC_N   =  0 + 256, // Never
+    SPARC_CC_ICC_NE  =  9 + 256, // Not Equal
+    SPARC_CC_ICC_E   =  1 + 256, // Equal
+    SPARC_CC_ICC_G   = 10 + 256, // Greater
+    SPARC_CC_ICC_LE  =  2 + 256, // Less or Equal
+    SPARC_CC_ICC_GE  = 11 + 256, // Greater or Equal
+    SPARC_CC_ICC_L   =  3 + 256, // Less
+    SPARC_CC_ICC_GU  = 12 + 256, // Greater Unsigned
+    SPARC_CC_ICC_LEU =  4 + 256, // Less or Equal Unsigned
+    SPARC_CC_ICC_CC  = 13 + 256, // Carry Clear/Great or Equal Unsigned
+    SPARC_CC_ICC_CS  =  5 + 256, // Carry Set/Less Unsigned
+    SPARC_CC_ICC_POS = 14 + 256, // Positive
+    SPARC_CC_ICC_NEG =  6 + 256, // Negative
+    SPARC_CC_ICC_VC  = 15 + 256, // Overflow Clear
+    SPARC_CC_ICC_VS  =  7 + 256, // Overflow Set
+
+    //> Floating condition codes
+    SPARC_CC_FCC_A   =  8 + 16 + 256, // Always
+    SPARC_CC_FCC_N   =  0 + 16 + 256, // Never
+    SPARC_CC_FCC_U   =  7 + 16 + 256, // Unordered
+    SPARC_CC_FCC_G   =  6 + 16 + 256, // Greater
+    SPARC_CC_FCC_UG  =  5 + 16 + 256, // Unordered or Greater
+    SPARC_CC_FCC_L   =  4 + 16 + 256, // Less
+    SPARC_CC_FCC_UL  =  3 + 16 + 256, // Unordered or Less
+    SPARC_CC_FCC_LG  =  2 + 16 + 256, // Less or Greater
+    SPARC_CC_FCC_NE  =  1 + 16 + 256, // Not Equal
+    SPARC_CC_FCC_E   =  9 + 16 + 256, // Equal
+    SPARC_CC_FCC_UE  = 10 + 16 + 256, // Unordered or Equal
+    SPARC_CC_FCC_GE  = 11 + 16 + 256, // Greater or Equal
+    SPARC_CC_FCC_UGE = 12 + 16 + 256, // Unordered or Greater or Equal
+    SPARC_CC_FCC_LE  = 13 + 16 + 256, // Less or Equal
+    SPARC_CC_FCC_ULE = 14 + 16 + 256, // Unordered or Less or Equal
+    SPARC_CC_FCC_O   = 15 + 16 + 256, // Ordered
+} sparc_cc;
+
+//> Branch hint
+typedef enum sparc_hint
+{
+    SPARC_HINT_INVALID = 0, // no hint
+    SPARC_HINT_A    = 1 << 0,   // annul delay slot instruction
+    SPARC_HINT_PT   = 1 << 1,   // branch taken
+    SPARC_HINT_PN   = 1 << 2,   // branch NOT taken
+} sparc_hint;
+
+//> Operand type for instruction's operands
+typedef enum sparc_op_type
+{
+    SPARC_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+    SPARC_OP_REG, // = CS_OP_REG (Register operand).
+    SPARC_OP_IMM, // = CS_OP_IMM (Immediate operand).
+    SPARC_OP_MEM, // = CS_OP_MEM (Memory operand).
+} sparc_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with SPARC_OP_MEM operand type above
+typedef struct sparc_op_mem
+{
+    uint8_t base;   // base register
+    uint8_t index;  // index register
+    int32_t disp;   // displacement/offset value
+} sparc_op_mem;
+
+// Instruction operand
+typedef struct cs_sparc_op
+{
+    sparc_op_type type; // operand type
+    union
+    {
+        unsigned int reg;   // register value for REG operand
+        int32_t imm;        // immediate value for IMM operand
+        sparc_op_mem mem;       // base/disp value for MEM operand
+    };
+} cs_sparc_op;
+
+// Instruction structure
+typedef struct cs_sparc
+{
+    sparc_cc cc;    // code condition for this insn
+    sparc_hint hint;    // branch hint: encoding as bitwise OR of sparc_hint.
+    // Number of operands of this instruction,
+    // or 0 when instruction has no operand.
+    uint8_t op_count;
+    cs_sparc_op operands[4]; // operands for this instruction.
+} cs_sparc;
+
+//> SPARC registers
+typedef enum sparc_reg
+{
+    SPARC_REG_INVALID = 0,
+
+    SPARC_REG_F0,
+    SPARC_REG_F1,
+    SPARC_REG_F2,
+    SPARC_REG_F3,
+    SPARC_REG_F4,
+    SPARC_REG_F5,
+    SPARC_REG_F6,
+    SPARC_REG_F7,
+    SPARC_REG_F8,
+    SPARC_REG_F9,
+    SPARC_REG_F10,
+    SPARC_REG_F11,
+    SPARC_REG_F12,
+    SPARC_REG_F13,
+    SPARC_REG_F14,
+    SPARC_REG_F15,
+    SPARC_REG_F16,
+    SPARC_REG_F17,
+    SPARC_REG_F18,
+    SPARC_REG_F19,
+    SPARC_REG_F20,
+    SPARC_REG_F21,
+    SPARC_REG_F22,
+    SPARC_REG_F23,
+    SPARC_REG_F24,
+    SPARC_REG_F25,
+    SPARC_REG_F26,
+    SPARC_REG_F27,
+    SPARC_REG_F28,
+    SPARC_REG_F29,
+    SPARC_REG_F30,
+    SPARC_REG_F31,
+    SPARC_REG_F32,
+    SPARC_REG_F34,
+    SPARC_REG_F36,
+    SPARC_REG_F38,
+    SPARC_REG_F40,
+    SPARC_REG_F42,
+    SPARC_REG_F44,
+    SPARC_REG_F46,
+    SPARC_REG_F48,
+    SPARC_REG_F50,
+    SPARC_REG_F52,
+    SPARC_REG_F54,
+    SPARC_REG_F56,
+    SPARC_REG_F58,
+    SPARC_REG_F60,
+    SPARC_REG_F62,
+    SPARC_REG_FCC0, // Floating condition codes
+    SPARC_REG_FCC1,
+    SPARC_REG_FCC2,
+    SPARC_REG_FCC3,
+    SPARC_REG_FP,
+    SPARC_REG_G0,
+    SPARC_REG_G1,
+    SPARC_REG_G2,
+    SPARC_REG_G3,
+    SPARC_REG_G4,
+    SPARC_REG_G5,
+    SPARC_REG_G6,
+    SPARC_REG_G7,
+    SPARC_REG_I0,
+    SPARC_REG_I1,
+    SPARC_REG_I2,
+    SPARC_REG_I3,
+    SPARC_REG_I4,
+    SPARC_REG_I5,
+    SPARC_REG_I7,
+    SPARC_REG_ICC,  // Integer condition codes
+    SPARC_REG_L0,
+    SPARC_REG_L1,
+    SPARC_REG_L2,
+    SPARC_REG_L3,
+    SPARC_REG_L4,
+    SPARC_REG_L5,
+    SPARC_REG_L6,
+    SPARC_REG_L7,
+    SPARC_REG_O0,
+    SPARC_REG_O1,
+    SPARC_REG_O2,
+    SPARC_REG_O3,
+    SPARC_REG_O4,
+    SPARC_REG_O5,
+    SPARC_REG_O7,
+    SPARC_REG_SP,
+    SPARC_REG_Y,
+
+    // special register
+    SPARC_REG_XCC,
+
+    SPARC_REG_ENDING,   // <-- mark the end of the list of registers
+
+    // extras
+    SPARC_REG_O6 = SPARC_REG_SP,
+    SPARC_REG_I6 = SPARC_REG_FP,
+} sparc_reg;
+
+//> SPARC instruction
+typedef enum sparc_insn
+{
+    SPARC_INS_INVALID = 0,
+
+    SPARC_INS_ADDCC,
+    SPARC_INS_ADDX,
+    SPARC_INS_ADDXCC,
+    SPARC_INS_ADDXC,
+    SPARC_INS_ADDXCCC,
+    SPARC_INS_ADD,
+    SPARC_INS_ALIGNADDR,
+    SPARC_INS_ALIGNADDRL,
+    SPARC_INS_ANDCC,
+    SPARC_INS_ANDNCC,
+    SPARC_INS_ANDN,
+    SPARC_INS_AND,
+    SPARC_INS_ARRAY16,
+    SPARC_INS_ARRAY32,
+    SPARC_INS_ARRAY8,
+    SPARC_INS_B,
+    SPARC_INS_JMP,
+    SPARC_INS_BMASK,
+    SPARC_INS_FB,
+    SPARC_INS_BRGEZ,
+    SPARC_INS_BRGZ,
+    SPARC_INS_BRLEZ,
+    SPARC_INS_BRLZ,
+    SPARC_INS_BRNZ,
+    SPARC_INS_BRZ,
+    SPARC_INS_BSHUFFLE,
+    SPARC_INS_CALL,
+    SPARC_INS_CASX,
+    SPARC_INS_CAS,
+    SPARC_INS_CMASK16,
+    SPARC_INS_CMASK32,
+    SPARC_INS_CMASK8,
+    SPARC_INS_CMP,
+    SPARC_INS_EDGE16,
+    SPARC_INS_EDGE16L,
+    SPARC_INS_EDGE16LN,
+    SPARC_INS_EDGE16N,
+    SPARC_INS_EDGE32,
+    SPARC_INS_EDGE32L,
+    SPARC_INS_EDGE32LN,
+    SPARC_INS_EDGE32N,
+    SPARC_INS_EDGE8,
+    SPARC_INS_EDGE8L,
+    SPARC_INS_EDGE8LN,
+    SPARC_INS_EDGE8N,
+    SPARC_INS_FABSD,
+    SPARC_INS_FABSQ,
+    SPARC_INS_FABSS,
+    SPARC_INS_FADDD,
+    SPARC_INS_FADDQ,
+    SPARC_INS_FADDS,
+    SPARC_INS_FALIGNDATA,
+    SPARC_INS_FAND,
+    SPARC_INS_FANDNOT1,
+    SPARC_INS_FANDNOT1S,
+    SPARC_INS_FANDNOT2,
+    SPARC_INS_FANDNOT2S,
+    SPARC_INS_FANDS,
+    SPARC_INS_FCHKSM16,
+    SPARC_INS_FCMPD,
+    SPARC_INS_FCMPEQ16,
+    SPARC_INS_FCMPEQ32,
+    SPARC_INS_FCMPGT16,
+    SPARC_INS_FCMPGT32,
+    SPARC_INS_FCMPLE16,
+    SPARC_INS_FCMPLE32,
+    SPARC_INS_FCMPNE16,
+    SPARC_INS_FCMPNE32,
+    SPARC_INS_FCMPQ,
+    SPARC_INS_FCMPS,
+    SPARC_INS_FDIVD,
+    SPARC_INS_FDIVQ,
+    SPARC_INS_FDIVS,
+    SPARC_INS_FDMULQ,
+    SPARC_INS_FDTOI,
+    SPARC_INS_FDTOQ,
+    SPARC_INS_FDTOS,
+    SPARC_INS_FDTOX,
+    SPARC_INS_FEXPAND,
+    SPARC_INS_FHADDD,
+    SPARC_INS_FHADDS,
+    SPARC_INS_FHSUBD,
+    SPARC_INS_FHSUBS,
+    SPARC_INS_FITOD,
+    SPARC_INS_FITOQ,
+    SPARC_INS_FITOS,
+    SPARC_INS_FLCMPD,
+    SPARC_INS_FLCMPS,
+    SPARC_INS_FLUSHW,
+    SPARC_INS_FMEAN16,
+    SPARC_INS_FMOVD,
+    SPARC_INS_FMOVQ,
+    SPARC_INS_FMOVRDGEZ,
+    SPARC_INS_FMOVRQGEZ,
+    SPARC_INS_FMOVRSGEZ,
+    SPARC_INS_FMOVRDGZ,
+    SPARC_INS_FMOVRQGZ,
+    SPARC_INS_FMOVRSGZ,
+    SPARC_INS_FMOVRDLEZ,
+    SPARC_INS_FMOVRQLEZ,
+    SPARC_INS_FMOVRSLEZ,
+    SPARC_INS_FMOVRDLZ,
+    SPARC_INS_FMOVRQLZ,
+    SPARC_INS_FMOVRSLZ,
+    SPARC_INS_FMOVRDNZ,
+    SPARC_INS_FMOVRQNZ,
+    SPARC_INS_FMOVRSNZ,
+    SPARC_INS_FMOVRDZ,
+    SPARC_INS_FMOVRQZ,
+    SPARC_INS_FMOVRSZ,
+    SPARC_INS_FMOVS,
+    SPARC_INS_FMUL8SUX16,
+    SPARC_INS_FMUL8ULX16,
+    SPARC_INS_FMUL8X16,
+    SPARC_INS_FMUL8X16AL,
+    SPARC_INS_FMUL8X16AU,
+    SPARC_INS_FMULD,
+    SPARC_INS_FMULD8SUX16,
+    SPARC_INS_FMULD8ULX16,
+    SPARC_INS_FMULQ,
+    SPARC_INS_FMULS,
+    SPARC_INS_FNADDD,
+    SPARC_INS_FNADDS,
+    SPARC_INS_FNAND,
+    SPARC_INS_FNANDS,
+    SPARC_INS_FNEGD,
+    SPARC_INS_FNEGQ,
+    SPARC_INS_FNEGS,
+    SPARC_INS_FNHADDD,
+    SPARC_INS_FNHADDS,
+    SPARC_INS_FNOR,
+    SPARC_INS_FNORS,
+    SPARC_INS_FNOT1,
+    SPARC_INS_FNOT1S,
+    SPARC_INS_FNOT2,
+    SPARC_INS_FNOT2S,
+    SPARC_INS_FONE,
+    SPARC_INS_FONES,
+    SPARC_INS_FOR,
+    SPARC_INS_FORNOT1,
+    SPARC_INS_FORNOT1S,
+    SPARC_INS_FORNOT2,
+    SPARC_INS_FORNOT2S,
+    SPARC_INS_FORS,
+    SPARC_INS_FPACK16,
+    SPARC_INS_FPACK32,
+    SPARC_INS_FPACKFIX,
+    SPARC_INS_FPADD16,
+    SPARC_INS_FPADD16S,
+    SPARC_INS_FPADD32,
+    SPARC_INS_FPADD32S,
+    SPARC_INS_FPADD64,
+    SPARC_INS_FPMERGE,
+    SPARC_INS_FPSUB16,
+    SPARC_INS_FPSUB16S,
+    SPARC_INS_FPSUB32,
+    SPARC_INS_FPSUB32S,
+    SPARC_INS_FQTOD,
+    SPARC_INS_FQTOI,
+    SPARC_INS_FQTOS,
+    SPARC_INS_FQTOX,
+    SPARC_INS_FSLAS16,
+    SPARC_INS_FSLAS32,
+    SPARC_INS_FSLL16,
+    SPARC_INS_FSLL32,
+    SPARC_INS_FSMULD,
+    SPARC_INS_FSQRTD,
+    SPARC_INS_FSQRTQ,
+    SPARC_INS_FSQRTS,
+    SPARC_INS_FSRA16,
+    SPARC_INS_FSRA32,
+    SPARC_INS_FSRC1,
+    SPARC_INS_FSRC1S,
+    SPARC_INS_FSRC2,
+    SPARC_INS_FSRC2S,
+    SPARC_INS_FSRL16,
+    SPARC_INS_FSRL32,
+    SPARC_INS_FSTOD,
+    SPARC_INS_FSTOI,
+    SPARC_INS_FSTOQ,
+    SPARC_INS_FSTOX,
+    SPARC_INS_FSUBD,
+    SPARC_INS_FSUBQ,
+    SPARC_INS_FSUBS,
+    SPARC_INS_FXNOR,
+    SPARC_INS_FXNORS,
+    SPARC_INS_FXOR,
+    SPARC_INS_FXORS,
+    SPARC_INS_FXTOD,
+    SPARC_INS_FXTOQ,
+    SPARC_INS_FXTOS,
+    SPARC_INS_FZERO,
+    SPARC_INS_FZEROS,
+    SPARC_INS_JMPL,
+    SPARC_INS_LDD,
+    SPARC_INS_LD,
+    SPARC_INS_LDQ,
+    SPARC_INS_LDSB,
+    SPARC_INS_LDSH,
+    SPARC_INS_LDSW,
+    SPARC_INS_LDUB,
+    SPARC_INS_LDUH,
+    SPARC_INS_LDX,
+    SPARC_INS_LZCNT,
+    SPARC_INS_MEMBAR,
+    SPARC_INS_MOVDTOX,
+    SPARC_INS_MOV,
+    SPARC_INS_MOVRGEZ,
+    SPARC_INS_MOVRGZ,
+    SPARC_INS_MOVRLEZ,
+    SPARC_INS_MOVRLZ,
+    SPARC_INS_MOVRNZ,
+    SPARC_INS_MOVRZ,
+    SPARC_INS_MOVSTOSW,
+    SPARC_INS_MOVSTOUW,
+    SPARC_INS_MULX,
+    SPARC_INS_NOP,
+    SPARC_INS_ORCC,
+    SPARC_INS_ORNCC,
+    SPARC_INS_ORN,
+    SPARC_INS_OR,
+    SPARC_INS_PDIST,
+    SPARC_INS_PDISTN,
+    SPARC_INS_POPC,
+    SPARC_INS_RD,
+    SPARC_INS_RESTORE,
+    SPARC_INS_RETT,
+    SPARC_INS_SAVE,
+    SPARC_INS_SDIVCC,
+    SPARC_INS_SDIVX,
+    SPARC_INS_SDIV,
+    SPARC_INS_SETHI,
+    SPARC_INS_SHUTDOWN,
+    SPARC_INS_SIAM,
+    SPARC_INS_SLLX,
+    SPARC_INS_SLL,
+    SPARC_INS_SMULCC,
+    SPARC_INS_SMUL,
+    SPARC_INS_SRAX,
+    SPARC_INS_SRA,
+    SPARC_INS_SRLX,
+    SPARC_INS_SRL,
+    SPARC_INS_STBAR,
+    SPARC_INS_STB,
+    SPARC_INS_STD,
+    SPARC_INS_ST,
+    SPARC_INS_STH,
+    SPARC_INS_STQ,
+    SPARC_INS_STX,
+    SPARC_INS_SUBCC,
+    SPARC_INS_SUBX,
+    SPARC_INS_SUBXCC,
+    SPARC_INS_SUB,
+    SPARC_INS_SWAP,
+    SPARC_INS_TADDCCTV,
+    SPARC_INS_TADDCC,
+    SPARC_INS_T,
+    SPARC_INS_TSUBCCTV,
+    SPARC_INS_TSUBCC,
+    SPARC_INS_UDIVCC,
+    SPARC_INS_UDIVX,
+    SPARC_INS_UDIV,
+    SPARC_INS_UMULCC,
+    SPARC_INS_UMULXHI,
+    SPARC_INS_UMUL,
+    SPARC_INS_UNIMP,
+    SPARC_INS_FCMPED,
+    SPARC_INS_FCMPEQ,
+    SPARC_INS_FCMPES,
+    SPARC_INS_WR,
+    SPARC_INS_XMULX,
+    SPARC_INS_XMULXHI,
+    SPARC_INS_XNORCC,
+    SPARC_INS_XNOR,
+    SPARC_INS_XORCC,
+    SPARC_INS_XOR,
+
+    // alias instructions
+    SPARC_INS_RET,
+    SPARC_INS_RETL,
+
+    SPARC_INS_ENDING,   // <-- mark the end of the list of instructions
+} sparc_insn;
+
+//> Group of SPARC instructions
+typedef enum sparc_insn_group
+{
+    SPARC_GRP_INVALID = 0, // = CS_GRP_INVALID
+
+    //> Generic groups
+    // all jump instructions (conditional+direct+indirect jumps)
+    SPARC_GRP_JUMP, // = CS_GRP_JUMP
+
+    //> Architecture-specific groups
+    SPARC_GRP_HARDQUAD = 128,
+    SPARC_GRP_V9,
+    SPARC_GRP_VIS,
+    SPARC_GRP_VIS2,
+    SPARC_GRP_VIS3,
+    SPARC_GRP_32BIT,
+    SPARC_GRP_64BIT,
+
+    SPARC_GRP_ENDING,   // <-- mark the end of the list of groups
+} sparc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/capstone/systemz.h

@@ -0,0 +1,838 @@
+#ifndef CAPSTONE_SYSTEMZ_H
+#define CAPSTONE_SYSTEMZ_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Enums corresponding to SystemZ condition codes
+typedef enum sysz_cc
+{
+    SYSZ_CC_INVALID = 0,    // invalid CC (default)
+
+    SYSZ_CC_O,
+    SYSZ_CC_H,
+    SYSZ_CC_NLE,
+    SYSZ_CC_L,
+    SYSZ_CC_NHE,
+    SYSZ_CC_LH,
+    SYSZ_CC_NE,
+    SYSZ_CC_E,
+    SYSZ_CC_NLH,
+    SYSZ_CC_HE,
+    SYSZ_CC_NL,
+    SYSZ_CC_LE,
+    SYSZ_CC_NH,
+    SYSZ_CC_NO,
+} sysz_cc;
+
+//> Operand type for instruction's operands
+typedef enum sysz_op_type
+{
+    SYSZ_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+    SYSZ_OP_REG, // = CS_OP_REG (Register operand).
+    SYSZ_OP_IMM, // = CS_OP_IMM (Immediate operand).
+    SYSZ_OP_MEM, // = CS_OP_MEM (Memory operand).
+    SYSZ_OP_ACREG = 64, // Access register operand.
+} sysz_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with SYSZ_OP_MEM operand type above
+typedef struct sysz_op_mem
+{
+    uint8_t base;   // base register
+    uint8_t index;  // index register
+    uint64_t length;    // BDLAddr operand
+    int64_t disp;   // displacement/offset value
+} sysz_op_mem;
+
+// Instruction operand
+typedef struct cs_sysz_op
+{
+    sysz_op_type type;  // operand type
+    union
+    {
+        unsigned int reg;   // register value for REG operand
+        int64_t imm;        // immediate value for IMM operand
+        sysz_op_mem mem;        // base/disp value for MEM operand
+    };
+} cs_sysz_op;
+
+// Instruction structure
+typedef struct cs_sysz
+{
+    sysz_cc cc;     // Code condition
+    // Number of operands of this instruction,
+    // or 0 when instruction has no operand.
+    uint8_t op_count;
+    cs_sysz_op operands[6]; // operands for this instruction.
+} cs_sysz;
+
+//> SystemZ registers
+typedef enum sysz_reg
+{
+    SYSZ_REG_INVALID = 0,
+
+    SYSZ_REG_0,
+    SYSZ_REG_1,
+    SYSZ_REG_2,
+    SYSZ_REG_3,
+    SYSZ_REG_4,
+    SYSZ_REG_5,
+    SYSZ_REG_6,
+    SYSZ_REG_7,
+    SYSZ_REG_8,
+    SYSZ_REG_9,
+    SYSZ_REG_10,
+    SYSZ_REG_11,
+    SYSZ_REG_12,
+    SYSZ_REG_13,
+    SYSZ_REG_14,
+    SYSZ_REG_15,
+    SYSZ_REG_CC,
+    SYSZ_REG_F0,
+    SYSZ_REG_F1,
+    SYSZ_REG_F2,
+    SYSZ_REG_F3,
+    SYSZ_REG_F4,
+    SYSZ_REG_F5,
+    SYSZ_REG_F6,
+    SYSZ_REG_F7,
+    SYSZ_REG_F8,
+    SYSZ_REG_F9,
+    SYSZ_REG_F10,
+    SYSZ_REG_F11,
+    SYSZ_REG_F12,
+    SYSZ_REG_F13,
+    SYSZ_REG_F14,
+    SYSZ_REG_F15,
+
+    SYSZ_REG_R0L,
+
+    SYSZ_REG_ENDING,
+} sysz_reg;
+
+//> SystemZ instruction
+typedef enum sysz_insn
+{
+    SYSZ_INS_INVALID = 0,
+
+    SYSZ_INS_A,
+    SYSZ_INS_ADB,
+    SYSZ_INS_ADBR,
+    SYSZ_INS_AEB,
+    SYSZ_INS_AEBR,
+    SYSZ_INS_AFI,
+    SYSZ_INS_AG,
+    SYSZ_INS_AGF,
+    SYSZ_INS_AGFI,
+    SYSZ_INS_AGFR,
+    SYSZ_INS_AGHI,
+    SYSZ_INS_AGHIK,
+    SYSZ_INS_AGR,
+    SYSZ_INS_AGRK,
+    SYSZ_INS_AGSI,
+    SYSZ_INS_AH,
+    SYSZ_INS_AHI,
+    SYSZ_INS_AHIK,
+    SYSZ_INS_AHY,
+    SYSZ_INS_AIH,
+    SYSZ_INS_AL,
+    SYSZ_INS_ALC,
+    SYSZ_INS_ALCG,
+    SYSZ_INS_ALCGR,
+    SYSZ_INS_ALCR,
+    SYSZ_INS_ALFI,
+    SYSZ_INS_ALG,
+    SYSZ_INS_ALGF,
+    SYSZ_INS_ALGFI,
+    SYSZ_INS_ALGFR,
+    SYSZ_INS_ALGHSIK,
+    SYSZ_INS_ALGR,
+    SYSZ_INS_ALGRK,
+    SYSZ_INS_ALHSIK,
+    SYSZ_INS_ALR,
+    SYSZ_INS_ALRK,
+    SYSZ_INS_ALY,
+    SYSZ_INS_AR,
+    SYSZ_INS_ARK,
+    SYSZ_INS_ASI,
+    SYSZ_INS_AXBR,
+    SYSZ_INS_AY,
+    SYSZ_INS_BCR,
+    SYSZ_INS_BRC,
+    SYSZ_INS_BRCL,
+    SYSZ_INS_CGIJ,
+    SYSZ_INS_CGRJ,
+    SYSZ_INS_CIJ,
+    SYSZ_INS_CLGIJ,
+    SYSZ_INS_CLGRJ,
+    SYSZ_INS_CLIJ,
+    SYSZ_INS_CLRJ,
+    SYSZ_INS_CRJ,
+    SYSZ_INS_BER,
+    SYSZ_INS_JE,
+    SYSZ_INS_JGE,
+    SYSZ_INS_LOCE,
+    SYSZ_INS_LOCGE,
+    SYSZ_INS_LOCGRE,
+    SYSZ_INS_LOCRE,
+    SYSZ_INS_STOCE,
+    SYSZ_INS_STOCGE,
+    SYSZ_INS_BHR,
+    SYSZ_INS_BHER,
+    SYSZ_INS_JHE,
+    SYSZ_INS_JGHE,
+    SYSZ_INS_LOCHE,
+    SYSZ_INS_LOCGHE,
+    SYSZ_INS_LOCGRHE,
+    SYSZ_INS_LOCRHE,
+    SYSZ_INS_STOCHE,
+    SYSZ_INS_STOCGHE,
+    SYSZ_INS_JH,
+    SYSZ_INS_JGH,
+    SYSZ_INS_LOCH,
+    SYSZ_INS_LOCGH,
+    SYSZ_INS_LOCGRH,
+    SYSZ_INS_LOCRH,
+    SYSZ_INS_STOCH,
+    SYSZ_INS_STOCGH,
+    SYSZ_INS_CGIJNLH,
+    SYSZ_INS_CGRJNLH,
+    SYSZ_INS_CIJNLH,
+    SYSZ_INS_CLGIJNLH,
+    SYSZ_INS_CLGRJNLH,
+    SYSZ_INS_CLIJNLH,
+    SYSZ_INS_CLRJNLH,
+    SYSZ_INS_CRJNLH,
+    SYSZ_INS_CGIJE,
+    SYSZ_INS_CGRJE,
+    SYSZ_INS_CIJE,
+    SYSZ_INS_CLGIJE,
+    SYSZ_INS_CLGRJE,
+    SYSZ_INS_CLIJE,
+    SYSZ_INS_CLRJE,
+    SYSZ_INS_CRJE,
+    SYSZ_INS_CGIJNLE,
+    SYSZ_INS_CGRJNLE,
+    SYSZ_INS_CIJNLE,
+    SYSZ_INS_CLGIJNLE,
+    SYSZ_INS_CLGRJNLE,
+    SYSZ_INS_CLIJNLE,
+    SYSZ_INS_CLRJNLE,
+    SYSZ_INS_CRJNLE,
+    SYSZ_INS_CGIJH,
+    SYSZ_INS_CGRJH,
+    SYSZ_INS_CIJH,
+    SYSZ_INS_CLGIJH,
+    SYSZ_INS_CLGRJH,
+    SYSZ_INS_CLIJH,
+    SYSZ_INS_CLRJH,
+    SYSZ_INS_CRJH,
+    SYSZ_INS_CGIJNL,
+    SYSZ_INS_CGRJNL,
+    SYSZ_INS_CIJNL,
+    SYSZ_INS_CLGIJNL,
+    SYSZ_INS_CLGRJNL,
+    SYSZ_INS_CLIJNL,
+    SYSZ_INS_CLRJNL,
+    SYSZ_INS_CRJNL,
+    SYSZ_INS_CGIJHE,
+    SYSZ_INS_CGRJHE,
+    SYSZ_INS_CIJHE,
+    SYSZ_INS_CLGIJHE,
+    SYSZ_INS_CLGRJHE,
+    SYSZ_INS_CLIJHE,
+    SYSZ_INS_CLRJHE,
+    SYSZ_INS_CRJHE,
+    SYSZ_INS_CGIJNHE,
+    SYSZ_INS_CGRJNHE,
+    SYSZ_INS_CIJNHE,
+    SYSZ_INS_CLGIJNHE,
+    SYSZ_INS_CLGRJNHE,
+    SYSZ_INS_CLIJNHE,
+    SYSZ_INS_CLRJNHE,
+    SYSZ_INS_CRJNHE,
+    SYSZ_INS_CGIJL,
+    SYSZ_INS_CGRJL,
+    SYSZ_INS_CIJL,
+    SYSZ_INS_CLGIJL,
+    SYSZ_INS_CLGRJL,
+    SYSZ_INS_CLIJL,
+    SYSZ_INS_CLRJL,
+    SYSZ_INS_CRJL,
+    SYSZ_INS_CGIJNH,
+    SYSZ_INS_CGRJNH,
+    SYSZ_INS_CIJNH,
+    SYSZ_INS_CLGIJNH,
+    SYSZ_INS_CLGRJNH,
+    SYSZ_INS_CLIJNH,
+    SYSZ_INS_CLRJNH,
+    SYSZ_INS_CRJNH,
+    SYSZ_INS_CGIJLE,
+    SYSZ_INS_CGRJLE,
+    SYSZ_INS_CIJLE,
+    SYSZ_INS_CLGIJLE,
+    SYSZ_INS_CLGRJLE,
+    SYSZ_INS_CLIJLE,
+    SYSZ_INS_CLRJLE,
+    SYSZ_INS_CRJLE,
+    SYSZ_INS_CGIJNE,
+    SYSZ_INS_CGRJNE,
+    SYSZ_INS_CIJNE,
+    SYSZ_INS_CLGIJNE,
+    SYSZ_INS_CLGRJNE,
+    SYSZ_INS_CLIJNE,
+    SYSZ_INS_CLRJNE,
+    SYSZ_INS_CRJNE,
+    SYSZ_INS_CGIJLH,
+    SYSZ_INS_CGRJLH,
+    SYSZ_INS_CIJLH,
+    SYSZ_INS_CLGIJLH,
+    SYSZ_INS_CLGRJLH,
+    SYSZ_INS_CLIJLH,
+    SYSZ_INS_CLRJLH,
+    SYSZ_INS_CRJLH,
+    SYSZ_INS_BLR,
+    SYSZ_INS_BLER,
+    SYSZ_INS_JLE,
+    SYSZ_INS_JGLE,
+    SYSZ_INS_LOCLE,
+    SYSZ_INS_LOCGLE,
+    SYSZ_INS_LOCGRLE,
+    SYSZ_INS_LOCRLE,
+    SYSZ_INS_STOCLE,
+    SYSZ_INS_STOCGLE,
+    SYSZ_INS_BLHR,
+    SYSZ_INS_JLH,
+    SYSZ_INS_JGLH,
+    SYSZ_INS_LOCLH,
+    SYSZ_INS_LOCGLH,
+    SYSZ_INS_LOCGRLH,
+    SYSZ_INS_LOCRLH,
+    SYSZ_INS_STOCLH,
+    SYSZ_INS_STOCGLH,
+    SYSZ_INS_JL,
+    SYSZ_INS_JGL,
+    SYSZ_INS_LOCL,
+    SYSZ_INS_LOCGL,
+    SYSZ_INS_LOCGRL,
+    SYSZ_INS_LOCRL,
+    SYSZ_INS_LOC,
+    SYSZ_INS_LOCG,
+    SYSZ_INS_LOCGR,
+    SYSZ_INS_LOCR,
+    SYSZ_INS_STOCL,
+    SYSZ_INS_STOCGL,
+    SYSZ_INS_BNER,
+    SYSZ_INS_JNE,
+    SYSZ_INS_JGNE,
+    SYSZ_INS_LOCNE,
+    SYSZ_INS_LOCGNE,
+    SYSZ_INS_LOCGRNE,
+    SYSZ_INS_LOCRNE,
+    SYSZ_INS_STOCNE,
+    SYSZ_INS_STOCGNE,
+    SYSZ_INS_BNHR,
+    SYSZ_INS_BNHER,
+    SYSZ_INS_JNHE,
+    SYSZ_INS_JGNHE,
+    SYSZ_INS_LOCNHE,
+    SYSZ_INS_LOCGNHE,
+    SYSZ_INS_LOCGRNHE,
+    SYSZ_INS_LOCRNHE,
+    SYSZ_INS_STOCNHE,
+    SYSZ_INS_STOCGNHE,
+    SYSZ_INS_JNH,
+    SYSZ_INS_JGNH,
+    SYSZ_INS_LOCNH,
+    SYSZ_INS_LOCGNH,
+    SYSZ_INS_LOCGRNH,
+    SYSZ_INS_LOCRNH,
+    SYSZ_INS_STOCNH,
+    SYSZ_INS_STOCGNH,
+    SYSZ_INS_BNLR,
+    SYSZ_INS_BNLER,
+    SYSZ_INS_JNLE,
+    SYSZ_INS_JGNLE,
+    SYSZ_INS_LOCNLE,
+    SYSZ_INS_LOCGNLE,
+    SYSZ_INS_LOCGRNLE,
+    SYSZ_INS_LOCRNLE,
+    SYSZ_INS_STOCNLE,
+    SYSZ_INS_STOCGNLE,
+    SYSZ_INS_BNLHR,
+    SYSZ_INS_JNLH,
+    SYSZ_INS_JGNLH,
+    SYSZ_INS_LOCNLH,
+    SYSZ_INS_LOCGNLH,
+    SYSZ_INS_LOCGRNLH,
+    SYSZ_INS_LOCRNLH,
+    SYSZ_INS_STOCNLH,
+    SYSZ_INS_STOCGNLH,
+    SYSZ_INS_JNL,
+    SYSZ_INS_JGNL,
+    SYSZ_INS_LOCNL,
+    SYSZ_INS_LOCGNL,
+    SYSZ_INS_LOCGRNL,
+    SYSZ_INS_LOCRNL,
+    SYSZ_INS_STOCNL,
+    SYSZ_INS_STOCGNL,
+    SYSZ_INS_BNOR,
+    SYSZ_INS_JNO,
+    SYSZ_INS_JGNO,
+    SYSZ_INS_LOCNO,
+    SYSZ_INS_LOCGNO,
+    SYSZ_INS_LOCGRNO,
+    SYSZ_INS_LOCRNO,
+    SYSZ_INS_STOCNO,
+    SYSZ_INS_STOCGNO,
+    SYSZ_INS_BOR,
+    SYSZ_INS_JO,
+    SYSZ_INS_JGO,
+    SYSZ_INS_LOCO,
+    SYSZ_INS_LOCGO,
+    SYSZ_INS_LOCGRO,
+    SYSZ_INS_LOCRO,
+    SYSZ_INS_STOCO,
+    SYSZ_INS_STOCGO,
+    SYSZ_INS_STOC,
+    SYSZ_INS_STOCG,
+    SYSZ_INS_BASR,
+    SYSZ_INS_BR,
+    SYSZ_INS_BRAS,
+    SYSZ_INS_BRASL,
+    SYSZ_INS_J,
+    SYSZ_INS_JG,
+    SYSZ_INS_BRCT,
+    SYSZ_INS_BRCTG,
+    SYSZ_INS_C,
+    SYSZ_INS_CDB,
+    SYSZ_INS_CDBR,
+    SYSZ_INS_CDFBR,
+    SYSZ_INS_CDGBR,
+    SYSZ_INS_CDLFBR,
+    SYSZ_INS_CDLGBR,
+    SYSZ_INS_CEB,
+    SYSZ_INS_CEBR,
+    SYSZ_INS_CEFBR,
+    SYSZ_INS_CEGBR,
+    SYSZ_INS_CELFBR,
+    SYSZ_INS_CELGBR,
+    SYSZ_INS_CFDBR,
+    SYSZ_INS_CFEBR,
+    SYSZ_INS_CFI,
+    SYSZ_INS_CFXBR,
+    SYSZ_INS_CG,
+    SYSZ_INS_CGDBR,
+    SYSZ_INS_CGEBR,
+    SYSZ_INS_CGF,
+    SYSZ_INS_CGFI,
+    SYSZ_INS_CGFR,
+    SYSZ_INS_CGFRL,
+    SYSZ_INS_CGH,
+    SYSZ_INS_CGHI,
+    SYSZ_INS_CGHRL,
+    SYSZ_INS_CGHSI,
+    SYSZ_INS_CGR,
+    SYSZ_INS_CGRL,
+    SYSZ_INS_CGXBR,
+    SYSZ_INS_CH,
+    SYSZ_INS_CHF,
+    SYSZ_INS_CHHSI,
+    SYSZ_INS_CHI,
+    SYSZ_INS_CHRL,
+    SYSZ_INS_CHSI,
+    SYSZ_INS_CHY,
+    SYSZ_INS_CIH,
+    SYSZ_INS_CL,
+    SYSZ_INS_CLC,
+    SYSZ_INS_CLFDBR,
+    SYSZ_INS_CLFEBR,
+    SYSZ_INS_CLFHSI,
+    SYSZ_INS_CLFI,
+    SYSZ_INS_CLFXBR,
+    SYSZ_INS_CLG,
+    SYSZ_INS_CLGDBR,
+    SYSZ_INS_CLGEBR,
+    SYSZ_INS_CLGF,
+    SYSZ_INS_CLGFI,
+    SYSZ_INS_CLGFR,
+    SYSZ_INS_CLGFRL,
+    SYSZ_INS_CLGHRL,
+    SYSZ_INS_CLGHSI,
+    SYSZ_INS_CLGR,
+    SYSZ_INS_CLGRL,
+    SYSZ_INS_CLGXBR,
+    SYSZ_INS_CLHF,
+    SYSZ_INS_CLHHSI,
+    SYSZ_INS_CLHRL,
+    SYSZ_INS_CLI,
+    SYSZ_INS_CLIH,
+    SYSZ_INS_CLIY,
+    SYSZ_INS_CLR,
+    SYSZ_INS_CLRL,
+    SYSZ_INS_CLST,
+    SYSZ_INS_CLY,
+    SYSZ_INS_CPSDR,
+    SYSZ_INS_CR,
+    SYSZ_INS_CRL,
+    SYSZ_INS_CS,
+    SYSZ_INS_CSG,
+    SYSZ_INS_CSY,
+    SYSZ_INS_CXBR,
+    SYSZ_INS_CXFBR,
+    SYSZ_INS_CXGBR,
+    SYSZ_INS_CXLFBR,
+    SYSZ_INS_CXLGBR,
+    SYSZ_INS_CY,
+    SYSZ_INS_DDB,
+    SYSZ_INS_DDBR,
+    SYSZ_INS_DEB,
+    SYSZ_INS_DEBR,
+    SYSZ_INS_DL,
+    SYSZ_INS_DLG,
+    SYSZ_INS_DLGR,
+    SYSZ_INS_DLR,
+    SYSZ_INS_DSG,
+    SYSZ_INS_DSGF,
+    SYSZ_INS_DSGFR,
+    SYSZ_INS_DSGR,
+    SYSZ_INS_DXBR,
+    SYSZ_INS_EAR,
+    SYSZ_INS_FIDBR,
+    SYSZ_INS_FIDBRA,
+    SYSZ_INS_FIEBR,
+    SYSZ_INS_FIEBRA,
+    SYSZ_INS_FIXBR,
+    SYSZ_INS_FIXBRA,
+    SYSZ_INS_FLOGR,
+    SYSZ_INS_IC,
+    SYSZ_INS_ICY,
+    SYSZ_INS_IIHF,
+    SYSZ_INS_IIHH,
+    SYSZ_INS_IIHL,
+    SYSZ_INS_IILF,
+    SYSZ_INS_IILH,
+    SYSZ_INS_IILL,
+    SYSZ_INS_IPM,
+    SYSZ_INS_L,
+    SYSZ_INS_LA,
+    SYSZ_INS_LAA,
+    SYSZ_INS_LAAG,
+    SYSZ_INS_LAAL,
+    SYSZ_INS_LAALG,
+    SYSZ_INS_LAN,
+    SYSZ_INS_LANG,
+    SYSZ_INS_LAO,
+    SYSZ_INS_LAOG,
+    SYSZ_INS_LARL,
+    SYSZ_INS_LAX,
+    SYSZ_INS_LAXG,
+    SYSZ_INS_LAY,
+    SYSZ_INS_LB,
+    SYSZ_INS_LBH,
+    SYSZ_INS_LBR,
+    SYSZ_INS_LCDBR,
+    SYSZ_INS_LCEBR,
+    SYSZ_INS_LCGFR,
+    SYSZ_INS_LCGR,
+    SYSZ_INS_LCR,
+    SYSZ_INS_LCXBR,
+    SYSZ_INS_LD,
+    SYSZ_INS_LDEB,
+    SYSZ_INS_LDEBR,
+    SYSZ_INS_LDGR,
+    SYSZ_INS_LDR,
+    SYSZ_INS_LDXBR,
+    SYSZ_INS_LDXBRA,
+    SYSZ_INS_LDY,
+    SYSZ_INS_LE,
+    SYSZ_INS_LEDBR,
+    SYSZ_INS_LEDBRA,
+    SYSZ_INS_LER,
+    SYSZ_INS_LEXBR,
+    SYSZ_INS_LEXBRA,
+    SYSZ_INS_LEY,
+    SYSZ_INS_LFH,
+    SYSZ_INS_LG,
+    SYSZ_INS_LGB,
+    SYSZ_INS_LGBR,
+    SYSZ_INS_LGDR,
+    SYSZ_INS_LGF,
+    SYSZ_INS_LGFI,
+    SYSZ_INS_LGFR,
+    SYSZ_INS_LGFRL,
+    SYSZ_INS_LGH,
+    SYSZ_INS_LGHI,
+    SYSZ_INS_LGHR,
+    SYSZ_INS_LGHRL,
+    SYSZ_INS_LGR,
+    SYSZ_INS_LGRL,
+    SYSZ_INS_LH,
+    SYSZ_INS_LHH,
+    SYSZ_INS_LHI,
+    SYSZ_INS_LHR,
+    SYSZ_INS_LHRL,
+    SYSZ_INS_LHY,
+    SYSZ_INS_LLC,
+    SYSZ_INS_LLCH,
+    SYSZ_INS_LLCR,
+    SYSZ_INS_LLGC,
+    SYSZ_INS_LLGCR,
+    SYSZ_INS_LLGF,
+    SYSZ_INS_LLGFR,
+    SYSZ_INS_LLGFRL,
+    SYSZ_INS_LLGH,
+    SYSZ_INS_LLGHR,
+    SYSZ_INS_LLGHRL,
+    SYSZ_INS_LLH,
+    SYSZ_INS_LLHH,
+    SYSZ_INS_LLHR,
+    SYSZ_INS_LLHRL,
+    SYSZ_INS_LLIHF,
+    SYSZ_INS_LLIHH,
+    SYSZ_INS_LLIHL,
+    SYSZ_INS_LLILF,
+    SYSZ_INS_LLILH,
+    SYSZ_INS_LLILL,
+    SYSZ_INS_LMG,
+    SYSZ_INS_LNDBR,
+    SYSZ_INS_LNEBR,
+    SYSZ_INS_LNGFR,
+    SYSZ_INS_LNGR,
+    SYSZ_INS_LNR,
+    SYSZ_INS_LNXBR,
+    SYSZ_INS_LPDBR,
+    SYSZ_INS_LPEBR,
+    SYSZ_INS_LPGFR,
+    SYSZ_INS_LPGR,
+    SYSZ_INS_LPR,
+    SYSZ_INS_LPXBR,
+    SYSZ_INS_LR,
+    SYSZ_INS_LRL,
+    SYSZ_INS_LRV,
+    SYSZ_INS_LRVG,
+    SYSZ_INS_LRVGR,
+    SYSZ_INS_LRVR,
+    SYSZ_INS_LT,
+    SYSZ_INS_LTDBR,
+    SYSZ_INS_LTEBR,
+    SYSZ_INS_LTG,
+    SYSZ_INS_LTGF,
+    SYSZ_INS_LTGFR,
+    SYSZ_INS_LTGR,
+    SYSZ_INS_LTR,
+    SYSZ_INS_LTXBR,
+    SYSZ_INS_LXDB,
+    SYSZ_INS_LXDBR,
+    SYSZ_INS_LXEB,
+    SYSZ_INS_LXEBR,
+    SYSZ_INS_LXR,
+    SYSZ_INS_LY,
+    SYSZ_INS_LZDR,
+    SYSZ_INS_LZER,
+    SYSZ_INS_LZXR,
+    SYSZ_INS_MADB,
+    SYSZ_INS_MADBR,
+    SYSZ_INS_MAEB,
+    SYSZ_INS_MAEBR,
+    SYSZ_INS_MDB,
+    SYSZ_INS_MDBR,
+    SYSZ_INS_MDEB,
+    SYSZ_INS_MDEBR,
+    SYSZ_INS_MEEB,
+    SYSZ_INS_MEEBR,
+    SYSZ_INS_MGHI,
+    SYSZ_INS_MH,
+    SYSZ_INS_MHI,
+    SYSZ_INS_MHY,
+    SYSZ_INS_MLG,
+    SYSZ_INS_MLGR,
+    SYSZ_INS_MS,
+    SYSZ_INS_MSDB,
+    SYSZ_INS_MSDBR,
+    SYSZ_INS_MSEB,
+    SYSZ_INS_MSEBR,
+    SYSZ_INS_MSFI,
+    SYSZ_INS_MSG,
+    SYSZ_INS_MSGF,
+    SYSZ_INS_MSGFI,
+    SYSZ_INS_MSGFR,
+    SYSZ_INS_MSGR,
+    SYSZ_INS_MSR,
+    SYSZ_INS_MSY,
+    SYSZ_INS_MVC,
+    SYSZ_INS_MVGHI,
+    SYSZ_INS_MVHHI,
+    SYSZ_INS_MVHI,
+    SYSZ_INS_MVI,
+    SYSZ_INS_MVIY,
+    SYSZ_INS_MVST,
+    SYSZ_INS_MXBR,
+    SYSZ_INS_MXDB,
+    SYSZ_INS_MXDBR,
+    SYSZ_INS_N,
+    SYSZ_INS_NC,
+    SYSZ_INS_NG,
+    SYSZ_INS_NGR,
+    SYSZ_INS_NGRK,
+    SYSZ_INS_NI,
+    SYSZ_INS_NIHF,
+    SYSZ_INS_NIHH,
+    SYSZ_INS_NIHL,
+    SYSZ_INS_NILF,
+    SYSZ_INS_NILH,
+    SYSZ_INS_NILL,
+    SYSZ_INS_NIY,
+    SYSZ_INS_NR,
+    SYSZ_INS_NRK,
+    SYSZ_INS_NY,
+    SYSZ_INS_O,
+    SYSZ_INS_OC,
+    SYSZ_INS_OG,
+    SYSZ_INS_OGR,
+    SYSZ_INS_OGRK,
+    SYSZ_INS_OI,
+    SYSZ_INS_OIHF,
+    SYSZ_INS_OIHH,
+    SYSZ_INS_OIHL,
+    SYSZ_INS_OILF,
+    SYSZ_INS_OILH,
+    SYSZ_INS_OILL,
+    SYSZ_INS_OIY,
+    SYSZ_INS_OR,
+    SYSZ_INS_ORK,
+    SYSZ_INS_OY,
+    SYSZ_INS_PFD,
+    SYSZ_INS_PFDRL,
+    SYSZ_INS_RISBG,
+    SYSZ_INS_RISBHG,
+    SYSZ_INS_RISBLG,
+    SYSZ_INS_RLL,
+    SYSZ_INS_RLLG,
+    SYSZ_INS_RNSBG,
+    SYSZ_INS_ROSBG,
+    SYSZ_INS_RXSBG,
+    SYSZ_INS_S,
+    SYSZ_INS_SDB,
+    SYSZ_INS_SDBR,
+    SYSZ_INS_SEB,
+    SYSZ_INS_SEBR,
+    SYSZ_INS_SG,
+    SYSZ_INS_SGF,
+    SYSZ_INS_SGFR,
+    SYSZ_INS_SGR,
+    SYSZ_INS_SGRK,
+    SYSZ_INS_SH,
+    SYSZ_INS_SHY,
+    SYSZ_INS_SL,
+    SYSZ_INS_SLB,
+    SYSZ_INS_SLBG,
+    SYSZ_INS_SLBR,
+    SYSZ_INS_SLFI,
+    SYSZ_INS_SLG,
+    SYSZ_INS_SLBGR,
+    SYSZ_INS_SLGF,
+    SYSZ_INS_SLGFI,
+    SYSZ_INS_SLGFR,
+    SYSZ_INS_SLGR,
+    SYSZ_INS_SLGRK,
+    SYSZ_INS_SLL,
+    SYSZ_INS_SLLG,
+    SYSZ_INS_SLLK,
+    SYSZ_INS_SLR,
+    SYSZ_INS_SLRK,
+    SYSZ_INS_SLY,
+    SYSZ_INS_SQDB,
+    SYSZ_INS_SQDBR,
+    SYSZ_INS_SQEB,
+    SYSZ_INS_SQEBR,
+    SYSZ_INS_SQXBR,
+    SYSZ_INS_SR,
+    SYSZ_INS_SRA,
+    SYSZ_INS_SRAG,
+    SYSZ_INS_SRAK,
+    SYSZ_INS_SRK,
+    SYSZ_INS_SRL,
+    SYSZ_INS_SRLG,
+    SYSZ_INS_SRLK,
+    SYSZ_INS_SRST,
+    SYSZ_INS_ST,
+    SYSZ_INS_STC,
+    SYSZ_INS_STCH,
+    SYSZ_INS_STCY,
+    SYSZ_INS_STD,
+    SYSZ_INS_STDY,
+    SYSZ_INS_STE,
+    SYSZ_INS_STEY,
+    SYSZ_INS_STFH,
+    SYSZ_INS_STG,
+    SYSZ_INS_STGRL,
+    SYSZ_INS_STH,
+    SYSZ_INS_STHH,
+    SYSZ_INS_STHRL,
+    SYSZ_INS_STHY,
+    SYSZ_INS_STMG,
+    SYSZ_INS_STRL,
+    SYSZ_INS_STRV,
+    SYSZ_INS_STRVG,
+    SYSZ_INS_STY,
+    SYSZ_INS_SXBR,
+    SYSZ_INS_SY,
+    SYSZ_INS_TM,
+    SYSZ_INS_TMHH,
+    SYSZ_INS_TMHL,
+    SYSZ_INS_TMLH,
+    SYSZ_INS_TMLL,
+    SYSZ_INS_TMY,
+    SYSZ_INS_X,
+    SYSZ_INS_XC,
+    SYSZ_INS_XG,
+    SYSZ_INS_XGR,
+    SYSZ_INS_XGRK,
+    SYSZ_INS_XI,
+    SYSZ_INS_XIHF,
+    SYSZ_INS_XILF,
+    SYSZ_INS_XIY,
+    SYSZ_INS_XR,
+    SYSZ_INS_XRK,
+    SYSZ_INS_XY,
+
+    SYSZ_INS_ENDING,   // <-- mark the end of the list of instructions
+} sysz_insn;
+
+//> Group of SystemZ instructions
+typedef enum sysz_insn_group
+{
+    SYSZ_GRP_INVALID = 0, // = CS_GRP_INVALID
+
+    //> Generic groups
+    // all jump instructions (conditional+direct+indirect jumps)
+    SYSZ_GRP_JUMP,  // = CS_GRP_JUMP
+
+    //> Architecture-specific groups
+    SYSZ_GRP_DISTINCTOPS = 128,
+    SYSZ_GRP_FPEXTENSION,
+    SYSZ_GRP_HIGHWORD,
+    SYSZ_GRP_INTERLOCKEDACCESS1,
+    SYSZ_GRP_LOADSTOREONCOND,
+
+    SYSZ_GRP_ENDING,   // <-- mark the end of the list of groups
+} sysz_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/capstone/xcore.h

@@ -0,0 +1,242 @@
+#ifndef CAPSTONE_XCORE_H
+#define CAPSTONE_XCORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <[email protected]>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Operand type for instruction's operands
+typedef enum xcore_op_type
+{
+    XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+    XCORE_OP_REG, // = CS_OP_REG (Register operand).
+    XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand).
+    XCORE_OP_MEM, // = CS_OP_MEM (Memory operand).
+} xcore_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with XCORE_OP_MEM operand type above
+typedef struct xcore_op_mem
+{
+    uint8_t base;   // base register
+    uint8_t index;  // index register
+    int32_t disp;   // displacement/offset value
+    int     direct; // +1: forward, -1: backward
+} xcore_op_mem;
+
+// Instruction operand
+typedef struct cs_xcore_op
+{
+    xcore_op_type type; // operand type
+    union
+    {
+        unsigned int reg;   // register value for REG operand
+        int32_t imm;        // immediate value for IMM operand
+        xcore_op_mem mem;       // base/disp value for MEM operand
+    };
+} cs_xcore_op;
+
+// Instruction structure
+typedef struct cs_xcore
+{
+    // Number of operands of this instruction,
+    // or 0 when instruction has no operand.
+    uint8_t op_count;
+    cs_xcore_op operands[8]; // operands for this instruction.
+} cs_xcore;
+
+//> XCore registers
+typedef enum xcore_reg
+{
+    XCORE_REG_INVALID = 0,
+
+    XCORE_REG_CP,
+    XCORE_REG_DP,
+    XCORE_REG_LR,
+    XCORE_REG_SP,
+    XCORE_REG_R0,
+    XCORE_REG_R1,
+    XCORE_REG_R2,
+    XCORE_REG_R3,
+    XCORE_REG_R4,
+    XCORE_REG_R5,
+    XCORE_REG_R6,
+    XCORE_REG_R7,
+    XCORE_REG_R8,
+    XCORE_REG_R9,
+    XCORE_REG_R10,
+    XCORE_REG_R11,
+
+    //> pseudo registers
+    XCORE_REG_PC,   // pc
+
+    // internal thread registers
+    // see The-XMOS-XS1-Architecture(X7879A).pdf
+    XCORE_REG_SCP,  // save pc
+    XCORE_REG_SSR,  // save status
+    XCORE_REG_ET,   // exception type
+    XCORE_REG_ED,   // exception data
+    XCORE_REG_SED,  // save exception data
+    XCORE_REG_KEP,  // kernel entry pointer
+    XCORE_REG_KSP,  // kernel stack pointer
+    XCORE_REG_ID,   // thread ID
+
+    XCORE_REG_ENDING,   // <-- mark the end of the list of registers
+} xcore_reg;
+
+//> XCore instruction
+typedef enum xcore_insn
+{
+    XCORE_INS_INVALID = 0,
+
+    XCORE_INS_ADD,
+    XCORE_INS_ANDNOT,
+    XCORE_INS_AND,
+    XCORE_INS_ASHR,
+    XCORE_INS_BAU,
+    XCORE_INS_BITREV,
+    XCORE_INS_BLA,
+    XCORE_INS_BLAT,
+    XCORE_INS_BL,
+    XCORE_INS_BF,
+    XCORE_INS_BT,
+    XCORE_INS_BU,
+    XCORE_INS_BRU,
+    XCORE_INS_BYTEREV,
+    XCORE_INS_CHKCT,
+    XCORE_INS_CLRE,
+    XCORE_INS_CLRPT,
+    XCORE_INS_CLRSR,
+    XCORE_INS_CLZ,
+    XCORE_INS_CRC8,
+    XCORE_INS_CRC32,
+    XCORE_INS_DCALL,
+    XCORE_INS_DENTSP,
+    XCORE_INS_DGETREG,
+    XCORE_INS_DIVS,
+    XCORE_INS_DIVU,
+    XCORE_INS_DRESTSP,
+    XCORE_INS_DRET,
+    XCORE_INS_ECALLF,
+    XCORE_INS_ECALLT,
+    XCORE_INS_EDU,
+    XCORE_INS_EEF,
+    XCORE_INS_EET,
+    XCORE_INS_EEU,
+    XCORE_INS_ENDIN,
+    XCORE_INS_ENTSP,
+    XCORE_INS_EQ,
+    XCORE_INS_EXTDP,
+    XCORE_INS_EXTSP,
+    XCORE_INS_FREER,
+    XCORE_INS_FREET,
+    XCORE_INS_GETD,
+    XCORE_INS_GET,
+    XCORE_INS_GETN,
+    XCORE_INS_GETR,
+    XCORE_INS_GETSR,
+    XCORE_INS_GETST,
+    XCORE_INS_GETTS,
+    XCORE_INS_INCT,
+    XCORE_INS_INIT,
+    XCORE_INS_INPW,
+    XCORE_INS_INSHR,
+    XCORE_INS_INT,
+    XCORE_INS_IN,
+    XCORE_INS_KCALL,
+    XCORE_INS_KENTSP,
+    XCORE_INS_KRESTSP,
+    XCORE_INS_KRET,
+    XCORE_INS_LADD,
+    XCORE_INS_LD16S,
+    XCORE_INS_LD8U,
+    XCORE_INS_LDA16,
+    XCORE_INS_LDAP,
+    XCORE_INS_LDAW,
+    XCORE_INS_LDC,
+    XCORE_INS_LDW,
+    XCORE_INS_LDIVU,
+    XCORE_INS_LMUL,
+    XCORE_INS_LSS,
+    XCORE_INS_LSUB,
+    XCORE_INS_LSU,
+    XCORE_INS_MACCS,
+    XCORE_INS_MACCU,
+    XCORE_INS_MJOIN,
+    XCORE_INS_MKMSK,
+    XCORE_INS_MSYNC,
+    XCORE_INS_MUL,
+    XCORE_INS_NEG,
+    XCORE_INS_NOT,
+    XCORE_INS_OR,
+    XCORE_INS_OUTCT,
+    XCORE_INS_OUTPW,
+    XCORE_INS_OUTSHR,
+    XCORE_INS_OUTT,
+    XCORE_INS_OUT,
+    XCORE_INS_PEEK,
+    XCORE_INS_REMS,
+    XCORE_INS_REMU,
+    XCORE_INS_RETSP,
+    XCORE_INS_SETCLK,
+    XCORE_INS_SET,
+    XCORE_INS_SETC,
+    XCORE_INS_SETD,
+    XCORE_INS_SETEV,
+    XCORE_INS_SETN,
+    XCORE_INS_SETPSC,
+    XCORE_INS_SETPT,
+    XCORE_INS_SETRDY,
+    XCORE_INS_SETSR,
+    XCORE_INS_SETTW,
+    XCORE_INS_SETV,
+    XCORE_INS_SEXT,
+    XCORE_INS_SHL,
+    XCORE_INS_SHR,
+    XCORE_INS_SSYNC,
+    XCORE_INS_ST16,
+    XCORE_INS_ST8,
+    XCORE_INS_STW,
+    XCORE_INS_SUB,
+    XCORE_INS_SYNCR,
+    XCORE_INS_TESTCT,
+    XCORE_INS_TESTLCL,
+    XCORE_INS_TESTWCT,
+    XCORE_INS_TSETMR,
+    XCORE_INS_START,
+    XCORE_INS_WAITEF,
+    XCORE_INS_WAITET,
+    XCORE_INS_WAITEU,
+    XCORE_INS_XOR,
+    XCORE_INS_ZEXT,
+
+    XCORE_INS_ENDING,   // <-- mark the end of the list of instructions
+} xcore_insn;
+
+//> Group of XCore instructions
+typedef enum xcore_insn_group
+{
+    XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID
+
+    //> Generic groups
+    // all jump instructions (conditional+direct+indirect jumps)
+    XCORE_GRP_JUMP, // = CS_GRP_JUMP
+
+    XCORE_GRP_ENDING,   // <-- mark the end of the list of groups
+} xcore_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

pluginsdk/jansson/jansson.h

@@ -15,18 +15,17 @@
 #include "jansson_config.h"
 
 #ifdef __cplusplus
-extern "C"
+extern "C" {
-{
 #endif
 
 /* version */
 
 #define JANSSON_MAJOR_VERSION  2
-#define JANSSON_MINOR_VERSION  6
+#define JANSSON_MINOR_VERSION  7
 #define JANSSON_MICRO_VERSION  0
 
 /* Micro version is omitted if it's 0 */
-#define JANSSON_VERSION  "2.6"
+#define JANSSON_VERSION  "2.7"
 
 /* Version as a 3-byte hex number, e.g. 0x010201 == 1.2.1. Use this
    for numeric comparisons, e.g. #if JANSSON_VERSION_HEX >= ... */
@@ -55,8 +54,6 @@ typedef struct json_t
     size_t refcount;
 } json_t;
 
-typedef json_t* JSON;
-
 #ifndef JANSSON_USING_CMAKE /* disabled if using cmake */
 #if JSON_INTEGER_IS_LONG_LONG
 #ifdef _WIN32
@@ -93,17 +90,6 @@ __declspec(dllimport) json_t* json_stringn(const char* value, size_t len);
 __declspec(dllimport) json_t* json_string_nocheck(const char* value);
 __declspec(dllimport) json_t* json_stringn_nocheck(const char* value, size_t len);
 __declspec(dllimport) json_t* json_integer(json_int_t value);
-static JSON_INLINE
-json_t* json_hex(json_int_t value)
-{
-    char hexvalue[20];
-#ifdef _WIN64
-    sprintf(hexvalue, "0x%llX", value);
-#else //x64
-    sprintf(hexvalue, "0x%X", value);
-#endif //_WIN64
-    return json_string(hexvalue);
-}
 __declspec(dllimport) json_t* json_real(double value);
 __declspec(dllimport) json_t* json_true(void);
 __declspec(dllimport) json_t* json_false(void);
@@ -222,21 +208,6 @@ int json_array_insert(json_t* array, size_t ind, json_t* value)
 __declspec(dllimport) const char* json_string_value(const json_t* string);
 __declspec(dllimport) size_t json_string_length(const json_t* string);
 __declspec(dllimport) json_int_t json_integer_value(const json_t* integer);
-static JSON_INLINE
-json_int_t json_hex_value(const json_t* hex)
-{
-    json_int_t ret;
-    const char* hexvalue;
-    hexvalue = json_string_value(hex);
-    if(!hexvalue)
-        return 0;
-#ifdef _WIN64
-    sscanf(hexvalue, "0x%llX", &ret);
-#else //x64
-    sscanf(hexvalue, "0x%X", &ret);
-#endif //_WIN64
-    return ret;
-}
 __declspec(dllimport) double json_real_value(const json_t* real);
 __declspec(dllimport) double json_number_value(const json_t* json);
 
@@ -291,7 +262,8 @@ __declspec(dllimport) json_t* json_load_callback(json_load_callback_t callback,
 
 /* encoding */
 
-#define JSON_INDENT(n)          ((n) & 0x1F)
+#define JSON_MAX_INDENT         0x1F
+#define JSON_INDENT(n)          ((n) & JSON_MAX_INDENT)
 #define JSON_COMPACT            0x20
 #define JSON_ENSURE_ASCII       0x40
 #define JSON_SORT_KEYS          0x80

pluginsdk/jansson/jansson_x64dbg.h

@@ -0,0 +1,29 @@
+typedef json_t* JSON;
+
+static JSON_INLINE
+json_t* json_hex(unsigned json_int_t value)
+{
+    char hexvalue[20];
+#ifdef _WIN64
+    sprintf(hexvalue, "0x%llX", value);
+#else //x64
+    sprintf(hexvalue, "0x%X", value);
+#endif //_WIN64
+    return json_string(hexvalue);
+}
+
+static JSON_INLINE
+unsigned json_int_t json_hex_value(const json_t* hex)
+{
+    unsigned json_int_t ret;
+    const char* hexvalue;
+    hexvalue = json_string_value(hex);
+    if(!hexvalue)
+        return 0;
+#ifdef _WIN64
+    sscanf(hexvalue, "0x%llX", &ret);
+#else //x64
+    sscanf(hexvalue, "0x%X", &ret);
+#endif //_WIN64
+    return ret;
+}

pluginsdk/yara/yara/object.h

@@ -20,8 +20,8 @@ limitations under the License.
 #ifdef _MSC_VER
 #include <float.h>
 #define isnan _isnan
-#define INFINITY (DBL_MAX + DBL_MAX)
+//#define INFINITY (DBL_MAX + DBL_MAX)
-#define NAN (INFINITY-INFINITY)
+//#define NAN (INFINITY-INFINITY)
 #endif
 
 #include "types.h"

test.cpp

@@ -4,6 +4,7 @@
 #include <windows.h>
 #include <stdio.h>
 #include <psapi.h>
+#include "icons.h"
 
 static void adler32selection(const SELECTIONDATA & sel)
 {
@@ -400,6 +401,18 @@ void testStop()
 
 void testSetup()
 {
+    ICONDATA rocket;
+    rocket.data = icon_rocket;
+    rocket.size = sizeof(icon_rocket);
+    ICONDATA adler32;
+    adler32.data = icon_adler32;
+    adler32.size = sizeof(icon_adler32);
+
+    _plugin_menuseticon(hMenu, &rocket);
+    _plugin_menuseticon(hMenuDisasm, &rocket);
+    _plugin_menuseticon(hMenuDump, &rocket);
+    _plugin_menuseticon(hMenuStack, &rocket);
+
     _plugin_menuaddentry(hMenu, MENU_DUMP, "&DumpProcess...");
     _plugin_menuaddentry(hMenu, MENU_TEST, "&Menu Test");
     _plugin_menuaddentry(hMenu, MENU_SELECTION, "&Selection API Test");
@@ -409,9 +422,12 @@ void testSetup()
     _plugin_menuaddentry(hGraphMenu, MENU_GRAPH_FUNCTION, "&Function");
 
     _plugin_menuaddentry(hMenuDisasm, MENU_DISASM_ADLER32, "&Adler32 Selection");
+    _plugin_menuentryseticon(pluginHandle, MENU_DISASM_ADLER32, &adler32);
     _plugin_menuaddseparator(hMenuDisasm);
     _plugin_menuaddentry(hMenuDisasm, MENU_DISASM_GRAPH_SELECTION, "&Graph Selection");
     _plugin_menuaddentry(hMenuDisasm, MENU_DISASM_GRAPH_FUNCTION, "Graph &Function");
     _plugin_menuaddentry(hMenuDump, MENU_DUMP_ADLER32, "&Adler32 Selection");
+    _plugin_menuentryseticon(pluginHandle, MENU_DUMP_ADLER32, &adler32);
     _plugin_menuaddentry(hMenuStack, MENU_STACK_ADLER32, "&Adler32 Selection");
+    _plugin_menuentryseticon(pluginHandle, MENU_STACK_ADLER32, &adler32);
 }

x64_dbg_testplugin.vcxproj

@@ -17,12 +17,19 @@
   </ItemGroup>
   <ItemGroup>
     <ClInclude Include="FunctionGraph.h" />
+    <ClInclude Include="icons.h" />
     <ClInclude Include="pluginmain.h" />
-    <ClInclude Include="pluginsdk\BeaEngine\basic_types.h" />
-    <ClInclude Include="pluginsdk\BeaEngine\BeaEngine.h" />
-    <ClInclude Include="pluginsdk\BeaEngine\export.h" />
-    <ClInclude Include="pluginsdk\BeaEngine\macros.h" />
     <ClInclude Include="pluginsdk\bridgemain.h" />
+    <ClInclude Include="pluginsdk\capstone\arm.h" />
+    <ClInclude Include="pluginsdk\capstone\arm64.h" />
+    <ClInclude Include="pluginsdk\capstone\capstone.h" />
+    <ClInclude Include="pluginsdk\capstone\mips.h" />
+    <ClInclude Include="pluginsdk\capstone\platform.h" />
+    <ClInclude Include="pluginsdk\capstone\ppc.h" />
+    <ClInclude Include="pluginsdk\capstone\sparc.h" />
+    <ClInclude Include="pluginsdk\capstone\systemz.h" />
+    <ClInclude Include="pluginsdk\capstone\x86.h" />
+    <ClInclude Include="pluginsdk\capstone\xcore.h" />
     <ClInclude Include="pluginsdk\dbghelp\dbghelp.h" />
     <ClInclude Include="pluginsdk\DeviceNameResolver\DeviceNameResolver.h" />
     <ClInclude Include="pluginsdk\jansson\jansson.h" />
@@ -32,6 +39,36 @@
     <ClInclude Include="pluginsdk\lz4\lz4hc.h" />
     <ClInclude Include="pluginsdk\TitanEngine\TitanEngine.h" />
     <ClInclude Include="pluginsdk\XEDParse\XEDParse.h" />
+    <ClInclude Include="pluginsdk\yara\yara.h" />
+    <ClInclude Include="pluginsdk\yara\yara\ahocorasick.h" />
+    <ClInclude Include="pluginsdk\yara\yara\arena.h" />
+    <ClInclude Include="pluginsdk\yara\yara\atoms.h" />
+    <ClInclude Include="pluginsdk\yara\yara\compiler.h" />
+    <ClInclude Include="pluginsdk\yara\yara\elf.h" />
+    <ClInclude Include="pluginsdk\yara\yara\error.h" />
+    <ClInclude Include="pluginsdk\yara\yara\exec.h" />
+    <ClInclude Include="pluginsdk\yara\yara\exefiles.h" />
+    <ClInclude Include="pluginsdk\yara\yara\filemap.h" />
+    <ClInclude Include="pluginsdk\yara\yara\globals.h" />
+    <ClInclude Include="pluginsdk\yara\yara\hash.h" />
+    <ClInclude Include="pluginsdk\yara\yara\hex_lexer.h" />
+    <ClInclude Include="pluginsdk\yara\yara\lexer.h" />
+    <ClInclude Include="pluginsdk\yara\yara\libyara.h" />
+    <ClInclude Include="pluginsdk\yara\yara\limits.h" />
+    <ClInclude Include="pluginsdk\yara\yara\mem.h" />
+    <ClInclude Include="pluginsdk\yara\yara\modules.h" />
+    <ClInclude Include="pluginsdk\yara\yara\object.h" />
+    <ClInclude Include="pluginsdk\yara\yara\parser.h" />
+    <ClInclude Include="pluginsdk\yara\yara\pe.h" />
+    <ClInclude Include="pluginsdk\yara\yara\proc.h" />
+    <ClInclude Include="pluginsdk\yara\yara\re.h" />
+    <ClInclude Include="pluginsdk\yara\yara\re_lexer.h" />
+    <ClInclude Include="pluginsdk\yara\yara\rules.h" />
+    <ClInclude Include="pluginsdk\yara\yara\scan.h" />
+    <ClInclude Include="pluginsdk\yara\yara\sizedstr.h" />
+    <ClInclude Include="pluginsdk\yara\yara\strutils.h" />
+    <ClInclude Include="pluginsdk\yara\yara\types.h" />
+    <ClInclude Include="pluginsdk\yara\yara\utils.h" />
     <ClInclude Include="pluginsdk\_dbgfunctions.h" />
     <ClInclude Include="pluginsdk\_plugins.h" />
     <ClInclude Include="pluginsdk\_plugin_types.h" />
@@ -85,7 +122,7 @@
       <SubSystem>Windows</SubSystem>
       <EnableCOMDATFolding>true</EnableCOMDATFolding>
       <OptimizeReferences>true</OptimizeReferences>
-      <AdditionalDependencies>psapi.lib;pluginsdk\x32_dbg.lib;pluginsdk\x32_bridge.lib;pluginsdk\TitanEngine\TitanEngine_x86.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalDependencies>psapi.lib;pluginsdk\x32dbg.lib;pluginsdk\x32bridge.lib;pluginsdk\TitanEngine\TitanEngine_x86.lib;%(AdditionalDependencies)</AdditionalDependencies>
     </Link>
   </ItemDefinitionGroup>
   <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">
@@ -100,7 +137,7 @@
       <SubSystem>Windows</SubSystem>
       <EnableCOMDATFolding>true</EnableCOMDATFolding>
       <OptimizeReferences>true</OptimizeReferences>
-      <AdditionalDependencies>psapi.lib;pluginsdk\x64_dbg.lib;pluginsdk\x64_bridge.lib;pluginsdk\TitanEngine\TitanEngine_x64.lib;%(AdditionalDependencies)</AdditionalDependencies>
+      <AdditionalDependencies>psapi.lib;pluginsdk\x64dbg.lib;pluginsdk\x64bridge.lib;pluginsdk\TitanEngine\TitanEngine_x64.lib;%(AdditionalDependencies)</AdditionalDependencies>
     </Link>
   </ItemDefinitionGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />

x64_dbg_testplugin.vcxproj.filters

@@ -22,9 +22,6 @@
     <Filter Include="Header Files\pluginsdk\XEDParse">
       <UniqueIdentifier>{9a9250a7-4eba-4138-ab27-aac113d2311d}</UniqueIdentifier>
     </Filter>
-    <Filter Include="Header Files\pluginsdk\BeaEngine">
-      <UniqueIdentifier>{3224b0d7-55d2-45a9-bfde-15adfda46e7d}</UniqueIdentifier>
-    </Filter>
     <Filter Include="Header Files\pluginsdk\dbghelp">
       <UniqueIdentifier>{88c799f9-d796-4cf1-be07-6d317ab7e298}</UniqueIdentifier>
     </Filter>
@@ -37,6 +34,15 @@
     <Filter Include="Header Files\pluginsdk\lz4">
       <UniqueIdentifier>{d0acf554-96b2-439c-a87e-01db279bec62}</UniqueIdentifier>
     </Filter>
+    <Filter Include="Header Files\pluginsdk\yara">
+      <UniqueIdentifier>{ca4b08fa-9d60-4777-9b89-15f3d0cd7507}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="Header Files\pluginsdk\yara\yara">
+      <UniqueIdentifier>{adc26eed-1e00-4f24-8662-ec8902a11c2f}</UniqueIdentifier>
+    </Filter>
+    <Filter Include="Header Files\pluginsdk\capstone">
+      <UniqueIdentifier>{159fe27f-06af-4f64-ab68-272e61a3608e}</UniqueIdentifier>
+    </Filter>
   </ItemGroup>
   <ItemGroup>
     <ClCompile Include="pluginmain.cpp">
@@ -71,18 +77,6 @@
     <ClInclude Include="pluginsdk\_dbgfunctions.h">
       <Filter>Header Files\pluginsdk</Filter>
     </ClInclude>
-    <ClInclude Include="pluginsdk\BeaEngine\basic_types.h">
-      <Filter>Header Files\pluginsdk\BeaEngine</Filter>
-    </ClInclude>
-    <ClInclude Include="pluginsdk\BeaEngine\BeaEngine.h">
-      <Filter>Header Files\pluginsdk\BeaEngine</Filter>
-    </ClInclude>
-    <ClInclude Include="pluginsdk\BeaEngine\export.h">
-      <Filter>Header Files\pluginsdk\BeaEngine</Filter>
-    </ClInclude>
-    <ClInclude Include="pluginsdk\BeaEngine\macros.h">
-      <Filter>Header Files\pluginsdk\BeaEngine</Filter>
-    </ClInclude>
     <ClInclude Include="pluginsdk\dbghelp\dbghelp.h">
       <Filter>Header Files\pluginsdk\dbghelp</Filter>
     </ClInclude>
@@ -110,5 +104,128 @@
     <ClInclude Include="FunctionGraph.h">
       <Filter>Header Files</Filter>
     </ClInclude>
+    <ClInclude Include="pluginsdk\yara\yara\ahocorasick.h">
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